diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
| commit | fce3433b2eb764d9519ffbc4c7e95049f3200ba3 (patch) | |
| tree | 26e90c5190c4751532683d1f4b5bf6094e6ba4b7 /tests/long/fs/10.linux-boot/ref/alpha/linux | |
| parent | c4898b15bcf5458e35f17cb0c3b4185cec0081aa (diff) | |
| download | gem5-fce3433b2eb764d9519ffbc4c7e95049f3200ba3.tar.xz | |
stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
3 files changed, 3602 insertions, 3622 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 30313ea26..40315f031 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.901720 # Number of seconds simulated -sim_ticks 1901719660500 # Number of ticks simulated -final_tick 1901719660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.898811 # Number of seconds simulated +sim_ticks 1898811181000 # Number of ticks simulated +final_tick 1898811181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97307 # Simulator instruction rate (inst/s) -host_op_rate 97307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3261646555 # Simulator tick rate (ticks/s) -host_mem_usage 383552 # Number of bytes of host memory used -host_seconds 583.06 # Real time elapsed on the host -sim_insts 56735321 # Number of instructions simulated -sim_ops 56735321 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24596992 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2651904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 118720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 533440 # Number of bytes read from this memory -system.physmem.bytes_read::total 28758656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 857600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 118720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 976320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7726912 # Number of bytes written to this memory -system.physmem.bytes_written::total 7726912 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 384328 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41436 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1855 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8335 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449354 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120733 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120733 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 450960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12934079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1394477 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 62428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 280504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15122448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 450960 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 62428 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513388 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4063118 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4063118 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4063118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 450960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12934079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1394477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 62428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 280504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19185566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449354 # Total number of read requests seen -system.physmem.writeReqs 120733 # Total number of write requests seen -system.physmem.cpureqs 587676 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28758656 # Total number of bytes read from memory -system.physmem.bytesWritten 7726912 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28758656 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7726912 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4987 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28470 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27991 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28541 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28079 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28255 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28278 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27937 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28148 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28117 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27877 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27868 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27749 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7940 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7547 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7751 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7437 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7593 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7293 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7361 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7614 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7612 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7616 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7622 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7539 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7418 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7408 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7246 # Track writes on a per bank basis +host_inst_rate 163774 # Simulator instruction rate (inst/s) +host_op_rate 163774 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5540525376 # Simulator tick rate (ticks/s) +host_mem_usage 339592 # Number of bytes of host memory used +host_seconds 342.71 # Real time elapsed on the host +sim_insts 56127436 # Number of instructions simulated +sim_ops 56127436 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 739584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24165760 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 241984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1058688 # Number of bytes read from this memory +system.physmem.bytes_read::total 28856384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 739584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 241984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 981568 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7824192 # Number of bytes written to this memory +system.physmem.bytes_written::total 7824192 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11556 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 377590 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41412 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3781 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16542 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450881 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122253 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122253 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 389498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12726784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1395804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 127440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 557553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15197079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 389498 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 127440 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516938 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4120574 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4120574 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4120574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 389498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12726784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1395804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 127440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 557553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19317653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450881 # Total number of read requests seen +system.physmem.writeReqs 122253 # Total number of write requests seen +system.physmem.cpureqs 582476 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28856384 # Total number of bytes read from memory +system.physmem.bytesWritten 7824192 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28856384 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7824192 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 66 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3389 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28644 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28625 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28250 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28253 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28243 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28343 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 28155 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28192 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27999 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28056 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27988 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28022 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27871 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27898 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8087 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7991 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7846 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7763 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7721 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7658 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7765 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7698 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7705 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7559 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7625 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7394 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7457 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7400 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7239 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7345 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 393 # Number of times wr buffer was full causing retry -system.physmem.totGap 1901668058000 # Total gap between requests +system.physmem.numWrRetry 1873 # Number of times wr buffer was full causing retry +system.physmem.totGap 1898811160000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 449354 # Categorize read packet sizes +system.physmem.readPktSize::6 450881 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -107,7 +107,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 121126 # categorize write packet sizes +system.physmem.writePktSize::6 124126 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -116,33 +116,33 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4987 # categorize neither packet sizes +system.physmem.neitherpktsize::6 3389 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 322670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 320280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7745 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2644 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1519 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1411 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 760 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -152,225 +152,225 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5315 # 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number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120840.897727 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120840.897727 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256518.502262 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256518.502262 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255946.242427 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255946.242427 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255946.242427 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255946.242427 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 284980 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 22877 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27128 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.332211 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.505013 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 41522 # number of writebacks +system.iocache.writebacks::total 41522 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12298000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12298000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7352694535 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7352694535 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7364992535 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7364992535 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7364992535 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7364992535 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12115250 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12115250 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8496857845 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8496857845 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8508973095 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8508973095 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8508973095 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8508973095 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -591,14 +591,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68703.910615 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68703.910615 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176951.639753 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176951.639753 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176487.324411 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176487.324411 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176487.324411 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176487.324411 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68836.647727 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68836.647727 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204487.337433 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204487.337433 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203915.191119 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203915.191119 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203915.191119 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203915.191119 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -612,35 +612,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12372868 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10433314 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 330387 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8151024 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5278103 # Number of BTB hits +system.cpu0.branchPred.lookups 10581841 # Number of BP lookups +system.cpu0.branchPred.condPredicted 8959361 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 281985 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7046138 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4567974 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 64.753864 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 784011 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 32544 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 64.829471 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 656046 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29257 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8796431 # DTB read hits -system.cpu0.dtb.read_misses 31428 # DTB read misses -system.cpu0.dtb.read_acv 541 # DTB read access violations -system.cpu0.dtb.read_accesses 625134 # DTB read accesses -system.cpu0.dtb.write_hits 5759616 # DTB write hits -system.cpu0.dtb.write_misses 8293 # DTB write misses -system.cpu0.dtb.write_acv 340 # DTB write access violations -system.cpu0.dtb.write_accesses 208056 # DTB write accesses -system.cpu0.dtb.data_hits 14556047 # DTB hits -system.cpu0.dtb.data_misses 39721 # DTB misses -system.cpu0.dtb.data_acv 881 # DTB access violations -system.cpu0.dtb.data_accesses 833190 # DTB accesses -system.cpu0.itb.fetch_hits 984271 # ITB hits -system.cpu0.itb.fetch_misses 30098 # ITB misses -system.cpu0.itb.fetch_acv 957 # ITB acv -system.cpu0.itb.fetch_accesses 1014369 # ITB accesses +system.cpu0.dtb.read_hits 7560815 # DTB read hits +system.cpu0.dtb.read_misses 30461 # DTB read misses +system.cpu0.dtb.read_acv 538 # DTB read access violations +system.cpu0.dtb.read_accesses 623625 # DTB read accesses +system.cpu0.dtb.write_hits 5040625 # DTB write hits +system.cpu0.dtb.write_misses 7520 # DTB write misses +system.cpu0.dtb.write_acv 334 # DTB write access violations +system.cpu0.dtb.write_accesses 206551 # DTB write accesses +system.cpu0.dtb.data_hits 12601440 # DTB hits +system.cpu0.dtb.data_misses 37981 # DTB misses +system.cpu0.dtb.data_acv 872 # DTB access violations +system.cpu0.dtb.data_accesses 830176 # DTB accesses +system.cpu0.itb.fetch_hits 911527 # ITB hits +system.cpu0.itb.fetch_misses 30644 # ITB misses +system.cpu0.itb.fetch_acv 921 # ITB acv +system.cpu0.itb.fetch_accesses 942171 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -653,269 +653,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 101814962 # number of cpu cycles simulated +system.cpu0.numCycles 89753559 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 24931217 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63627814 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12372868 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6062114 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11958171 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1721751 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 36639586 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31996 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 197160 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 291451 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 250 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7650026 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 223701 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 75155119 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.846620 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.185016 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 21107693 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 54367118 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 10581841 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5224020 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10262063 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1458036 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 30903552 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 30207 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 199263 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 186050 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 96 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6657299 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 195043 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 63623646 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.854511 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.189260 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 63196948 84.09% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 760434 1.01% 85.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1555219 2.07% 87.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 695943 0.93% 88.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2597980 3.46% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 515321 0.69% 92.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 570202 0.76% 93.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 825200 1.10% 94.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4437872 5.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 53361583 83.87% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 672459 1.06% 84.93% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1316592 2.07% 87.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 583007 0.92% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2295308 3.61% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 445844 0.70% 92.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 472664 0.74% 92.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 743494 1.17% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3732695 5.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 75155119 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.121523 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.624936 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26159678 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36134055 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10861438 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 929510 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1070437 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 506952 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35177 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62384726 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 105081 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1070437 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27188236 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 14621537 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18000496 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10158555 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4115856 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 58951339 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6767 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 643786 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1455498 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39478397 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 71801839 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 71417626 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 384213 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34623741 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4854648 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1439423 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 209577 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11309679 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9204846 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6035425 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1140474 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 743155 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52262338 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1790513 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 51072320 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 91453 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5903524 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3097982 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1211963 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 75155119 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.679559 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.328921 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 63623646 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.117899 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.605738 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 22232367 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 30357900 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9303163 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 825009 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 905206 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 419214 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 29823 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 53368764 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 92723 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 905206 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 23093913 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 11627753 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15736016 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8768275 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3492481 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 50503220 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6655 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 393829 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1341574 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 33876980 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 61564678 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 61250531 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 314147 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 29813717 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4063255 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1268860 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 187899 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 9409132 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7922191 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5257693 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 964170 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 651506 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 44858999 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1558626 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 43884207 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 67322 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 4967350 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2566909 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1055206 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 63623646 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.689747 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.329677 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 52460165 69.80% 69.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10326519 13.74% 83.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4642920 6.18% 89.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3073584 4.09% 93.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2437230 3.24% 97.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1208862 1.61% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 646282 0.86% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 308169 0.41% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 51388 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 43919799 69.03% 69.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9075335 14.26% 83.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4098408 6.44% 89.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2614119 4.11% 93.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2006211 3.15% 97.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1055812 1.66% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 551217 0.87% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 263467 0.41% 99.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 39278 0.06% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 75155119 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 63623646 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 82854 12.32% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 311669 46.35% 58.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 277938 41.33% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 62740 10.88% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 271097 47.03% 57.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 242616 42.09% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35204584 68.93% 68.94% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56105 0.11% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15686 0.03% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9153958 17.92% 87.01% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5827340 11.41% 98.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 808994 1.58% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3777 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 30137882 68.68% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 45897 0.10% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 14285 0.03% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.82% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.83% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 7870096 17.93% 86.76% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5096964 11.61% 98.37% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 713427 1.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 51072320 # Type of FU issued -system.cpu0.iq.rate 0.501619 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 672462 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013167 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 177512873 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59702358 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50032811 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 550800 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 266343 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 260046 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51452584 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 288424 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 541788 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 43884207 # Type of FU issued +system.cpu0.iq.rate 0.488941 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 576453 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013136 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 151584762 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 51176195 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43017955 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 451072 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 219118 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 212749 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 44220901 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 235982 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 487348 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1120800 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2789 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12579 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 457772 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 958085 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2941 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 10552 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 366818 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18421 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 147130 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 13186 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 117811 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1070437 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10393328 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 793846 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57261563 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 642303 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9204846 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6035425 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1577054 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 582295 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5281 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12579 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 164111 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 347239 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 511350 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 50686887 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8851053 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 385432 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 905206 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8069118 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 677733 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 49115212 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 536411 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7922191 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5257693 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1375945 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 564143 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4652 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 10552 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 138850 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 301409 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 440259 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 43556869 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 7611218 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 327337 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3208712 # number of nop insts executed -system.cpu0.iew.exec_refs 14632506 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8068479 # Number of branches executed -system.cpu0.iew.exec_stores 5781453 # Number of stores executed -system.cpu0.iew.exec_rate 0.497833 # Inst execution rate -system.cpu0.iew.wb_sent 50383937 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50292857 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25094352 # num instructions producing a value -system.cpu0.iew.wb_consumers 33818001 # num instructions consuming a value +system.cpu0.iew.exec_nop 2697587 # number of nop insts executed +system.cpu0.iew.exec_refs 12670581 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6879787 # Number of branches executed +system.cpu0.iew.exec_stores 5059363 # Number of stores executed +system.cpu0.iew.exec_rate 0.485294 # Inst execution rate +system.cpu0.iew.wb_sent 43311636 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43230704 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 21537449 # num instructions producing a value +system.cpu0.iew.wb_consumers 28771492 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.493963 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742041 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.481660 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.748569 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6371688 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 578550 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 477828 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 74084682 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.685601 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.604018 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5358562 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 503420 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 412035 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 62718440 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.696169 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.614251 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 55026515 74.28% 74.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7939418 10.72% 84.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4342581 5.86% 90.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2354466 3.18% 94.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1312338 1.77% 95.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 550007 0.74% 96.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 466229 0.63% 97.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 437204 0.59% 97.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1655924 2.24% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 46279929 73.79% 73.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6945490 11.07% 84.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3654930 5.83% 90.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2050520 3.27% 93.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1130391 1.80% 95.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 454158 0.72% 96.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 393863 0.63% 97.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 373108 0.59% 97.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1436051 2.29% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 74084682 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 50792559 # Number of instructions committed -system.cpu0.commit.committedOps 50792559 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 62718440 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 43662606 # Number of instructions committed +system.cpu0.commit.committedOps 43662606 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13661699 # Number of memory references committed -system.cpu0.commit.loads 8084046 # Number of loads committed -system.cpu0.commit.membars 197074 # Number of memory barriers committed -system.cpu0.commit.branches 7671683 # Number of branches committed -system.cpu0.commit.fp_insts 257823 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47034170 # Number of committed integer instructions. -system.cpu0.commit.function_calls 648346 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1655924 # number cycles where commit BW limit reached +system.cpu0.commit.refs 11854981 # Number of memory references committed +system.cpu0.commit.loads 6964106 # Number of loads committed +system.cpu0.commit.membars 168172 # Number of memory barriers committed +system.cpu0.commit.branches 6551324 # Number of branches committed +system.cpu0.commit.fp_insts 210613 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 40489033 # Number of committed integer instructions. +system.cpu0.commit.function_calls 540020 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1436051 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 129398549 # The number of ROB reads -system.cpu0.rob.rob_writes 115399767 # The number of ROB writes -system.cpu0.timesIdled 1054205 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26659843 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3701617819 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 47867129 # Number of Instructions Simulated -system.cpu0.committedOps 47867129 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 47867129 # Number of Instructions Simulated -system.cpu0.cpi 2.127033 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.127033 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.470138 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.470138 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 66695316 # number of integer regfile reads -system.cpu0.int_regfile_writes 36408183 # number of integer regfile writes -system.cpu0.fp_regfile_reads 127649 # number of floating regfile reads -system.cpu0.fp_regfile_writes 129302 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1695809 # number of misc regfile reads -system.cpu0.misc_regfile_writes 808592 # number of misc regfile writes +system.cpu0.rob.rob_reads 110111593 # The number of ROB reads +system.cpu0.rob.rob_writes 98948174 # The number of ROB writes +system.cpu0.timesIdled 879648 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26129913 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3707863967 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 41199881 # Number of Instructions Simulated +system.cpu0.committedOps 41199881 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 41199881 # Number of Instructions Simulated +system.cpu0.cpi 2.178491 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.178491 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.459033 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.459033 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 57370310 # number of integer regfile reads +system.cpu0.int_regfile_writes 31317782 # number of integer regfile writes +system.cpu0.fp_regfile_reads 104569 # number of floating regfile reads +system.cpu0.fp_regfile_writes 105332 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1463769 # number of misc regfile reads +system.cpu0.misc_regfile_writes 718581 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -947,245 +947,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 867960 # number of replacements -system.cpu0.icache.tagsinuse 510.328414 # Cycle average of tags in use -system.cpu0.icache.total_refs 6737923 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 868472 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.758365 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 20312098000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.328414 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996735 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996735 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6737923 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6737923 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6737923 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6737923 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6737923 # number of overall hits -system.cpu0.icache.overall_hits::total 6737923 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 912101 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 912101 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 912101 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 912101 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 912101 # number of overall misses -system.cpu0.icache.overall_misses::total 912101 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12723011493 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12723011493 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12723011493 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12723011493 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12723011493 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12723011493 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7650024 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7650024 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7650024 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7650024 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7650024 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7650024 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119229 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.119229 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119229 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.119229 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119229 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.119229 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13949.125692 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13949.125692 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13949.125692 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13949.125692 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13949.125692 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13949.125692 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3314 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 438 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 144 # number of cycles access was blocked +system.cpu0.icache.replacements 728874 # number of replacements +system.cpu0.icache.tagsinuse 510.265304 # Cycle average of tags in use +system.cpu0.icache.total_refs 5890439 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 729383 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.075920 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 20962478000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.265304 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996612 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996612 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5890439 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5890439 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5890439 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5890439 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5890439 # number of overall hits +system.cpu0.icache.overall_hits::total 5890439 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 766860 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 766860 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 766860 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 766860 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 766860 # number of overall misses +system.cpu0.icache.overall_misses::total 766860 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10795349496 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10795349496 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10795349496 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10795349496 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10795349496 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10795349496 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6657299 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6657299 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6657299 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6657299 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6657299 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6657299 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.115191 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.115191 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.115191 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.115191 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.115191 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.115191 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14077.340709 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14077.340709 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14077.340709 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14077.340709 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14077.340709 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14077.340709 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2177 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 468 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 128 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.013889 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 438 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.007812 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 468 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43445 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 43445 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43445 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 43445 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43445 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 43445 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 868656 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 868656 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 868656 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 868656 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 868656 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 868656 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10487782996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10487782996 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10487782996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10487782996 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10487782996 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10487782996 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113549 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113549 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113549 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12073.574575 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12073.574575 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12073.574575 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37318 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 37318 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 37318 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 37318 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 37318 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 37318 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 729542 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 729542 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 729542 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 729542 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 729542 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 729542 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8901782997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8901782997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8901782997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8901782997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8901782997 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8901782997 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.109585 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.109585 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.109585 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.109585 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12201.878709 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12201.878709 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12201.878709 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12201.878709 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1274576 # number of replacements -system.cpu0.dcache.tagsinuse 505.658053 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10359284 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1275088 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.124368 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 21802000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.658053 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.987613 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.987613 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6368256 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6368256 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3633863 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3633863 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160621 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 160621 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 185111 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 185111 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10002119 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10002119 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10002119 # number of overall hits -system.cpu0.dcache.overall_hits::total 10002119 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1588144 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1588144 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1741180 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1741180 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20406 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20406 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2921 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2921 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3329324 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3329324 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3329324 # number of overall misses -system.cpu0.dcache.overall_misses::total 3329324 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34092049500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 34092049500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 69554473067 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 69554473067 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 288471000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 288471000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 21390500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 21390500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 103646522567 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 103646522567 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 103646522567 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 103646522567 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7956400 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7956400 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5375043 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5375043 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 181027 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 181027 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 188032 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 188032 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13331443 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13331443 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13331443 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13331443 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199606 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.199606 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323938 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323938 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112724 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112724 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015535 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015535 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249735 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.249735 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249735 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.249735 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21466.598432 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 21466.598432 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39946.744775 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39946.744775 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14136.577477 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14136.577477 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7323.005820 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7323.005820 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31131.401620 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31131.401620 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31131.401620 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31131.401620 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2393556 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1763 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 48538 # number of cycles access was blocked +system.cpu0.dcache.replacements 1051655 # number of replacements +system.cpu0.dcache.tagsinuse 479.291529 # Cycle average of tags in use +system.cpu0.dcache.total_refs 8945957 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1052167 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.502412 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 22123000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 479.291529 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.936116 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.936116 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5529733 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5529733 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3096724 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3096724 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 145068 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 145068 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 167974 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 167974 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8626457 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8626457 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8626457 # number of overall hits +system.cpu0.dcache.overall_hits::total 8626457 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1297164 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1297164 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1613226 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1613226 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 15668 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 15668 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 766 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 766 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2910390 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2910390 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2910390 # number of overall misses +system.cpu0.dcache.overall_misses::total 2910390 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 30009249500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 30009249500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 61556935480 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 61556935480 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 231982500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 231982500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4680500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4680500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 91566184980 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 91566184980 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 91566184980 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 91566184980 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6826897 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6826897 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4709950 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4709950 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160736 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 160736 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 168740 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 168740 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11536847 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11536847 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11536847 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11536847 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.190008 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.190008 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.342514 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.342514 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.097477 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.097477 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004540 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004540 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.252269 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.252269 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.252269 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.252269 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23134.506893 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 23134.506893 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38157.663886 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38157.663886 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14806.133521 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14806.133521 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6110.313316 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6110.313316 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31461.826415 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31461.826415 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31461.826415 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31461.826415 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2024468 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 671 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 45038 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 49.313033 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 251.857143 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.950220 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 95.857143 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 749955 # number of writebacks -system.cpu0.dcache.writebacks::total 749955 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 587926 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 587926 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1468148 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1468148 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4517 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4517 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2056074 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2056074 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2056074 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2056074 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1000218 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1000218 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 273032 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 273032 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15889 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15889 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2921 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2921 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1273250 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1273250 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1273250 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1273250 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21325955000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21325955000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10169026713 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10169026713 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 181062500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 181062500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15548500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15548500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31494981713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31494981713 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31494981713 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31494981713 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1455479000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1455479000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2128324998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2128324998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3583803998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3583803998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125712 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125712 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050796 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050796 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087771 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087771 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015535 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015535 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095507 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.095507 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095507 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.095507 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21321.306955 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21321.306955 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37244.816406 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37244.816406 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11395.462269 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.462269 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5323.005820 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5323.005820 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24735.897674 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24735.897674 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24735.897674 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24735.897674 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 554167 # number of writebacks +system.cpu0.dcache.writebacks::total 554167 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 497870 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 497870 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1365575 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1365575 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3772 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3772 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1863445 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1863445 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1863445 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1863445 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 799294 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 799294 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 247651 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 247651 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 11896 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11896 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 766 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 766 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1046945 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1046945 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1046945 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1046945 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19199342000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19199342000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8924614838 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8924614838 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 148344000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148344000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3148500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3148500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 28123956838 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 28123956838 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 28123956838 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 28123956838 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 991461500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 991461500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1668991999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1668991999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2660453499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2660453499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117080 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117080 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052580 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052580 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.074010 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.074010 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004540 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004540 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090748 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.090748 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090748 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.090748 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24020.375481 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24020.375481 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36037.063602 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36037.063602 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12470.073974 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12470.073974 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4110.313316 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4110.313316 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26862.878984 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26862.878984 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26862.878984 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26862.878984 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1193,35 +1193,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2617746 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2161338 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 77903 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1516620 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 873996 # Number of BTB hits +system.cpu1.branchPred.lookups 4327546 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3555815 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 137782 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2736457 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1529937 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.627883 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 182212 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 8242 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 55.909411 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 311519 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 14646 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1943067 # DTB read hits -system.cpu1.dtb.read_misses 10795 # DTB read misses -system.cpu1.dtb.read_acv 23 # DTB read access violations -system.cpu1.dtb.read_accesses 324453 # DTB read accesses -system.cpu1.dtb.write_hits 1254400 # DTB write hits -system.cpu1.dtb.write_misses 2201 # DTB write misses -system.cpu1.dtb.write_acv 63 # DTB write access violations -system.cpu1.dtb.write_accesses 132933 # DTB write accesses -system.cpu1.dtb.data_hits 3197467 # DTB hits -system.cpu1.dtb.data_misses 12996 # DTB misses -system.cpu1.dtb.data_acv 86 # DTB access violations -system.cpu1.dtb.data_accesses 457386 # DTB accesses -system.cpu1.itb.fetch_hits 434450 # ITB hits -system.cpu1.itb.fetch_misses 7705 # ITB misses -system.cpu1.itb.fetch_acv 232 # ITB acv -system.cpu1.itb.fetch_accesses 442155 # ITB accesses +system.cpu1.dtb.read_hits 3068448 # DTB read hits +system.cpu1.dtb.read_misses 13337 # DTB read misses +system.cpu1.dtb.read_acv 21 # DTB read access violations +system.cpu1.dtb.read_accesses 325420 # DTB read accesses +system.cpu1.dtb.write_hits 1915630 # DTB write hits +system.cpu1.dtb.write_misses 2521 # DTB write misses +system.cpu1.dtb.write_acv 68 # DTB write access violations +system.cpu1.dtb.write_accesses 132592 # DTB write accesses +system.cpu1.dtb.data_hits 4984078 # DTB hits +system.cpu1.dtb.data_misses 15858 # DTB misses +system.cpu1.dtb.data_acv 89 # DTB access violations +system.cpu1.dtb.data_accesses 458012 # DTB accesses +system.cpu1.itb.fetch_hits 498592 # ITB hits +system.cpu1.itb.fetch_misses 6957 # ITB misses +system.cpu1.itb.fetch_acv 210 # ITB acv +system.cpu1.itb.fetch_accesses 505549 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1234,508 +1234,508 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 16039611 # number of cpu cycles simulated +system.cpu1.numCycles 28341850 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6032367 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 12375417 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2617746 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1056208 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2219979 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 406574 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 6282819 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 27064 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 67109 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 53469 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1501296 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 52568 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14943285 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.828159 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.202626 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 9666058 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 20746660 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4327546 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1841456 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 3769607 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 667538 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 11516910 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 24752 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 65971 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 157862 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 2430728 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 90320 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 25638274 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.809207 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.171586 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 12723306 85.14% 85.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 143447 0.96% 86.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 238457 1.60% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 178791 1.20% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 308600 2.07% 90.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 118341 0.79% 91.75% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 133550 0.89% 92.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 199066 1.33% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 899727 6.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 21868667 85.30% 85.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 217825 0.85% 86.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 471767 1.84% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 290566 1.13% 89.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 572691 2.23% 91.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 192619 0.75% 92.11% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 225020 0.88% 92.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 283328 1.11% 94.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1515791 5.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14943285 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.163205 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.771553 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5967965 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6534138 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2076282 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 111928 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 252971 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 114663 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7593 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 12129871 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22496 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 252971 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 6175430 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 499012 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5393527 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1978606 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 643737 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 11250530 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 66 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 56207 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 157985 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 7407591 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 13449617 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 13309138 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 140479 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 6324692 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1082899 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 450684 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 43314 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1976964 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2055976 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1329039 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 193469 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 109268 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9879442 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 495628 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9611427 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 29957 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1443490 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 718060 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 356268 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14943285 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.643194 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.319140 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 25638274 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.152691 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.732015 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 9733408 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 11767392 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 3496252 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 218180 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 423041 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 197160 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 14107 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 20339380 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 42509 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 423041 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 10090973 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3436285 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 7189136 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 3265501 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1233336 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 19035683 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 265 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 302354 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 266371 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 12573410 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 22727510 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 22552449 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 175061 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 10671795 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1901615 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 598380 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 62207 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3655619 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 3246585 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 2021315 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 341799 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 191681 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 16730301 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 718132 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 16236732 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 38678 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2401085 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1178363 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 514161 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 25638274 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.633301 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.313801 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10722627 71.76% 71.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1934278 12.94% 84.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 829364 5.55% 90.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 551304 3.69% 93.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 470726 3.15% 97.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 216087 1.45% 98.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 139402 0.93% 99.47% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 71218 0.48% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 8279 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 18618463 72.62% 72.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 3106773 12.12% 84.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1368758 5.34% 90.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 986929 3.85% 93.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 856057 3.34% 97.26% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 349630 1.36% 98.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 219211 0.86% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 115612 0.45% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 16841 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14943285 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 25638274 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3634 1.84% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 107033 54.32% 56.16% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 86373 43.84% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 22162 7.89% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 144030 51.29% 59.18% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 114619 40.82% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5997328 62.40% 62.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16465 0.17% 62.61% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10793 0.11% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.74% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2032935 21.15% 83.89% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1277891 13.30% 97.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 270726 2.82% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3527 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 10692350 65.85% 65.87% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 24766 0.15% 66.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.03% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11484 0.07% 66.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 3204356 19.74% 85.84% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1945149 11.98% 97.82% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 353337 2.18% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9611427 # Type of FU issued -system.cpu1.iq.rate 0.599231 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 197040 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020501 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 34189984 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11721176 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 9344184 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 203152 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 99152 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 96176 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9699010 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 105931 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 93506 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 16236732 # Type of FU issued +system.cpu1.iq.rate 0.572889 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 280811 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.017295 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 58178646 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 19730507 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 15830008 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 252581 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 122599 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 119620 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 16382145 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 131871 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 151965 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 286352 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1028 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1836 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 129863 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 456957 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 998 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3692 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 187617 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 382 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 9210 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 5626 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 16438 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 252971 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 330484 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 40597 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10884350 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 145943 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2055976 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1329039 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 449000 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 33362 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2246 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1836 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 35752 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 100142 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 135894 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9521603 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1961135 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 89824 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 423041 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2638422 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 162147 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 18437863 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 211636 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 3246585 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 2021315 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 643129 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 60084 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2152 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3692 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 66784 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 149088 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 215872 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 16080551 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 3090638 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 156181 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 509280 # number of nop insts executed -system.cpu1.iew.exec_refs 3223669 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1421889 # Number of branches executed -system.cpu1.iew.exec_stores 1262534 # Number of stores executed -system.cpu1.iew.exec_rate 0.593631 # Inst execution rate -system.cpu1.iew.wb_sent 9469121 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 9440360 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4419848 # num instructions producing a value -system.cpu1.iew.wb_consumers 6207573 # num instructions consuming a value +system.cpu1.iew.exec_nop 989430 # number of nop insts executed +system.cpu1.iew.exec_refs 5015230 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2535241 # Number of branches executed +system.cpu1.iew.exec_stores 1924592 # Number of stores executed +system.cpu1.iew.exec_rate 0.567378 # Inst execution rate +system.cpu1.iew.wb_sent 15988482 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 15949628 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 7724743 # num instructions producing a value +system.cpu1.iew.wb_consumers 10881499 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.588565 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.712009 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.562759 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.709897 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1489613 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 139360 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 127942 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 14690314 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.634143 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.577922 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2575173 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 203971 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 201824 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 25215233 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.626683 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.561616 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 11205689 76.28% 76.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1626477 11.07% 87.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 606444 4.13% 91.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 368240 2.51% 93.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 264133 1.80% 95.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 104886 0.71% 96.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 108759 0.74% 97.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 107326 0.73% 97.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 298360 2.03% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 19361338 76.78% 76.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2499341 9.91% 86.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1261575 5.00% 91.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 645749 2.56% 94.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 410067 1.63% 95.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 193046 0.77% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 184525 0.73% 97.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 147171 0.58% 97.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 512421 2.03% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 14690314 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 9315763 # Number of instructions committed -system.cpu1.commit.committedOps 9315763 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 25215233 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 15801951 # Number of instructions committed +system.cpu1.commit.committedOps 15801951 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2968800 # Number of memory references committed -system.cpu1.commit.loads 1769624 # Number of loads committed -system.cpu1.commit.membars 44277 # Number of memory barriers committed -system.cpu1.commit.branches 1334383 # Number of branches committed -system.cpu1.commit.fp_insts 94889 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8635888 # Number of committed integer instructions. -system.cpu1.commit.function_calls 148923 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 298360 # number cycles where commit BW limit reached +system.cpu1.commit.refs 4623326 # Number of memory references committed +system.cpu1.commit.loads 2789628 # Number of loads committed +system.cpu1.commit.membars 68640 # Number of memory barriers committed +system.cpu1.commit.branches 2366242 # Number of branches committed +system.cpu1.commit.fp_insts 118314 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 14589318 # Number of committed integer instructions. +system.cpu1.commit.function_calls 250839 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 512421 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 25106022 # The number of ROB reads -system.cpu1.rob.rob_writes 21862282 # The number of ROB writes -system.cpu1.timesIdled 131003 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1096326 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3786825078 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8868192 # Number of Instructions Simulated -system.cpu1.committedOps 8868192 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 8868192 # Number of Instructions Simulated -system.cpu1.cpi 1.808668 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.808668 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.552893 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.552893 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 12288735 # number of integer regfile reads -system.cpu1.int_regfile_writes 6719305 # number of integer regfile writes -system.cpu1.fp_regfile_reads 52595 # number of floating regfile reads -system.cpu1.fp_regfile_writes 52295 # number of floating regfile writes -system.cpu1.misc_regfile_reads 519807 # number of misc regfile reads -system.cpu1.misc_regfile_writes 218837 # number of misc regfile writes -system.cpu1.icache.replacements 223384 # number of replacements -system.cpu1.icache.tagsinuse 470.911172 # Cycle average of tags in use -system.cpu1.icache.total_refs 1268764 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 223896 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.666756 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1876151234000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 470.911172 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.919748 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.919748 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1268764 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1268764 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1268764 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1268764 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1268764 # number of overall hits -system.cpu1.icache.overall_hits::total 1268764 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 232532 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 232532 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 232532 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 232532 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 232532 # number of overall misses -system.cpu1.icache.overall_misses::total 232532 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3191119498 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3191119498 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3191119498 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3191119498 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3191119498 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3191119498 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1501296 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1501296 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1501296 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1501296 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1501296 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1501296 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154888 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.154888 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154888 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.154888 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154888 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.154888 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13723.356347 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13723.356347 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13723.356347 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13723.356347 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13723.356347 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13723.356347 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 852 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 37.043478 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 42991260 # The number of ROB reads +system.cpu1.rob.rob_writes 37176651 # The number of ROB writes +system.cpu1.timesIdled 292999 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2703576 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3768655732 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 14927555 # Number of Instructions Simulated +system.cpu1.committedOps 14927555 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 14927555 # Number of Instructions Simulated +system.cpu1.cpi 1.898626 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.898626 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.526697 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.526697 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 20802804 # number of integer regfile reads +system.cpu1.int_regfile_writes 11409368 # number of integer regfile writes +system.cpu1.fp_regfile_reads 63889 # number of floating regfile reads +system.cpu1.fp_regfile_writes 64169 # number of floating regfile writes +system.cpu1.misc_regfile_reads 688257 # number of misc regfile reads +system.cpu1.misc_regfile_writes 294653 # number of misc regfile writes +system.cpu1.icache.replacements 359909 # number of replacements +system.cpu1.icache.tagsinuse 505.656535 # Cycle average of tags in use +system.cpu1.icache.total_refs 2054105 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 360421 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.699182 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 43308699500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 505.656535 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.987610 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.987610 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 2054105 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 2054105 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 2054105 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 2054105 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 2054105 # number of overall hits +system.cpu1.icache.overall_hits::total 2054105 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 376623 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 376623 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 376623 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 376623 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 376623 # number of overall misses +system.cpu1.icache.overall_misses::total 376623 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5258660997 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5258660997 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5258660997 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5258660997 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5258660997 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5258660997 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 2430728 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2430728 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 2430728 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 2430728 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 2430728 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 2430728 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154942 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.154942 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154942 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.154942 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154942 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.154942 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13962.665575 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13962.665575 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13962.665575 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13962.665575 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13962.665575 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13962.665575 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2479 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 1476 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 54 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 45.907407 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 1476 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8568 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 8568 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 8568 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 8568 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 8568 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 8568 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 223964 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 223964 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 223964 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 223964 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 223964 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 223964 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2651052998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2651052998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2651052998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2651052998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2651052998 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2651052998 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.149180 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.149180 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.149180 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11836.960395 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11836.960395 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11836.960395 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 16134 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 16134 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 16134 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 16134 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 16134 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 16134 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 360489 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 360489 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 360489 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 360489 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 360489 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 360489 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4342433998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4342433998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4342433998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4342433998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4342433998 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4342433998 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.148305 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.148305 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.148305 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.148305 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12045.954240 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12045.954240 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12045.954240 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12045.954240 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12045.954240 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12045.954240 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 107089 # number of replacements -system.cpu1.dcache.tagsinuse 492.773988 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2615920 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 107493 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 24.335724 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 38980492000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 492.773988 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.962449 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.962449 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1604976 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1604976 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 940707 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 940707 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 33481 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 33481 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32051 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 32051 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2545683 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2545683 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2545683 # number of overall hits -system.cpu1.dcache.overall_hits::total 2545683 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 206048 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 206048 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 217271 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 217271 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5237 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5237 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3060 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3060 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 423319 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 423319 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 423319 # number of overall misses -system.cpu1.dcache.overall_misses::total 423319 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3148302000 # 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number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1811024 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1811024 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1157978 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1157978 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 38718 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 38718 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35111 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 35111 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2969002 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2969002 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2969002 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2969002 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.113774 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.113774 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.187630 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.187630 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135260 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135260 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087152 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087152 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.142580 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.142580 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.142580 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.142580 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15279.459155 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15279.459155 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40782.120412 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 40782.120412 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10443.001719 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10443.001719 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7233.333333 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7233.333333 # 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Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.972223 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.972223 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2307913 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2307913 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1365825 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1365825 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47088 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 47088 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50932 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50932 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3673738 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3673738 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3673738 # number of overall hits +system.cpu1.dcache.overall_hits::total 3673738 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 542018 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 542018 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 408775 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 408775 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9102 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9102 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 780 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 780 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 950793 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 950793 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 950793 # number of overall misses +system.cpu1.dcache.overall_misses::total 950793 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8456828000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8456828000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13523509258 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 13523509258 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 132387000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 132387000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5554000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5554000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 21980337258 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 21980337258 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 21980337258 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 21980337258 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2849931 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2849931 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1774600 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1774600 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56190 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 56190 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 51712 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 51712 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4624531 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4624531 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4624531 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4624531 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.190186 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.190186 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.230348 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.230348 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.161986 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.161986 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.015084 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.015084 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.205598 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.205598 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.205598 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.205598 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15602.485526 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15602.485526 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33083.014514 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 33083.014514 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14544.825313 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14544.825313 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7120.512821 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7120.512821 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23117.899751 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23117.899751 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23117.899751 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23117.899751 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 393760 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3910 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 7994 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 86.716113 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 49.256943 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 70825 # number of writebacks -system.cpu1.dcache.writebacks::total 70825 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 127864 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 127864 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 178553 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 178553 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 567 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 567 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 306417 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 306417 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 306417 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 306417 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 78184 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 78184 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 38718 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 38718 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4670 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4670 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3058 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3058 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 116902 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 116902 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 116902 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 116902 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 956868500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 956868500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1322831987 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1322831987 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38016500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38016500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16018000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16018000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2279700487 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2279700487 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2279700487 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2279700487 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30982500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30982500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 645432500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 645432500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 676415000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 676415000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043171 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043171 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033436 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033436 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120616 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120616 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087095 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087095 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039374 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039374 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039374 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039374 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12238.674153 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12238.674153 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34165.814014 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34165.814014 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8140.578158 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.578158 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5238.064094 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5238.064094 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19500.953679 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19500.953679 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19500.953679 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19500.953679 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 289966 # number of writebacks +system.cpu1.dcache.writebacks::total 289966 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 235266 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 235266 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 338145 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 338145 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1764 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1764 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 573411 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 573411 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 573411 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 573411 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 306752 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 306752 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 70630 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 70630 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7338 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7338 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 780 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 780 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 377382 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 377382 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 377382 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 377382 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4029157000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4029157000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2036960738 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2036960738 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87414000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87414000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3994000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3994000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6066117738 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6066117738 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6066117738 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6066117738 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 491781000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 491781000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 942840000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 942840000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1434621000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1434621000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.107635 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.107635 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.039801 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.039801 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130593 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130593 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.015084 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.015084 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.081604 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.081604 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.081604 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.081604 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13134.900506 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13134.900506 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28839.880193 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28839.880193 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11912.510221 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11912.510221 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5120.512821 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5120.512821 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16074.210582 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16074.210582 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16074.210582 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16074.210582 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1744,32 +1744,32 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6541 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 182292 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 64399 40.43% 40.43% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 137 0.09% 40.52% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1928 1.21% 41.73% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 188 0.12% 41.85% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 92618 58.15% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 159270 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 63397 49.20% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 137 0.11% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1928 1.50% 50.80% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 188 0.15% 50.95% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 63212 49.05% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 128862 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1866521704000 98.15% 98.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63425000 0.00% 98.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 571234500 0.03% 98.18% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 91794500 0.00% 98.19% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 34470644500 1.81% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1901718802500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984441 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4837 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 159566 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 54412 39.60% 39.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.10% 39.69% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.40% 41.09% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.10% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 80931 58.90% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 137415 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 53531 49.06% 49.06% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.76% 50.94% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.01% 50.96% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 53515 49.04% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 109118 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1866933879000 98.32% 98.32% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 62852000 0.00% 98.32% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 558860500 0.03% 98.35% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8730000 0.00% 98.35% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 31246000500 1.65% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1898810322000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983809 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682502 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.809079 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.661242 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.794076 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed @@ -1801,60 +1801,60 @@ system.cpu0.kern.syscall::144 1 0.50% 99.01% # nu system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 202 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 291 0.17% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3482 2.08% 2.25% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.28% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::swpipl 152520 91.05% 93.34% # number of callpals executed -system.cpu0.kern.callpal::rdps 6170 3.68% 97.03% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal::rti 4499 2.69% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 333 0.20% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 167505 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7002 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1256 # number of protection mode switches +system.cpu0.kern.callpal::wripir 107 0.07% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2838 1.96% 2.03% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.07% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.07% # number of callpals executed +system.cpu0.kern.callpal::swpipl 131134 90.46% 92.54% # number of callpals executed +system.cpu0.kern.callpal::rdps 6127 4.23% 96.76% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.77% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.01% 96.77% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed +system.cpu0.kern.callpal::rti 4208 2.90% 99.68% # number of callpals executed +system.cpu0.kern.callpal::callsys 333 0.23% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 144957 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6180 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1255 -system.cpu0.kern.mode_good::user 1256 +system.cpu0.kern.mode_good::kernel 1257 +system.cpu0.kern.mode_good::user 1258 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.179235 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.203398 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.304069 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1899848666000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1870128500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.338129 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1896878389500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1931924500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3483 # number of times the context was actually changed +system.cpu0.kern.swap_context 2839 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2459 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 57520 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 17961 36.86% 36.86% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1928 3.96% 40.82% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 291 0.60% 41.41% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 28549 58.59% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 48729 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 17586 47.40% 47.40% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1928 5.20% 52.60% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 291 0.78% 53.38% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 17296 46.62% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 37101 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1876762048000 98.70% 98.70% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 532687000 0.03% 98.73% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 132052500 0.01% 98.74% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 24006771500 1.26% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1901433559000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.979121 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3835 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 77998 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27220 39.42% 39.42% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1923 2.78% 42.20% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 107 0.15% 42.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 39804 57.64% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69054 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26724 48.26% 48.26% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1923 3.47% 51.74% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 107 0.19% 51.93% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 26617 48.07% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 55371 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1869610475000 98.48% 98.48% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533425500 0.03% 98.51% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 50588500 0.00% 98.51% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 28306196500 1.49% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1898500685500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981778 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.605836 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.761374 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.668702 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.801851 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed @@ -1878,36 +1878,36 @@ system.cpu1.kern.syscall::132 3 2.42% 99.19% # nu system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 124 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 188 0.37% 0.37% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1118 2.21% 2.58% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.60% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed -system.cpu1.kern.callpal::swpipl 43429 85.72% 88.33% # number of callpals executed -system.cpu1.kern.callpal::rdps 2596 5.12% 93.45% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.45% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.46% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.46% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.47% # number of callpals executed -system.cpu1.kern.callpal::rti 3081 6.08% 99.55% # number of callpals executed -system.cpu1.kern.callpal::callsys 184 0.36% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1407 1.97% 2.00% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 2.01% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.02% # number of callpals executed +system.cpu1.kern.callpal::swpipl 64017 89.75% 91.76% # number of callpals executed +system.cpu1.kern.callpal::rdps 2632 3.69% 95.45% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 95.45% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 95.46% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 95.46% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 95.47% # number of callpals executed +system.cpu1.kern.callpal::rti 3006 4.21% 99.68% # number of callpals executed +system.cpu1.kern.callpal::callsys 184 0.26% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 50665 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1406 # number of protection mode switches +system.cpu1.kern.callpal::total 71331 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1876 # number of protection mode switches system.cpu1.kern.mode_switch::user 488 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2430 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 704 +system.cpu1.kern.mode_switch::idle 2061 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 557 system.cpu1.kern.mode_good::user 488 -system.cpu1.kern.mode_good::idle 216 -system.cpu1.kern.mode_switch_good::kernel 0.500711 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 69 +system.cpu1.kern.mode_switch_good::kernel 0.296908 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.088889 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.325624 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4780653500 0.25% 0.25% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 828450500 0.04% 0.29% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1895813783000 99.71% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1119 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.033479 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.251751 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 39690497500 2.09% 2.09% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 850597000 0.04% 2.14% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1857949530000 97.86% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1408 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 2f976aa78..0fbfca2a6 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.854344 # Number of seconds simulated -sim_ticks 1854344296500 # Number of ticks simulated -final_tick 1854344296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.854310 # Number of seconds simulated +sim_ticks 1854309852000 # Number of ticks simulated +final_tick 1854309852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90928 # Simulator instruction rate (inst/s) -host_op_rate 90928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3182808238 # Simulator tick rate (ticks/s) -host_mem_usage 379332 # Number of bytes of host memory used -host_seconds 582.61 # Real time elapsed on the host -sim_insts 52976017 # Number of instructions simulated -sim_ops 52976017 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 964864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879424 # Number of bytes read from this memory +host_inst_rate 117975 # Simulator instruction rate (inst/s) +host_op_rate 117975 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4129044881 # Simulator tick rate (ticks/s) +host_mem_usage 335500 # Number of bytes of host memory used +host_seconds 449.09 # Real time elapsed on the host +sim_insts 52981417 # Number of instructions simulated +sim_ops 52981417 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 964672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24877888 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28496576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 964864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 964864 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 28494848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 964672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 964672 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7516416 # Number of bytes written to this memory system.physmem.bytes_written::total 7516416 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15076 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388741 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 15073 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388717 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445259 # Number of read requests responded to by this memory +system.physmem.num_reads::total 445232 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 117444 # Number of write requests responded to by this memory system.physmem.num_writes::total 117444 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13416831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1430310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15367468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520326 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520326 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4053409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4053409 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4053409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13416831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1430310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19420877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445259 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 520232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13416252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1430337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15366821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 520232 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520232 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4053484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4053484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4053484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 520232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13416252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1430337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19420306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445232 # Total number of read requests seen system.physmem.writeReqs 117444 # Total number of write requests seen -system.physmem.cpureqs 564803 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28496576 # Total number of bytes read from memory +system.physmem.cpureqs 565193 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28494848 # Total number of bytes read from memory system.physmem.bytesWritten 7516416 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28496576 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 28494848 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7516416 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 63 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 176 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28168 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27749 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27864 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27384 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28323 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28119 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27841 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27856 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27503 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27630 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27839 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27855 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27734 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27895 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7646 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7290 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6889 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7790 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7556 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7291 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7179 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7418 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7047 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7168 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7402 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7478 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7343 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7210 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7328 # Track writes on a per bank basis +system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 171 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28112 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27866 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27716 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27523 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27754 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27723 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28230 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27914 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28000 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27799 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27706 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27921 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27830 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27718 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7631 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7398 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7277 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7173 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7281 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7238 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7147 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7771 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7465 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7554 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7212 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7327 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7265 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7201 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1365 # Number of times wr buffer was full causing retry -system.physmem.totGap 1854338900000 # Total gap between requests +system.physmem.numWrRetry 1787 # Number of times wr buffer was full causing retry +system.physmem.totGap 1854304427000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445259 # Categorize read packet sizes +system.physmem.readPktSize::6 445232 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -97,7 +97,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 118809 # categorize write packet sizes +system.physmem.writePktSize::6 119231 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -106,32 +106,32 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 176 # categorize neither packet sizes +system.physmem.neitherpktsize::6 171 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 331910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 65137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1645 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 323360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2640 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 910 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 761 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -142,15 +142,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5096 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see @@ -165,46 +165,46 @@ system.physmem.wrQLenPdf::19 5106 # Wh system.physmem.wrQLenPdf::20 5106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5106 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 6228802493 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13434068493 # Sum of mem lat for all requests -system.physmem.totBusLat 1780784000 # Total cycles spent in databus access -system.physmem.totBankLat 5424482000 # Total cycles spent in bank access -system.physmem.avgQLat 13991.15 # Average queueing delay per request -system.physmem.avgBankLat 12184.48 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30175.63 # Average memory access latency +system.physmem.totQLat 7898633503 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15636428503 # Sum of mem lat for all requests +system.physmem.totBusLat 2225860000 # Total cycles spent in databus access +system.physmem.totBankLat 5511935000 # Total cycles spent in bank access +system.physmem.avgQLat 17742.88 # Average queueing delay per request +system.physmem.avgBankLat 12381.59 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 35124.47 # Average memory access latency system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 11.37 # Average write queue length over time -system.physmem.readRowHits 425317 # Number of row buffer hits during reads -system.physmem.writeRowHits 76610 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.23 # Row buffer hit rate for writes -system.physmem.avgGap 3295413.21 # Average gap between requests +system.physmem.avgWrQLen 10.74 # Average write queue length over time +system.physmem.readRowHits 417598 # Number of row buffer hits during reads +system.physmem.writeRowHits 91555 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.96 # Row buffer hit rate for writes +system.physmem.avgGap 3295510.08 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.265367 # Cycle average of tags in use +system.iocache.tagsinuse 1.265033 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1704469917000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.265367 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079085 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079085 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1704476002000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.265033 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079065 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079065 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -215,12 +215,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9519862806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9519862806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9540790804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9540790804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9540790804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9540790804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10574791806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10574791806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10595719804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10595719804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10595719804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10595719804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -239,17 +239,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229107.210387 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 229107.210387 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 228658.856896 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228658.856896 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 228658.856896 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228658.856896 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 189620 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254495.374615 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 254495.374615 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 253941.756836 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 253941.756836 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 253941.756836 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 253941.756836 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 280489 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 22696 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27002 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.354776 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.387712 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -263,14 +263,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7357096000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7357096000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7369027000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7369027000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7369027000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7369027000 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8412803020 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8412803020 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8424734270 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8424734270 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8424734270 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8424734270 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -279,14 +279,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177057.566423 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 177057.566423 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176609.394847 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176609.394847 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176609.394847 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176609.394847 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202464.454659 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 202464.454659 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 201910.947154 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 201910.947154 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 201910.947154 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 201910.947154 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -300,35 +300,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13851594 # Number of BP lookups -system.cpu.branchPred.condPredicted 11614390 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 401305 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9533712 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5819078 # Number of BTB hits +system.cpu.branchPred.lookups 13854519 # Number of BP lookups +system.cpu.branchPred.condPredicted 11622006 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 399782 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9584331 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5815567 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.036855 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 909714 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39020 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 60.677861 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 905443 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 39042 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9948747 # DTB read hits -system.cpu.dtb.read_misses 41658 # DTB read misses -system.cpu.dtb.read_acv 544 # DTB read access violations -system.cpu.dtb.read_accesses 942034 # DTB read accesses -system.cpu.dtb.write_hits 6596243 # DTB write hits -system.cpu.dtb.write_misses 10259 # DTB write misses -system.cpu.dtb.write_acv 405 # DTB write access violations -system.cpu.dtb.write_accesses 337916 # DTB write accesses -system.cpu.dtb.data_hits 16544990 # DTB hits -system.cpu.dtb.data_misses 51917 # DTB misses -system.cpu.dtb.data_acv 949 # DTB access violations -system.cpu.dtb.data_accesses 1279950 # DTB accesses -system.cpu.itb.fetch_hits 1308175 # ITB hits -system.cpu.itb.fetch_misses 37074 # ITB misses -system.cpu.itb.fetch_acv 1064 # ITB acv -system.cpu.itb.fetch_accesses 1345249 # ITB accesses +system.cpu.dtb.read_hits 9921013 # DTB read hits +system.cpu.dtb.read_misses 41705 # DTB read misses +system.cpu.dtb.read_acv 547 # DTB read access violations +system.cpu.dtb.read_accesses 941529 # DTB read accesses +system.cpu.dtb.write_hits 6598119 # DTB write hits +system.cpu.dtb.write_misses 10489 # DTB write misses +system.cpu.dtb.write_acv 411 # DTB write access violations +system.cpu.dtb.write_accesses 338424 # DTB write accesses +system.cpu.dtb.data_hits 16519132 # DTB hits +system.cpu.dtb.data_misses 52194 # DTB misses +system.cpu.dtb.data_acv 958 # DTB access violations +system.cpu.dtb.data_accesses 1279953 # DTB accesses +system.cpu.itb.fetch_hits 1307587 # ITB hits +system.cpu.itb.fetch_misses 36909 # ITB misses +system.cpu.itb.fetch_acv 1032 # ITB acv +system.cpu.itb.fetch_accesses 1344496 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -341,269 +341,269 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 108725026 # number of cpu cycles simulated +system.cpu.numCycles 109625107 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28116472 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70876145 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13851594 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6728792 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13285208 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2019522 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37381794 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 254614 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 318469 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 142 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8594512 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 267109 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80688804 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.878389 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.221787 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28053642 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70690468 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13854519 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6721010 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13247907 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1985368 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37409434 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32200 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 254032 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 293409 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 622 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8552479 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 266219 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80576938 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.877304 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.221000 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67403596 83.54% 83.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 853020 1.06% 84.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1704381 2.11% 86.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 825297 1.02% 87.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2770281 3.43% 91.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 565024 0.70% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 647860 0.80% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1009692 1.25% 93.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4909653 6.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67329031 83.56% 83.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 853166 1.06% 84.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1699610 2.11% 86.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 825917 1.03% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2751267 3.41% 91.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 561372 0.70% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 646563 0.80% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1011071 1.25% 93.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4898941 6.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80688804 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.127400 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.651884 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29267449 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37052866 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12136986 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 973710 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1257792 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 584936 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42720 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69563521 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129851 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1257792 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30404358 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13652369 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19747652 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11366309 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4260322 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65705710 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6891 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 503348 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1491459 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43870153 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79781182 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79301924 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479258 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38177024 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5693121 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1683221 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 240085 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12184382 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10464940 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6914709 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1324795 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 859458 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58224316 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2050276 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56824991 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 109552 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6935340 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3625371 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1389407 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80688804 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.704249 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.364971 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80576938 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126381 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.644838 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29188607 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37070199 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12111886 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962831 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1243414 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 585279 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42689 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69390201 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129780 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1243414 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30310150 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13624817 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19789639 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11346848 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4262068 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65638780 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6929 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 510249 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1482252 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43832025 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79671797 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79192798 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 478999 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38181176 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5650841 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682596 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239958 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12134086 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10437264 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6898844 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1303944 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 867300 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58187512 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2050080 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56823763 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 104138 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6892850 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3517048 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1389102 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80576938 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.705211 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.366405 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56018871 69.43% 69.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10823549 13.41% 82.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5172467 6.41% 89.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3386571 4.20% 93.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2641337 3.27% 96.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1466438 1.82% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 753039 0.93% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 331233 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 95299 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55928630 69.41% 69.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10806018 13.41% 82.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5163609 6.41% 89.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3379495 4.19% 93.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2652407 3.29% 96.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1461056 1.81% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 758797 0.94% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 331056 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 95870 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80688804 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80576938 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 89852 11.44% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 373396 47.53% 58.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 322395 41.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 90990 11.53% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 373752 47.37% 58.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 324325 41.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38724808 68.15% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61690 0.11% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10379587 18.27% 86.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6673501 11.74% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 948876 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38746520 68.19% 68.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61714 0.11% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10353275 18.22% 86.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6676641 11.75% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949084 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56824991 # Type of FU issued -system.cpu.iq.rate 0.522649 # Inst issue rate -system.cpu.iq.fu_busy_cnt 785643 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013826 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194541335 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66886966 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55559556 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692645 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336736 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327839 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57241937 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361411 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 597577 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56823763 # Type of FU issued +system.cpu.iq.rate 0.518346 # Inst issue rate +system.cpu.iq.fu_busy_cnt 789067 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013886 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194424766 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66808135 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55585961 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692902 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336093 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327887 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57243591 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361953 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 600271 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1373561 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3601 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14111 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 537300 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1344993 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3536 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14132 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 520971 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17953 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 206148 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17952 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 173575 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1257792 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9964029 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 681966 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63803743 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 689880 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10464940 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6914709 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1805552 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 511141 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18669 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14111 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 204181 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411284 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 615465 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56359720 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10018596 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 465270 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1243414 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9953615 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 683685 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63765437 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 675848 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10437264 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6898844 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1805870 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 511832 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18204 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14132 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 202521 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411600 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 614121 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56355375 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9990908 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 468387 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3529151 # number of nop insts executed -system.cpu.iew.exec_refs 16640307 # number of memory reference insts executed -system.cpu.iew.exec_branches 8921025 # Number of branches executed -system.cpu.iew.exec_stores 6621711 # Number of stores executed -system.cpu.iew.exec_rate 0.518369 # Inst execution rate -system.cpu.iew.wb_sent 56002392 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55887395 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27763328 # num instructions producing a value -system.cpu.iew.wb_consumers 37600496 # num instructions consuming a value +system.cpu.iew.exec_nop 3527845 # number of nop insts executed +system.cpu.iew.exec_refs 16614745 # number of memory reference insts executed +system.cpu.iew.exec_branches 8928138 # Number of branches executed +system.cpu.iew.exec_stores 6623837 # Number of stores executed +system.cpu.iew.exec_rate 0.514074 # Inst execution rate +system.cpu.iew.wb_sent 56029038 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55913848 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27775021 # num instructions producing a value +system.cpu.iew.wb_consumers 37616621 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.514025 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738377 # average fanout of values written-back +system.cpu.iew.wb_rate 0.510046 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738371 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7517612 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660869 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 569940 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79431012 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.707112 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.636757 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7476360 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660978 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 568527 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79333524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.708051 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.637595 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58662505 73.85% 73.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8598581 10.83% 84.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4616252 5.81% 90.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2527219 3.18% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1515396 1.91% 95.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 608578 0.77% 96.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 519366 0.65% 97.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 531746 0.67% 97.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1851369 2.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58563645 73.82% 73.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8604221 10.85% 84.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4603933 5.80% 90.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2533514 3.19% 93.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1516762 1.91% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 607132 0.77% 96.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 522001 0.66% 97.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 533698 0.67% 97.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1848618 2.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79431012 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56166586 # Number of instructions committed -system.cpu.commit.committedOps 56166586 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79333524 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56172173 # Number of instructions committed +system.cpu.commit.committedOps 56172173 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15468788 # Number of memory references committed -system.cpu.commit.loads 9091379 # Number of loads committed -system.cpu.commit.membars 226331 # Number of memory barriers committed -system.cpu.commit.branches 8439881 # Number of branches committed +system.cpu.commit.refs 15470144 # Number of memory references committed +system.cpu.commit.loads 9092271 # Number of loads committed +system.cpu.commit.membars 226349 # Number of memory barriers committed +system.cpu.commit.branches 8440686 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52016583 # Number of committed integer instructions. -system.cpu.commit.function_calls 740455 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1851369 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52021801 # Number of committed integer instructions. +system.cpu.commit.function_calls 740555 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1848618 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141014350 # The number of ROB reads -system.cpu.rob.rob_writes 128628080 # The number of ROB writes -system.cpu.timesIdled 1177475 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 28036222 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599957129 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52976017 # Number of Instructions Simulated -system.cpu.committedOps 52976017 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52976017 # Number of Instructions Simulated -system.cpu.cpi 2.052344 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.052344 # CPI: Total CPI of All Threads -system.cpu.ipc 0.487248 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.487248 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73894396 # number of integer regfile reads -system.cpu.int_regfile_writes 40308039 # number of integer regfile writes -system.cpu.fp_regfile_reads 165978 # number of floating regfile reads -system.cpu.fp_regfile_writes 167424 # number of floating regfile writes -system.cpu.misc_regfile_reads 1987130 # number of misc regfile reads -system.cpu.misc_regfile_writes 938828 # number of misc regfile writes +system.cpu.rob.rob_reads 140883934 # The number of ROB reads +system.cpu.rob.rob_writes 128542305 # The number of ROB writes +system.cpu.timesIdled 1179238 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29048169 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598988155 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52981417 # Number of Instructions Simulated +system.cpu.committedOps 52981417 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52981417 # Number of Instructions Simulated +system.cpu.cpi 2.069124 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.069124 # CPI: Total CPI of All Threads +system.cpu.ipc 0.483296 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.483296 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73895852 # number of integer regfile reads +system.cpu.int_regfile_writes 40324169 # number of integer regfile writes +system.cpu.fp_regfile_reads 166027 # number of floating regfile reads +system.cpu.fp_regfile_writes 167433 # number of floating regfile writes +system.cpu.misc_regfile_reads 1987804 # number of misc regfile reads +system.cpu.misc_regfile_writes 938984 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -635,189 +635,189 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1010112 # number of replacements -system.cpu.icache.tagsinuse 510.299453 # Cycle average of tags in use -system.cpu.icache.total_refs 7527432 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1010620 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.448331 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20108875000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.299453 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996679 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996679 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7527433 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7527433 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7527433 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7527433 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7527433 # number of overall hits -system.cpu.icache.overall_hits::total 7527433 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1067079 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1067079 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1067079 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1067079 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1067079 # number of overall misses -system.cpu.icache.overall_misses::total 1067079 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14519095993 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14519095993 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14519095993 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14519095993 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14519095993 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14519095993 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8594512 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8594512 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8594512 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8594512 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8594512 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8594512 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124158 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124158 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124158 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124158 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124158 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124158 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13606.392772 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13606.392772 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13606.392772 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13606.392772 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13606.392772 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13606.392772 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4279 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 166 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 25.777108 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14679368493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14679368493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8552478 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8552478 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8552478 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8552478 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8552478 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8552478 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124588 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124588 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124588 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124588 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124588 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124588 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13776.498135 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13776.498135 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13776.498135 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13776.498135 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13776.498135 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13776.498135 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6928 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 616 # 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number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010840 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1010840 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1010840 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1010840 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1010840 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1010840 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11925850497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11925850497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11925850497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11925850497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11925850497 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34312.355755 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14500.885714 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14500.885714 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54431.134810 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54431.134810 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56529.079674 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39419.373920 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40057.322348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56529.079674 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39419.373920 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40057.322348 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -899,161 +899,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1400546 # number of replacements -system.cpu.dcache.tagsinuse 511.995190 # Cycle average of tags in use -system.cpu.dcache.total_refs 11813976 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1401058 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.432182 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21532000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.995190 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1401345 # number of replacements +system.cpu.dcache.tagsinuse 511.995159 # Cycle average of tags in use +system.cpu.dcache.total_refs 11814052 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1401857 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.427430 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21807000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.995159 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999991 # 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miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316042 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316042 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108978 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108978 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247141 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247141 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247141 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247141 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19048.951425 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19048.951425 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33610.193460 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33610.193460 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13445.360236 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13445.360236 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27944.519378 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27944.519378 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27944.519378 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27944.519378 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2603227 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 567 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 95613 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26600.712715 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26600.712715 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26600.712715 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26600.712715 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2209173 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1658 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 95967 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.226706 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 81 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 23.020132 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 236.857143 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840422 # number of writebacks -system.cpu.dcache.writebacks::total 840422 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717194 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 717194 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642682 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1642682 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5172 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5172 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2359876 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2359876 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2359876 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2359876 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083393 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083393 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300315 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300315 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17494 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17494 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1383708 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1383708 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1383708 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1383708 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21171794000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21171794000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10766258774 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10766258774 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199318000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199318000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31938052774 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31938052774 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31938052774 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31938052774 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423872500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423872500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997246998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997246998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421119498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421119498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120263 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120263 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083806 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083806 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091299 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091299 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091299 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091299 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19542.118142 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19542.118142 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35849.886865 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35849.886865 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11393.506345 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11393.506345 # average LoadLockedReq mshr miss latency +system.cpu.dcache.writebacks::writebacks 840942 # number of writebacks +system.cpu.dcache.writebacks::total 840942 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 719404 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 719404 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642459 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1642459 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5206 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5206 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2361863 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2361863 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2361863 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2361863 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083996 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083996 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300459 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300459 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17543 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17543 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384455 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384455 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384455 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384455 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21792492000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21792492000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9914016773 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9914016773 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199792500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199792500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31706508773 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31706508773 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31706508773 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31706508773 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423893000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423893000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997872998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997872998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421765998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421765998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120297 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120297 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048874 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048874 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084039 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084039 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091331 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091331 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091331 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091331 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20103.849092 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20103.849092 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32996.238332 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32996.238332 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11388.730548 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11388.730548 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23081.497523 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23081.497523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23081.497523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23081.497523 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22901.798017 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22901.798017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22901.798017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22901.798017 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1062,28 +1062,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 210969 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74649 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211023 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74671 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105543 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182201 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73282 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182254 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73304 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73282 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148573 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818511438500 98.07% 98.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 63990000 0.00% 98.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 557700000 0.03% 98.10% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 35210339500 1.90% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1854343468000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981688 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73304 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817865196000 98.03% 98.03% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 63825500 0.00% 98.04% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 556558000 0.03% 98.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 35823437500 1.93% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1854309017000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694333 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815435 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694344 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815444 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1122,29 +1122,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175088 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175139 91.23% 93.44% # number of callpals executed +system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191930 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.callpal::total 191983 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1741 +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326778 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326210 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394590 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29685190500 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2663206500 0.14% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1821995063000 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.394052 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29463172000 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2708574500 0.15% 1.73% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1822137262500 98.27% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index a2c647b2a..97e7b92d5 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841687 # Number of seconds simulated -sim_ticks 1841687115500 # Number of ticks simulated -final_tick 1841687115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841686 # Number of seconds simulated +sim_ticks 1841685645500 # Number of ticks simulated +final_tick 1841685645500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 216690 # Simulator instruction rate (inst/s) -host_op_rate 216690 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5785819991 # Simulator tick rate (ticks/s) -host_mem_usage 360768 # Number of bytes of host memory used -host_seconds 318.31 # Real time elapsed on the host -sim_insts 68974794 # Number of instructions simulated -sim_ops 68974794 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 474496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19299136 # Number of bytes read from this memory +host_inst_rate 340884 # Simulator instruction rate (inst/s) +host_op_rate 340884 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9045969324 # Simulator tick rate (ticks/s) +host_mem_usage 315876 # Number of bytes of host memory used +host_seconds 203.59 # Real time elapsed on the host +sim_insts 69401254 # Number of instructions simulated +sim_ops 69401254 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 474368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19389440 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 150016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2831040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 294592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2739200 # Number of bytes read from this memory -system.physmem.bytes_read::total 28440768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 474496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 150016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 294592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 919104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7474752 # Number of bytes written to this memory -system.physmem.bytes_written::total 7474752 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7414 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 301549 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 150272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2812736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 293952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2665600 # Number of bytes read from this memory +system.physmem.bytes_read::total 28438656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 474368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 150272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 293952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 918592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7476160 # Number of bytes written to this memory +system.physmem.bytes_written::total 7476160 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7412 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 302960 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2344 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 44235 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4603 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 42800 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444387 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116793 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116793 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 257642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10479053 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1440140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 81456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1537199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 159958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1487332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15442779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 257642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 81456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 159958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 499055 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4058644 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4058644 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4058644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 257642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10479053 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1440140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 81456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1537199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 159958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1487332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19501423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 111257 # Total number of read requests seen -system.physmem.writeReqs 46272 # Total number of write requests seen -system.physmem.cpureqs 157922 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 7120448 # Total number of bytes read from memory -system.physmem.bytesWritten 2961408 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 7120448 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2961408 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 8 # Number of read reqs serviced by write Q +system.physmem.num_reads::cpu1.inst 2348 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 43949 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4593 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41650 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444354 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116815 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116815 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 257573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10528094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1440142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 81595 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1527262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 159610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1447370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15441645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 257573 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 81595 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 159610 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498778 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4059412 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4059412 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4059412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 257573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10528094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1440142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 81595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1527262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 159610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1447370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19501057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 109303 # Total number of read requests seen +system.physmem.writeReqs 45531 # Total number of write requests seen +system.physmem.cpureqs 156037 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 6995392 # Total number of bytes read from memory +system.physmem.bytesWritten 2913984 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 6995392 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2913984 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 6 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 41 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 7200 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6995 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6907 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6539 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7006 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 7093 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 7124 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7176 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 6877 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6675 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 6909 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6929 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 7088 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 7137 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6752 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6842 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 3139 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2979 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2910 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2542 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 3003 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 2801 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2642 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 2700 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2850 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 3184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 3157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2742 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2711 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 6941 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6714 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6576 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6492 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 6845 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 6834 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6769 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 6799 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7016 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6828 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7161 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6927 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 6799 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6925 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6890 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6781 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 2987 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2793 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2679 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2608 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2843 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 2755 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2723 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2826 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3041 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2937 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 3162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2868 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 2817 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2876 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2850 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2766 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 191 # Number of times wr buffer was full causing retry -system.physmem.totGap 1840675056500 # Total gap between requests +system.physmem.numWrRetry 1002 # Number of times wr buffer was full causing retry +system.physmem.totGap 1840673558000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 111257 # Categorize read packet sizes +system.physmem.readPktSize::6 109303 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -117,7 +117,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 46463 # categorize write packet sizes +system.physmem.writePktSize::6 46533 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -129,27 +129,27 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 41 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 82762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 747 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 662 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 742 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 511 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 80133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1099 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1052 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -162,243 +162,239 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 2012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 2011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 2007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 2006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 2005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 2003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1656369284 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 3548083284 # Sum of mem lat for all requests -system.physmem.totBusLat 444996000 # Total cycles spent in databus access -system.physmem.totBankLat 1446718000 # Total cycles spent in bank access -system.physmem.avgQLat 14888.85 # Average queueing delay per request -system.physmem.avgBankLat 13004.32 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31893.17 # Average memory access latency -system.physmem.avgRdBW 3.87 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.61 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.87 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.61 # 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Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.078485 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.078485 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1693876367000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.255467 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.078467 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.078467 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -525,14 +521,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # 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miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 53052.011561 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 95029.078961 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 95029.078961 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 94855.033841 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 94855.033841 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 94855.033841 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 94855.033841 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 78872 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 60682.069364 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 60682.069364 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103976.605314 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 103976.605314 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 103797.097711 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 103797.097711 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 103797.097711 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 103797.097711 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 116360 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9708 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11123 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.124433 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.461207 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -569,36 +565,36 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 17280 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 17280 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 17349 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 17349 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 17349 # 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number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3454881655 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.415794 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.415794 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 81000 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176461.156192 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176461.156192 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176081.490518 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176081.490518 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176081.490518 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176081.490518 # average overall mshr miss latency +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.403543 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.403523 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 100134.043478 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 100134.043478 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 205628.125358 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 205628.125358 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205195.798242 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 205195.798242 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205195.798242 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 205195.798242 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -616,22 +612,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4860289 # DTB read hits -system.cpu0.dtb.read_misses 5912 # DTB read misses -system.cpu0.dtb.read_acv 109 # DTB read access violations -system.cpu0.dtb.read_accesses 426830 # DTB read accesses -system.cpu0.dtb.write_hits 3490049 # DTB write hits -system.cpu0.dtb.write_misses 657 # DTB write misses -system.cpu0.dtb.write_acv 81 # DTB write access violations -system.cpu0.dtb.write_accesses 163148 # DTB write accesses -system.cpu0.dtb.data_hits 8350338 # DTB hits -system.cpu0.dtb.data_misses 6569 # DTB misses -system.cpu0.dtb.data_acv 190 # DTB access violations -system.cpu0.dtb.data_accesses 589978 # DTB accesses -system.cpu0.itb.fetch_hits 2736650 # ITB hits -system.cpu0.itb.fetch_misses 2973 # ITB misses -system.cpu0.itb.fetch_acv 97 # ITB acv -system.cpu0.itb.fetch_accesses 2739623 # ITB accesses +system.cpu0.dtb.read_hits 4870224 # DTB read hits +system.cpu0.dtb.read_misses 6004 # DTB read misses +system.cpu0.dtb.read_acv 119 # DTB read access violations +system.cpu0.dtb.read_accesses 427226 # DTB read accesses +system.cpu0.dtb.write_hits 3495920 # DTB write hits +system.cpu0.dtb.write_misses 662 # DTB write misses +system.cpu0.dtb.write_acv 82 # DTB write access violations +system.cpu0.dtb.write_accesses 162893 # DTB write accesses +system.cpu0.dtb.data_hits 8366144 # DTB hits +system.cpu0.dtb.data_misses 6666 # DTB misses +system.cpu0.dtb.data_acv 201 # DTB access violations +system.cpu0.dtb.data_accesses 590119 # DTB accesses +system.cpu0.itb.fetch_hits 2742252 # ITB hits +system.cpu0.itb.fetch_misses 2999 # ITB misses +system.cpu0.itb.fetch_acv 100 # ITB acv +system.cpu0.itb.fetch_accesses 2745251 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -644,51 +640,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928580994 # number of cpu cycles simulated +system.cpu0.numCycles 928524557 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32061485 # Number of instructions committed -system.cpu0.committedOps 32061485 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 29946926 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 167785 # Number of float alu accesses -system.cpu0.num_func_calls 806855 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4176537 # number of instructions that are conditional controls -system.cpu0.num_int_insts 29946926 # number of integer instructions -system.cpu0.num_fp_insts 167785 # number of float instructions -system.cpu0.num_int_register_reads 41669823 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21912533 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 86645 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 88213 # number of times the floating registers were written -system.cpu0.num_mem_refs 8379762 # number of memory refs -system.cpu0.num_load_insts 4881104 # Number of load instructions -system.cpu0.num_store_insts 3498658 # Number of store instructions -system.cpu0.num_idle_cycles 214035268696.310638 # Number of idle cycles -system.cpu0.num_busy_cycles -213106687702.310638 # Number of busy cycles -system.cpu0.not_idle_fraction -229.497146 # Percentage of non-idle cycles -system.cpu0.idle_fraction 230.497146 # Percentage of idle cycles +system.cpu0.committedInsts 32346409 # Number of instructions committed +system.cpu0.committedOps 32346409 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 30227601 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 167714 # Number of float alu accesses +system.cpu0.num_func_calls 807221 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4255838 # number of instructions that are conditional controls +system.cpu0.num_int_insts 30227601 # number of integer instructions +system.cpu0.num_fp_insts 167714 # number of float instructions +system.cpu0.num_int_register_reads 42120333 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22107858 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 86620 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 88185 # number of times the floating registers were written +system.cpu0.num_mem_refs 8395831 # number of memory refs +system.cpu0.num_load_insts 4891260 # Number of load instructions +system.cpu0.num_store_insts 3504571 # Number of store instructions +system.cpu0.num_idle_cycles 213109834303.356140 # Number of idle cycles +system.cpu0.num_busy_cycles -212181309746.356140 # Number of busy cycles +system.cpu0.not_idle_fraction -228.514484 # Percentage of non-idle cycles +system.cpu0.idle_fraction 229.514484 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6422 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211380 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74799 40.97% 40.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 205 0.11% 41.08% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211363 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74796 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105691 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182573 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73432 49.30% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 205 0.14% 49.44% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 105684 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182561 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73429 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73433 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148948 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818622166500 98.75% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39746000 0.00% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 363817000 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22660629500 1.23% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841686359000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 73429 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148939 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818585880000 98.75% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39023000 0.00% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 363355500 0.02% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22696630500 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841684889000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694790 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815827 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694798 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815831 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -724,33 +720,33 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175314 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175304 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192228 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches +system.cpu0.kern.callpal::total 192218 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2095 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1908 system.cpu0.kern.mode_good::user 1738 system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322188 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29768907500 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2544697000 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809372751000 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4177 # number of times the context was actually changed +system.cpu0.kern.mode_ticks::kernel 29741942000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2557109000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809385834500 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -782,372 +778,356 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 953436 # number of replacements -system.cpu0.icache.tagsinuse 511.198067 # Cycle average of tags in use -system.cpu0.icache.total_refs 41560742 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 953947 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 43.567139 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 10234504000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 256.477356 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 79.519770 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 175.200941 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.500932 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.155312 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.342189 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998434 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 31547031 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7721485 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2292226 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 41560742 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31547031 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7721485 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2292226 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 41560742 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31547031 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7721485 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2292226 # number of overall hits -system.cpu0.icache.overall_hits::total 41560742 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 521213 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 129218 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 320460 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 970891 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 521213 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 129218 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 320460 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 970891 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 521213 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 129218 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 320460 # number of overall misses -system.cpu0.icache.overall_misses::total 970891 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1794259500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4426264489 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6220523989 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1794259500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4426264489 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6220523989 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1794259500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4426264489 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6220523989 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32068244 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7850703 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2612686 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 42531633 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32068244 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7850703 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2612686 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 42531633 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32068244 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7850703 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2612686 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 42531633 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016253 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016459 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122655 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.022828 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016253 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016459 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122655 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.022828 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016253 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016459 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122655 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.022828 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13885.522915 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13812.221460 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6407.026112 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13885.522915 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13812.221460 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6407.026112 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13885.522915 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13812.221460 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6407.026112 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1940 # number of cycles access was blocked +system.cpu0.icache.replacements 952687 # number of replacements +system.cpu0.icache.tagsinuse 511.197182 # Cycle average of tags in use +system.cpu0.icache.total_refs 41854963 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 953198 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 43.910041 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 10248069000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 255.807414 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 79.618511 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 175.771256 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.499624 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.155505 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.343303 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998432 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 31831928 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7734859 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2288176 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 41854963 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31831928 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7734859 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2288176 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 41854963 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31831928 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7734859 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2288176 # number of overall hits +system.cpu0.icache.overall_hits::total 41854963 # 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miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122714 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.022658 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016114 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016395 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122714 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.022658 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016114 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016395 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122714 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.022658 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14069.483980 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13977.681331 # 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number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 645594000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 754135000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1399729000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086179 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088589 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041134 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053154 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045410 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021712 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101943 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.101948 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.038763 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000038 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000010 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.071970 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071870 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033208 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.071970 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071870 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033208 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18815.879750 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16354.540243 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17048.811169 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27397.157676 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26952.040582 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27112.738692 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11175.589837 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12738.099436 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12300.850686 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21542.717096 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18947.219743 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19734.009477 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21542.717096 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18947.219743 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19734.009477 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 836144 # number of writebacks +system.cpu0.dcache.writebacks::total 836144 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 285747 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 285747 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 477794 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 477794 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1510 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1510 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 763541 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 763541 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 763541 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 763541 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 103680 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 261914 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 365594 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 48063 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 85208 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 133271 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2193 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5492 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7685 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 151743 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 347122 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 498865 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 151743 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 347122 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 498865 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1965520000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4314581000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6280101000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1297796000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2151055620 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3448851620 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24542500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69880000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94422500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3263316000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6465636620 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9728952620 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3263316000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6465636620 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9728952620 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287578500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342019500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 629598000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357171000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 418642000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 775813000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 644749500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 760661500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1405411000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086309 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088191 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040957 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053019 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045421 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021663 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102152 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098733 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037849 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.071991 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071633 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033085 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.071991 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071633 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033085 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18957.561728 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16473.273670 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17177.801058 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27001.976572 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25244.761290 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25878.485342 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11191.290470 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12723.962127 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12286.597267 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21505.545561 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18626.409793 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19502.175178 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21505.545561 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18626.409793 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19502.175178 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1162,22 +1142,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1220100 # DTB read hits -system.cpu1.dtb.read_misses 1488 # DTB read misses -system.cpu1.dtb.read_acv 40 # DTB read access violations -system.cpu1.dtb.read_accesses 143779 # DTB read accesses -system.cpu1.dtb.write_hits 928690 # DTB write hits -system.cpu1.dtb.write_misses 201 # DTB write misses +system.cpu1.dtb.read_hits 1220324 # DTB read hits +system.cpu1.dtb.read_misses 1556 # DTB read misses +system.cpu1.dtb.read_acv 46 # DTB read access violations +system.cpu1.dtb.read_accesses 144016 # DTB read accesses +system.cpu1.dtb.write_hits 928239 # DTB write hits +system.cpu1.dtb.write_misses 207 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 59743 # DTB write accesses -system.cpu1.dtb.data_hits 2148790 # DTB hits -system.cpu1.dtb.data_misses 1689 # DTB misses -system.cpu1.dtb.data_acv 64 # DTB access violations -system.cpu1.dtb.data_accesses 203522 # DTB accesses -system.cpu1.itb.fetch_hits 872643 # ITB hits -system.cpu1.itb.fetch_misses 756 # ITB misses -system.cpu1.itb.fetch_acv 43 # ITB acv -system.cpu1.itb.fetch_accesses 873399 # ITB accesses +system.cpu1.dtb.write_accesses 60107 # DTB write accesses +system.cpu1.dtb.data_hits 2148563 # DTB hits +system.cpu1.dtb.data_misses 1763 # DTB misses +system.cpu1.dtb.data_acv 70 # DTB access violations +system.cpu1.dtb.data_accesses 204123 # DTB accesses +system.cpu1.itb.fetch_hits 875123 # ITB hits +system.cpu1.itb.fetch_misses 774 # ITB misses +system.cpu1.itb.fetch_acv 46 # ITB acv +system.cpu1.itb.fetch_accesses 875897 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1190,28 +1170,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953546573 # number of cpu cycles simulated +system.cpu1.numCycles 953544050 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7848949 # Number of instructions committed -system.cpu1.committedOps 7848949 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7301756 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45390 # Number of float alu accesses -system.cpu1.num_func_calls 212250 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 958041 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7301756 # number of integer instructions -system.cpu1.num_fp_insts 45390 # number of float instructions -system.cpu1.num_int_register_reads 10145726 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5312805 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24524 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24770 # number of times the floating registers were written -system.cpu1.num_mem_refs 2156479 # number of memory refs -system.cpu1.num_load_insts 1225350 # Number of load instructions -system.cpu1.num_store_insts 931129 # Number of store instructions -system.cpu1.num_idle_cycles -1690648572.086683 # Number of idle cycles -system.cpu1.num_busy_cycles 2644195145.086683 # Number of busy cycles -system.cpu1.not_idle_fraction 2.773011 # Percentage of non-idle cycles -system.cpu1.idle_fraction -1.773011 # Percentage of idle cycles +system.cpu1.committedInsts 7861954 # Number of instructions committed +system.cpu1.committedOps 7861954 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7314134 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45433 # Number of float alu accesses +system.cpu1.num_func_calls 212083 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 960162 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7314134 # number of integer instructions +system.cpu1.num_fp_insts 45433 # number of float instructions +system.cpu1.num_int_register_reads 10166177 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5323216 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24545 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24803 # number of times the floating registers were written +system.cpu1.num_mem_refs 2156447 # number of memory refs +system.cpu1.num_load_insts 1225739 # Number of load instructions +system.cpu1.num_store_insts 930708 # Number of store instructions +system.cpu1.num_idle_cycles 195910529.325868 # Number of idle cycles +system.cpu1.num_busy_cycles 757633520.674132 # Number of busy cycles +system.cpu1.not_idle_fraction 0.794545 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.205455 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1229,35 +1209,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8367198 # Number of BP lookups -system.cpu2.branchPred.condPredicted 7675066 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 129021 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6898028 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5713360 # Number of BTB hits +system.cpu2.branchPred.lookups 8412637 # Number of BP lookups +system.cpu2.branchPred.condPredicted 7718594 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 129281 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 6816710 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 5762098 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 82.825990 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 286292 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 15213 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 84.529018 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 288280 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 15520 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3233315 # DTB read hits -system.cpu2.dtb.read_misses 12189 # DTB read misses -system.cpu2.dtb.read_acv 135 # DTB read access violations -system.cpu2.dtb.read_accesses 219207 # DTB read accesses -system.cpu2.dtb.write_hits 2006633 # DTB write hits -system.cpu2.dtb.write_misses 2635 # DTB write misses -system.cpu2.dtb.write_acv 145 # DTB write access violations -system.cpu2.dtb.write_accesses 81760 # DTB write accesses -system.cpu2.dtb.data_hits 5239948 # DTB hits -system.cpu2.dtb.data_misses 14824 # DTB misses -system.cpu2.dtb.data_acv 280 # DTB access violations -system.cpu2.dtb.data_accesses 300967 # DTB accesses -system.cpu2.itb.fetch_hits 374893 # ITB hits -system.cpu2.itb.fetch_misses 5781 # ITB misses -system.cpu2.itb.fetch_acv 261 # ITB acv -system.cpu2.itb.fetch_accesses 380674 # ITB accesses +system.cpu2.dtb.read_hits 3230835 # DTB read hits +system.cpu2.dtb.read_misses 11458 # DTB read misses +system.cpu2.dtb.read_acv 112 # DTB read access violations +system.cpu2.dtb.read_accesses 217040 # DTB read accesses +system.cpu2.dtb.write_hits 2001660 # DTB write hits +system.cpu2.dtb.write_misses 2605 # DTB write misses +system.cpu2.dtb.write_acv 143 # DTB write access violations +system.cpu2.dtb.write_accesses 81606 # DTB write accesses +system.cpu2.dtb.data_hits 5232495 # DTB hits +system.cpu2.dtb.data_misses 14063 # DTB misses +system.cpu2.dtb.data_acv 255 # DTB access violations +system.cpu2.dtb.data_accesses 298646 # DTB accesses +system.cpu2.itb.fetch_hits 371714 # ITB hits +system.cpu2.itb.fetch_misses 5691 # ITB misses +system.cpu2.itb.fetch_acv 245 # ITB acv +system.cpu2.itb.fetch_accesses 377405 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1270,270 +1250,270 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30553382 # number of cpu cycles simulated +system.cpu2.numCycles 30535701 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8548806 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 34839646 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8367198 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 5999652 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8085881 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 623525 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9702754 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 9910 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1956 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 65426 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 78066 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 227 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2612689 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 89635 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 26899441 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.295181 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.310992 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8533986 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 34964689 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8412637 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6050378 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8133499 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 621333 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9684422 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 10316 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 62496 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 78611 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2608249 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 90274 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 26910354 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.299302 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.309788 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18813560 69.94% 69.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 273460 1.02% 70.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 442537 1.65% 72.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4198605 15.61% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 738968 2.75% 90.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 167733 0.62% 91.58% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 196064 0.73% 92.31% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 433736 1.61% 93.92% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1634778 6.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18776855 69.78% 69.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 272793 1.01% 70.79% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 440434 1.64% 72.43% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4254201 15.81% 88.23% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 737771 2.74% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 167398 0.62% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 196636 0.73% 92.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433593 1.61% 93.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1630673 6.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 26899441 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.273855 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.140288 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8679846 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9796545 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7488897 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 294076 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 394122 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 169250 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12966 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34438242 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40605 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 394122 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 9036155 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2833856 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5793548 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7343930 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1251886 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33280862 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2342 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 235752 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 410323 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 22341851 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41449381 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41284168 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 165213 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20505105 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1836746 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 509428 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 60335 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3708993 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3395949 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2096293 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 374269 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 256431 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30745321 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 631973 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30290863 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 30934 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2196077 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1091992 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 446408 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 26899441 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.126078 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.565187 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 26910354 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.275502 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.145043 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8661365 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9779402 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7537150 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 294171 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 392382 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 168927 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12968 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34563094 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 40757 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 392382 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 9017323 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2819487 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5795757 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7393744 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1245786 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33400489 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2356 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 234346 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 410991 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 22419821 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 41624595 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41459018 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 165577 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20586998 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1832823 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 505460 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 60216 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3692928 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3393863 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2097985 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 374320 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 252386 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 30872998 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 630971 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 30415497 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 38395 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2194504 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1105046 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 445283 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 26910354 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.130253 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.565604 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15349062 57.06% 57.06% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3113388 11.57% 68.64% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1556519 5.79% 74.42% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5024470 18.68% 93.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 916558 3.41% 96.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 490691 1.82% 98.33% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 288280 1.07% 99.40% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 142124 0.53% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18349 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15319537 56.93% 56.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3107474 11.55% 68.48% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1555934 5.78% 74.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5075643 18.86% 93.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 913365 3.39% 96.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 492006 1.83% 98.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 286832 1.07% 99.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 141760 0.53% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 17803 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 26899441 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 26910354 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 35139 13.92% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.92% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 113314 44.90% 58.82% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 103925 41.18% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 34989 13.90% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.90% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 113310 45.00% 58.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 103504 41.11% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24571272 81.12% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20288 0.07% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8510 0.03% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.23% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3364677 11.11% 92.33% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2029119 6.70% 99.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 293313 0.97% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2444 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 24705605 81.23% 81.24% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20302 0.07% 81.30% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.30% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8486 0.03% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1222 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.33% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3362289 11.05% 92.39% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2024695 6.66% 99.05% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 290454 0.95% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30290863 # Type of FU issued -system.cpu2.iq.rate 0.991408 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 252378 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.008332 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 87527172 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33461701 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 29889528 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 237307 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 115799 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 112442 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30417117 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 123668 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 190380 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 30415497 # Type of FU issued +system.cpu2.iq.rate 0.996063 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 251803 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.008279 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 87793643 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 33586183 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 30009832 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 237903 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 116334 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 112629 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 30540939 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 123917 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 191281 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 417328 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 909 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4219 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 161835 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 420182 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 991 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4150 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 166078 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5028 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 23504 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4737 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 23355 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 394122 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2048539 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 212384 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32667767 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 225947 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3395949 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2096293 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 561038 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 149803 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2446 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4219 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 66256 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 130204 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196460 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30129770 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3254028 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 161093 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 392382 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2039220 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 211536 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32790346 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 224393 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3393863 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2097985 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 560382 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 149727 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2248 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4150 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 66680 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 129830 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 196510 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 30250738 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3250585 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 164759 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1290473 # number of nop insts executed -system.cpu2.iew.exec_refs 5267847 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6767321 # Number of branches executed -system.cpu2.iew.exec_stores 2013819 # Number of stores executed -system.cpu2.iew.exec_rate 0.986135 # Inst execution rate -system.cpu2.iew.wb_sent 30034994 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 30001970 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17305763 # num instructions producing a value -system.cpu2.iew.wb_consumers 20552521 # num instructions consuming a value +system.cpu2.iew.exec_nop 1286377 # number of nop insts executed +system.cpu2.iew.exec_refs 5259361 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6817854 # Number of branches executed +system.cpu2.iew.exec_stores 2008776 # Number of stores executed +system.cpu2.iew.exec_rate 0.990668 # Inst execution rate +system.cpu2.iew.wb_sent 30155470 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 30122461 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17393526 # num instructions producing a value +system.cpu2.iew.wb_consumers 20640191 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.981953 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.842026 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.986467 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.842702 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2377399 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 185565 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 182360 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26505319 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.141095 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.851284 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2374784 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 185688 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 182288 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26517972 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.145282 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.851176 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16405167 61.89% 61.89% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2334119 8.81% 70.70% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1221930 4.61% 75.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4753276 17.93% 93.24% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 503631 1.90% 95.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 187421 0.71% 95.85% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 180293 0.68% 96.53% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 181960 0.69% 97.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 737522 2.78% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16375650 61.75% 61.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2329506 8.78% 70.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1218962 4.60% 75.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4807374 18.13% 93.26% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 502647 1.90% 95.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 186920 0.70% 95.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 179412 0.68% 96.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 180660 0.68% 97.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 736841 2.78% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26505319 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30245090 # Number of instructions committed -system.cpu2.commit.committedOps 30245090 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26517972 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30370560 # Number of instructions committed +system.cpu2.commit.committedOps 30370560 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4913079 # Number of memory references committed -system.cpu2.commit.loads 2978621 # Number of loads committed -system.cpu2.commit.membars 65145 # Number of memory barriers committed -system.cpu2.commit.branches 6616794 # Number of branches committed -system.cpu2.commit.fp_insts 111215 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28779164 # Number of committed integer instructions. -system.cpu2.commit.function_calls 231926 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 737522 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4905588 # Number of memory references committed +system.cpu2.commit.loads 2973681 # Number of loads committed +system.cpu2.commit.membars 65235 # Number of memory barriers committed +system.cpu2.commit.branches 6667985 # Number of branches committed +system.cpu2.commit.fp_insts 111312 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28908362 # Number of committed integer instructions. +system.cpu2.commit.function_calls 232233 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 736841 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 58315466 # The number of ROB reads -system.cpu2.rob.rob_writes 65639010 # The number of ROB writes -system.cpu2.timesIdled 244602 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3653941 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745271968 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 29064360 # Number of Instructions Simulated -system.cpu2.committedOps 29064360 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 29064360 # Number of Instructions Simulated -system.cpu2.cpi 1.051232 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.051232 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.951265 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.951265 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39620111 # number of integer regfile reads -system.cpu2.int_regfile_writes 21211926 # number of integer regfile writes -system.cpu2.fp_regfile_reads 68528 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68903 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4553685 # number of misc regfile reads -system.cpu2.misc_regfile_writes 261693 # number of misc regfile writes +system.cpu2.rob.rob_reads 58454827 # The number of ROB reads +system.cpu2.rob.rob_writes 65882898 # The number of ROB writes +system.cpu2.timesIdled 242873 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3625347 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745288097 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 29192891 # Number of Instructions Simulated +system.cpu2.committedOps 29192891 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 29192891 # Number of Instructions Simulated +system.cpu2.cpi 1.045998 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.045998 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.956025 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.956025 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 39779581 # number of integer regfile reads +system.cpu2.int_regfile_writes 21289103 # number of integer regfile writes +system.cpu2.fp_regfile_reads 68643 # number of floating regfile reads +system.cpu2.fp_regfile_writes 68941 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4607989 # number of misc regfile reads +system.cpu2.misc_regfile_writes 260558 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed |