diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:25 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-02 06:08:25 -0500 |
| commit | 6489598fb449531c34bfb25a52189196ee2b1086 (patch) | |
| tree | 5f8bb88862ffd187cb7b182f4a0d20599b4409bf /tests/long/fs/10.linux-boot/ref/alpha/linux | |
| parent | 966c3f4bc5581347a411c25db1440afb97f12dab (diff) | |
| download | gem5-6489598fb449531c34bfb25a52189196ee2b1086.tar.xz | |
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
4 files changed, 5647 insertions, 5633 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 85db7b5af..d1ad31617 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,108 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.883224 # Number of seconds simulated -sim_ticks 1883224346500 # Number of ticks simulated -final_tick 1883224346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.884241 # Number of seconds simulated +sim_ticks 1884241273000 # Number of ticks simulated +final_tick 1884241273000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 279379 # Simulator instruction rate (inst/s) -host_op_rate 279379 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9375076807 # Simulator tick rate (ticks/s) -host_mem_usage 311380 # Number of bytes of host memory used -host_seconds 200.88 # Real time elapsed on the host -sim_insts 56120453 # Number of instructions simulated -sim_ops 56120453 # Number of ops (including micro ops) simulated +host_inst_rate 193195 # Simulator instruction rate (inst/s) +host_op_rate 193195 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6486085343 # Simulator tick rate (ticks/s) +host_mem_usage 317148 # Number of bytes of host memory used +host_seconds 290.51 # Real time elapsed on the host +sim_insts 56124126 # Number of instructions simulated +sim_ops 56124126 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 25931648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 25914944 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25932608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1052800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1052800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4903936 # Number of bytes written to this memory -system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7563264 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 405182 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25915904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1052928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1052928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7561408 # Number of bytes written to this memory +system.physmem.bytes_written::total 7561408 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 404921 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 405197 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 76624 # Number of write requests responded to by this memory -system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118176 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13769813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13770323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 559041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 559041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2604011 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1412114 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4016125 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2604011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13769813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1412624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17786448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 405197 # Number of read requests accepted -system.physmem.writeReqs 118176 # Number of write requests accepted -system.physmem.readBursts 405197 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118176 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25920704 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11904 # Total number of bytes read from write queue -system.physmem.bytesWritten 7562112 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25932608 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7563264 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 186 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25484 # Per bank write bursts -system.physmem.perBankRdBursts::1 25740 # Per bank write bursts -system.physmem.perBankRdBursts::2 25857 # Per bank write bursts -system.physmem.perBankRdBursts::3 25788 # Per bank write bursts -system.physmem.perBankRdBursts::4 25237 # Per bank write bursts -system.physmem.perBankRdBursts::5 24959 # Per bank write bursts +system.physmem.num_reads::total 404936 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118147 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118147 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13753517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13754026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 558807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 558807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4012972 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4012972 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4012972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13753517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17766999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404936 # Number of read requests accepted +system.physmem.writeReqs 159699 # Number of write requests accepted +system.physmem.readBursts 404936 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159699 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25909568 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue +system.physmem.bytesWritten 10083392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25915904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10220736 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2126 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 153 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25482 # Per bank write bursts +system.physmem.perBankRdBursts::1 25742 # Per bank write bursts +system.physmem.perBankRdBursts::2 25842 # Per bank write bursts +system.physmem.perBankRdBursts::3 25776 # Per bank write bursts +system.physmem.perBankRdBursts::4 25226 # Per bank write bursts +system.physmem.perBankRdBursts::5 24953 # Per bank write bursts system.physmem.perBankRdBursts::6 24814 # Per bank write bursts -system.physmem.perBankRdBursts::7 24586 # Per bank write bursts -system.physmem.perBankRdBursts::8 25127 # Per bank write bursts -system.physmem.perBankRdBursts::9 25284 # Per bank write bursts -system.physmem.perBankRdBursts::10 25531 # Per bank write bursts -system.physmem.perBankRdBursts::11 24857 # Per bank write bursts -system.physmem.perBankRdBursts::12 24549 # Per bank write bursts -system.physmem.perBankRdBursts::13 25592 # Per bank write bursts -system.physmem.perBankRdBursts::14 25866 # Per bank write bursts -system.physmem.perBankRdBursts::15 25740 # Per bank write bursts -system.physmem.perBankWrBursts::0 7812 # Per bank write bursts -system.physmem.perBankWrBursts::1 7680 # Per bank write bursts -system.physmem.perBankWrBursts::2 8067 # Per bank write bursts -system.physmem.perBankWrBursts::3 7745 # Per bank write bursts -system.physmem.perBankWrBursts::4 7320 # Per bank write bursts -system.physmem.perBankWrBursts::5 6957 # Per bank write bursts -system.physmem.perBankWrBursts::6 6792 # Per bank write bursts -system.physmem.perBankWrBursts::7 6401 # Per bank write bursts -system.physmem.perBankWrBursts::8 7236 # Per bank write bursts -system.physmem.perBankWrBursts::9 6892 # Per bank write bursts -system.physmem.perBankWrBursts::10 7391 # Per bank write bursts -system.physmem.perBankWrBursts::11 6866 # Per bank write bursts -system.physmem.perBankWrBursts::12 7045 # Per bank write bursts -system.physmem.perBankWrBursts::13 8010 # Per bank write bursts -system.physmem.perBankWrBursts::14 7989 # Per bank write bursts -system.physmem.perBankWrBursts::15 7955 # Per bank write bursts +system.physmem.perBankRdBursts::7 24563 # Per bank write bursts +system.physmem.perBankRdBursts::8 25102 # Per bank write bursts +system.physmem.perBankRdBursts::9 25273 # Per bank write bursts +system.physmem.perBankRdBursts::10 25528 # Per bank write bursts +system.physmem.perBankRdBursts::11 24851 # Per bank write bursts +system.physmem.perBankRdBursts::12 24526 # Per bank write bursts +system.physmem.perBankRdBursts::13 25574 # Per bank write bursts +system.physmem.perBankRdBursts::14 25842 # Per bank write bursts +system.physmem.perBankRdBursts::15 25743 # Per bank write bursts +system.physmem.perBankWrBursts::0 10288 # Per bank write bursts +system.physmem.perBankWrBursts::1 10037 # Per bank write bursts +system.physmem.perBankWrBursts::2 10678 # Per bank write bursts +system.physmem.perBankWrBursts::3 10053 # Per bank write bursts +system.physmem.perBankWrBursts::4 9806 # Per bank write bursts +system.physmem.perBankWrBursts::5 9437 # Per bank write bursts +system.physmem.perBankWrBursts::6 9137 # Per bank write bursts +system.physmem.perBankWrBursts::7 8750 # Per bank write bursts +system.physmem.perBankWrBursts::8 9885 # Per bank write bursts +system.physmem.perBankWrBursts::9 8937 # Per bank write bursts +system.physmem.perBankWrBursts::10 9881 # Per bank write bursts +system.physmem.perBankWrBursts::11 9301 # Per bank write bursts +system.physmem.perBankWrBursts::12 9770 # Per bank write bursts +system.physmem.perBankWrBursts::13 10691 # Per bank write bursts +system.physmem.perBankWrBursts::14 10395 # Per bank write bursts +system.physmem.perBankWrBursts::15 10507 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 1883215617500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1884232486500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 405197 # Read request sizes (log2) +system.physmem.readPktSize::6 404936 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118176 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402689 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see +system.physmem.writePktSize::6 159699 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 71 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -147,337 +144,188 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63140 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 530.294837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 322.585016 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.640457 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14650 23.20% 23.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10589 16.77% 39.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5075 8.04% 48.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3003 4.76% 52.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2370 3.75% 56.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2105 3.33% 59.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1364 2.16% 62.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1607 2.55% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22377 35.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63140 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5316 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.186983 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2896.748549 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5313 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65749 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 547.429771 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 335.789885 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 418.130322 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14719 22.39% 22.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10714 16.30% 38.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4807 7.31% 45.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3176 4.83% 50.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2550 3.88% 54.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1953 2.97% 57.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1437 2.19% 59.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1697 2.58% 62.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24696 37.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65749 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5738 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.553154 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2788.767091 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5735 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5316 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5316 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.226862 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.933757 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.590348 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4662 87.70% 87.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 15 0.28% 87.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 21 0.40% 88.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 225 4.23% 92.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 46 0.87% 93.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 10 0.19% 93.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 7 0.13% 93.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.13% 93.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 19 0.36% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.06% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.04% 94.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.04% 94.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 12 0.23% 94.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.02% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.11% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 29 0.55% 95.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 14 0.26% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.04% 95.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 12 0.23% 95.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 164 3.09% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.09% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 3 0.06% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.08% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.06% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 8 0.15% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 6 0.11% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 12 0.23% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.06% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.06% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5316 # Writes before turning the bus around for reads -system.physmem.totQLat 2156220500 # Total ticks spent queuing -system.physmem.totMemAccLat 9750176750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2025055000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5323.86 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5738 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5738 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.457825 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.746842 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 34.017596 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4693 81.79% 81.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 187 3.26% 85.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 275 4.79% 89.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 67 1.17% 91.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 92 1.60% 92.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 47 0.82% 93.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 24 0.42% 93.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 11 0.19% 94.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 19 0.33% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 7 0.12% 94.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 14 0.24% 94.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 6 0.10% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 7 0.12% 94.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 4 0.07% 95.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 17 0.30% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 47 0.82% 96.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 17 0.30% 96.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 17 0.30% 96.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 79 1.38% 98.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 32 0.56% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 20 0.35% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 19 0.33% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 15 0.26% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 7 0.12% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 4 0.07% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 3 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 3 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5738 # Writes before turning the bus around for reads +system.physmem.totQLat 2167079250 # Total ticks spent queuing +system.physmem.totMemAccLat 9757773000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2024185000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5352.97 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24073.86 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.76 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.02 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 24102.97 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.75 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 5.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.75 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.42 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.67 # Average write queue length when enqueuing -system.physmem.readRowHits 364400 # Number of row buffer hits during reads -system.physmem.writeRowHits 95629 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.97 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.92 # Row buffer hit rate for writes -system.physmem.avgGap 3598228.45 # Average gap between requests -system.physmem.pageHitRate 87.93 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1774012993500 # Time in different power states -system.physmem.memoryStateTime::REF 62884900000 # Time in different power states +system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing +system.physmem.readRowHits 364185 # Number of row buffer hits during reads +system.physmem.writeRowHits 132456 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.96 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.06 # Row buffer hit rate for writes +system.physmem.avgGap 3337080.57 # Average gap between requests +system.physmem.pageHitRate 88.31 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1774592996500 # Time in different power states +system.physmem.memoryStateTime::REF 62918700000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 46323736500 # Time in different power states +system.physmem.memoryStateTime::ACT 46722146000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 232613640 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 244724760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 126922125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 133530375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1579227000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1579858800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 380855520 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 384808320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 123002864400 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 123002864400 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 59595719580 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 60657122565 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1077656022750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1076724967500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1262574225015 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1262727876720 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.433163 # Core power per rank (mW) -system.physmem.averagePower::1 670.514753 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 295760 # Transaction distribution -system.membus.trans_dist::ReadResp 295744 # Transaction distribution -system.membus.trans_dist::WriteReq 9618 # Transaction distribution -system.membus.trans_dist::WriteResp 9618 # Transaction distribution -system.membus.trans_dist::Writeback 76624 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 154 # Transaction distribution -system.membus.trans_dist::UpgradeResp 154 # Transaction distribution -system.membus.trans_dist::ReadExReq 116541 # Transaction distribution -system.membus.trans_dist::ReadExResp 116541 # Transaction distribution -system.membus.trans_dist::BadAddressError 16 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33096 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887296 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1003716 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30835584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30879892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33540180 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 158 # Total snoops (count) -system.membus.snoop_fanout::samples 523708 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 523708 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 523708 # Request fanout histogram -system.membus.reqLayer0.occupancy 30927500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1547261750 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3825161596 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43114249 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.288180 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1728025257000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.288180 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.080511 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.080511 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses -system.iocache.demand_misses::total 173 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 173 # number of overall misses -system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 41552 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512658057 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512658057 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14964931 # Number of BP lookups -system.cpu.branchPred.condPredicted 12983118 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 374694 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9691016 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5184483 # Number of BTB hits +system.physmem.actEnergy::0 242668440 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 254394000 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 132408375 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 138806250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1578704400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1579024200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 506645280 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 514298160 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 123068977200 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 123068977200 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 59931006120 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 60719870160 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1077969239250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1077277253250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1263429649065 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1263552623220 # Total energy per rank (pJ) +system.physmem.averagePower::0 670.526996 # Core power per rank (mW) +system.physmem.averagePower::1 670.592261 # Core power per rank (mW) +system.cpu.branchPred.lookups 15011318 # Number of BP lookups +system.cpu.branchPred.condPredicted 13019220 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 376037 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9980368 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5204970 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 53.497827 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 807557 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32108 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 52.152085 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 808971 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32603 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9237824 # DTB read hits -system.cpu.dtb.read_misses 17804 # DTB read misses +system.cpu.dtb.read_hits 9241438 # DTB read hits +system.cpu.dtb.read_misses 17791 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766148 # DTB read accesses -system.cpu.dtb.write_hits 6384867 # DTB write hits -system.cpu.dtb.write_misses 2306 # DTB write misses +system.cpu.dtb.read_accesses 766265 # DTB read accesses +system.cpu.dtb.write_hits 6385998 # DTB write hits +system.cpu.dtb.write_misses 2317 # DTB write misses system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298467 # DTB write accesses -system.cpu.dtb.data_hits 15622691 # DTB hits -system.cpu.dtb.data_misses 20110 # DTB misses +system.cpu.dtb.write_accesses 298404 # DTB write accesses +system.cpu.dtb.data_hits 15627436 # DTB hits +system.cpu.dtb.data_misses 20108 # DTB misses system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1064615 # DTB accesses -system.cpu.itb.fetch_hits 3999749 # ITB hits -system.cpu.itb.fetch_misses 6851 # ITB misses -system.cpu.itb.fetch_acv 647 # ITB acv -system.cpu.itb.fetch_accesses 4006600 # ITB accesses +system.cpu.dtb.data_accesses 1064669 # DTB accesses +system.cpu.itb.fetch_hits 4019003 # ITB hits +system.cpu.itb.fetch_misses 6884 # ITB misses +system.cpu.itb.fetch_acv 661 # ITB acv +system.cpu.itb.fetch_accesses 4025887 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -490,39 +338,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 174888375 # number of cpu cycles simulated +system.cpu.numCycles 175285694 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56120453 # Number of instructions committed -system.cpu.committedOps 56120453 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2530516 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5527 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3591560318 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.116304 # CPI: cycles per instruction -system.cpu.ipc 0.320893 # IPC: instructions per cycle +system.cpu.committedInsts 56124126 # Number of instructions committed +system.cpu.committedOps 56124126 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2495853 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5575 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3593196852 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.123179 # CPI: cycles per instruction +system.cpu.ipc 0.320187 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211459 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74787 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211480 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74791 40.94% 40.94% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1900 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105855 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182673 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73420 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105868 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182691 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73424 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1900 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73420 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148871 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1832868777500 97.33% 97.33% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 80360500 0.00% 97.33% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 672864500 0.04% 97.37% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 49601349000 2.63% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1883223351500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981721 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73424 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148880 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1833816082000 97.32% 97.32% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 80474500 0.00% 97.33% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 673053000 0.04% 97.36% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 49670669500 2.64% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1884240279000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693590 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814959 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693543 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814928 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -558,71 +406,475 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175516 91.23% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6803 3.54% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175532 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5125 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192398 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5867 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.callpal::total 192418 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5870 # number of protection mode switches +system.cpu.kern.mode_switch::user 1743 # number of protection mode switches system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1741 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.325550 # fraction of useful protection mode switches +system.cpu.kern.mode_good::kernel 1913 +system.cpu.kern.mode_good::user 1743 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.325894 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393571 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36222818500 1.92% 1.92% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4061127000 0.22% 2.14% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1842939396000 97.86% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed -system.cpu.tickCycles 83840328 # Number of cycles that the object actually ticked -system.cpu.idleCycles 91048047 # Total number of cycles that the object has spent stopped -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.393986 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 36270859500 1.92% 1.92% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4083023000 0.22% 2.14% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1843886386500 97.86% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.tickCycles 84485847 # Number of cycles that the object actually ticked +system.cpu.idleCycles 90799847 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395229 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.982334 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13773041 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395741 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.867906 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 86820250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982334 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.999965 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 63657366 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63657366 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 7814636 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7814636 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 5576637 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5576637 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182736 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182736 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 198999 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 198999 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 13391273 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13391273 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 13391273 # number of overall hits +system.cpu.dcache.overall_hits::total 13391273 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 1201532 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201532 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 573582 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573582 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17284 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17284 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.inst 1775114 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10831.431116 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.831524 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165275 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996799 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1458 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5147 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2791 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55536 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 30249203 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 30249203 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 2261508 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2261508 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 838115 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 838115 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 187530 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187530 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2449038 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2449038 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2449038 # number of overall hits +system.cpu.l2cache.overall_hits::total 2449038 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 288693 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 288693 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.inst 17 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 116655 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116655 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 405348 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405348 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 405348 # number of overall misses +system.cpu.l2cache.overall_misses::total 405348 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18932535000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18932535000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 214497 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 214497 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8075894612 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8075894612 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27008429612 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 27008429612 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27008429612 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 27008429612 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 2550201 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2550201 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 838115 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 838115 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 21 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304185 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304185 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 2854386 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2854386 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2854386 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2854386 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113204 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.113204 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.809524 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383500 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383500 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.142009 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.142009 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.142009 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.142009 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65580.166474 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 65580.166474 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 12617.470588 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12617.470588 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69228.876705 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69228.876705 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66630.227883 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66630.227883 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66630.227883 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66630.227883 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 76635 # number of writebacks +system.cpu.l2cache.writebacks::total 76635 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288693 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288693 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116655 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116655 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 405348 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405348 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 405348 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405348 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15323296500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15323296500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 271014 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271014 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6608324888 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6608324888 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21931621388 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21931621388 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21931621388 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21931621388 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333779000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333779000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1887481500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887481500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3221260500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221260500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113204 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113204 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.809524 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383500 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383500 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142009 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.142009 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142009 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.142009 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53078.171275 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53078.171275 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 15942 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15942 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56648.449599 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56648.449599 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54105.660785 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54105.660785 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54105.660785 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54105.660785 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 2557364 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2557331 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 838115 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917316 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662927 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6580243 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143021148 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236373340 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41941 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3734307 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.011173 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105112 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3692582 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41725 1.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3734307 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2697490998 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 2191666369 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2194528153 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51170 # Transaction distribution -system.iobus.trans_dist::WriteResp 51170 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5092 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51171 # Transaction distribution +system.iobus.trans_dist::WriteResp 9619 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5094 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -634,11 +886,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33096 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33098 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116546 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20376 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -650,11 +902,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44308 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44316 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705916 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4703000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705924 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4705000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -676,435 +928,188 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374407689 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406196790 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23478000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42013751 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 1457910 # number of replacements -system.cpu.icache.tags.tagsinuse 509.626980 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 18940924 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1458421 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12.987281 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 31560714250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.626980 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995365 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995365 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 21858119 # Number of tag accesses -system.cpu.icache.tags.data_accesses 21858119 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 18940927 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 18940927 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 18940927 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 18940927 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 18940927 # number of overall hits -system.cpu.icache.overall_hits::total 18940927 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1458596 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1458596 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1458596 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1458596 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1458596 # number of overall misses -system.cpu.icache.overall_misses::total 1458596 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20022164568 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20022164568 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20022164568 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20022164568 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20022164568 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20022164568 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 20399523 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 20399523 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 20399523 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 20399523 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 20399523 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 20399523 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071501 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.071501 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.071501 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.071501 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.071501 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.071501 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.011844 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13727.011844 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.011844 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13727.011844 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.011844 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13727.011844 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458596 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1458596 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1458596 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1458596 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1458596 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1458596 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17097663432 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17097663432 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17097663432 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17097663432 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17097663432 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17097663432 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071501 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071501 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071501 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11722.000768 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11722.000768 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11722.000768 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11722.000768 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11722.000768 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11722.000768 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2557139 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2557106 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 838111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917133 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662791 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6579924 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93346368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143016724 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236363092 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41947 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3734153 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.011176 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105123 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3692421 98.88% 98.88% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41732 1.12% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3734153 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2697404999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2191548568 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194491404 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 339424 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65327.181695 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2981337 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 404586 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.368859 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5872511750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 54492.967363 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10834.214332 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.831497 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165317 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996814 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1457 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5166 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2781 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55528 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 30247978 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 30247978 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2261320 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2261320 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 838111 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 838111 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 187575 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187575 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2448895 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2448895 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2448895 # number of overall hits -system.cpu.l2cache.overall_hits::total 2448895 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 288657 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 288657 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.inst 17 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 116678 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116678 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 405335 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405335 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 405335 # number of overall misses -system.cpu.l2cache.overall_misses::total 405335 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18918279000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18918279000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 115495 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 115495 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8105432113 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8105432113 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27023711113 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27023711113 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27023711113 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27023711113 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 2549977 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2549977 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 838111 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 838111 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 21 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304253 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304253 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 2854230 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2854230 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2854230 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2854230 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113200 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.113200 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.809524 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383490 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383490 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.142012 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.142012 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.142012 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.142012 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65538.958002 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 65538.958002 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 6793.823529 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 6793.823529 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69468.384040 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69468.384040 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66670.065780 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66670.065780 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66670.065780 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66670.065780 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76624 # number of writebacks -system.cpu.l2cache.writebacks::total 76624 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288657 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288657 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116678 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116678 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 405335 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405335 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 405335 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405335 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15309425000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15309425000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 170516 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 170516 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6604759387 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6604759387 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21914184387 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21914184387 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21914184387 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21914184387 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333304000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333304000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1888377500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1888377500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3221681500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221681500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113200 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113200 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383490 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383490 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142012 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.142012 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142012 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.142012 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53036.735641 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53036.735641 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10030.352941 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.352941 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56606.724378 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56606.724378 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54064.377335 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54064.377335 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54064.377335 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54064.377335 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1395163 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.982303 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13764370 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395675 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.862160 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 86814250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982303 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999965 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63622669 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63622669 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 7806418 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7806418 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 5576177 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5576177 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182756 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182756 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 198986 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 198986 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 13382595 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13382595 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 13382595 # number of overall hits -system.cpu.dcache.overall_hits::total 13382595 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1201460 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201460 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 573699 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573699 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17252 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17252 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.inst 1775159 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1775159 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1775159 # number of overall misses -system.cpu.dcache.overall_misses::total 1775159 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31026314750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31026314750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20775588791 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20775588791 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 230892000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 230892000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 51801903541 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51801903541 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 51801903541 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51801903541 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 9007878 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9007878 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 6149876 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6149876 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200008 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200008 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198986 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 198986 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 15157754 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15157754 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 15157754 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15157754 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133379 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133379 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093286 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093286 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086257 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086257 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.117112 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117112 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.117112 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117112 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25823.843282 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25823.843282 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36213.395511 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36213.395511 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13383.491769 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13383.491769 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29181.556999 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29181.556999 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29181.556999 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29181.556999 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838111 # number of writebacks -system.cpu.dcache.writebacks::total 838111 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127232 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127232 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269462 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269462 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 396694 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 396694 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 396694 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 396694 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074228 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074228 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304237 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304237 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17249 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17249 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1378465 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378465 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1378465 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378465 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26911701750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26911701750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10289625346 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10289625346 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196226500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196226500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37201327096 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37201327096 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37201327096 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37201327096 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423395500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423395500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2003794000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2003794000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3427189500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3427189500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119254 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119254 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049470 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049470 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086242 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086242 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090941 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090941 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090941 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090941 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25052.132089 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25052.132089 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33821.084700 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33821.084700 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11376.108760 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11376.108760 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26987.502110 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26987.502110 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26987.502110 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26987.502110 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.tags.replacements 41685 # number of replacements +system.iocache.tags.tagsinuse 1.296059 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1728026020000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.296059 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081004 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081004 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375525 # Number of tag accesses +system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses +system.iocache.ReadReq_misses::total 173 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses +system.iocache.demand_misses::total 173 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 173 # number of overall misses +system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635314907 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13635314907 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328150.628297 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328150.628297 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 206297 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23564 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.754753 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 41512 # number of writebacks +system.iocache.writebacks::total 41512 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474610907 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474610907 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276150.628297 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276150.628297 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 295796 # Transaction distribution +system.membus.trans_dist::ReadResp 295780 # Transaction distribution +system.membus.trans_dist::WriteReq 9619 # Transaction distribution +system.membus.trans_dist::WriteResp 9619 # Transaction distribution +system.membus.trans_dist::Writeback 118147 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 155 # Transaction distribution +system.membus.trans_dist::UpgradeResp 155 # Transaction distribution +system.membus.trans_dist::ReadExReq 116517 # Transaction distribution +system.membus.trans_dist::ReadExResp 116517 # Transaction distribution +system.membus.trans_dist::BadAddressError 16 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887058 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920188 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1044992 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30819584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30863900 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36180956 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 433 # Total snoops (count) +system.membus.snoop_fanout::samples 565237 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 565237 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 565237 # Request fanout histogram +system.membus.reqLayer0.occupancy 30298500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1878232500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3792450097 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 4efdefebb..092a1319f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,125 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.905068 # Number of seconds simulated -sim_ticks 1905067807000 # Number of ticks simulated -final_tick 1905067807000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.901187 # Number of seconds simulated +sim_ticks 1901187238000 # Number of ticks simulated +final_tick 1901187238000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 154638 # Simulator instruction rate (inst/s) -host_op_rate 154638 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5148903745 # Simulator tick rate (ticks/s) -host_mem_usage 378896 # Number of bytes of host memory used -host_seconds 369.99 # Real time elapsed on the host -sim_insts 57215334 # Number of instructions simulated -sim_ops 57215334 # Number of ops (including micro ops) simulated +host_inst_rate 164685 # Simulator instruction rate (inst/s) +host_op_rate 164685 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5473626023 # Simulator tick rate (ticks/s) +host_mem_usage 324480 # Number of bytes of host memory used +host_seconds 347.34 # Real time elapsed on the host +sim_insts 57201060 # Number of instructions simulated +sim_ops 57201060 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 865344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24709248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 118912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 545600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 886592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24764800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 96384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 525056 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26240064 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 865344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 118912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 984256 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5157696 # Number of bytes written to this memory -system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7817024 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13521 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386082 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1858 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8525 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26273792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 886592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 96384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 982976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7873024 # Number of bytes written to this memory +system.physmem.bytes_written::total 7873024 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13853 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386950 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1506 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8204 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410001 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 80589 # Number of write requests responded to by this memory -system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122141 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 454233 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12970272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 62419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 286394 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13773822 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 454233 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 62419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516651 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2707356 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1395923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4103279 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2707356 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 454233 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12970272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 62419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 286394 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1396427 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17877100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410001 # Number of read requests accepted -system.physmem.writeReqs 122141 # Number of write requests accepted -system.physmem.readBursts 410001 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122141 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26227648 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 12416 # Total number of bytes read from write queue -system.physmem.bytesWritten 7815104 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26240064 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7817024 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 194 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 6364 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25988 # Per bank write bursts -system.physmem.perBankRdBursts::1 25697 # Per bank write bursts -system.physmem.perBankRdBursts::2 25753 # Per bank write bursts -system.physmem.perBankRdBursts::3 25768 # Per bank write bursts -system.physmem.perBankRdBursts::4 25192 # Per bank write bursts -system.physmem.perBankRdBursts::5 25524 # Per bank write bursts -system.physmem.perBankRdBursts::6 25779 # Per bank write bursts -system.physmem.perBankRdBursts::7 25095 # Per bank write bursts -system.physmem.perBankRdBursts::8 25528 # Per bank write bursts -system.physmem.perBankRdBursts::9 25751 # Per bank write bursts -system.physmem.perBankRdBursts::10 25719 # Per bank write bursts -system.physmem.perBankRdBursts::11 25446 # Per bank write bursts -system.physmem.perBankRdBursts::12 25795 # Per bank write bursts -system.physmem.perBankRdBursts::13 25643 # Per bank write bursts -system.physmem.perBankRdBursts::14 25930 # Per bank write bursts -system.physmem.perBankRdBursts::15 25199 # Per bank write bursts -system.physmem.perBankWrBursts::0 8301 # Per bank write bursts -system.physmem.perBankWrBursts::1 7506 # Per bank write bursts -system.physmem.perBankWrBursts::2 7807 # Per bank write bursts -system.physmem.perBankWrBursts::3 7337 # Per bank write bursts -system.physmem.perBankWrBursts::4 6902 # Per bank write bursts -system.physmem.perBankWrBursts::5 7063 # Per bank write bursts -system.physmem.perBankWrBursts::6 7447 # Per bank write bursts -system.physmem.perBankWrBursts::7 6982 # Per bank write bursts -system.physmem.perBankWrBursts::8 7245 # Per bank write bursts -system.physmem.perBankWrBursts::9 7339 # Per bank write bursts -system.physmem.perBankWrBursts::10 7570 # Per bank write bursts -system.physmem.perBankWrBursts::11 7510 # Per bank write bursts -system.physmem.perBankWrBursts::12 8378 # Per bank write bursts -system.physmem.perBankWrBursts::13 8362 # Per bank write bursts -system.physmem.perBankWrBursts::14 8512 # Per bank write bursts -system.physmem.perBankWrBursts::15 7850 # Per bank write bursts +system.physmem.num_reads::total 410528 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123016 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123016 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 466336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13025966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 50697 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 276173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13819676 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 466336 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 50697 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517033 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4141109 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4141109 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4141109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 466336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13025966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 50697 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 276173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17960785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410528 # Number of read requests accepted +system.physmem.writeReqs 164568 # Number of write requests accepted +system.physmem.readBursts 410528 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 164568 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26267072 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue +system.physmem.bytesWritten 10385920 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26273792 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10532352 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2261 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 6311 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25881 # Per bank write bursts +system.physmem.perBankRdBursts::1 25672 # Per bank write bursts +system.physmem.perBankRdBursts::2 26260 # Per bank write bursts +system.physmem.perBankRdBursts::3 25757 # Per bank write bursts +system.physmem.perBankRdBursts::4 25283 # Per bank write bursts +system.physmem.perBankRdBursts::5 25202 # Per bank write bursts +system.physmem.perBankRdBursts::6 25755 # Per bank write bursts +system.physmem.perBankRdBursts::7 25257 # Per bank write bursts +system.physmem.perBankRdBursts::8 25550 # Per bank write bursts +system.physmem.perBankRdBursts::9 25721 # Per bank write bursts +system.physmem.perBankRdBursts::10 25770 # Per bank write bursts +system.physmem.perBankRdBursts::11 25804 # Per bank write bursts +system.physmem.perBankRdBursts::12 25810 # Per bank write bursts +system.physmem.perBankRdBursts::13 25881 # Per bank write bursts +system.physmem.perBankRdBursts::14 25644 # Per bank write bursts +system.physmem.perBankRdBursts::15 25176 # Per bank write bursts +system.physmem.perBankWrBursts::0 10943 # Per bank write bursts +system.physmem.perBankWrBursts::1 9789 # Per bank write bursts +system.physmem.perBankWrBursts::2 10222 # Per bank write bursts +system.physmem.perBankWrBursts::3 9625 # Per bank write bursts +system.physmem.perBankWrBursts::4 9290 # Per bank write bursts +system.physmem.perBankWrBursts::5 9560 # Per bank write bursts +system.physmem.perBankWrBursts::6 10277 # Per bank write bursts +system.physmem.perBankWrBursts::7 9346 # Per bank write bursts +system.physmem.perBankWrBursts::8 9649 # Per bank write bursts +system.physmem.perBankWrBursts::9 9784 # Per bank write bursts +system.physmem.perBankWrBursts::10 9978 # Per bank write bursts +system.physmem.perBankWrBursts::11 10113 # Per bank write bursts +system.physmem.perBankWrBursts::12 11182 # Per bank write bursts +system.physmem.perBankWrBursts::13 11629 # Per bank write bursts +system.physmem.perBankWrBursts::14 10712 # Per bank write bursts +system.physmem.perBankWrBursts::15 10181 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 1905063366000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1901182789000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410001 # Read request sizes (log2) +system.physmem.readPktSize::6 410528 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122141 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 40469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9026 # What read queue length does an incoming req see +system.physmem.writePktSize::6 164568 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 40637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9157 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -161,192 +158,187 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64430 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 528.357101 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 319.789036 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.784578 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14909 23.14% 23.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11361 17.63% 40.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5102 7.92% 48.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2869 4.45% 53.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2286 3.55% 56.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1687 2.62% 59.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1558 2.42% 61.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1655 2.57% 64.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23003 35.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64430 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5515 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.305712 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2843.118152 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5512 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 12067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67066 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 546.521218 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 334.319778 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 419.846112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14858 22.15% 22.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11363 16.94% 39.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5157 7.69% 46.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2935 4.38% 51.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2350 3.50% 54.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1701 2.54% 57.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1587 2.37% 59.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1704 2.54% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25411 37.89% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67066 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 68.402667 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2725.840527 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5997 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5515 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5515 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.141614 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.970992 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.024334 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4751 86.15% 86.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 123 2.23% 88.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 15 0.27% 88.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 231 4.19% 92.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 39 0.71% 93.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 12 0.22% 93.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 8 0.15% 93.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 4 0.07% 93.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 23 0.42% 94.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.05% 94.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.09% 94.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.04% 94.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 7 0.13% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.05% 94.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.09% 94.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 28 0.51% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 10 0.18% 95.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.04% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 17 0.31% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 177 3.21% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.05% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.04% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.04% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 4 0.07% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.04% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.07% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 5 0.09% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.05% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.09% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 8 0.15% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.04% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.07% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5515 # Writes before turning the bus around for reads -system.physmem.totQLat 3875472500 # Total ticks spent queuing -system.physmem.totMemAccLat 11559353750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2049035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9456.82 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6000 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.046667 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.651184 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 33.190276 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4953 82.55% 82.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 193 3.22% 85.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 289 4.82% 90.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 50 0.83% 91.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 96 1.60% 93.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 44 0.73% 93.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 19 0.32% 94.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 8 0.13% 94.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 23 0.38% 94.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 10 0.17% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 13 0.22% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 6 0.10% 95.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 7 0.12% 95.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 5 0.08% 95.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 20 0.33% 95.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 38 0.63% 96.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 17 0.28% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 12 0.20% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 91 1.52% 98.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 43 0.72% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 17 0.28% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 19 0.32% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 8 0.13% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 2 0.03% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 9 0.15% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 3 0.05% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6000 # Writes before turning the bus around for reads +system.physmem.totQLat 3893190750 # Total ticks spent queuing +system.physmem.totMemAccLat 11588622000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2052115000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9485.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28206.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28235.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 5.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.82 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.54 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.97 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.10 # Average write queue length when enqueuing -system.physmem.readRowHits 369467 # Number of row buffer hits during reads -system.physmem.writeRowHits 98020 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.25 # Row buffer hit rate for writes -system.physmem.avgGap 3579990.62 # Average gap between requests -system.physmem.pageHitRate 87.88 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1804432107750 # Time in different power states -system.physmem.memoryStateTime::REF 63614200000 # Time in different power states +system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing +system.physmem.readRowHits 370176 # Number of row buffer hits during reads +system.physmem.writeRowHits 135461 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 83.46 # Row buffer hit rate for writes +system.physmem.avgGap 3305852.92 # Average gap between requests +system.physmem.pageHitRate 88.29 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1800384684500 # Time in different power states +system.physmem.memoryStateTime::REF 63484720000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37016700250 # Time in different power states +system.physmem.memoryStateTime::ACT 37315104250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 243908280 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 243137160 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 133084875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 132664125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1597408800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1598750400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 384555600 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 406470960 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 124429375200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 124429375200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 57078983475 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 56985810705 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1092967983000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1093049713500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1276835299230 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1276845922050 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.232898 # Core power per rank (mW) -system.physmem.averagePower::1 670.238474 # Core power per rank (mW) -system.cpu0.branchPred.lookups 14962614 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13045209 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 300344 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 9143692 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5116520 # Number of BTB hits +system.physmem.actEnergy::0 252216720 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 254802240 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 137618250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 139029000 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1599522600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1601776800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 512256960 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 539317440 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 124176112320 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 124176112320 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 57055460715 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 57001965930 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1090662047250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1090708972500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1274395234815 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1274421976230 # Total energy per rank (pJ) +system.physmem.averagePower::0 670.316446 # Core power per rank (mW) +system.physmem.averagePower::1 670.330512 # Core power per rank (mW) +system.cpu0.branchPred.lookups 15024669 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13090822 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 302150 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 9266199 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5129053 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 55.956828 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 756655 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 14726 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 55.352286 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 762066 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 14857 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8668714 # DTB read hits -system.cpu0.dtb.read_misses 31568 # DTB read misses -system.cpu0.dtb.read_acv 533 # DTB read access violations -system.cpu0.dtb.read_accesses 683834 # DTB read accesses -system.cpu0.dtb.write_hits 5507711 # DTB write hits -system.cpu0.dtb.write_misses 6832 # DTB write misses -system.cpu0.dtb.write_acv 377 # DTB write access violations -system.cpu0.dtb.write_accesses 235007 # DTB write accesses -system.cpu0.dtb.data_hits 14176425 # DTB hits -system.cpu0.dtb.data_misses 38400 # DTB misses -system.cpu0.dtb.data_acv 910 # DTB access violations -system.cpu0.dtb.data_accesses 918841 # DTB accesses -system.cpu0.itb.fetch_hits 1355401 # ITB hits -system.cpu0.itb.fetch_misses 29256 # ITB misses -system.cpu0.itb.fetch_acv 621 # ITB acv -system.cpu0.itb.fetch_accesses 1384657 # ITB accesses +system.cpu0.dtb.read_hits 8699665 # DTB read hits +system.cpu0.dtb.read_misses 31652 # DTB read misses +system.cpu0.dtb.read_acv 518 # DTB read access violations +system.cpu0.dtb.read_accesses 684964 # DTB read accesses +system.cpu0.dtb.write_hits 5527628 # DTB write hits +system.cpu0.dtb.write_misses 7312 # DTB write misses +system.cpu0.dtb.write_acv 384 # DTB write access violations +system.cpu0.dtb.write_accesses 236678 # DTB write accesses +system.cpu0.dtb.data_hits 14227293 # DTB hits +system.cpu0.dtb.data_misses 38964 # DTB misses +system.cpu0.dtb.data_acv 902 # DTB access violations +system.cpu0.dtb.data_accesses 921642 # DTB accesses +system.cpu0.itb.fetch_hits 1360805 # ITB hits +system.cpu0.itb.fetch_misses 29325 # ITB misses +system.cpu0.itb.fetch_acv 623 # ITB acv +system.cpu0.itb.fetch_accesses 1390130 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -359,467 +351,467 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 108456707 # number of cpu cycles simulated +system.cpu0.numCycles 108792579 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 24325754 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 66694894 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 14962614 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5873175 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 76828249 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1001726 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 825 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 30281 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1454626 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 459540 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 204 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7777949 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 213350 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.icacheStallCycles 24480610 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 66921510 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 15024669 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5891119 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 76960209 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1006918 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 587 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 30320 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1459024 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 459440 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 228 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7808182 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 214478 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 103600342 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.643771 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.943909 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 103893877 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.644133 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.944480 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 91056774 87.89% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 810107 0.78% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1760430 1.70% 90.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 739408 0.71% 91.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2516394 2.43% 93.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 557837 0.54% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 633248 0.61% 94.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 717698 0.69% 95.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4808446 4.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 91308838 87.89% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 814381 0.78% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1763801 1.70% 90.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 741690 0.71% 91.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2523255 2.43% 93.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 561128 0.54% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 635570 0.61% 94.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 719335 0.69% 95.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4825879 4.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 103600342 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.137959 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.614945 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 19762809 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 73625982 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8017389 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1725855 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 468306 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 492047 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 33030 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 58728782 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 102789 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 468306 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 20585060 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 48251734 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17899835 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8819055 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7576350 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 56729728 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 201548 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2018005 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 142949 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 3756211 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 38050244 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 69305662 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 69181835 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 114815 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33467059 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4583177 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1358842 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 197413 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12487165 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8791454 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5770533 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1295730 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 947864 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50680779 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1726956 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 49798033 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 52306 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5972660 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2859786 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1187974 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 103600342 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.480674 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.214257 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 103893877 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.138104 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.615129 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 19900832 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 73745257 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8046257 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1730950 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 470580 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 495026 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 33344 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 58913691 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 103815 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 470580 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 20722206 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 48316669 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17970373 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8856068 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7557979 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 56901533 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 202703 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2015999 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 141191 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 3736855 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 38160864 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 69501237 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 69376844 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 115358 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33567232 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4593624 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1365129 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 198221 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12480015 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8824182 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5791367 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1299957 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 953544 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50831435 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1735186 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 49951846 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 52661 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5989483 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2856975 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1193961 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 103893877 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.480797 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.214404 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 83011266 80.13% 80.13% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 8965198 8.65% 88.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3720190 3.59% 92.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2652497 2.56% 94.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2683429 2.59% 97.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1272361 1.23% 98.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 837773 0.81% 99.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 348219 0.34% 99.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 109409 0.11% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 83240383 80.12% 80.12% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 8994841 8.66% 88.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3729897 3.59% 92.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2662216 2.56% 94.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2692674 2.59% 97.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1272103 1.22% 98.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 842802 0.81% 99.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 349148 0.34% 99.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 109813 0.11% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 103600342 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 103893877 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 174041 19.05% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.05% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 435557 47.67% 66.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 304020 33.28% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 174329 19.02% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 437335 47.71% 66.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 305033 33.28% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 34383436 69.05% 69.05% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 54432 0.11% 69.16% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.16% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 27661 0.06% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.22% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8987932 18.05% 87.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5577936 11.20% 98.47% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 760973 1.53% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 34481483 69.03% 69.04% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 54630 0.11% 69.15% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.15% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 27712 0.06% 69.20% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.20% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.20% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.20% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.21% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9019851 18.06% 87.26% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5598402 11.21% 98.47% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 764115 1.53% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 49798033 # Type of FU issued -system.cpu0.iq.rate 0.459151 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 913618 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018346 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 203658933 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 58161397 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 48529720 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 503398 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 236532 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 231367 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 50437037 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 270834 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 558638 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 49951846 # Type of FU issued +system.cpu0.iq.rate 0.459148 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 916697 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018352 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 204260867 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 58336070 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 48679612 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 506059 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 237571 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 232415 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 50592327 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 272446 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 560089 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1034329 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4271 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 17854 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 485625 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1038811 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4304 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 17864 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 487331 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18828 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348593 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18869 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 349661 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 468306 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 44263410 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1515089 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 55600538 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 120472 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8791454 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5770533 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1526368 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 47186 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1245112 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 17854 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 151677 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 326896 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 478573 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 49327282 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8721913 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 470750 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 470580 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 44276704 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1577501 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 55768983 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 120052 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8824182 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5791367 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1533608 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 47079 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1307470 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 17864 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 152204 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 328517 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 480721 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 49479281 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8753036 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 472564 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3192803 # number of nop insts executed -system.cpu0.iew.exec_refs 14249477 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7854369 # Number of branches executed -system.cpu0.iew.exec_stores 5527564 # Number of stores executed -system.cpu0.iew.exec_rate 0.454811 # Inst execution rate -system.cpu0.iew.wb_sent 48871282 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 48761087 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25232648 # num instructions producing a value -system.cpu0.iew.wb_consumers 34850080 # num instructions consuming a value +system.cpu0.iew.exec_nop 3202362 # number of nop insts executed +system.cpu0.iew.exec_refs 14301032 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7879408 # Number of branches executed +system.cpu0.iew.exec_stores 5547996 # Number of stores executed +system.cpu0.iew.exec_rate 0.454804 # Inst execution rate +system.cpu0.iew.wb_sent 49022541 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 48912027 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25297454 # num instructions producing a value +system.cpu0.iew.wb_consumers 34938196 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.wb_rate 0.449590 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.724034 # average fanout of values written-back +system.cpu0.iew.wb_fanout 0.724063 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6529157 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 538982 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 437949 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 102449449 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.477940 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.411753 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6548409 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 541225 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 440159 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 102738863 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.478033 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.411836 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 85074848 83.04% 83.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6905483 6.74% 89.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3794087 3.70% 93.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1998795 1.95% 95.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1509892 1.47% 96.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 553563 0.54% 97.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 413229 0.40% 97.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 408476 0.40% 98.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1791076 1.75% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 85310078 83.04% 83.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6928869 6.74% 89.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3804927 3.70% 93.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2004533 1.95% 95.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1514323 1.47% 96.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 555844 0.54% 97.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 414883 0.40% 97.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 408778 0.40% 98.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1796628 1.75% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 102449449 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 48964739 # Number of instructions committed -system.cpu0.commit.committedOps 48964739 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 102738863 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 49112602 # Number of instructions committed +system.cpu0.commit.committedOps 49112602 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13042033 # Number of memory references committed -system.cpu0.commit.loads 7757125 # Number of loads committed -system.cpu0.commit.membars 182252 # Number of memory barriers committed -system.cpu0.commit.branches 7421354 # Number of branches committed -system.cpu0.commit.fp_insts 228314 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 45387875 # Number of committed integer instructions. -system.cpu0.commit.function_calls 614232 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2794177 5.71% 5.71% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 32097051 65.55% 71.26% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 53183 0.11% 71.37% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.37% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 27190 0.06% 71.42% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.42% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.42% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.42% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.43% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7939377 16.21% 87.64% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5290905 10.81% 98.45% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 760973 1.55% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13089407 # Number of memory references committed +system.cpu0.commit.loads 7785371 # Number of loads committed +system.cpu0.commit.membars 183023 # Number of memory barriers committed +system.cpu0.commit.branches 7443994 # Number of branches committed +system.cpu0.commit.fp_insts 229281 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 45524861 # Number of committed integer instructions. +system.cpu0.commit.function_calls 617737 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2801788 5.70% 5.70% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 32185758 65.53% 71.24% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 53394 0.11% 71.35% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.35% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 27239 0.06% 71.40% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.40% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.40% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.40% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.41% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7968394 16.22% 87.63% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5310031 10.81% 98.44% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 764115 1.56% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 48964739 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1791076 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 49112602 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1796628 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 155949601 # The number of ROB reads -system.cpu0.rob.rob_writes 112132496 # The number of ROB writes -system.cpu0.timesIdled 444606 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 4856365 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3701678908 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 46174329 # Number of Instructions Simulated -system.cpu0.committedOps 46174329 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.348853 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.348853 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.425740 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.425740 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 65048250 # number of integer regfile reads -system.cpu0.int_regfile_writes 35377381 # number of integer regfile writes -system.cpu0.fp_regfile_reads 113752 # number of floating regfile reads -system.cpu0.fp_regfile_writes 114375 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1675774 # number of misc regfile reads -system.cpu0.misc_regfile_writes 759002 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1223787 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.953471 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9930066 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1224299 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.110818 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 156399894 # The number of ROB reads +system.cpu0.rob.rob_writes 112470885 # The number of ROB writes +system.cpu0.timesIdled 448982 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 4898702 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3693581898 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 46314581 # Number of Instructions Simulated +system.cpu0.committedOps 46314581 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.348992 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.348992 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.425715 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.425715 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 65241971 # number of integer regfile reads +system.cpu0.int_regfile_writes 35484902 # number of integer regfile writes +system.cpu0.fp_regfile_reads 114300 # number of floating regfile reads +system.cpu0.fp_regfile_writes 114851 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1680980 # number of misc regfile reads +system.cpu0.misc_regfile_writes 762179 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1226061 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.967877 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9972327 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1226573 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.130235 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 25151000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.953471 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988190 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988190 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.967877 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988219 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988219 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 236 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 53654077 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 53654077 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6167393 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6167393 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3426848 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3426848 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 149101 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 149101 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171294 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 171294 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9594241 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9594241 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9594241 # number of overall hits -system.cpu0.dcache.overall_hits::total 9594241 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1498647 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1498647 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1667216 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1667216 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19081 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19081 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4721 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 4721 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3165863 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3165863 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3165863 # number of overall misses -system.cpu0.dcache.overall_misses::total 3165863 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39188841077 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 39188841077 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77581958562 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 77581958562 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 288599741 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 288599741 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 35650235 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 35650235 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 116770799639 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 116770799639 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 116770799639 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 116770799639 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7666040 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7666040 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5094064 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5094064 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 168182 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 168182 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176015 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 176015 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12760104 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12760104 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12760104 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12760104 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195492 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.195492 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.327286 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.327286 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113454 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113454 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026822 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026822 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248106 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248106 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248106 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248106 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26149.480883 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26149.480883 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46533.837584 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 46533.837584 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15124.979875 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15124.979875 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7551.416014 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7551.416014 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36884.350220 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36884.350220 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36884.350220 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36884.350220 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3791444 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2983 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 159835 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 87 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.720987 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 34.287356 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 53849509 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 53849509 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6192446 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6192446 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3442531 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3442531 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 150135 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 150135 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 172107 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 172107 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9634977 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9634977 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9634977 # number of overall hits +system.cpu0.dcache.overall_hits::total 9634977 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1501821 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1501821 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1669841 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1669841 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19141 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19141 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4636 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 4636 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3171662 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3171662 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3171662 # number of overall misses +system.cpu0.dcache.overall_misses::total 3171662 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39101656628 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 39101656628 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78115764371 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 78115764371 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 290102987 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 290102987 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 35172730 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 35172730 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 117217420999 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 117217420999 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 117217420999 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 117217420999 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7694267 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7694267 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5112372 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5112372 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 169276 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 169276 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176743 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 176743 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12806639 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12806639 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12806639 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12806639 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195187 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.195187 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.326627 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.326627 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113076 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113076 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026230 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026230 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247658 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.247658 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247658 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.247658 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26036.163183 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26036.163183 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46780.360748 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 46780.360748 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15156.104018 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15156.104018 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7586.870147 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7586.870147 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36957.727841 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36957.727841 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36957.727841 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36957.727841 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 3837622 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3343 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 160954 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 89 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.842974 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 37.561798 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 710527 # number of writebacks -system.cpu0.dcache.writebacks::total 710527 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 518299 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 518299 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1417662 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1417662 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4443 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4443 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1935961 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1935961 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1935961 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1935961 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 980348 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 980348 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249554 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249554 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14638 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14638 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4721 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 4721 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1229902 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1229902 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1229902 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1229902 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27067717433 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27067717433 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11277928082 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11277928082 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 147839258 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147839258 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26206765 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26206765 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38345645515 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38345645515 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38345645515 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38345645515 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1453124500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1453124500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2199080998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2199080998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3652205498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3652205498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127882 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127882 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048989 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048989 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087037 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087037 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026822 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026822 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096387 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.096387 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096387 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.096387 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27610.315350 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27610.315350 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45192.335454 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45192.335454 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10099.689712 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10099.689712 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5551.104639 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5551.104639 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31177.805642 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31177.805642 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31177.805642 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31177.805642 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 711843 # number of writebacks +system.cpu0.dcache.writebacks::total 711843 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 520027 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 520027 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1419840 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1419840 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4544 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4544 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1939867 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1939867 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1939867 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1939867 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 981794 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 981794 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 250001 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250001 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14597 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14597 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4636 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4636 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1231795 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1231795 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1231795 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1231795 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27071690424 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27071690424 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11368022018 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11368022018 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 148174261 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148174261 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25899270 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25899270 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38439712442 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38439712442 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38439712442 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38439712442 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1458085000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1458085000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2211101998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2211101998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3669186998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3669186998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127601 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127601 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048901 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048901 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086232 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086232 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026230 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026230 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096184 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096184 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096184 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096184 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27573.697154 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27573.697154 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45471.906184 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45471.906184 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10151.007810 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10151.007810 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5586.555220 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5586.555220 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31206.257894 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31206.257894 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31206.257894 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31206.257894 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -827,126 +819,126 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 815495 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.595712 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6922237 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 816007 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.483061 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 821620 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.585426 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6946118 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 822130 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.448929 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 26485869250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.595712 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995304 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995304 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 411 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 8594091 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 8594091 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6922237 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6922237 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6922237 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6922237 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6922237 # number of overall hits -system.cpu0.icache.overall_hits::total 6922237 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 855710 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 855710 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 855710 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 855710 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 855710 # number of overall misses -system.cpu0.icache.overall_misses::total 855710 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12231378721 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12231378721 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12231378721 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12231378721 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12231378721 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12231378721 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7777947 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7777947 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7777947 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7777947 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7777947 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7777947 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110017 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.110017 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110017 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.110017 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110017 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.110017 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14293.836371 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14293.836371 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14293.836371 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14293.836371 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14293.836371 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14293.836371 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4554 # number of cycles access was blocked +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.585426 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995284 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995284 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 431 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8630516 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8630516 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6946118 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6946118 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6946118 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6946118 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6946118 # number of overall hits +system.cpu0.icache.overall_hits::total 6946118 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 862061 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 862061 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 862061 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 862061 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 862061 # number of overall misses +system.cpu0.icache.overall_misses::total 862061 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12338398473 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12338398473 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12338398473 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12338398473 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12338398473 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12338398473 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7808179 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7808179 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7808179 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7808179 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7808179 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7808179 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110405 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.110405 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110405 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.110405 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110405 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.110405 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14312.674478 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14312.674478 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14312.674478 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14312.674478 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14312.674478 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14312.674478 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4878 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 181 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 185 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.160221 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.367568 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 39566 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 39566 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 39566 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 39566 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 39566 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 39566 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 816144 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 816144 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 816144 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 816144 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 816144 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 816144 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10088624022 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10088624022 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10088624022 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10088624022 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10088624022 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10088624022 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.104931 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.104931 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.104931 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.104931 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.104931 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.104931 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12361.328420 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12361.328420 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12361.328420 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12361.328420 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12361.328420 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12361.328420 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 39724 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 39724 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 39724 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 39724 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 39724 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 39724 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 822337 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 822337 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 822337 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 822337 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 822337 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 822337 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10177943027 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10177943027 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10177943027 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10177943027 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10177943027 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10177943027 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105317 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105317 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105317 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.105317 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105317 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.105317 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12376.851616 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12376.851616 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12376.851616 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12376.851616 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12376.851616 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12376.851616 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 4639832 # Number of BP lookups -system.cpu1.branchPred.condPredicted 4063901 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 82203 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2874870 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1132301 # Number of BTB hits +system.cpu1.branchPred.lookups 4575539 # Number of BP lookups +system.cpu1.branchPred.condPredicted 4011453 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 80159 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2846769 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1118608 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 39.386164 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 224009 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7064 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 39.293950 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 219011 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 6943 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2413283 # DTB read hits -system.cpu1.dtb.read_misses 10075 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 292262 # DTB read accesses -system.cpu1.dtb.write_hits 1597058 # DTB write hits -system.cpu1.dtb.write_misses 2093 # DTB write misses -system.cpu1.dtb.write_acv 37 # DTB write access violations -system.cpu1.dtb.write_accesses 110264 # DTB write accesses -system.cpu1.dtb.data_hits 4010341 # DTB hits -system.cpu1.dtb.data_misses 12168 # DTB misses +system.cpu1.dtb.read_hits 2376918 # DTB read hits +system.cpu1.dtb.read_misses 9978 # DTB read misses +system.cpu1.dtb.read_acv 5 # DTB read access violations +system.cpu1.dtb.read_accesses 290947 # DTB read accesses +system.cpu1.dtb.write_hits 1576285 # DTB write hits +system.cpu1.dtb.write_misses 2026 # DTB write misses +system.cpu1.dtb.write_acv 38 # DTB write access violations +system.cpu1.dtb.write_accesses 109535 # DTB write accesses +system.cpu1.dtb.data_hits 3953203 # DTB hits +system.cpu1.dtb.data_misses 12004 # DTB misses system.cpu1.dtb.data_acv 43 # DTB access violations -system.cpu1.dtb.data_accesses 402526 # DTB accesses -system.cpu1.itb.fetch_hits 608432 # ITB hits -system.cpu1.itb.fetch_misses 5602 # ITB misses -system.cpu1.itb.fetch_acv 65 # ITB acv -system.cpu1.itb.fetch_accesses 614034 # ITB accesses +system.cpu1.dtb.data_accesses 400482 # DTB accesses +system.cpu1.itb.fetch_hits 602928 # ITB hits +system.cpu1.itb.fetch_misses 5576 # ITB misses +system.cpu1.itb.fetch_acv 51 # ITB acv +system.cpu1.itb.fetch_accesses 608504 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -959,257 +951,257 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 19085086 # number of cpu cycles simulated +system.cpu1.numCycles 18735029 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8490084 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 17874574 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4639832 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1356310 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9216388 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 327612 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 26792 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 219924 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 67319 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1967111 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 67009 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 18184335 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.982966 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.394246 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8327481 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 17619609 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4575539 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1337619 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9079051 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 321428 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 26636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 222369 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 65129 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1934705 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 65647 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 17881393 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.985360 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.396691 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 15065350 82.85% 82.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 205923 1.13% 83.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 307986 1.69% 85.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 226074 1.24% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 391185 2.15% 89.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 151633 0.83% 89.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 170482 0.94% 90.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 296956 1.63% 92.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1368746 7.53% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 14806869 82.81% 82.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 203122 1.14% 83.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 303524 1.70% 85.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 223355 1.25% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 384843 2.15% 89.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 149669 0.84% 89.88% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 166893 0.93% 90.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 294645 1.65% 92.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1348473 7.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 18184335 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.243113 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.936573 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 6979571 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 8518725 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2274233 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 256003 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 155802 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 137194 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 8084 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 14619784 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 26597 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 155802 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 7159934 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 614392 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6924569 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2350603 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 979033 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 13886683 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 9133 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 71770 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 16856 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 365854 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 9047331 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 16422939 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 16337871 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 78141 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 7835755 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1211576 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 562751 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 58900 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2353285 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2494844 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1679253 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 277357 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 156260 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 12201401 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 661557 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 11978627 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 22551 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1735034 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 788886 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 473891 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 18184335 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.658733 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.375592 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 17881393 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.244224 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.940463 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 6834927 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8400269 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2240291 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 252863 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 153042 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 134285 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7749 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 14408505 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 25621 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 153042 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 7012697 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 586426 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6840794 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2316099 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 972333 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 13683407 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 9781 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 69005 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 16467 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 367791 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 8910587 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 16181694 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 16097130 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 77675 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 7724005 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1186582 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 556647 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 57942 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2323703 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2456737 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1657029 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 275399 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 155321 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 12021391 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 653222 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 11806375 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 22216 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1705669 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 770229 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 468205 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 17881393 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.660260 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.377042 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 13164849 72.40% 72.40% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2231541 12.27% 84.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 929377 5.11% 89.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 639609 3.52% 93.30% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 582340 3.20% 96.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 317160 1.74% 98.24% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 211313 1.16% 99.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 78701 0.43% 99.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 29445 0.16% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 12935770 72.34% 72.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2198264 12.29% 84.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 914656 5.12% 89.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 630896 3.53% 93.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 572849 3.20% 96.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 314457 1.76% 98.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 208202 1.16% 99.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 77174 0.43% 99.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 29125 0.16% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 18184335 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 17881393 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 24291 8.14% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 162499 54.43% 62.57% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 111756 37.43% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 23808 8.12% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 159009 54.21% 62.33% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 110483 37.67% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 3518 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 7464610 62.32% 62.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 20078 0.17% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 12377 0.10% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.63% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2524426 21.07% 83.71% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1623488 13.55% 97.26% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 328371 2.74% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7355530 62.30% 62.33% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 19854 0.17% 62.50% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 12327 0.10% 62.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2486397 21.06% 83.68% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1602376 13.57% 97.25% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 324614 2.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 11978627 # Type of FU issued -system.cpu1.iq.rate 0.627643 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 298546 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.024923 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 42145115 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 14453685 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 11556214 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 317571 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 148430 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 146304 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 12102736 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 170919 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 117615 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 11806375 # Type of FU issued +system.cpu1.iq.rate 0.630176 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 293300 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.024843 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 41494201 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 14236824 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 11389686 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 315458 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 147457 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 145351 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 11926347 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 169810 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 115792 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 314973 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1097 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4259 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 145447 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 308768 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1081 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4102 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 143102 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 424 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 56672 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 395 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 55406 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 155802 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 328818 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 249531 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 13597003 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 38106 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2494844 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1679253 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 593871 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4649 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 243688 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4259 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 37580 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 120039 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 157619 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 11824953 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2433073 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 153674 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 153042 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 303896 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 248843 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 13398271 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 36703 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2456737 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1657029 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 586577 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4501 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 243181 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4102 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 36741 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 118067 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 154808 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 11654930 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2396476 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 151445 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 734045 # number of nop insts executed -system.cpu1.iew.exec_refs 4040076 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1766091 # Number of branches executed -system.cpu1.iew.exec_stores 1607003 # Number of stores executed -system.cpu1.iew.exec_rate 0.619591 # Inst execution rate -system.cpu1.iew.wb_sent 11733612 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 11702518 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5498346 # num instructions producing a value -system.cpu1.iew.wb_consumers 7839453 # num instructions consuming a value +system.cpu1.iew.exec_nop 723658 # number of nop insts executed +system.cpu1.iew.exec_refs 3982565 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1739472 # Number of branches executed +system.cpu1.iew.exec_stores 1586089 # Number of stores executed +system.cpu1.iew.exec_rate 0.622093 # Inst execution rate +system.cpu1.iew.wb_sent 11565622 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 11535037 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5422471 # num instructions producing a value +system.cpu1.iew.wb_consumers 7736628 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.613176 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.701369 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.615694 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.700883 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1874564 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 187666 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 145503 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 17835799 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.653281 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.639800 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1839025 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 185017 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 142916 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 17538839 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.655077 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.643008 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 13664737 76.61% 76.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1906046 10.69% 87.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 699754 3.92% 91.22% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 424730 2.38% 93.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 316948 1.78% 95.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 133544 0.75% 96.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 114109 0.64% 96.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 155571 0.87% 97.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 420360 2.36% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 13431880 76.58% 76.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1875136 10.69% 87.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 688221 3.92% 91.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 418119 2.38% 93.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 312509 1.78% 95.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 131127 0.75% 96.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 110360 0.63% 96.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 156367 0.89% 97.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 415120 2.37% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 17835799 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 11651787 # Number of instructions committed -system.cpu1.commit.committedOps 11651787 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 17538839 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 11489295 # Number of instructions committed +system.cpu1.commit.committedOps 11489295 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3713677 # Number of memory references committed -system.cpu1.commit.loads 2179871 # Number of loads committed -system.cpu1.commit.membars 62781 # Number of memory barriers committed -system.cpu1.commit.branches 1664922 # Number of branches committed -system.cpu1.commit.fp_insts 144632 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 10748857 # Number of committed integer instructions. -system.cpu1.commit.function_calls 187454 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 614300 5.27% 5.27% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 6897823 59.20% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 19873 0.17% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 12372 0.11% 64.75% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.75% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.75% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.75% # Class of committed instruction +system.cpu1.commit.refs 3661896 # Number of memory references committed +system.cpu1.commit.loads 2147969 # Number of loads committed +system.cpu1.commit.membars 61867 # Number of memory barriers committed +system.cpu1.commit.branches 1640602 # Number of branches committed +system.cpu1.commit.fp_insts 143665 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 10598150 # Number of committed integer instructions. +system.cpu1.commit.function_calls 183822 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 606334 5.28% 5.28% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 6800030 59.19% 64.46% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 19654 0.17% 64.63% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.63% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 12323 0.11% 64.74% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.74% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.74% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.74% # Class of committed instruction system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.76% # Class of committed instruction system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.76% # Class of committed instruction system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.76% # Class of committed instruction @@ -1232,190 +1224,190 @@ system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.76% system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.76% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.76% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 2242652 19.25% 84.01% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1534637 13.17% 97.18% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 328371 2.82% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 2209836 19.23% 83.99% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1514745 13.18% 97.17% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 324614 2.83% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 11651787 # Class of committed instruction -system.cpu1.commit.bw_lim_events 420360 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 11489295 # Class of committed instruction +system.cpu1.commit.bw_lim_events 415120 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 30855147 # The number of ROB reads -system.cpu1.rob.rob_writes 27397116 # The number of ROB writes -system.cpu1.timesIdled 166983 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 900751 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3790431319 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 11041005 # Number of Instructions Simulated -system.cpu1.committedOps 11041005 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.728564 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.728564 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.578515 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.578515 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 15169687 # number of integer regfile reads -system.cpu1.int_regfile_writes 8276758 # number of integer regfile writes -system.cpu1.fp_regfile_reads 77475 # number of floating regfile reads -system.cpu1.fp_regfile_writes 77542 # number of floating regfile writes -system.cpu1.misc_regfile_reads 1124650 # number of misc regfile reads -system.cpu1.misc_regfile_writes 280447 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 140166 # number of replacements -system.cpu1.dcache.tags.tagsinuse 492.227589 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3241153 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 140473 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.073139 # Average number of references to valid blocks. +system.cpu1.rob.rob_reads 30366198 # The number of ROB reads +system.cpu1.rob.rob_writes 26995045 # The number of ROB writes +system.cpu1.timesIdled 163095 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 853636 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3782985916 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 10886479 # Number of Instructions Simulated +system.cpu1.committedOps 10886479 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.720945 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.720945 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.581076 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.581076 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 14951888 # number of integer regfile reads +system.cpu1.int_regfile_writes 8155185 # number of integer regfile writes +system.cpu1.fp_regfile_reads 77020 # number of floating regfile reads +system.cpu1.fp_regfile_writes 77068 # number of floating regfile writes +system.cpu1.misc_regfile_reads 1117526 # number of misc regfile reads +system.cpu1.misc_regfile_writes 276759 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 138501 # number of replacements +system.cpu1.dcache.tags.tagsinuse 492.617684 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3193598 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 138812 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.006642 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 39570817000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.227589 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.961382 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.961382 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.599609 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 15302146 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 15302146 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1936775 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1936775 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1212075 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1212075 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 45668 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 45668 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 44613 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 44613 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3148850 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3148850 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3148850 # number of overall hits -system.cpu1.dcache.overall_hits::total 3148850 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 269383 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 269383 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 265424 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 265424 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8139 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8139 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 4996 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 4996 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 534807 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 534807 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 534807 # number of overall misses -system.cpu1.dcache.overall_misses::total 534807 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4084517434 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4084517434 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8552113041 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 8552113041 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77678496 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 77678496 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 36778735 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 36778735 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12636630475 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12636630475 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12636630475 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12636630475 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2206158 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2206158 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1477499 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1477499 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 53807 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 53807 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 49609 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 49609 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3683657 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3683657 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3683657 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3683657 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.122105 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.122105 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.179644 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.179644 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.151263 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.151263 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100708 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100708 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.145184 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.145184 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.145184 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.145184 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15162.491449 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15162.491449 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32220.571768 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32220.571768 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9543.985256 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9543.985256 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7361.636309 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7361.636309 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23628.393935 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23628.393935 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23628.393935 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23628.393935 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 376916 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 344 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 18544 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.325496 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 31.272727 # average number of cycles each access was blocked +system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.617684 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.962144 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.962144 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 15087685 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 15087685 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1906947 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1906947 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1195571 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1195571 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 44901 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 44901 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 43886 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 43886 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3102518 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3102518 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3102518 # number of overall hits +system.cpu1.dcache.overall_hits::total 3102518 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 266692 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 266692 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 262982 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 262982 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8052 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8052 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 4916 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 4916 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 529674 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 529674 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 529674 # number of overall misses +system.cpu1.dcache.overall_misses::total 529674 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4020623652 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4020623652 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8531401983 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 8531401983 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 76759992 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 76759992 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 36344731 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 36344731 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12552025635 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12552025635 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12552025635 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12552025635 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2173639 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2173639 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1458553 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1458553 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 52953 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 52953 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 48802 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 48802 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3632192 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3632192 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3632192 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3632192 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.122694 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.122694 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.180303 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.180303 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152059 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152059 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100734 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100734 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.145828 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.145828 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.145828 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.145828 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15075.906484 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15075.906484 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32441.011107 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32441.011107 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9533.034277 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9533.034277 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7393.151139 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7393.151139 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23697.643522 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23697.643522 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23697.643522 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23697.643522 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 379144 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 215 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 18342 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 9 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.670810 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 23.888889 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 94206 # number of writebacks -system.cpu1.dcache.writebacks::total 94206 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 165989 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 165989 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 215339 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 215339 # number of WriteReq MSHR hits +system.cpu1.dcache.writebacks::writebacks 93139 # number of writebacks +system.cpu1.dcache.writebacks::total 93139 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 164682 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 164682 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 213530 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 213530 # number of WriteReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 655 # number of LoadLockedReq MSHR hits system.cpu1.dcache.LoadLockedReq_mshr_hits::total 655 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 381328 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 381328 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 381328 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 381328 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 103394 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 103394 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 50085 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 50085 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7484 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7484 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 4996 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 4996 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 153479 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 153479 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 153479 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 153479 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1212902508 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1212902508 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1317911046 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1317911046 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 54853004 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 54853004 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 26784265 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 26784265 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2530813554 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2530813554 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2530813554 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2530813554 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29140000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29140000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 708818500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 708818500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 737958500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 737958500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.046866 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.046866 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033899 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033899 # 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average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26313.487990 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26313.487990 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7329.369856 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7329.369856 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.141914 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.141914 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16489.640628 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16489.640628 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16489.640628 # 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number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 4916 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 4916 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 151462 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 151462 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 151462 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 151462 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1194457513 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1194457513 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1312928589 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1312928589 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 54001007 # 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average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13451.169159 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13451.169159 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13451.169159 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 528 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 24 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.208333 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.307692 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9701 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 9701 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 9701 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 9701 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 9701 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 9701 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 313325 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 313325 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 313325 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 313325 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 313325 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 313325 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3639863451 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3639863451 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3639863451 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3639863451 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3639863451 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3639863451 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.159282 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.159282 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.159282 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.159282 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.159282 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.159282 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11616.894442 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11616.894442 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11616.894442 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9341 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 9341 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 9341 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 9341 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 9341 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 9341 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 306705 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 306705 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 306705 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 306705 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 306705 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 306705 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3543296218 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3543296218 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3543296218 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3543296218 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3543296218 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3543296218 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.158528 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.158528 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.158528 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.158528 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.158528 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.158528 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11552.782700 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11552.782700 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11552.782700 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11552.782700 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11552.782700 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11552.782700 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1524,13 +1517,13 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7369 # Transaction distribution -system.iobus.trans_dist::ReadResp 7369 # Transaction distribution -system.iobus.trans_dist::WriteReq 55215 # Transaction distribution -system.iobus.trans_dist::WriteResp 55217 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 2 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 464 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7368 # Transaction distribution +system.iobus.trans_dist::ReadResp 7368 # Transaction distribution +system.iobus.trans_dist::WriteReq 55198 # Transaction distribution +system.iobus.trans_dist::WriteResp 13646 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13082 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1541,12 +1534,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 41714 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125172 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 52504 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 41682 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 125132 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 52328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1557,13 +1550,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 78682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2740322 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12481000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 78554 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2740162 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12437000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 347000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1583,277 +1576,285 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374418188 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406224779 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28049000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28036000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42021755 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42010550 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41697 # number of replacements -system.iocache.tags.tagsinuse 0.496947 # Cycle average of tags in use +system.iocache.tags.replacements 41693 # number of replacements +system.iocache.tags.tagsinuse 0.465320 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41713 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41709 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710336805000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.496947 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.031059 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.031059 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710336865000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.465320 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.029083 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.029083 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375577 # Number of tag accesses -system.iocache.tags.data_accesses 375577 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses -system.iocache.ReadReq_misses::total 177 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 2 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 2 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 177 # number of demand (read+write) misses -system.iocache.demand_misses::total 177 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 177 # number of overall misses -system.iocache.overall_misses::total 177 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21586383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21586383 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21586383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21586383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21586383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21586383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41554 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41554 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 177 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 177 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 177 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 177 # number of overall (read+write) accesses +system.iocache.tags.tag_accesses 375525 # Number of tag accesses +system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses +system.iocache.ReadReq_misses::total 173 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses +system.iocache.demand_misses::total 173 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 173 # number of overall misses +system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13658910846 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13658910846 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21134383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21134383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21134383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21134383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000048 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000048 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121956.966102 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 121956.966102 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 121956.966102 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 121956.966102 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 121956.966102 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 121956.966102 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328718.493598 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328718.493598 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122164.063584 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122164.063584 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122164.063584 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122164.063584 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 207096 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23572 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.785678 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 41552 # number of fast writes performed +system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 177 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 177 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 177 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12381383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12381383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512854560 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512854560 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12381383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12381383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12381383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12381383 # number of overall MSHR miss cycles +system.iocache.writebacks::writebacks 41520 # number of writebacks +system.iocache.writebacks::total 41520 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11498106946 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11498106946 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12137383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12137383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12137383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12137383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 69951.316384 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # 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average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70158.283237 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70158.283237 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 344236 # number of replacements -system.l2c.tags.tagsinuse 65255.823465 # Cycle average of tags in use -system.l2c.tags.total_refs 2587778 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 409374 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.321305 # Average number of references to valid blocks. +system.l2c.tags.replacements 345011 # number of replacements +system.l2c.tags.tagsinuse 65255.839207 # Cycle average of tags in use +system.l2c.tags.total_refs 2587062 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 410177 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.307184 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 7093665750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53392.763161 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5322.213179 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6227.888257 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 220.740542 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 92.218326 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.814709 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081211 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.095030 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003368 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001407 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 53401.606938 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5320.695867 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6228.167915 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 214.693065 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 90.675422 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.814844 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.081187 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.095034 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003276 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001384 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.995725 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65138 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 3694 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 4797 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4255 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52162 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.993927 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27098951 # Number of tag accesses -system.l2c.tags.data_accesses 27098951 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 802459 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 696077 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 311437 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 94339 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1904312 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 804733 # 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number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 745 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1481 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113374 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7659 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121033 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13534 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 386573 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1862 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8566 # number of demand (read+write) misses -system.l2c.demand_misses::total 410535 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13534 # number of overall misses -system.l2c.overall_misses::cpu0.data 386573 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1862 # 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number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 147621500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 877698956 # number of overall miss cycles -system.l2c.overall_miss_latency::total 29404319549 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 815993 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 969276 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 313299 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 95246 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2193814 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 804733 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 804733 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3036 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1993 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5029 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 788 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 771 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1559 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 251654 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 42468 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 294122 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 815993 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1220930 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 313299 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 137714 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2487936 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 815993 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1220930 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 313299 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 137714 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2487936 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.016586 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.281859 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005943 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.009523 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.131963 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.945323 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.783743 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.881289 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.934010 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.966278 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.949968 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.450515 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.180348 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.411506 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.016586 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.316622 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005943 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.062201 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.165010 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.016586 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.316622 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005943 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.062201 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.165010 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76890.756613 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 65708.802924 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 79281.149302 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 88322.489526 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 66389.692465 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 382.040070 # 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Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 975389 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1100201 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 78554 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31488576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31567130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36884698 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 18563 # Total snoops (count) +system.membus.snoop_fanout::samples 600049 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 557285 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 600049 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 557285 # Request fanout histogram -system.membus.reqLayer0.occupancy 40450499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 600049 # Request fanout histogram +system.membus.reqLayer0.occupancy 40411498 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1545398747 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1927899500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 102000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 99500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3825672402 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3832783452 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43153245 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43159450 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2231724 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2231628 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13665 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13665 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 804733 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 14709 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 9717 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 24426 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295921 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295921 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1632137 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3219560 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 626624 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 407513 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5885834 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 52223552 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 123671600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20051136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 14868394 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 210814682 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 92075 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3391171 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012307 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.110253 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2231232 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2231137 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13646 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13646 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 804982 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 14411 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 9552 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 23963 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296031 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296031 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 79 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1644513 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3224840 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 613391 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 402307 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5885051 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 52619264 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 123882452 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19627904 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 14694726 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 210824346 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 91368 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3390565 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012306 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.110249 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3349435 98.77% 98.77% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41736 1.23% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3348840 98.77% 98.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41725 1.23% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3391171 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4911486557 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3390565 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4912159072 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 706500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3677796473 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3705712969 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5655554210 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5664612723 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1411093549 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1381251781 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 701201756 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 692182943 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2119,161 +2120,161 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6701 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 170162 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 59106 40.33% 40.33% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.42% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1925 1.31% 41.73% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 339 0.23% 41.96% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 85060 58.04% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 146561 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 58406 49.14% 49.14% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6735 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 170888 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 59399 40.36% 40.36% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.45% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1921 1.31% 41.76% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 339 0.23% 41.99% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 85372 58.01% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 147162 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 58699 49.14% 49.14% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.11% 49.25% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1925 1.62% 50.86% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 339 0.29% 51.15% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 58067 48.85% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 118868 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1864755925000 97.88% 97.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 61031500 0.00% 97.89% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 543238000 0.03% 97.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 152147500 0.01% 97.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 39554606000 2.08% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1905066948000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.988157 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1921 1.61% 50.86% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 339 0.28% 51.14% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 58360 48.86% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 119450 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1860822176500 97.88% 97.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 61176000 0.00% 97.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 541931500 0.03% 97.91% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 152116500 0.01% 97.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 39608995500 2.08% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1901186396000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.988215 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682659 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811048 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed -system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 225 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.683596 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811691 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.22% 28.02% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.45% # number of syscalls executed +system.cpu0.kern.syscall::17 9 3.88% 32.33% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.31% 36.64% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.59% 39.22% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.66% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.29% 40.95% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.02% 43.97% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.86% 44.83% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.81% 61.64% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.29% 62.93% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.31% 67.24% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.31% 71.55% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 71.98% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.59% 74.57% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.64% 86.21% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.29% 87.50% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.02% 90.52% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 90.95% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.29% 92.24% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.88% 96.12% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.86% 96.98% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.86% 97.84% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.28% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.86% 99.14% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 232 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 439 0.28% 0.28% # number of callpals executed +system.cpu0.kern.callpal::wripir 432 0.28% 0.28% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.28% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.29% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3223 2.08% 2.37% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.28% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.28% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3241 2.09% 2.37% # number of callpals executed system.cpu0.kern.callpal::tbi 50 0.03% 2.40% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.41% # number of callpals executed -system.cpu0.kern.callpal::swpipl 139738 90.30% 92.70% # number of callpals executed -system.cpu0.kern.callpal::rdps 6333 4.09% 96.79% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.79% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.40% # number of callpals executed +system.cpu0.kern.callpal::swpipl 140334 90.29% 92.69% # number of callpals executed +system.cpu0.kern.callpal::rdps 6381 4.11% 96.80% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.80% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.80% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.01% 96.80% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.80% # number of callpals executed -system.cpu0.kern.callpal::rti 4427 2.86% 99.66% # number of callpals executed -system.cpu0.kern.callpal::callsys 382 0.25% 99.91% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.81% # number of callpals executed +system.cpu0.kern.callpal::rti 4436 2.85% 99.66% # number of callpals executed +system.cpu0.kern.callpal::callsys 391 0.25% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 154756 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6973 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1341 # number of protection mode switches +system.cpu0.kern.callpal::total 155429 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7000 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1355 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1340 -system.cpu0.kern.mode_good::user 1341 +system.cpu0.kern.mode_good::kernel 1354 +system.cpu0.kern.mode_good::user 1355 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.192170 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.193429 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.322468 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1903068198000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1998742000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.324237 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1899184407000 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2001981000 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3224 # number of times the context was actually changed +system.cpu0.kern.swap_context 3242 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2621 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 71304 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 23839 38.11% 38.11% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1924 3.08% 41.19% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 439 0.70% 41.89% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 36346 58.11% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 62548 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 23162 48.01% 48.01% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1924 3.99% 51.99% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 439 0.91% 52.90% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 22723 47.10% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 48248 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1872982420000 98.33% 98.33% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 531501500 0.03% 98.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 197949500 0.01% 98.37% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 31046317000 1.63% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1904758188000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.971601 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2589 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 70429 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 23508 38.03% 38.03% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1920 3.11% 41.14% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 432 0.70% 41.84% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 35949 58.16% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 61809 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 22831 47.98% 47.98% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1920 4.04% 52.02% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 432 0.91% 52.93% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 22399 47.07% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 47582 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1869145937500 98.33% 98.33% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 530408500 0.03% 98.36% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 194479500 0.01% 98.37% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 30989632500 1.63% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1900860458000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.971201 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.625186 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.771376 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed -system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed -system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed -system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 101 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.623077 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.769823 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed +system.cpu1.kern.syscall::17 6 6.38% 27.66% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.19% 30.85% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.19% 34.04% # number of syscalls executed +system.cpu1.kern.syscall::33 4 4.26% 38.30% # number of syscalls executed +system.cpu1.kern.syscall::45 15 15.96% 54.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.19% 57.45% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.06% 58.51% # number of syscalls executed +system.cpu1.kern.syscall::71 27 28.72% 87.23% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.57% 96.81% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 94 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 339 0.52% 0.52% # number of callpals executed +system.cpu1.kern.callpal::wripir 339 0.53% 0.53% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.53% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.53% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1674 2.58% 3.11% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.11% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.13% # number of callpals executed -system.cpu1.kern.callpal::swpipl 56749 87.55% 90.68% # number of callpals executed -system.cpu1.kern.callpal::rdps 2425 3.74% 94.42% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.42% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.42% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.43% # number of callpals executed -system.cpu1.kern.callpal::rti 3435 5.30% 99.73% # number of callpals executed -system.cpu1.kern.callpal::callsys 133 0.21% 99.93% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1656 2.59% 3.12% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.13% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.14% # number of callpals executed +system.cpu1.kern.callpal::swpipl 56045 87.56% 90.70% # number of callpals executed +system.cpu1.kern.callpal::rdps 2366 3.70% 94.40% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.40% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.41% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.41% # number of callpals executed +system.cpu1.kern.callpal::rti 3411 5.33% 99.74% # number of callpals executed +system.cpu1.kern.callpal::callsys 124 0.19% 99.93% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.07% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 64819 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1725 # number of protection mode switches -system.cpu1.kern.mode_switch::user 395 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2719 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 758 -system.cpu1.kern.mode_good::user 395 -system.cpu1.kern.mode_good::idle 363 -system.cpu1.kern.mode_switch_good::kernel 0.439420 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 64005 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1702 # number of protection mode switches +system.cpu1.kern.mode_switch::user 384 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2700 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 740 +system.cpu1.kern.mode_good::user 384 +system.cpu1.kern.mode_good::idle 356 +system.cpu1.kern.mode_switch_good::kernel 0.434783 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.133505 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.313288 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 6292990000 0.33% 0.33% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 709362000 0.04% 0.37% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1897439269000 99.63% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1675 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.131852 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.309235 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 6130779500 0.32% 0.32% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 692688500 0.04% 0.36% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893719133000 99.64% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1657 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 987719302..44e9b2e2b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,114 +1,111 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.859039 # Number of seconds simulated -sim_ticks 1859038679000 # Number of ticks simulated -final_tick 1859038679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.859049 # Number of seconds simulated +sim_ticks 1859049148500 # Number of ticks simulated +final_tick 1859049148500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164458 # Simulator instruction rate (inst/s) -host_op_rate 164458 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5776457310 # Simulator tick rate (ticks/s) -host_mem_usage 314484 # Number of bytes of host memory used -host_seconds 321.83 # Real time elapsed on the host -sim_insts 52927600 # Number of instructions simulated -sim_ops 52927600 # Number of ops (including micro ops) simulated +host_inst_rate 168870 # Simulator instruction rate (inst/s) +host_op_rate 168870 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5931192571 # Simulator tick rate (ticks/s) +host_mem_usage 320216 # Number of bytes of host memory used +host_seconds 313.44 # Real time elapsed on the host +sim_insts 52930035 # Number of instructions simulated +sim_ops 52930035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 968256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24892608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 967168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24875776 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25861824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 968256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 968256 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4860032 # Number of bytes written to this memory -system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7519360 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15129 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388947 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25843904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 967168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 967168 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7516224 # Number of bytes written to this memory +system.physmem.bytes_written::total 7516224 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388684 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404091 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 75938 # Number of write requests responded to by this memory -system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117490 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520837 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13390043 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403811 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117441 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117441 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 520249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13380914 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13911396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520837 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520837 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2614272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1430486 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4044757 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2614272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13390043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1431002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17956154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404091 # Number of read requests accepted -system.physmem.writeReqs 117490 # Number of write requests accepted -system.physmem.readBursts 404091 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117490 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25850368 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11456 # Total number of bytes read from write queue -system.physmem.bytesWritten 7517888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25861824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7519360 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 179 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 193 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25747 # Per bank write bursts -system.physmem.perBankRdBursts::1 25572 # Per bank write bursts -system.physmem.perBankRdBursts::2 25523 # Per bank write bursts -system.physmem.perBankRdBursts::3 25355 # Per bank write bursts -system.physmem.perBankRdBursts::4 25392 # Per bank write bursts -system.physmem.perBankRdBursts::5 24811 # Per bank write bursts -system.physmem.perBankRdBursts::6 25029 # Per bank write bursts -system.physmem.perBankRdBursts::7 25134 # Per bank write bursts -system.physmem.perBankRdBursts::8 24968 # Per bank write bursts -system.physmem.perBankRdBursts::9 25052 # Per bank write bursts -system.physmem.perBankRdBursts::10 25439 # Per bank write bursts -system.physmem.perBankRdBursts::11 24779 # Per bank write bursts -system.physmem.perBankRdBursts::12 24568 # Per bank write bursts -system.physmem.perBankRdBursts::13 25250 # Per bank write bursts -system.physmem.perBankRdBursts::14 25688 # Per bank write bursts -system.physmem.perBankRdBursts::15 25605 # Per bank write bursts -system.physmem.perBankWrBursts::0 8041 # Per bank write bursts -system.physmem.perBankWrBursts::1 7603 # Per bank write bursts -system.physmem.perBankWrBursts::2 7894 # Per bank write bursts -system.physmem.perBankWrBursts::3 7385 # Per bank write bursts -system.physmem.perBankWrBursts::4 7327 # Per bank write bursts -system.physmem.perBankWrBursts::5 6730 # Per bank write bursts -system.physmem.perBankWrBursts::6 6858 # Per bank write bursts -system.physmem.perBankWrBursts::7 6765 # Per bank write bursts -system.physmem.perBankWrBursts::8 7133 # Per bank write bursts -system.physmem.perBankWrBursts::9 6722 # Per bank write bursts -system.physmem.perBankWrBursts::10 7301 # Per bank write bursts -system.physmem.perBankWrBursts::11 6871 # Per bank write bursts -system.physmem.perBankWrBursts::12 7190 # Per bank write bursts -system.physmem.perBankWrBursts::13 7853 # Per bank write bursts -system.physmem.perBankWrBursts::14 7964 # Per bank write bursts -system.physmem.perBankWrBursts::15 7830 # Per bank write bursts +system.physmem.bw_read::total 13901679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 520249 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520249 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4043047 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4043047 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4043047 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 520249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13380914 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17944726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403811 # Number of read requests accepted +system.physmem.writeReqs 158993 # Number of write requests accepted +system.physmem.readBursts 403811 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 158993 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25836928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue +system.physmem.bytesWritten 10037376 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25843904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10175552 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2130 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 189 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25744 # Per bank write bursts +system.physmem.perBankRdBursts::1 25560 # Per bank write bursts +system.physmem.perBankRdBursts::2 25512 # Per bank write bursts +system.physmem.perBankRdBursts::3 25342 # Per bank write bursts +system.physmem.perBankRdBursts::4 25388 # Per bank write bursts +system.physmem.perBankRdBursts::5 24802 # Per bank write bursts +system.physmem.perBankRdBursts::6 25022 # Per bank write bursts +system.physmem.perBankRdBursts::7 25128 # Per bank write bursts +system.physmem.perBankRdBursts::8 24929 # Per bank write bursts +system.physmem.perBankRdBursts::9 25033 # Per bank write bursts +system.physmem.perBankRdBursts::10 25435 # Per bank write bursts +system.physmem.perBankRdBursts::11 24778 # Per bank write bursts +system.physmem.perBankRdBursts::12 24542 # Per bank write bursts +system.physmem.perBankRdBursts::13 25239 # Per bank write bursts +system.physmem.perBankRdBursts::14 25649 # Per bank write bursts +system.physmem.perBankRdBursts::15 25599 # Per bank write bursts +system.physmem.perBankWrBursts::0 10531 # Per bank write bursts +system.physmem.perBankWrBursts::1 10049 # Per bank write bursts +system.physmem.perBankWrBursts::2 10576 # Per bank write bursts +system.physmem.perBankWrBursts::3 9740 # Per bank write bursts +system.physmem.perBankWrBursts::4 9614 # Per bank write bursts +system.physmem.perBankWrBursts::5 9115 # Per bank write bursts +system.physmem.perBankWrBursts::6 9087 # Per bank write bursts +system.physmem.perBankWrBursts::7 8933 # Per bank write bursts +system.physmem.perBankWrBursts::8 9694 # Per bank write bursts +system.physmem.perBankWrBursts::9 8895 # Per bank write bursts +system.physmem.perBankWrBursts::10 9699 # Per bank write bursts +system.physmem.perBankWrBursts::11 9449 # Per bank write bursts +system.physmem.perBankWrBursts::12 10004 # Per bank write bursts +system.physmem.perBankWrBursts::13 10709 # Per bank write bursts +system.physmem.perBankWrBursts::14 10413 # Per bank write bursts +system.physmem.perBankWrBursts::15 10326 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 1859033424000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 1859043836000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404091 # Read request sizes (log2) +system.physmem.readPktSize::6 403811 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117490 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 315071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 37620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see +system.physmem.writePktSize::6 158993 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 37560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 57 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -151,344 +148,189 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 156 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61280 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 544.521149 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 334.160448 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 418.029082 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13483 22.00% 22.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10372 16.93% 38.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4758 7.76% 46.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2785 4.54% 51.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2293 3.74% 54.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1673 2.73% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1477 2.41% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1592 2.60% 62.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22847 37.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61280 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5232 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.198394 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2919.153555 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5229 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::48 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63789 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 562.390130 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 348.747922 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 419.715872 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13502 21.17% 21.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10319 16.18% 37.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4795 7.52% 44.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2857 4.48% 49.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2332 3.66% 53.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1655 2.59% 55.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1501 2.35% 57.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1587 2.49% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25241 39.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63789 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5661 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.309309 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2806.420357 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5658 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5232 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5232 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.451644 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.067800 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.155033 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4469 85.42% 85.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 138 2.64% 88.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 12 0.23% 88.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 232 4.43% 92.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 44 0.84% 93.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.04% 93.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 5 0.10% 93.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.19% 93.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 17 0.32% 94.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.04% 94.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.02% 94.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.04% 94.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 7 0.13% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.06% 94.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.08% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.02% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 28 0.54% 95.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 15 0.29% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 15 0.29% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 171 3.27% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.11% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.04% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.04% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 5 0.10% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 6 0.11% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.08% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 11 0.21% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.04% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 7 0.13% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5232 # Writes before turning the bus around for reads -system.physmem.totQLat 3681492750 # Total ticks spent queuing -system.physmem.totMemAccLat 11254842750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2019560000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9114.59 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5661 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5661 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.704293 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.909682 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 34.456612 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4621 81.63% 81.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 191 3.37% 85.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 281 4.96% 89.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 54 0.95% 90.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 96 1.70% 92.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 48 0.85% 93.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 17 0.30% 93.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 14 0.25% 94.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 19 0.34% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.09% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 15 0.26% 94.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.07% 94.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 5 0.09% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.04% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 19 0.34% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 42 0.74% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 21 0.37% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 11 0.19% 96.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 96 1.70% 98.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 35 0.62% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 14 0.25% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 13 0.23% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 10 0.18% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 5 0.09% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 5 0.09% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.04% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 5 0.09% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 6 0.11% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5661 # Writes before turning the bus around for reads +system.physmem.totQLat 3666880250 # Total ticks spent queuing +system.physmem.totMemAccLat 11236292750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018510000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9083.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27864.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.91 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.91 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27833.14 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 5.40 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.47 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing -system.physmem.readRowHits 364830 # Number of row buffer hits during reads -system.physmem.writeRowHits 95269 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.32 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.09 # Row buffer hit rate for writes -system.physmem.avgGap 3564227.65 # Average gap between requests -system.physmem.pageHitRate 88.24 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1761056207000 # Time in different power states -system.physmem.memoryStateTime::REF 62077340000 # Time in different power states +system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing +system.physmem.readRowHits 364667 # Number of row buffer hits during reads +system.physmem.writeRowHits 132080 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.20 # Row buffer hit rate for writes +system.physmem.avgGap 3303181.63 # Average gap between requests +system.physmem.pageHitRate 88.62 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1760890123500 # Time in different power states +system.physmem.memoryStateTime::REF 62077600000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 35903990500 # Time in different power states +system.physmem.memoryStateTime::ACT 36077600250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 230322960 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 232953840 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 125672250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 127107750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1579991400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1570522200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 379747440 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 381438720 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 121423277040 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 121423277040 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 55561357620 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 55436078745 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1066684481250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1066794375000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1245984849960 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1245965753295 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.231146 # Core power per rank (mW) -system.physmem.averagePower::1 670.220874 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 296046 # Transaction distribution -system.membus.trans_dist::ReadResp 295957 # Transaction distribution -system.membus.trans_dist::WriteReq 9597 # Transaction distribution -system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 75938 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 188 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.membus.trans_dist::UpgradeResp 193 # Transaction distribution -system.membus.trans_dist::ReadExReq 115222 # Transaction distribution -system.membus.trans_dist::ReadExResp 115222 # Transaction distribution -system.membus.trans_dist::BadAddressError 89 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884476 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 178 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917708 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1001000 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30720896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30765036 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33425324 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 158 # Total snoops (count) -system.membus.snoop_fanout::samples 522030 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 522030 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 522030 # Request fanout histogram -system.membus.reqLayer0.occupancy 31457000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1484421249 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 110500 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3754388311 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43151211 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.260487 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1709355301000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.260487 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078780 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078780 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 376213 # Number of tag accesses -system.iocache.tags.data_accesses 376213 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 86 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 86 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses -system.iocache.demand_misses::total 173 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 173 # number of overall misses -system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41638 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41638 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.002065 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.002065 # miss rate for WriteInvalidateReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 41552 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2529714027 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2529714027 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 17804968 # Number of BP lookups -system.cpu.branchPred.condPredicted 15499600 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 379466 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11923628 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5932721 # Number of BTB hits +system.physmem.actEnergy::0 239795640 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 242449200 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 130840875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 132288750 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 1579484400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 1569391200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 503139600 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 513144720 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 121423785600 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 121423785600 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 55719498420 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 55486362150 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1066550433000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1066754938500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1246146977535 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1246122360120 # Total energy per rank (pJ) +system.physmem.averagePower::0 670.315549 # Core power per rank (mW) +system.physmem.averagePower::1 670.302307 # Core power per rank (mW) +system.cpu.branchPred.lookups 17761302 # Number of BP lookups +system.cpu.branchPred.condPredicted 15456576 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 379954 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12009119 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5937139 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 49.756005 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 914118 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21281 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 49.438589 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 914399 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21305 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10302215 # DTB read hits -system.cpu.dtb.read_misses 41309 # DTB read misses -system.cpu.dtb.read_acv 513 # DTB read access violations -system.cpu.dtb.read_accesses 965594 # DTB read accesses -system.cpu.dtb.write_hits 6646492 # DTB write hits -system.cpu.dtb.write_misses 9371 # DTB write misses -system.cpu.dtb.write_acv 419 # DTB write access violations -system.cpu.dtb.write_accesses 342338 # DTB write accesses -system.cpu.dtb.data_hits 16948707 # DTB hits -system.cpu.dtb.data_misses 50680 # DTB misses -system.cpu.dtb.data_acv 932 # DTB access violations -system.cpu.dtb.data_accesses 1307932 # DTB accesses -system.cpu.itb.fetch_hits 1774610 # ITB hits -system.cpu.itb.fetch_misses 34401 # ITB misses -system.cpu.itb.fetch_acv 653 # ITB acv -system.cpu.itb.fetch_accesses 1809011 # ITB accesses +system.cpu.dtb.read_hits 10308188 # DTB read hits +system.cpu.dtb.read_misses 41379 # DTB read misses +system.cpu.dtb.read_acv 521 # DTB read access violations +system.cpu.dtb.read_accesses 967155 # DTB read accesses +system.cpu.dtb.write_hits 6646702 # DTB write hits +system.cpu.dtb.write_misses 9325 # DTB write misses +system.cpu.dtb.write_acv 410 # DTB write access violations +system.cpu.dtb.write_accesses 342603 # DTB write accesses +system.cpu.dtb.data_hits 16954890 # DTB hits +system.cpu.dtb.data_misses 50704 # DTB misses +system.cpu.dtb.data_acv 931 # DTB access violations +system.cpu.dtb.data_accesses 1309758 # DTB accesses +system.cpu.itb.fetch_hits 1770443 # ITB hits +system.cpu.itb.fetch_misses 36092 # ITB misses +system.cpu.itb.fetch_acv 664 # ITB acv +system.cpu.itb.fetch_accesses 1806535 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -501,254 +343,254 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 118301061 # number of cpu cycles simulated +system.cpu.numCycles 118298016 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29562966 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78094807 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17804968 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6846839 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80553195 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1252096 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1416 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 27926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1649882 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 450417 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9025532 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 274121 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 112872082 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.691888 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.011514 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29541198 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78055768 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17761302 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6851538 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80476428 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1253224 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1384 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 28562 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1737629 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 451562 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 217 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9019799 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 273133 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 112863592 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.691594 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.010851 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 98296528 87.09% 87.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 933530 0.83% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1975700 1.75% 89.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 908755 0.81% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2800334 2.48% 92.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 638924 0.57% 93.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 725896 0.64% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1007040 0.89% 95.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5585375 4.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 98289284 87.09% 87.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 935566 0.83% 87.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1976201 1.75% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 911928 0.81% 90.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2795335 2.48% 92.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 642698 0.57% 93.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 727750 0.64% 94.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1007954 0.89% 95.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5576876 4.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 112872082 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.150506 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.660136 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24068860 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 76820836 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9500551 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1898196 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 583638 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 588301 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42850 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68299285 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 133126 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 583638 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24994916 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 47249741 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20742683 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10385328 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8915774 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65865702 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 202022 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2036806 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 141544 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4770005 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43944287 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79812474 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79631676 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168345 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38137411 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5806868 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1690855 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 241233 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13548292 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10425085 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6927485 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1490397 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1054253 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58626057 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2139161 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57592696 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 51229 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7502337 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3486338 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1478017 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 112872082 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.510247 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.252928 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 112863592 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.150140 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.659823 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24058379 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 76821722 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9496623 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1902660 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 584207 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 588094 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42817 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68303161 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 133250 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 584207 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24982800 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 47259981 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20734687 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10387203 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8914712 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65869472 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 202922 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2041149 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 141248 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4766165 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43946104 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79818079 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79637315 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168311 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38139253 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5806843 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1691151 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 241440 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13536828 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10424364 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6928356 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1483959 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1059889 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58630025 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2138995 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57603342 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 50950 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7503583 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3485287 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1477804 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 112863592 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.510380 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.252962 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 89394835 79.20% 79.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10016384 8.87% 88.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4304507 3.81% 91.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 2950730 2.61% 94.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3082787 2.73% 97.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1592384 1.41% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1013037 0.90% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 395526 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 121892 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 89383207 79.20% 79.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10013548 8.87% 88.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4301377 3.81% 91.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 2962557 2.62% 94.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3086274 2.73% 97.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1586017 1.41% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1012124 0.90% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 396460 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 122028 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 112872082 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 112863592 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 212963 18.82% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 545078 48.16% 66.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 373836 33.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 213045 18.77% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547519 48.24% 67.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 374446 32.99% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39097776 67.89% 67.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61804 0.11% 68.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38376 0.07% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39102059 67.88% 67.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61815 0.11% 68.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38377 0.07% 68.07% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.07% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.07% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10712581 18.60% 86.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6722276 11.67% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 948961 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10718615 18.61% 86.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6722522 11.67% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949032 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57592696 # Type of FU issued -system.cpu.iq.rate 0.486832 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1131877 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019653 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 228528169 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67952558 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55916727 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 712410 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 334609 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328997 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58334880 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 382407 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 639606 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57603342 # Type of FU issued +system.cpu.iq.rate 0.486934 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1135010 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019704 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 228544022 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67957775 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55921178 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 712213 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 334464 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328973 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58348779 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 382287 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 639736 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1340629 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4088 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1339690 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4038 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 20047 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 553798 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 554552 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18287 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 539247 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18285 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 544771 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 583638 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 44307486 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 616008 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64468948 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 145079 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10425085 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6927485 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1890835 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 42893 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 369751 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 584207 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 44318330 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 613096 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64473181 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 145267 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10424364 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6928356 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1890724 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 42751 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 366947 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 20047 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 190429 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 410127 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 600556 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 57009373 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10371242 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 583322 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 190952 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 410451 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 601403 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 57018878 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10377294 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 584463 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3703730 # number of nop insts executed -system.cpu.iew.exec_refs 17042240 # number of memory reference insts executed -system.cpu.iew.exec_branches 8981920 # Number of branches executed -system.cpu.iew.exec_stores 6670998 # Number of stores executed -system.cpu.iew.exec_rate 0.481901 # Inst execution rate -system.cpu.iew.wb_sent 56380366 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56245724 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28936691 # num instructions producing a value -system.cpu.iew.wb_consumers 40310167 # num instructions consuming a value +system.cpu.iew.exec_nop 3704161 # number of nop insts executed +system.cpu.iew.exec_refs 17048455 # number of memory reference insts executed +system.cpu.iew.exec_branches 8982580 # Number of branches executed +system.cpu.iew.exec_stores 6671161 # Number of stores executed +system.cpu.iew.exec_rate 0.481994 # Inst execution rate +system.cpu.iew.wb_sent 56384919 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56250151 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28947314 # num instructions producing a value +system.cpu.iew.wb_consumers 40326252 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.475446 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717851 # average fanout of values written-back +system.cpu.iew.wb_rate 0.475495 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717828 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8239182 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661144 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 548042 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 111437316 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.503568 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.455315 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8239076 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661191 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 548552 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 111427799 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.503633 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.455266 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91810154 82.39% 82.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7802563 7.00% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4132031 3.71% 93.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2155493 1.93% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1853584 1.66% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 616181 0.55% 97.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 467348 0.42% 97.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 515869 0.46% 98.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2084093 1.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91796177 82.38% 82.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7808087 7.01% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4129534 3.71% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2155296 1.93% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1855711 1.67% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 615462 0.55% 97.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 470761 0.42% 97.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 513166 0.46% 98.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2083605 1.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 111437316 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56116260 # Number of instructions committed -system.cpu.commit.committedOps 56116260 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 111427799 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56118765 # Number of instructions committed +system.cpu.commit.committedOps 56118765 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15458143 # Number of memory references committed -system.cpu.commit.loads 9084456 # Number of loads committed -system.cpu.commit.membars 226334 # Number of memory barriers committed -system.cpu.commit.branches 8434463 # Number of branches committed +system.cpu.commit.refs 15458478 # Number of memory references committed +system.cpu.commit.loads 9084674 # Number of loads committed +system.cpu.commit.membars 226351 # Number of memory barriers committed +system.cpu.commit.branches 8434924 # Number of branches committed system.cpu.commit.fp_insts 324518 # Number of committed floating point instructions. -system.cpu.commit.int_insts 51967854 # Number of committed integer instructions. -system.cpu.commit.function_calls 739911 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3195933 5.70% 5.70% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36178550 64.47% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60663 0.11% 70.27% # Class of committed instruction +system.cpu.commit.int_insts 51970227 # Number of committed integer instructions. +system.cpu.commit.function_calls 739937 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3196003 5.70% 5.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36180557 64.47% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60666 0.11% 70.27% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38089 0.07% 70.34% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction @@ -776,66 +618,550 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9310790 16.59% 86.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6379639 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 948960 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9311025 16.59% 86.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6379757 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949032 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56116260 # Class of committed instruction -system.cpu.commit.bw_lim_events 2084093 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 56118765 # Class of committed instruction +system.cpu.commit.bw_lim_events 2083605 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 173459156 # The number of ROB reads -system.cpu.rob.rob_writes 130141826 # The number of ROB writes -system.cpu.timesIdled 576115 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5428979 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599776298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52927600 # Number of Instructions Simulated -system.cpu.committedOps 52927600 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.235149 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.235149 # CPI: Total CPI of All Threads -system.cpu.ipc 0.447398 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.447398 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74648651 # number of integer regfile reads -system.cpu.int_regfile_writes 40584029 # number of integer regfile writes -system.cpu.fp_regfile_reads 166982 # number of floating regfile reads -system.cpu.fp_regfile_writes 167600 # number of floating regfile writes -system.cpu.misc_regfile_reads 2029015 # number of misc regfile reads -system.cpu.misc_regfile_writes 939371 # number of misc regfile writes -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.cpu.rob.rob_reads 173452486 # The number of ROB reads +system.cpu.rob.rob_writes 130147702 # The number of ROB writes +system.cpu.timesIdled 575947 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5434424 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599800282 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52930035 # Number of Instructions Simulated +system.cpu.committedOps 52930035 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.234988 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.234988 # CPI: Total CPI of All Threads +system.cpu.ipc 0.447430 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.447430 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74659793 # number of integer regfile reads +system.cpu.int_regfile_writes 40587610 # number of integer regfile writes +system.cpu.fp_regfile_reads 166949 # number of floating regfile reads +system.cpu.fp_regfile_writes 167607 # number of floating regfile writes +system.cpu.misc_regfile_reads 2029497 # number of misc regfile reads +system.cpu.misc_regfile_writes 939434 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1404580 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994645 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11874772 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1405092 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.451242 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994645 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 413 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 63937777 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63937777 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7284414 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7284414 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4188003 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4188003 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186359 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186359 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215726 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215726 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11472417 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11472417 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11472417 # number of overall hits +system.cpu.dcache.overall_hits::total 11472417 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1780024 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1780024 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1955346 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1955346 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23271 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23271 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3735370 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3735370 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3735370 # number of overall misses +system.cpu.dcache.overall_misses::total 3735370 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39520730746 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39520730746 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 78084026192 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 78084026192 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 364876749 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 364876749 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 441006 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 441006 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117604756938 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117604756938 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117604756938 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117604756938 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9064438 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9064438 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6143349 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6143349 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209630 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209630 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215754 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215754 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15207787 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15207787 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15207787 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15207787 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196374 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.196374 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318287 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318287 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111010 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111010 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.245622 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.245622 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.245622 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.245622 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22202.358365 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22202.358365 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39933.610825 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39933.610825 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15679.461519 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15679.461519 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15750.214286 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15750.214286 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31484.098480 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31484.098480 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31484.098480 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31484.098480 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3992388 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1705 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 180260 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 24 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.147942 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 71.041667 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 842675 # number of writebacks +system.cpu.dcache.writebacks::total 842675 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 683874 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 683874 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664228 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1664228 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5276 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5276 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2348102 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2348102 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2348102 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2348102 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1096150 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1096150 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291118 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 291118 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17995 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17995 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1387268 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1387268 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1387268 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1387268 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27519652282 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27519652282 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11779193020 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11779193020 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204738251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204738251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 384994 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 384994 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39298845302 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 39298845302 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39298845302 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 39298845302 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423580000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423580000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999637498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999637498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423217498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423217498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120929 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120929 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047388 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047388 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085842 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085842 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091221 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091221 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25105.735786 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25105.735786 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40461.919290 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40461.919290 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11377.507697 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11377.507697 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13749.785714 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13749.785714 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28328.228794 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28328.228794 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28328.228794 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28328.228794 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 1035530 # number of replacements +system.cpu.icache.tags.tagsinuse 509.402349 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7932375 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1036038 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.656452 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26422155250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.402349 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994926 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994926 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 10056088 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10056088 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7932376 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7932376 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7932376 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7932376 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7932376 # number of overall hits +system.cpu.icache.overall_hits::total 7932376 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1087421 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1087421 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1087421 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1087421 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1087421 # number of overall misses +system.cpu.icache.overall_misses::total 1087421 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15131971529 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15131971529 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15131971529 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15131971529 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15131971529 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15131971529 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9019797 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9019797 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9019797 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9019797 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9019797 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9019797 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120559 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.120559 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.120559 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.120559 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.120559 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.120559 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13915.467449 # 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average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64141.599947 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58731.716824 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58933.940814 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64141.599947 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58731.716824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58933.940814 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 2146647 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2146537 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 842675 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301933 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301933 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 93 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2072410 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3686471 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5758881 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66311616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143911276 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 210222892 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 42053 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3325984 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.012545 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.111300 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3284259 98.75% 98.75% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41725 1.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3325984 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2497867498 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1558461609 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2189866891 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51063 # Transaction distribution -system.iobus.trans_dist::WriteResp 51149 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 86 # Transaction distribution +system.iobus.trans_dist::WriteReq 51149 # Transaction distribution +system.iobus.trans_dist::WriteResp 9597 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) @@ -890,540 +1216,213 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374547621 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406221775 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42014789 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42010536 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.trans_dist::ReadReq 2147499 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2147393 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 842679 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41561 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 81 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 26 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 301934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 89 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2074254 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3686339 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5760593 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66370688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143907436 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 210278124 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 42060 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3326850 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012545 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.111298 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3285116 98.75% 98.75% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41734 1.25% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3326850 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2498300996 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1559854344 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2189806641 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1036451 # number of replacements -system.cpu.icache.tags.tagsinuse 509.402237 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7937240 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1036959 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.654343 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26422155250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.402237 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994926 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994926 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10062742 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10062742 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7937241 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7937241 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7937241 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7937241 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7937241 # number of overall hits -system.cpu.icache.overall_hits::total 7937241 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1088289 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1088289 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1088289 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1088289 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1088289 # number of overall misses -system.cpu.icache.overall_misses::total 1088289 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15130440508 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15130440508 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15130440508 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15130440508 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15130440508 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15130440508 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9025530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9025530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9025530 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9025530 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9025530 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9025530 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120579 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.120579 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.120579 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.120579 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.120579 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.120579 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13902.961904 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13902.961904 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13902.961904 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13902.961904 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13902.961904 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13902.961904 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4627 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 22.793103 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51077 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 51077 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 51077 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 51077 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 51077 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 51077 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1037212 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1037212 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1037212 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1037212 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1037212 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1037212 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12445124401 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12445124401 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12445124401 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12445124401 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12445124401 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12445124401 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114920 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114920 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114920 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.631332 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.631332 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.631332 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.631332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.631332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.631332 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338311 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65336.723406 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2577279 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403479 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.387641 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5538371750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53740.150485 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5341.296148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6255.276773 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.820010 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081502 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.095448 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996959 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 497 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3500 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3328 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2421 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55422 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26985288 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26985288 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1021912 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 829370 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1851282 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 842679 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 842679 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 33 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 33 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 21 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 21 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 186572 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 186572 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1021912 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1015942 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2037854 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1021912 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1015942 # number of overall hits -system.cpu.l2cache.overall_hits::total 2037854 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15130 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273814 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 288944 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 48 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 48 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 5 # 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number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 194993 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 194993 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 69497 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 69497 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9692879611 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9692879611 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1158124750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 27685022861 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28843147611 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1158124750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 27685022861 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28843147611 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1037042 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1103184 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2140226 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 842679 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 842679 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 81 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 81 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 26 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 26 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 301934 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 301934 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1037042 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1405118 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2442160 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1037042 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1405118 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2442160 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014590 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248203 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.135006 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.592593 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.592593 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.192308 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.192308 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382077 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.382077 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014590 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.276970 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.165553 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014590 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.276970 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.165553 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76544.927297 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65709.362012 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66276.745667 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4062.354167 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4062.354167 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 13899.400000 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 13899.400000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84021.424828 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84021.424828 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76544.927297 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71137.538957 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71339.895057 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76544.927297 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71137.538957 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71339.895057 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75938 # number of writebacks -system.cpu.l2cache.writebacks::total 75938 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15129 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273814 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288943 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115362 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115362 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15129 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389176 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404305 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15129 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389176 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 967311000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22867888639 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23835199639 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 967311000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22867888639 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23835199639 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333507000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333507000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884436000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884436000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3217943000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3217943000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248203 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135006 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.592593 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.592593 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.192308 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.192308 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382077 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382077 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276970 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165552 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014589 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276970 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165552 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63937.537180 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53251.375934 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53810.901285 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10271.770833 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10271.770833 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71834.021506 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71834.021506 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63937.537180 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58759.760723 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58953.511925 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63937.537180 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58759.760723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58953.511925 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1404516 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994651 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11877087 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1405028 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.453274 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994651 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63934725 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63934725 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7287009 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7287009 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4187789 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4187789 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186297 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186297 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215715 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215715 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11474798 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11474798 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11474798 # number of overall hits -system.cpu.dcache.overall_hits::total 11474798 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1776849 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1776849 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1955456 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1955456 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23283 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23283 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 26 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 26 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3732305 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3732305 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3732305 # number of overall misses -system.cpu.dcache.overall_misses::total 3732305 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 39503001495 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39503001495 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 78159072008 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 78159072008 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 364867750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 364867750 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 402005 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 402005 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117662073503 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117662073503 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117662073503 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117662073503 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9063858 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9063858 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6143245 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6143245 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209580 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209580 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215741 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215741 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15207103 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15207103 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15207103 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15207103 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196037 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.196037 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318310 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.318310 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111094 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111094 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000121 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000121 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.245432 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.245432 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.245432 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.245432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22232.053199 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22232.053199 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39969.742100 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39969.742100 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15670.993858 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15670.993858 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15461.730769 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15461.730769 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31525.310365 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31525.310365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31525.310365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31525.310365 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3999248 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1376 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 180044 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 22 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.212615 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 62.545455 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 842679 # number of writebacks -system.cpu.dcache.writebacks::total 842679 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680758 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 680758 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664340 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1664340 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5292 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5292 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2345098 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2345098 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2345098 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2345098 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1096091 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1096091 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291116 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 291116 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17991 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17991 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 26 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 26 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1387207 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1387207 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1387207 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1387207 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27515724784 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27515724784 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11792803134 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11792803134 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204517750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204517750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 349995 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 349995 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39308527918 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 39308527918 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39308527918 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 39308527918 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423597000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423597000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999614498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999614498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423211498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423211498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120930 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120930 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047388 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047388 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085843 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085843 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000121 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000121 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091221 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091221 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25103.503983 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25103.503983 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40508.948783 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40508.948783 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11367.781113 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11367.781113 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13461.346154 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13461.346154 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28336.454414 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28336.454414 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28336.454414 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28336.454414 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.tags.replacements 41685 # number of replacements +system.iocache.tags.tagsinuse 1.260575 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1709355371000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.260575 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078786 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078786 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375525 # Number of tag accesses +system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses +system.iocache.ReadReq_misses::total 173 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses +system.iocache.demand_misses::total 173 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 173 # number of overall misses +system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13648838856 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13648838856 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328476.098768 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328476.098768 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 206574 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23538 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.776192 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks::writebacks 41512 # number of writebacks +system.iocache.writebacks::total 41512 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11488062928 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11488062928 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276474.367732 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276474.367732 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 296033 # Transaction distribution +system.membus.trans_dist::ReadResp 295940 # Transaction distribution +system.membus.trans_dist::WriteReq 9597 # Transaction distribution +system.membus.trans_dist::WriteResp 9597 # Transaction distribution +system.membus.trans_dist::Writeback 117441 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 186 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.membus.trans_dist::UpgradeResp 192 # Transaction distribution +system.membus.trans_dist::ReadExReq 115233 # Transaction distribution +system.membus.trans_dist::ReadExResp 115233 # Transaction distribution +system.membus.trans_dist::BadAddressError 93 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884176 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 186 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917416 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042220 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30746540 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36063596 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 435 # Total snoops (count) +system.membus.snoop_fanout::samples 563522 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 563522 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 563522 # Request fanout histogram +system.membus.reqLayer0.occupancy 31470000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 1857946999 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer2.occupancy 115000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3754266813 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 43145464 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 210986 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74656 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211003 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74662 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105550 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182216 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73289 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105561 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182233 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73295 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73289 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148588 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817327743500 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 61881000 0.00% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 521765000 0.03% 97.79% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41126450000 2.21% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1859037839500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981689 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73295 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148600 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817339213500 97.76% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 61863500 0.00% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 521835500 0.03% 97.79% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41125418500 2.21% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1859048331000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694353 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815450 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694338 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815440 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1462,7 +1461,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4178 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175101 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175118 91.22% 93.44% # number of callpals executed system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1471,20 +1470,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191946 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.callpal::total 191963 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1741 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326499 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29097785000 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2655967500 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827284079000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394468 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29096339500 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2660038000 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827291945500 98.29% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4179 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index def1f96ac..3aeb0bbf5 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,134 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841612 # Number of seconds simulated -sim_ticks 1841612450000 # Number of ticks simulated -final_tick 1841612450000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.842592 # Number of seconds simulated +sim_ticks 1842592129000 # Number of ticks simulated +final_tick 1842592129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 223623 # Simulator instruction rate (inst/s) -host_op_rate 223623 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6307109470 # Simulator tick rate (ticks/s) -host_mem_usage 313464 # Number of bytes of host memory used -host_seconds 291.99 # Real time elapsed on the host -sim_insts 65295558 # Number of instructions simulated -sim_ops 65295558 # Number of ops (including micro ops) simulated +host_inst_rate 226605 # Simulator instruction rate (inst/s) +host_op_rate 226605 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6393875150 # Simulator tick rate (ticks/s) +host_mem_usage 320256 # Number of bytes of host memory used +host_seconds 288.18 # Real time elapsed on the host +sim_insts 65303087 # Number of instructions simulated +sim_ops 65303087 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 476096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20002240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 480640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20073664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 146816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2246336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 292800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2554880 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2248832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 298304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2641344 # Number of bytes read from this memory -system.physmem.bytes_read::total 25814784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 476096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 298304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 921408 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4825792 # Number of bytes written to this memory -system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7485120 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7439 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 312535 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25796096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 480640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 146816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 292800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 920256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7481536 # Number of bytes written to this memory +system.physmem.bytes_written::total 7481536 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7510 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 313651 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2294 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 35099 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4575 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39920 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 35138 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4661 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41271 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403356 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 75403 # Number of write requests responded to by this memory -system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116955 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 258521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10861265 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403064 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116899 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116899 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 260850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10894253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1219117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 158907 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1386568 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1221121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 161980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1434256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14017490 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 258521 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79826 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 161980 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 500327 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2620417 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1444022 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4064438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2620417 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 258521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10861265 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1444543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1221121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 161980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1434256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18081928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 83382 # Number of read requests accepted -system.physmem.writeReqs 46694 # Number of write requests accepted -system.physmem.readBursts 83382 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 46694 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5333696 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2752 # Total number of bytes read from write queue -system.physmem.bytesWritten 2986816 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5336448 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2988416 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 55 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5371 # Per bank write bursts -system.physmem.perBankRdBursts::1 5100 # Per bank write bursts -system.physmem.perBankRdBursts::2 5085 # Per bank write bursts -system.physmem.perBankRdBursts::3 5221 # Per bank write bursts -system.physmem.perBankRdBursts::4 5159 # Per bank write bursts -system.physmem.perBankRdBursts::5 5196 # Per bank write bursts -system.physmem.perBankRdBursts::6 5274 # Per bank write bursts -system.physmem.perBankRdBursts::7 5273 # Per bank write bursts -system.physmem.perBankRdBursts::8 5416 # Per bank write bursts -system.physmem.perBankRdBursts::9 5013 # Per bank write bursts -system.physmem.perBankRdBursts::10 5453 # Per bank write bursts -system.physmem.perBankRdBursts::11 5267 # Per bank write bursts -system.physmem.perBankRdBursts::12 4696 # Per bank write bursts -system.physmem.perBankRdBursts::13 5103 # Per bank write bursts -system.physmem.perBankRdBursts::14 5623 # Per bank write bursts -system.physmem.perBankRdBursts::15 5089 # Per bank write bursts -system.physmem.perBankWrBursts::0 2944 # Per bank write bursts -system.physmem.perBankWrBursts::1 2803 # Per bank write bursts -system.physmem.perBankWrBursts::2 2831 # Per bank write bursts -system.physmem.perBankWrBursts::3 3111 # Per bank write bursts -system.physmem.perBankWrBursts::4 3010 # Per bank write bursts -system.physmem.perBankWrBursts::5 2812 # Per bank write bursts -system.physmem.perBankWrBursts::6 3230 # Per bank write bursts -system.physmem.perBankWrBursts::7 2824 # Per bank write bursts -system.physmem.perBankWrBursts::8 3325 # Per bank write bursts -system.physmem.perBankWrBursts::9 2680 # Per bank write bursts -system.physmem.perBankWrBursts::10 3123 # Per bank write bursts -system.physmem.perBankWrBursts::11 2945 # Per bank write bursts -system.physmem.perBankWrBursts::12 2356 # Per bank write bursts -system.physmem.perBankWrBursts::13 2727 # Per bank write bursts -system.physmem.perBankWrBursts::14 3249 # Per bank write bursts -system.physmem.perBankWrBursts::15 2699 # Per bank write bursts +system.physmem.bw_read::total 13999895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 260850 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79679 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 158907 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 499436 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4060332 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4060332 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4060332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 260850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10894253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1219117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 158907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1386568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18060227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 81903 # Number of read requests accepted +system.physmem.writeReqs 62699 # Number of write requests accepted +system.physmem.readBursts 81903 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 62699 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5240384 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1408 # Total number of bytes read from write queue +system.physmem.bytesWritten 3952512 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5241792 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4012736 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 22 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 916 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 49 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5341 # Per bank write bursts +system.physmem.perBankRdBursts::1 4966 # Per bank write bursts +system.physmem.perBankRdBursts::2 4940 # Per bank write bursts +system.physmem.perBankRdBursts::3 5071 # Per bank write bursts +system.physmem.perBankRdBursts::4 5028 # Per bank write bursts +system.physmem.perBankRdBursts::5 5062 # Per bank write bursts +system.physmem.perBankRdBursts::6 5140 # Per bank write bursts +system.physmem.perBankRdBursts::7 5148 # Per bank write bursts +system.physmem.perBankRdBursts::8 5331 # Per bank write bursts +system.physmem.perBankRdBursts::9 5012 # Per bank write bursts +system.physmem.perBankRdBursts::10 5278 # Per bank write bursts +system.physmem.perBankRdBursts::11 5132 # Per bank write bursts +system.physmem.perBankRdBursts::12 4684 # Per bank write bursts +system.physmem.perBankRdBursts::13 5065 # Per bank write bursts +system.physmem.perBankRdBursts::14 5602 # Per bank write bursts +system.physmem.perBankRdBursts::15 5081 # Per bank write bursts +system.physmem.perBankWrBursts::0 3943 # Per bank write bursts +system.physmem.perBankWrBursts::1 3578 # Per bank write bursts +system.physmem.perBankWrBursts::2 3780 # Per bank write bursts +system.physmem.perBankWrBursts::3 4114 # Per bank write bursts +system.physmem.perBankWrBursts::4 3703 # Per bank write bursts +system.physmem.perBankWrBursts::5 3530 # Per bank write bursts +system.physmem.perBankWrBursts::6 4127 # Per bank write bursts +system.physmem.perBankWrBursts::7 3704 # Per bank write bursts +system.physmem.perBankWrBursts::8 4410 # Per bank write bursts +system.physmem.perBankWrBursts::9 3736 # Per bank write bursts +system.physmem.perBankWrBursts::10 4083 # Per bank write bursts +system.physmem.perBankWrBursts::11 3942 # Per bank write bursts +system.physmem.perBankWrBursts::12 3446 # Per bank write bursts +system.physmem.perBankWrBursts::13 3846 # Per bank write bursts +system.physmem.perBankWrBursts::14 4153 # Per bank write bursts +system.physmem.perBankWrBursts::15 3663 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 1840600173500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1841579852500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 83382 # Read request sizes (log2) +system.physmem.readPktSize::6 81903 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 46694 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 66361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1778 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see +system.physmem.writePktSize::6 62699 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 65847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -162,640 +159,187 @@ system.physmem.wrQLenPdf::2 46 # Wh system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 3168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 64 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21619 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 384.870346 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 218.868855 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 380.663334 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7130 32.98% 32.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4830 22.34% 55.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1852 8.57% 63.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1050 4.86% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 916 4.24% 72.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 498 2.30% 75.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 396 1.83% 77.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 403 1.86% 78.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4544 21.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21619 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2039 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 40.867092 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1027.907354 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2037 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::47 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 22200 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 414.094414 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 234.871610 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 395.166984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 6979 31.44% 31.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4758 21.43% 52.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1802 8.12% 60.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1018 4.59% 65.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 909 4.09% 69.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 488 2.20% 71.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 377 1.70% 73.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 379 1.71% 75.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5490 24.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 22200 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2135 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 38.346604 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1004.576162 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2133 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2039 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2039 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.888180 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.579378 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.470267 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 42 2.06% 2.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 4 0.20% 2.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 1722 84.45% 86.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 114 5.59% 92.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 19 0.93% 93.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 3 0.15% 93.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 5 0.25% 93.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 2 0.10% 93.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 2 0.10% 93.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 3 0.15% 93.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 15 0.74% 94.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.25% 94.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 79 3.87% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 5 0.25% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.05% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 5 0.25% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 5 0.25% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 3 0.15% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.05% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 1 0.05% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.10% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2039 # Writes before turning the bus around for reads -system.physmem.totQLat 882163500 # Total ticks spent queuing -system.physmem.totMemAccLat 2444769750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 416695000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10585.24 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2135 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2135 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 28.926464 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.717874 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 36.556650 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 42 1.97% 1.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 3 0.14% 2.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 1647 77.14% 79.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 96 4.50% 83.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 109 5.11% 88.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 21 0.98% 89.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 47 2.20% 92.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 14 0.66% 92.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 5 0.23% 92.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 4 0.19% 93.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 8 0.37% 93.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 8 0.37% 93.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 2 0.09% 93.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 2 0.09% 94.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.05% 94.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 13 0.61% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 15 0.70% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 12 0.56% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 7 0.33% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 36 1.69% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 13 0.61% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 7 0.33% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 7 0.33% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 5 0.23% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.14% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 3 0.14% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.05% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::296-303 1 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2135 # Writes before turning the bus around for reads +system.physmem.totQLat 816878250 # Total ticks spent queuing +system.physmem.totMemAccLat 2352147000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 409405000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9976.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29335.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.62 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28726.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.15 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.38 # Average write queue length when enqueuing -system.physmem.readRowHits 71513 # Number of row buffer hits during reads -system.physmem.writeRowHits 36876 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.97 # Row buffer hit rate for writes -system.physmem.avgGap 14150190.45 # Average gap between requests -system.physmem.pageHitRate 83.35 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1766563042250 # Time in different power states -system.physmem.memoryStateTime::REF 61495460000 # Time in different power states +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 8.28 # Average write queue length when enqueuing +system.physmem.readRowHits 70255 # Number of row buffer hits during reads +system.physmem.writeRowHits 51184 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.80 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.84 # Row buffer hit rate for writes +system.physmem.avgGap 12735507.48 # Average gap between requests +system.physmem.pageHitRate 84.53 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1767479155500 # Time in different power states +system.physmem.memoryStateTime::REF 61527960000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 13553394000 # Time in different power states +system.physmem.memoryStateTime::ACT 13578075750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 81912600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 81527040 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 44694375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 44484000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 325096200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 324948000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 152701200 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 149713920 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 120285119760 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 120285119760 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 46099249605 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 45830401695 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1064529191250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1064765022750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1231517964990 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1231481217165 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.717430 # Core power per rank (mW) -system.physmem.averagePower::1 668.697476 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 294949 # Transaction distribution -system.membus.trans_dist::ReadResp 294942 # Transaction distribution -system.membus.trans_dist::WriteReq 9810 # Transaction distribution -system.membus.trans_dist::WriteResp 9810 # Transaction distribution -system.membus.trans_dist::Writeback 75403 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 148 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 150 # Transaction distribution -system.membus.trans_dist::ReadExReq 115716 # Transaction distribution -system.membus.trans_dist::ReadExResp 115716 # Transaction distribution -system.membus.trans_dist::BadAddressError 7 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882385 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 916307 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83395 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83395 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 999702 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30639616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30685184 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2666880 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2666880 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33352064 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 55 # Total snoops (count) -system.membus.snoop_fanout::samples 520629 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 520629 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 520629 # Request fanout histogram -system.membus.reqLayer0.occupancy 11839500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 516853000 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 782820695 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 17912499 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.physmem.actEnergy::0 83696760 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 84135240 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 45667875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 45907125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 317428800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 321243000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 197503920 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 202687920 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 120348689760 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 120348689760 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 46124478945 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 45810126225 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1065091037250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1065366785250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1232208503310 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1232179574520 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.738964 # Core power per rank (mW) +system.physmem.averagePower::1 668.723264 # Core power per rank (mW) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 337573 # number of replacements -system.l2c.tags.tagsinuse 65418.651212 # Cycle average of tags in use -system.l2c.tags.total_refs 2486411 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402735 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.173814 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54701.898581 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2338.827583 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2722.708612 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 571.952854 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 605.884854 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2274.772027 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2202.606700 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.834685 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.035688 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041545 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008727 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009245 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034710 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.033609 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998209 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1013 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5951 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2693 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55337 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26257052 # Number of tag accesses -system.l2c.tags.data_accesses 26257052 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 505398 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 481784 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 121841 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 80801 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 322748 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 255127 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1767699 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835833 # number of Writeback hits -system.l2c.Writeback_hits::total 835833 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 10 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 14 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 90729 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 25227 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 70911 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186867 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 505398 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 572513 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 121841 # 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number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 16797 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4661 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 18005 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287632 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 24 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu2.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 74189 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 18351 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 23300 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115840 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 7439 # 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number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 75403 # number of writebacks -system.l2c.writebacks::total 75403 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu1.inst 2297 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 16797 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 4661 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 18005 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 41760 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55259.687891 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63284.488307 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 64163.570439 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 60309.584911 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # 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number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5776462 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5776462 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 1039517841 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1039517841 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5776462 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5776462 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5776462 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5776462 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4820532 # DTB read hits -system.cpu0.dtb.read_misses 5970 # DTB read misses -system.cpu0.dtb.read_acv 109 # DTB read access violations -system.cpu0.dtb.read_accesses 427970 # DTB read accesses -system.cpu0.dtb.write_hits 3430087 # DTB write hits -system.cpu0.dtb.write_misses 674 # DTB write misses -system.cpu0.dtb.write_acv 81 # DTB write access violations -system.cpu0.dtb.write_accesses 164325 # DTB write accesses -system.cpu0.dtb.data_hits 8250619 # DTB hits -system.cpu0.dtb.data_misses 6644 # DTB misses -system.cpu0.dtb.data_acv 190 # DTB access violations -system.cpu0.dtb.data_accesses 592295 # DTB accesses -system.cpu0.itb.fetch_hits 2728150 # ITB hits -system.cpu0.itb.fetch_misses 3015 # ITB misses -system.cpu0.itb.fetch_acv 97 # ITB acv -system.cpu0.itb.fetch_accesses 2731165 # ITB accesses +system.cpu0.dtb.read_hits 4840766 # DTB read hits +system.cpu0.dtb.read_misses 6162 # DTB read misses +system.cpu0.dtb.read_acv 126 # DTB read access violations +system.cpu0.dtb.read_accesses 429577 # DTB read accesses +system.cpu0.dtb.write_hits 3449248 # DTB write hits +system.cpu0.dtb.write_misses 688 # DTB write misses +system.cpu0.dtb.write_acv 85 # DTB write access violations +system.cpu0.dtb.write_accesses 165228 # DTB write accesses +system.cpu0.dtb.data_hits 8290014 # DTB hits +system.cpu0.dtb.data_misses 6850 # DTB misses +system.cpu0.dtb.data_acv 211 # DTB access violations +system.cpu0.dtb.data_accesses 594805 # DTB accesses +system.cpu0.itb.fetch_hits 2745005 # ITB hits +system.cpu0.itb.fetch_misses 3071 # ITB misses +system.cpu0.itb.fetch_acv 104 # ITB acv +system.cpu0.itb.fetch_accesses 2748076 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -808,87 +352,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 929887646 # number of cpu cycles simulated +system.cpu0.numCycles 930170502 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 30964546 # Number of instructions committed -system.cpu0.committedOps 30964546 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 28877269 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 164895 # Number of float alu accesses -system.cpu0.num_func_calls 798898 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3870413 # number of instructions that are conditional controls -system.cpu0.num_int_insts 28877269 # number of integer instructions -system.cpu0.num_fp_insts 164895 # number of float instructions -system.cpu0.num_int_register_reads 39993375 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21214284 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 85263 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 86719 # number of times the floating registers were written -system.cpu0.num_mem_refs 8280000 # number of memory refs -system.cpu0.num_load_insts 4841351 # Number of load instructions -system.cpu0.num_store_insts 3438649 # Number of store instructions -system.cpu0.num_idle_cycles 908004121.642144 # Number of idle cycles -system.cpu0.num_busy_cycles 21883524.357856 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023534 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976466 # Percentage of idle cycles -system.cpu0.Branches 4926659 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1578204 5.10% 5.10% # Class of executed instruction -system.cpu0.op_class::IntAlu 20416117 65.92% 71.01% # Class of executed instruction -system.cpu0.op_class::IntMult 31858 0.10% 71.12% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12902 0.04% 71.16% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1598 0.01% 71.16% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.16% # Class of executed instruction -system.cpu0.op_class::MemRead 4972343 16.05% 87.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 3441751 11.11% 98.33% # Class of executed instruction -system.cpu0.op_class::IprAccess 516607 1.67% 100.00% # Class of executed instruction +system.cpu0.committedInsts 31084978 # Number of instructions committed +system.cpu0.committedOps 31084978 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 28990115 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 165280 # Number of float alu accesses +system.cpu0.num_func_calls 801354 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3884267 # number of instructions that are conditional controls +system.cpu0.num_int_insts 28990115 # number of integer instructions +system.cpu0.num_fp_insts 165280 # number of float instructions +system.cpu0.num_int_register_reads 40144651 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21293303 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 85481 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 86924 # number of times the floating registers were written +system.cpu0.num_mem_refs 8319976 # number of memory refs +system.cpu0.num_load_insts 4862063 # Number of load instructions +system.cpu0.num_store_insts 3457913 # Number of store instructions +system.cpu0.num_idle_cycles 907838728.357051 # Number of idle cycles +system.cpu0.num_busy_cycles 22331773.642949 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024008 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975992 # Percentage of idle cycles +system.cpu0.Branches 4943919 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1583961 5.09% 5.09% # Class of executed instruction +system.cpu0.op_class::IntAlu 20486094 65.89% 70.98% # Class of executed instruction +system.cpu0.op_class::IntMult 31888 0.10% 71.09% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.09% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12950 0.04% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1606 0.01% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::MemRead 4993462 16.06% 87.19% # Class of executed instruction +system.cpu0.op_class::MemWrite 3461022 11.13% 98.32% # Class of executed instruction +system.cpu0.op_class::IprAccess 521056 1.68% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 30971380 # Class of executed instruction +system.cpu0.op_class::total 31092039 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6422 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211354 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.hwrei 211371 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74797 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105681 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182556 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105691 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182570 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73430 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818780188000 98.76% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39182000 0.00% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 357649000 0.02% 98.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22434661500 1.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841611680500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73430 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148942 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1819773509500 98.76% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38545500 0.00% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 357643000 0.02% 98.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22421661500 1.22% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842591359500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694798 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815832 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694761 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815808 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -924,537 +468,278 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175299 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175311 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192210 # number of callpals executed +system.cpu0.kern.callpal::total 192226 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1907 +system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1908 system.cpu0.kern.mode_good::user 1738 -system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches +system.cpu0.kern.mode_good::idle 170 +system.cpu0.kern.mode_switch_good::kernel 0.322188 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391059 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29705567000 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2577814500 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809328294500 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4175 # number of times the context was actually changed -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2062606 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2062584 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 835833 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 17283 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 38 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 46 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302707 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302707 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 7 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1928849 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3657196 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5586045 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61721856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142735808 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 204457664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 41925 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3235706 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012896 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112826 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3193978 98.71% 98.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 41728 1.29% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3235706 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2218971499 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2034366165 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2306919756 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 7317 # Transaction distribution -system.iobus.trans_dist::ReadResp 7317 # Transaction distribution -system.iobus.trans_dist::WriteReq 51362 # Transaction distribution -system.iobus.trans_dist::WriteResp 27090 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 24272 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 756 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18256 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 952 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2208000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5523000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2079000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 11000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 155677802 # Layer occupancy (ticks) -system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9370000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17534501 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 963743 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.196442 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 40274426 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 964254 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 41.767445 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10190503250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 263.296847 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.404531 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 180.495065 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.514252 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131649 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.352529 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998431 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 42219519 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 42219519 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 30458523 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7341413 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2474490 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 40274426 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30458523 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7341413 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2474490 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 40274426 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 30458523 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7341413 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2474490 # number of overall hits -system.cpu0.icache.overall_hits::total 40274426 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 512857 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 124138 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 343653 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 980648 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 512857 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 124138 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 343653 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 980648 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 512857 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 124138 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 343653 # number of overall misses -system.cpu0.icache.overall_misses::total 980648 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1770888500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4833799298 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6604687798 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1770888500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4833799298 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6604687798 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1770888500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4833799298 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6604687798 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30971380 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7465551 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2818143 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 41255074 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30971380 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7465551 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2818143 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 41255074 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30971380 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7465551 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2818143 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 41255074 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016559 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016628 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.121943 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.023770 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016559 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016628 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.121943 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023770 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016559 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016628 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.121943 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023770 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14265.482769 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14065.930744 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6735.023982 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14265.482769 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14065.930744 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6735.023982 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14265.482769 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14065.930744 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6735.023982 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3646 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 161 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.645963 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16203 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16203 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16203 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16203 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16203 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16203 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 124138 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 327450 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 451588 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 124138 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 327450 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 451588 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 124138 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 327450 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 451588 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1521699500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3997566325 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5519265825 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1521699500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3997566325 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5519265825 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1521699500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3997566325 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5519265825 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016628 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116194 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010946 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016628 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116194 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010946 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016628 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116194 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010946 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.128051 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12208.173233 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12221.905420 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.128051 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12208.173233 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12221.905420 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.128051 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12208.173233 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12221.905420 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1393134 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13262946 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393646 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.516725 # Average number of references to valid blocks. +system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29639680500 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2561811500 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810389863000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4177 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1393201 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997818 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13277254 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393713 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.526534 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 261.690760 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 74.796063 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 175.510993 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.511115 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.146086 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.342795 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 261.608452 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 74.750107 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 175.639259 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.510954 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.145996 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.343045 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 267 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63351559 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63351559 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 3996259 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1054031 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2516397 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7566687 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3140432 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 808252 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1363715 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5312399 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114574 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 18764 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51112 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184450 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123404 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 20737 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55180 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199321 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7136691 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1862283 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3880112 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12879086 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7136691 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1862283 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3880112 # number of overall hits -system.cpu0.dcache.overall_hits::total 12879086 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 710837 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 95497 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 564447 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1370781 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 164929 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 43579 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 628162 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 836670 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9380 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2101 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7681 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19162 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 63354718 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63354718 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4014926 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1052133 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2504051 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7571110 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3157714 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 807247 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1357321 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5322282 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114982 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 18680 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 50783 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184445 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123850 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 20650 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 54829 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199329 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7172640 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1859380 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3861372 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12893392 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7172640 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1859380 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3861372 # number of overall hits +system.cpu0.dcache.overall_hits::total 12893392 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 712217 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 95395 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 559235 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1366847 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 166399 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 43585 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 617129 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 827113 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9420 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2097 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7598 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19115 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu2.data 8 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 875766 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 139076 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1192609 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2207451 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 875766 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 139076 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1192609 # number of overall misses -system.cpu0.dcache.overall_misses::total 2207451 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2207514000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9811838599 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 12019352599 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1651311760 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 20363561979 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 22014873739 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27705250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 128352996 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 156058246 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 130502 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 130502 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 3858825760 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 30175400578 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 34034226338 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3858825760 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 30175400578 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 34034226338 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4707096 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1149528 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3080844 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8937468 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3305361 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 851831 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1991877 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6149069 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123954 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 20865 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58793 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203612 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123404 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 20737 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55188 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199329 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8012457 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2001359 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5072721 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15086537 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8012457 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2001359 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5072721 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15086537 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151014 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083075 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.183212 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.153375 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049897 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051159 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315362 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.136065 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075673 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100695 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130645 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094110 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000145 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109301 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069491 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.235102 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.146319 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109301 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069491 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.235102 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.146319 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23116.056002 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17383.099917 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8768.251529 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37892.373850 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32417.691581 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 26312.493264 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13186.696811 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16710.453847 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8144.152281 # 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number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 319650500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 420043000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 739693500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 568111500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 762758000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1330869500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083131 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086875 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040447 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051226 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046842 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022128 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100929 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103287 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.039924 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000146 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069491 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071226 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033168 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069491 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071226 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033168 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21037.194886 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16748.244464 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17877.013920 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35701.168912 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31132.717850 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32580.329109 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11185.982865 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12131.377415 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11887.901814 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14312.250000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14312.250000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25632.102160 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20488.581777 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21918.158626 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25632.102160 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20488.581777 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21918.158626 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069547 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071185 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032981 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069547 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071185 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032981 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21018.538707 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16736.603555 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17866.492534 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35664.419869 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 30120.116351 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31896.003153 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11186.337625 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12086.443118 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11854.189984 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25611.578932 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20188.266777 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21703.031791 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25611.578932 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20188.266777 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21703.031791 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1465,26 +750,163 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 964194 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.195402 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 40365438 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 964705 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 41.842261 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10190503250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 263.118461 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.369800 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 180.707141 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.513903 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131582 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.352944 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998429 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 42311419 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 42311419 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 30577752 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7329263 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2458423 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 40365438 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 30577752 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7329263 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2458423 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 40365438 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 30577752 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7329263 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2458423 # number of overall hits +system.cpu0.icache.overall_hits::total 40365438 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 514287 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 123865 # 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number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 31092039 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7453128 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2801355 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 41346522 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 31092039 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7453128 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2801355 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 41346522 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016541 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016619 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122416 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.023728 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016541 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016619 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122416 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.023728 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016541 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016619 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122416 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.023728 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14259.990716 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14035.747889 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6706.480633 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14259.990716 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14035.747889 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6706.480633 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14259.990716 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14035.747889 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6706.480633 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3823 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 167 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.892216 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16187 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16187 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16187 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16187 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16187 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16187 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 123865 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 326745 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 450610 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 123865 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 326745 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 450610 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 123865 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 326745 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 450610 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1517675250 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3982959026 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5500634276 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1517675250 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3982959026 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5500634276 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1517675250 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3982959026 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5500634276 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016619 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116638 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010898 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016619 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116638 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010898 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016619 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116638 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010898 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12252.656118 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12189.808646 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12207.084343 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12252.656118 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12189.808646 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12207.084343 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12252.656118 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12189.808646 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12207.084343 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1168269 # DTB read hits -system.cpu1.dtb.read_misses 1330 # DTB read misses -system.cpu1.dtb.read_acv 35 # DTB read access violations -system.cpu1.dtb.read_accesses 141659 # DTB read accesses -system.cpu1.dtb.write_hits 872893 # DTB write hits -system.cpu1.dtb.write_misses 171 # DTB write misses +system.cpu1.dtb.read_hits 1166206 # DTB read hits +system.cpu1.dtb.read_misses 1314 # DTB read misses +system.cpu1.dtb.read_acv 34 # DTB read access violations +system.cpu1.dtb.read_accesses 141633 # DTB read accesses +system.cpu1.dtb.write_hits 871808 # DTB write hits +system.cpu1.dtb.write_misses 168 # DTB write misses system.cpu1.dtb.write_acv 22 # DTB write access violations -system.cpu1.dtb.write_accesses 57101 # DTB write accesses -system.cpu1.dtb.data_hits 2041162 # DTB hits -system.cpu1.dtb.data_misses 1501 # DTB misses -system.cpu1.dtb.data_acv 57 # DTB access violations -system.cpu1.dtb.data_accesses 198760 # DTB accesses -system.cpu1.itb.fetch_hits 849127 # ITB hits -system.cpu1.itb.fetch_misses 665 # ITB misses -system.cpu1.itb.fetch_acv 34 # ITB acv -system.cpu1.itb.fetch_accesses 849792 # ITB accesses +system.cpu1.dtb.write_accesses 57088 # DTB write accesses +system.cpu1.dtb.data_hits 2038014 # DTB hits +system.cpu1.dtb.data_misses 1482 # DTB misses +system.cpu1.dtb.data_acv 56 # DTB access violations +system.cpu1.dtb.data_accesses 198721 # DTB accesses +system.cpu1.itb.fetch_hits 847614 # ITB hits +system.cpu1.itb.fetch_misses 662 # ITB misses +system.cpu1.itb.fetch_acv 32 # ITB acv +system.cpu1.itb.fetch_accesses 848276 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1497,34 +919,34 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953403050 # number of cpu cycles simulated +system.cpu1.numCycles 953409628 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7463992 # Number of instructions committed -system.cpu1.committedOps 7463992 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6937939 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 43895 # Number of float alu accesses -system.cpu1.num_func_calls 203449 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 905325 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6937939 # number of integer instructions -system.cpu1.num_fp_insts 43895 # number of float instructions -system.cpu1.num_int_register_reads 9652072 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5060714 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 23736 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24066 # number of times the floating registers were written -system.cpu1.num_mem_refs 2048141 # number of memory refs -system.cpu1.num_load_insts 1172984 # Number of load instructions -system.cpu1.num_store_insts 875157 # Number of store instructions -system.cpu1.num_idle_cycles 923975246.943285 # Number of idle cycles -system.cpu1.num_busy_cycles 29427803.056715 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030866 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969134 # Percentage of idle cycles -system.cpu1.Branches 1173357 # Number of branches fetched -system.cpu1.op_class::No_OpClass 399705 5.35% 5.35% # Class of executed instruction -system.cpu1.op_class::IntAlu 4844088 64.89% 70.24% # Class of executed instruction -system.cpu1.op_class::IntMult 8214 0.11% 70.35% # Class of executed instruction +system.cpu1.committedInsts 7451589 # Number of instructions committed +system.cpu1.committedOps 7451589 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 6926409 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 43920 # Number of float alu accesses +system.cpu1.num_func_calls 202937 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 904115 # number of instructions that are conditional controls +system.cpu1.num_int_insts 6926409 # number of integer instructions +system.cpu1.num_fp_insts 43920 # number of float instructions +system.cpu1.num_int_register_reads 9636713 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5051586 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 23745 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24097 # number of times the floating registers were written +system.cpu1.num_mem_refs 2044932 # number of memory refs +system.cpu1.num_load_insts 1170872 # Number of load instructions +system.cpu1.num_store_insts 874060 # Number of store instructions +system.cpu1.num_idle_cycles 925046236.205368 # Number of idle cycles +system.cpu1.num_busy_cycles 28363391.794632 # Number of busy cycles +system.cpu1.not_idle_fraction 0.029749 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.970251 # Percentage of idle cycles +system.cpu1.Branches 1171500 # Number of branches fetched +system.cpu1.op_class::No_OpClass 399169 5.36% 5.36% # Class of executed instruction +system.cpu1.op_class::IntAlu 4836084 64.89% 70.24% # Class of executed instruction +system.cpu1.op_class::IntMult 8208 0.11% 70.35% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5110 0.07% 70.42% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5096 0.07% 70.42% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 70.42% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 70.42% # Class of executed instruction @@ -1550,11 +972,11 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.43% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 70.43% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.43% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::MemRead 1201071 16.09% 86.52% # Class of executed instruction -system.cpu1.op_class::MemWrite 876369 11.74% 98.26% # Class of executed instruction -system.cpu1.op_class::IprAccess 130183 1.74% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 1198833 16.08% 86.52% # Class of executed instruction +system.cpu1.op_class::MemWrite 875271 11.74% 98.26% # Class of executed instruction +system.cpu1.op_class::IprAccess 129656 1.74% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7465550 # Class of executed instruction +system.cpu1.op_class::total 7453127 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1572,35 +994,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9020137 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8282573 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 125563 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6965204 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 4892106 # Number of BTB hits +system.cpu2.branchPred.lookups 8975833 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8240091 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 125146 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 6986744 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 4884457 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 70.236364 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 299658 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7807 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 69.910347 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 298693 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7800 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3485260 # DTB read hits -system.cpu2.dtb.read_misses 12402 # DTB read misses -system.cpu2.dtb.read_acv 152 # DTB read access violations -system.cpu2.dtb.read_accesses 227268 # DTB read accesses -system.cpu2.dtb.write_hits 2138350 # DTB write hits -system.cpu2.dtb.write_misses 2805 # DTB write misses -system.cpu2.dtb.write_acv 140 # DTB write access violations -system.cpu2.dtb.write_accesses 85115 # DTB write accesses -system.cpu2.dtb.data_hits 5623610 # DTB hits -system.cpu2.dtb.data_misses 15207 # DTB misses -system.cpu2.dtb.data_acv 292 # DTB access violations -system.cpu2.dtb.data_accesses 312383 # DTB accesses -system.cpu2.itb.fetch_hits 538601 # ITB hits -system.cpu2.itb.fetch_misses 5813 # ITB misses -system.cpu2.itb.fetch_acv 166 # ITB acv -system.cpu2.itb.fetch_accesses 544414 # ITB accesses +system.cpu2.dtb.read_hits 3460113 # DTB read hits +system.cpu2.dtb.read_misses 12059 # DTB read misses +system.cpu2.dtb.read_acv 120 # DTB read access violations +system.cpu2.dtb.read_accesses 225843 # DTB read accesses +system.cpu2.dtb.write_hits 2120785 # DTB write hits +system.cpu2.dtb.write_misses 2578 # DTB write misses +system.cpu2.dtb.write_acv 111 # DTB write access violations +system.cpu2.dtb.write_accesses 84303 # DTB write accesses +system.cpu2.dtb.data_hits 5580898 # DTB hits +system.cpu2.dtb.data_misses 14637 # DTB misses +system.cpu2.dtb.data_acv 231 # DTB access violations +system.cpu2.dtb.data_accesses 310146 # DTB accesses +system.cpu2.itb.fetch_hits 534656 # ITB hits +system.cpu2.itb.fetch_misses 5715 # ITB misses +system.cpu2.itb.fetch_acv 156 # ITB acv +system.cpu2.itb.fetch_accesses 540371 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1613,305 +1035,892 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 29513686 # number of cpu cycles simulated +system.cpu2.numCycles 29309170 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9389582 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 35469274 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9020137 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 5191764 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 18021119 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 410530 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 647 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 9356 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 228650 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 98931 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 387 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2818143 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 92772 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27955647 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.268770 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.388372 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9355872 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 35312418 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8975833 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 5183150 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 17863271 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 408038 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 247 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9336 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1926 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 226509 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 98836 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 360 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2801357 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 93254 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27760138 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.272055 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.388957 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20239272 72.40% 72.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 311789 1.12% 73.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 473018 1.69% 75.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3278988 11.73% 86.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 836372 2.99% 89.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 194449 0.70% 90.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 239819 0.86% 91.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 437682 1.57% 93.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1944258 6.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 20067804 72.29% 72.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 312324 1.13% 73.42% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 471431 1.70% 75.11% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3277065 11.80% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 832356 3.00% 89.92% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 194310 0.70% 90.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 239050 0.86% 91.48% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 435621 1.57% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1930177 6.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27955647 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.305626 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.201791 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7697914 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 13194592 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6089531 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 535341 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 192357 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 175638 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13257 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 32098439 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 42458 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 192357 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7981444 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4806689 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6360452 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 6310892 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2057913 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 31276153 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 68586 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 406035 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 57262 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 980638 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 20937225 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 38641604 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 38581458 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56230 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 19023888 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1913337 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 532654 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63537 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3939185 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3509523 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2229292 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 463055 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 331167 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 28745476 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 680921 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 28394222 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 16375 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2445259 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1154216 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 487025 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27955647 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.015688 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.594887 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27760138 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.306247 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.204825 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7663207 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 13056286 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6071971 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 531660 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 191161 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 175121 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13218 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 31964587 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 42189 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 191161 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7944282 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4747926 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6306317 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 6292094 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2032514 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 31148031 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 68690 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 405455 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 57635 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 961672 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 20857546 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 38489272 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 38429323 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56078 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 18957389 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1900157 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 527032 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63032 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3906781 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3488819 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2211142 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 463556 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 329659 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 28630875 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 676639 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 28279580 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 16369 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2426454 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1141058 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 483735 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27760138 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.018712 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.595651 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17573743 62.86% 62.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2782129 9.95% 72.81% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1379697 4.94% 77.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4038946 14.45% 92.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1015784 3.63% 95.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 573145 2.05% 97.88% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 387606 1.39% 99.27% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 155412 0.56% 99.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 49185 0.18% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17419876 62.75% 62.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2765921 9.96% 72.72% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1372782 4.95% 77.66% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4034544 14.53% 92.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1009748 3.64% 95.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 570537 2.06% 97.89% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 383332 1.38% 99.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 154390 0.56% 99.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 49008 0.18% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27955647 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27760138 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 83781 21.60% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.60% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 179225 46.21% 67.82% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 124810 32.18% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 83197 21.73% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 176333 46.06% 67.80% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 123266 32.20% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 22268545 78.43% 78.43% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21109 0.07% 78.51% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 78.51% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20518 0.07% 78.58% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 78.58% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 78.58% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 78.58% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3613635 12.73% 91.31% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2162330 7.62% 98.93% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 304401 1.07% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 22202311 78.51% 78.52% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21087 0.07% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20489 0.07% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 78.67% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3587142 12.68% 91.35% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2144327 7.58% 98.94% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 300564 1.06% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 28394222 # Type of FU issued -system.cpu2.iq.rate 0.962070 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 387816 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.013658 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 84894498 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 31757890 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27813110 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 253784 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 119651 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 117192 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 28643478 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 136104 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 207211 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 28279580 # Type of FU issued +system.cpu2.iq.rate 0.964871 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 382796 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.013536 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 84465202 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 31620396 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27707676 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 253261 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 119445 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 116967 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 28524107 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 135829 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206522 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 438819 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1413 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6020 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 178766 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 435956 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1412 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6012 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 178431 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5023 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 176307 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5029 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 168380 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 192357 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4003600 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 328635 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 30811270 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 51966 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3509523 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2229292 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 606230 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 15640 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 265026 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6020 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 63511 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 134698 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 198209 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 28196871 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3506429 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 197351 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 191161 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3997544 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 279888 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 30686163 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 51755 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3488819 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2211142 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 602233 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 15645 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 216255 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6012 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63410 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 133827 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 197237 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 28083451 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3480678 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 196129 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1384873 # number of nop insts executed -system.cpu2.iew.exec_refs 5652310 # number of memory reference insts executed -system.cpu2.iew.exec_branches 5956275 # Number of branches executed -system.cpu2.iew.exec_stores 2145881 # Number of stores executed -system.cpu2.iew.exec_rate 0.955383 # Inst execution rate -system.cpu2.iew.wb_sent 27971955 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27930302 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15891558 # num instructions producing a value -system.cpu2.iew.wb_consumers 19546280 # num instructions consuming a value +system.cpu2.iew.exec_nop 1378649 # number of nop insts executed +system.cpu2.iew.exec_refs 5608668 # number of memory reference insts executed +system.cpu2.iew.exec_branches 5940571 # Number of branches executed +system.cpu2.iew.exec_stores 2127990 # Number of stores executed +system.cpu2.iew.exec_rate 0.958180 # Inst execution rate +system.cpu2.iew.wb_sent 27865492 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27824643 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15848860 # num instructions producing a value +system.cpu2.iew.wb_consumers 19489990 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.946351 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.813022 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.949349 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.813179 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2680068 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 193896 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 181086 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 27486207 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.021790 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.858200 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2662629 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 192904 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 180156 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 27293607 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.025131 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.859726 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18368842 66.83% 66.83% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2248676 8.18% 75.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1182960 4.30% 79.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 3745017 13.63% 92.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 544035 1.98% 94.92% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 201250 0.73% 95.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 165260 0.60% 96.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 179807 0.65% 96.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 850360 3.09% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18211809 66.73% 66.73% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2232896 8.18% 74.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1177901 4.32% 79.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 3741262 13.71% 92.93% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 541174 1.98% 94.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 200137 0.73% 95.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 164418 0.60% 96.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 176928 0.65% 96.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 847082 3.10% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 27486207 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 28085126 # Number of instructions committed -system.cpu2.commit.committedOps 28085126 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 27293607 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 27979525 # Number of instructions committed +system.cpu2.commit.committedOps 27979525 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5121230 # Number of memory references committed -system.cpu2.commit.loads 3070704 # Number of loads committed -system.cpu2.commit.membars 68250 # Number of memory barriers committed -system.cpu2.commit.branches 5783973 # Number of branches committed -system.cpu2.commit.fp_insts 115466 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 26570607 # Number of committed integer instructions. -system.cpu2.commit.function_calls 240322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1220562 4.35% 4.35% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 21327099 75.94% 80.28% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20651 0.07% 80.36% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 80.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20069 0.07% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1228 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3138954 11.18% 91.61% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2052162 7.31% 98.92% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 304401 1.08% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5085574 # Number of memory references committed +system.cpu2.commit.loads 3052863 # Number of loads committed +system.cpu2.commit.membars 67982 # Number of memory barriers committed +system.cpu2.commit.branches 5768887 # Number of branches committed +system.cpu2.commit.fp_insts 115191 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 26471742 # Number of committed integer instructions. +system.cpu2.commit.function_calls 239400 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1215445 4.34% 4.34% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 21266434 76.01% 80.35% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20635 0.07% 80.42% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 80.42% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20039 0.07% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 80.50% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3120845 11.15% 91.65% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2034343 7.27% 98.93% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 300564 1.07% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 28085126 # Class of committed instruction -system.cpu2.commit.bw_lim_events 850360 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 27979525 # Class of committed instruction +system.cpu2.commit.bw_lim_events 847082 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 57323983 # The number of ROB reads -system.cpu2.rob.rob_writes 61998256 # The number of ROB writes -system.cpu2.timesIdled 175445 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1558039 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1746293269 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 26867020 # Number of Instructions Simulated -system.cpu2.committedOps 26867020 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.098510 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.098510 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.910324 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.910324 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 36957336 # number of integer regfile reads -system.cpu2.int_regfile_writes 19827241 # number of integer regfile writes -system.cpu2.fp_regfile_reads 70923 # number of floating regfile reads -system.cpu2.fp_regfile_writes 71075 # number of floating regfile writes -system.cpu2.misc_regfile_reads 3638892 # number of misc regfile reads -system.cpu2.misc_regfile_writes 273174 # number of misc regfile writes +system.cpu2.rob.rob_reads 57015033 # The number of ROB reads +system.cpu2.rob.rob_writes 61749251 # The number of ROB writes +system.cpu2.timesIdled 174924 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1549032 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1748451761 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 26766520 # Number of Instructions Simulated +system.cpu2.committedOps 26766520 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.094994 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.094994 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.913247 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.913247 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 36812900 # number of integer regfile reads +system.cpu2.int_regfile_writes 19756149 # number of integer regfile writes +system.cpu2.fp_regfile_reads 70792 # number of floating regfile reads +system.cpu2.fp_regfile_writes 70904 # number of floating regfile writes +system.cpu2.misc_regfile_reads 3635366 # number of misc regfile reads +system.cpu2.misc_regfile_writes 270473 # number of misc regfile writes +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.iobus.trans_dist::ReadReq 7317 # Transaction distribution +system.iobus.trans_dist::ReadResp 7317 # Transaction distribution +system.iobus.trans_dist::WriteReq 51363 # Transaction distribution +system.iobus.trans_dist::WriteResp 9811 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5194 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33910 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 117360 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9128 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 45576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2707184 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2201000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 5523000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 2073000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer29.occupancy 169052512 # Layer occupancy (ticks) +system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 9350000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 17532500 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 41685 # number of replacements +system.iocache.tags.tagsinuse 1.262652 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1693890023000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.262652 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078916 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078916 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375525 # Number of tag accesses +system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses +system.iocache.ReadReq_misses::total 173 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses +system.iocache.demand_misses::total 173 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 173 # number of overall misses +system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 9417462 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9417462 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 5715176550 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 5715176550 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9417462 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9417462 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9417462 # 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miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54436.196532 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54436.196532 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 137542.754861 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 137542.754861 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 54436.196532 # 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average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75697.650273 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 66841.783802 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 9863.436993 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 21199.733333 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 13825.913043 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68546.223094 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82406.503670 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 26557.423218 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 74618.679163 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 67681.617446 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 75697.650273 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 75429.698545 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 14656.715115 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 74618.679163 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 67681.617446 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 75697.650273 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 75429.698545 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 14656.715115 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 75387 # number of writebacks +system.l2c.writebacks::total 75387 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu1.inst 2294 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 16797 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 4575 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 17928 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 41594 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 18351 # 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number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1938028510 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 288727250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2523552277 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 4892283287 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 141975250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1938028510 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 288727250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2523552277 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 4892283287 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 232613500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 320671000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 553284500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 301613500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 395814000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 697427500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 534227000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 716485000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1250712000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018520 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.172291 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014003 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.065943 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020232 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.652174 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.421049 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.237940 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.133520 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018520 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.249142 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014003 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.109693 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034773 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018520 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.249142 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014003 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.109693 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034773 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61889.821273 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54217.672799 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63109.781421 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54360.553324 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 55680.452710 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20600.800000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20600.800000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55982.467440 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70191.058410 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63740.086024 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61889.821273 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55139.083589 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63109.781421 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63095.116437 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59652.534196 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61889.821273 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55139.083589 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63109.781421 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63095.116437 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59652.534196 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 294926 # Transaction distribution +system.membus.trans_dist::ReadResp 294920 # Transaction distribution +system.membus.trans_dist::WriteReq 9811 # Transaction distribution +system.membus.trans_dist::WriteResp 9811 # Transaction distribution +system.membus.trans_dist::Writeback 116899 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 147 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 149 # Transaction distribution +system.membus.trans_dist::ReadExReq 115717 # Transaction distribution +system.membus.trans_dist::ReadExResp 115717 # Transaction distribution +system.membus.trans_dist::BadAddressError 6 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882240 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 916162 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124907 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124907 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1041069 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30632000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30677576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5323648 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 5323648 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36001224 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 140 # Total snoops (count) +system.membus.snoop_fanout::samples 562099 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 562099 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 562099 # Request fanout histogram +system.membus.reqLayer0.occupancy 11803000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 659094000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 769927201 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 17910500 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 2063113 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2063092 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 9811 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 9811 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 835902 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 17280 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 35 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 45 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302718 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302718 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1929756 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3657397 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5587153 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61750976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142744520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 204495496 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 41919 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3236289 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012893 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112812 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3194564 98.71% 98.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 41725 1.29% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3236289 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2206148499 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2029921963 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 2294082992 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed |