diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-12-05 16:48:34 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-12-05 16:48:34 -0500 |
| commit | ebd9018a139178aed432b257ff4ce6dc2d5f795f (patch) | |
| tree | 0d844028751908a7c7f66f82e5bd9564467086c9 /tests/long/fs/10.linux-boot/ref/alpha/linux | |
| parent | 9e57e4e89d3c6b6d7e0f0f182bfd01c5585c16c5 (diff) | |
| download | gem5-ebd9018a139178aed432b257ff4ce6dc2d5f795f.tar.xz | |
stats: Update stats to reflect cache changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux')
3 files changed, 3779 insertions, 3776 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 6d2c4821a..4852a1186 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,110 +1,110 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.893221 # Number of seconds simulated -sim_ticks 1893220881500 # Number of ticks simulated -final_tick 1893220881500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.893228 # Number of seconds simulated +sim_ticks 1893227633000 # Number of ticks simulated +final_tick 1893227633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25399 # Simulator instruction rate (inst/s) -host_op_rate 25399 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 856404595 # Simulator tick rate (ticks/s) -host_mem_usage 393548 # Number of bytes of host memory used -host_seconds 2210.66 # Real time elapsed on the host -sim_insts 56147815 # Number of instructions simulated -sim_ops 56147815 # Number of ops (including micro ops) simulated +host_inst_rate 25790 # Simulator instruction rate (inst/s) +host_op_rate 25790 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 869674472 # Simulator tick rate (ticks/s) +host_mem_usage 393476 # Number of bytes of host memory used +host_seconds 2176.94 # Real time elapsed on the host +sim_insts 56143729 # Number of instructions simulated +sim_ops 56143729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1046208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24860800 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1047552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24860352 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25907968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1046208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1046208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7566592 # Number of bytes written to this memory -system.physmem.bytes_written::total 7566592 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16347 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388450 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25908864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1047552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1047552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7567040 # Number of bytes written to this memory +system.physmem.bytes_written::total 7567040 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16368 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388443 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404812 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118228 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118228 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 552607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13131484 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404826 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118235 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118235 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 553315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13131201 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13684599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 552607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 552607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3996677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3996677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3996677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 552607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13131484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13685023 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 553315 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 553315 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3996899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3996899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3996899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 553315 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13131201 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17681276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404812 # Number of read requests accepted -system.physmem.writeReqs 118228 # Number of write requests accepted -system.physmem.readBursts 404812 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118228 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25900544 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue -system.physmem.bytesWritten 7565312 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25907968 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7566592 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17681922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404826 # Number of read requests accepted +system.physmem.writeReqs 118235 # Number of write requests accepted +system.physmem.readBursts 404826 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118235 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25901888 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue +system.physmem.bytesWritten 7565888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25908864 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7567040 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25483 # Per bank write bursts -system.physmem.perBankRdBursts::1 25705 # Per bank write bursts +system.physmem.perBankRdBursts::0 25487 # Per bank write bursts +system.physmem.perBankRdBursts::1 25708 # Per bank write bursts system.physmem.perBankRdBursts::2 25813 # Per bank write bursts -system.physmem.perBankRdBursts::3 25775 # Per bank write bursts -system.physmem.perBankRdBursts::4 25223 # Per bank write bursts +system.physmem.perBankRdBursts::3 25780 # Per bank write bursts +system.physmem.perBankRdBursts::4 25224 # Per bank write bursts system.physmem.perBankRdBursts::5 24955 # Per bank write bursts system.physmem.perBankRdBursts::6 24789 # Per bank write bursts -system.physmem.perBankRdBursts::7 24583 # Per bank write bursts -system.physmem.perBankRdBursts::8 25108 # Per bank write bursts +system.physmem.perBankRdBursts::7 24580 # Per bank write bursts +system.physmem.perBankRdBursts::8 25111 # Per bank write bursts system.physmem.perBankRdBursts::9 25258 # Per bank write bursts -system.physmem.perBankRdBursts::10 25518 # Per bank write bursts -system.physmem.perBankRdBursts::11 24875 # Per bank write bursts -system.physmem.perBankRdBursts::12 24528 # Per bank write bursts -system.physmem.perBankRdBursts::13 25564 # Per bank write bursts -system.physmem.perBankRdBursts::14 25798 # Per bank write bursts -system.physmem.perBankRdBursts::15 25721 # Per bank write bursts -system.physmem.perBankWrBursts::0 7829 # Per bank write bursts -system.physmem.perBankWrBursts::1 7671 # Per bank write bursts -system.physmem.perBankWrBursts::2 8071 # Per bank write bursts -system.physmem.perBankWrBursts::3 7745 # Per bank write bursts -system.physmem.perBankWrBursts::4 7318 # Per bank write bursts -system.physmem.perBankWrBursts::5 6944 # Per bank write bursts -system.physmem.perBankWrBursts::6 6788 # Per bank write bursts -system.physmem.perBankWrBursts::7 6427 # Per bank write bursts -system.physmem.perBankWrBursts::8 7237 # Per bank write bursts -system.physmem.perBankWrBursts::9 6873 # Per bank write bursts -system.physmem.perBankWrBursts::10 7386 # Per bank write bursts -system.physmem.perBankWrBursts::11 6888 # Per bank write bursts -system.physmem.perBankWrBursts::12 7081 # Per bank write bursts -system.physmem.perBankWrBursts::13 8010 # Per bank write bursts -system.physmem.perBankWrBursts::14 7995 # Per bank write bursts +system.physmem.perBankRdBursts::10 25520 # Per bank write bursts +system.physmem.perBankRdBursts::11 24876 # Per bank write bursts +system.physmem.perBankRdBursts::12 24529 # Per bank write bursts +system.physmem.perBankRdBursts::13 25563 # Per bank write bursts +system.physmem.perBankRdBursts::14 25801 # Per bank write bursts +system.physmem.perBankRdBursts::15 25723 # Per bank write bursts +system.physmem.perBankWrBursts::0 7828 # Per bank write bursts +system.physmem.perBankWrBursts::1 7672 # Per bank write bursts +system.physmem.perBankWrBursts::2 8070 # Per bank write bursts +system.physmem.perBankWrBursts::3 7747 # Per bank write bursts +system.physmem.perBankWrBursts::4 7316 # Per bank write bursts +system.physmem.perBankWrBursts::5 6943 # Per bank write bursts +system.physmem.perBankWrBursts::6 6787 # Per bank write bursts +system.physmem.perBankWrBursts::7 6421 # Per bank write bursts +system.physmem.perBankWrBursts::8 7240 # Per bank write bursts +system.physmem.perBankWrBursts::9 6874 # Per bank write bursts +system.physmem.perBankWrBursts::10 7389 # Per bank write bursts +system.physmem.perBankWrBursts::11 6891 # Per bank write bursts +system.physmem.perBankWrBursts::12 7084 # Per bank write bursts +system.physmem.perBankWrBursts::13 8012 # Per bank write bursts +system.physmem.perBankWrBursts::14 7998 # Per bank write bursts system.physmem.perBankWrBursts::15 7945 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 68 # Number of times write queue was full causing retry -system.physmem.totGap 1893211891000 # Total gap between requests +system.physmem.numWrRetry 56 # Number of times write queue was full causing retry +system.physmem.totGap 1893218679000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404812 # Read request sizes (log2) +system.physmem.readPktSize::6 404826 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118228 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118235 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -149,206 +149,205 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 169 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63319 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 528.527867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 322.547536 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.556682 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14397 22.74% 22.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11107 17.54% 40.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4705 7.43% 47.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3113 4.92% 52.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2233 3.53% 56.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2328 3.68% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1953 3.08% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1598 2.52% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21885 34.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63319 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5233 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.334798 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2918.735904 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5230 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 136 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63385 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 528.007825 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 321.906071 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.488828 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14518 22.90% 22.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11005 17.36% 40.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4663 7.36% 47.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3176 5.01% 52.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2328 3.67% 56.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2299 3.63% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1937 3.06% 62.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1572 2.48% 65.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21887 34.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63385 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5244 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.176964 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2915.674794 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5241 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5233 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5233 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.588955 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.741886 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.816216 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4718 90.16% 90.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 33 0.63% 90.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 174 3.33% 94.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 5 0.10% 94.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 3 0.06% 94.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 12 0.23% 94.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 8 0.15% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 1 0.02% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 32 0.61% 95.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.08% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 151 2.89% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 15 0.29% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 10 0.19% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.11% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 3 0.06% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 1 0.02% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 10 0.19% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.11% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 12 0.23% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 9 0.17% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 5 0.10% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.08% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5233 # Writes before turning the bus around for reads -system.physmem.totQLat 5895300250 # Total ticks spent queuing -system.physmem.totMemAccLat 13483350250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023480000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14567.23 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5244 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5244 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.543288 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.756988 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.319215 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4714 89.89% 89.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 44 0.84% 90.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 176 3.36% 94.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 4 0.08% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 4 0.08% 94.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 12 0.23% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 7 0.13% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 2 0.04% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 32 0.61% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.10% 95.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 158 3.01% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 14 0.27% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 6 0.11% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 4 0.08% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 6 0.11% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.04% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.04% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 11 0.21% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.08% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 14 0.27% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 9 0.17% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 4 0.08% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 3 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5244 # Writes before turning the bus around for reads +system.physmem.totQLat 5894702000 # Total ticks spent queuing +system.physmem.totMemAccLat 13483145750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023585000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14565.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33317.23 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 33315.00 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.68 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.69 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.81 # Average write queue length when enqueuing -system.physmem.readRowHits 363810 # Number of row buffer hits during reads -system.physmem.writeRowHits 95775 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.90 # Row buffer hit rate for reads +system.physmem.avgWrQLen 23.89 # Average write queue length when enqueuing +system.physmem.readRowHits 363769 # Number of row buffer hits during reads +system.physmem.writeRowHits 95780 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.88 # Row buffer hit rate for reads system.physmem.writeRowHitRate 81.01 # Row buffer hit rate for writes -system.physmem.avgGap 3619631.18 # Average gap between requests -system.physmem.pageHitRate 87.89 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 221882640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 117933420 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1444607640 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 306899460 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4693391040.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4737017490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 303974400 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 10896307530 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 5550083520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 443242644240 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 471515616450 # Total energy per rank (pJ) -system.physmem_0.averagePower 249.054730 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1881921702000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 481983250 # Time in different power states -system.physmem_0.memoryStateTime::REF 1993748000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1843690402750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 14453321750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8706248250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 23895177500 # Time in different power states -system.physmem_1.actEnergy 230215020 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122362185 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1444921800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 310146300 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4816933680.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4925461770 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 303573120 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11119407240 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 5660238720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 442986687510 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 471921610125 # Total energy per rank (pJ) -system.physmem_1.averagePower 249.269176 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1881622925500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 484393500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2046440000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1842500290250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 14740166500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9065047000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 24384544250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 15264339 # Number of BP lookups -system.cpu.branchPred.condPredicted 13122374 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 525708 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12102111 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4571092 # Number of BTB hits +system.physmem.avgGap 3619498.83 # Average gap between requests +system.physmem.pageHitRate 87.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 221604180 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 117785415 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1444679040 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 306852480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4717362000.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4796151000 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 296411520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 10938570180 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 5566653120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 443189598645 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 471596477220 # Total energy per rank (pJ) +system.physmem_0.averagePower 249.096553 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1881819292000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 462054000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2003948000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1843451492500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 14496450250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8825649500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 23988038750 # Time in different power states +system.physmem_1.actEnergy 230964720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122760660 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1445000340 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 310240260 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4792348080.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4813778250 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 297177120 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11174584380 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 5627937120 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 443035577925 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 471852130095 # Total energy per rank (pJ) +system.physmem_1.averagePower 249.231588 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1881891335250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 468372250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2035962000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1842731534750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 14656099500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8829934000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 24505730500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 15259378 # Number of BP lookups +system.cpu.branchPred.condPredicted 13119579 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 525820 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12061992 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4569562 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.771030 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 863726 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33596 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6525159 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 541190 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5983969 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 222121 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 37.883975 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 862888 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32219 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6522078 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 538261 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5983817 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 225046 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9321681 # DTB read hits -system.cpu.dtb.read_misses 17691 # DTB read misses +system.cpu.dtb.read_hits 9322510 # DTB read hits +system.cpu.dtb.read_misses 17386 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 764795 # DTB read accesses -system.cpu.dtb.write_hits 6394158 # DTB write hits -system.cpu.dtb.write_misses 2442 # DTB write misses -system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298776 # DTB write accesses -system.cpu.dtb.data_hits 15715839 # DTB hits -system.cpu.dtb.data_misses 20133 # DTB misses -system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1063571 # DTB accesses -system.cpu.itb.fetch_hits 4020046 # ITB hits -system.cpu.itb.fetch_misses 6280 # ITB misses -system.cpu.itb.fetch_acv 699 # ITB acv -system.cpu.itb.fetch_accesses 4026326 # ITB accesses +system.cpu.dtb.read_accesses 764595 # DTB read accesses +system.cpu.dtb.write_hits 6393584 # DTB write hits +system.cpu.dtb.write_misses 2379 # DTB write misses +system.cpu.dtb.write_acv 158 # DTB write access violations +system.cpu.dtb.write_accesses 298734 # DTB write accesses +system.cpu.dtb.data_hits 15716094 # DTB hits +system.cpu.dtb.data_misses 19765 # DTB misses +system.cpu.dtb.data_acv 369 # DTB access violations +system.cpu.dtb.data_accesses 1063329 # DTB accesses +system.cpu.itb.fetch_hits 4018414 # ITB hits +system.cpu.itb.fetch_misses 6313 # ITB misses +system.cpu.itb.fetch_acv 710 # ITB acv +system.cpu.itb.fetch_accesses 4024727 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -361,29 +360,29 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12752 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281786440.323087 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439974345.162947 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 369000 # Distribution of time spent in the clock gated state +system.cpu.numPwrStateTransitions 12750 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6375 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 281835914.509804 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 440008281.220830 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6375 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 224500 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 96550538000 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1796670343500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 193121889 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 6375 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 96523678000 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1796703955000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 193068084 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56147815 # Number of instructions committed -system.cpu.committedOps 56147815 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2978612 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593319874 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.439526 # CPI: cycles per instruction -system.cpu.ipc 0.290738 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 3199269 5.70% 5.70% # Class of committed instruction -system.cpu.op_class_0::IntAlu 36201024 64.47% 70.17% # Class of committed instruction -system.cpu.op_class_0::IntMult 60831 0.11% 70.28% # Class of committed instruction +system.cpu.committedInsts 56143729 # Number of instructions committed +system.cpu.committedOps 56143729 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2983109 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 6375 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3593387182 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.438818 # CPI: cycles per instruction +system.cpu.ipc 0.290798 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 3199033 5.70% 5.70% # Class of committed instruction +system.cpu.op_class_0::IntAlu 36198718 64.48% 70.17% # Class of committed instruction +system.cpu.op_class_0::IntMult 60825 0.11% 70.28% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction @@ -413,36 +412,36 @@ system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Cl system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::MemRead 9175906 16.34% 86.70% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6235361 11.11% 97.80% # Class of committed instruction +system.cpu.op_class_0::MemRead 9175039 16.34% 86.70% # Class of committed instruction +system.cpu.op_class_0::MemWrite 6234994 11.11% 97.80% # Class of committed instruction system.cpu.op_class_0::FloatMemRead 144497 0.26% 98.06% # Class of committed instruction system.cpu.op_class_0::FloatMemWrite 137980 0.25% 98.31% # Class of committed instruction -system.cpu.op_class_0::IprAccess 951232 1.69% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 950928 1.69% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 56147815 # Class of committed instruction +system.cpu.op_class_0::total 56143729 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211531 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74800 40.93% 40.93% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211453 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74770 40.93% 40.93% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105905 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182741 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73433 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105857 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182663 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73403 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73433 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148902 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1837683771000 97.07% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 86162500 0.00% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 712688000 0.04% 97.11% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 54737244500 2.89% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1893219866000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73403 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148842 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1837707081000 97.07% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 86418000 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 712034000 0.04% 97.11% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 54721100500 2.89% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1893226633500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981717 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693386 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814825 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693417 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814845 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed @@ -450,7 +449,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175574 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175496 91.22% 93.42% # number of callpals executed system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -459,31 +458,31 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192465 # number of callpals executed +system.cpu.kern.callpal::total 192387 # number of callpals executed system.cpu.kern.mode_switch::kernel 5875 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1905 -system.cpu.kern.mode_good::user 1737 +system.cpu.kern.mode_good::kernel 1907 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.324255 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324596 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392541 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 37297482500 1.97% 1.97% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4311459500 0.23% 2.20% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1851610914000 97.80% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.392872 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 37288586500 1.97% 1.97% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4317914500 0.23% 2.20% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1851620122500 97.80% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4174 # number of times the context was actually changed -system.cpu.tickCycles 85352026 # Number of cycles that the object actually ticked -system.cpu.idleCycles 107769863 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1394246 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.980074 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13946627 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1394758 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.999317 # Average number of references to valid blocks. +system.cpu.tickCycles 85319079 # Number of cycles that the object actually ticked +system.cpu.idleCycles 107749005 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1394486 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.980102 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13946466 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1394998 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.997481 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 99338500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.980074 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.980102 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -491,153 +490,153 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 225 system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63927104 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63927104 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7985415 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7985415 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5578562 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5578562 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183593 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183593 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199022 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199022 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13563977 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13563977 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13563977 # number of overall hits -system.cpu.dcache.overall_hits::total 13563977 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1096352 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1096352 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 573692 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573692 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 16450 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 16450 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1670044 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1670044 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1670044 # number of overall misses -system.cpu.dcache.overall_misses::total 1670044 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33571810000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33571810000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25337965000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25337965000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222587500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 222587500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 58909775000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 58909775000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 58909775000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 58909775000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9081767 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9081767 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152254 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152254 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200043 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200043 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199022 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199022 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15234021 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15234021 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15234021 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15234021 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120720 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120720 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093249 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093249 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082232 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082232 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.109626 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.109626 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.109626 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.109626 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30621.378900 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30621.378900 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44166.495262 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44166.495262 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13531.155015 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13531.155015 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35274.384986 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35274.384986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35274.384986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35274.384986 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63927467 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63927467 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 7985618 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7985618 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5578297 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5578297 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183538 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183538 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 198978 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 198978 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13563915 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13563915 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13563915 # number of overall hits +system.cpu.dcache.overall_hits::total 13563915 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1096590 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1096590 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 573634 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573634 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 16462 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 16462 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1670224 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1670224 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1670224 # number of overall misses +system.cpu.dcache.overall_misses::total 1670224 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33587119500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33587119500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25315634500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25315634500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222567500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 222567500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 58902754000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 58902754000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 58902754000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 58902754000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9082208 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9082208 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6151931 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6151931 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200000 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200000 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 198978 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 198978 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15234139 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15234139 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15234139 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15234139 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120740 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120740 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093245 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093245 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082310 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082310 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.109637 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.109637 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.109637 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.109637 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30628.693951 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30628.693951 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44132.032794 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44132.032794 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13520.076540 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13520.076540 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35266.379839 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35266.379839 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35266.379839 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35266.379839 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 837664 # number of writebacks -system.cpu.dcache.writebacks::total 837664 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21993 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21993 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269693 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269693 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 837775 # number of writebacks +system.cpu.dcache.writebacks::total 837775 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21966 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21966 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269674 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269674 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 291686 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 291686 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 291686 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 291686 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074359 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074359 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303999 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 303999 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16447 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16447 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378358 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378358 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378358 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378358 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 291640 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 291640 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 291640 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 291640 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074624 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074624 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303960 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 303960 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16459 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16459 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1378584 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378584 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1378584 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378584 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32011150000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32011150000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12927980000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12927980000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205437000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205437000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44939130000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 44939130000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44939130000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 44939130000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534184500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534184500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534184500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534184500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118298 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118298 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049413 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049413 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082217 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082217 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090479 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090479 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090479 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090479 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29795.580434 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29795.580434 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42526.389889 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42526.389889 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12490.849395 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12490.849395 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32603.380254 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32603.380254 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32603.380254 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32603.380254 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221383.044733 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221383.044733 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92683.169214 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92683.169214 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1477105 # number of replacements -system.cpu.icache.tags.tagsinuse 509.256263 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 19233040 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1477616 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13.016264 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 36168250500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.256263 # Average occupied blocks per requestor +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32024640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32024640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12912591500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12912591500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205405000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205405000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44937231500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44937231500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44937231500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44937231500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534181500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534181500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534181500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534181500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118322 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118322 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049409 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049409 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082295 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082295 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090493 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090493 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090493 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090493 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29800.786135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29800.786135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42481.219568 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42481.219568 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12479.798287 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12479.798287 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32596.658238 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32596.658238 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32596.658238 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32596.658238 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221382.611833 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221382.611833 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92682.987978 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92682.987978 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1476860 # number of replacements +system.cpu.icache.tags.tagsinuse 509.256241 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 19221452 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1477371 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.010579 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 36168783500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.256241 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.994641 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.994641 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -645,319 +644,320 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 104 system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 22188623 # Number of tag accesses -system.cpu.icache.tags.data_accesses 22188623 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 19233043 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 19233043 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 19233043 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 19233043 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 19233043 # number of overall hits -system.cpu.icache.overall_hits::total 19233043 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1477790 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1477790 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1477790 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1477790 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1477790 # number of overall misses -system.cpu.icache.overall_misses::total 1477790 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20696583500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20696583500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20696583500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20696583500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20696583500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20696583500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 20710833 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 20710833 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 20710833 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 20710833 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 20710833 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 20710833 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071353 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.071353 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.071353 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.071353 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.071353 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.071353 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14005.091048 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14005.091048 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14005.091048 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14005.091048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14005.091048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14005.091048 # average overall miss latency +system.cpu.icache.tags.tag_accesses 22176547 # Number of tag accesses +system.cpu.icache.tags.data_accesses 22176547 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 19221455 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 19221455 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 19221455 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 19221455 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 19221455 # number of overall hits +system.cpu.icache.overall_hits::total 19221455 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1477546 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1477546 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1477546 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1477546 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1477546 # number of overall misses +system.cpu.icache.overall_misses::total 1477546 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20691200000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20691200000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20691200000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20691200000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20691200000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20691200000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 20699001 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 20699001 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 20699001 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 20699001 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 20699001 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 20699001 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071382 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.071382 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.071382 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.071382 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.071382 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.071382 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14003.760289 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14003.760289 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14003.760289 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14003.760289 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14003.760289 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14003.760289 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1477105 # number of writebacks -system.cpu.icache.writebacks::total 1477105 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1477790 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1477790 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1477790 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1477790 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1477790 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1477790 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19218793500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19218793500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19218793500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19218793500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19218793500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19218793500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071353 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071353 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071353 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071353 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13005.091048 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13005.091048 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13005.091048 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13005.091048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13005.091048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13005.091048 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 339628 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65408.612363 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5336325 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 405150 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.171233 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6812996000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 268.308875 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5785.000603 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59355.302886 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.004094 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088272 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.905690 # Average percentage of cache occupancy +system.cpu.icache.writebacks::writebacks 1476860 # number of writebacks +system.cpu.icache.writebacks::total 1476860 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1477546 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1477546 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1477546 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1477546 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1477546 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1477546 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19213654000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19213654000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19213654000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19213654000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19213654000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19213654000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071382 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.071382 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.071382 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13003.760289 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13003.760289 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13003.760289 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13003.760289 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13003.760289 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13003.760289 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 339644 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65408.616626 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5336317 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 405166 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.170693 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6813000000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 268.269404 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5779.515007 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59360.832216 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.004093 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088188 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.905774 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998056 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 578 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 457 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59344 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5148 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59335 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 46341016 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 46341016 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 837664 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 837664 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1476525 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1476525 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 46341070 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 46341070 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 837775 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 837775 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1476292 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1476292 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 15 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187358 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187358 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461386 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1461386 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818548 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 818548 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1461386 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1005906 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2467292 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1461386 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1005906 # number of overall hits -system.cpu.l2cache.overall_hits::total 2467292 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187328 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187328 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461124 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1461124 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818824 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 818824 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1461124 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1006152 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2467276 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1461124 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1006152 # number of overall hits +system.cpu.l2cache.overall_hits::total 2467276 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116652 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116652 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16348 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 16348 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272226 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 272226 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 16348 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388878 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405226 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 16348 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388878 # number of overall misses -system.cpu.l2cache.overall_misses::total 405226 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 331000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 331000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10499091500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10499091500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1618484000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1618484000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21963269500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 21963269500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1618484000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 32462361000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34080845000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1618484000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 32462361000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34080845000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 837664 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 837664 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1476525 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1476525 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 116642 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116642 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16369 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 16369 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272228 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 272228 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 16369 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388870 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405239 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 16369 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388870 # number of overall misses +system.cpu.l2cache.overall_misses::total 405239 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 331500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 331500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10483953000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10483953000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1616348000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1616348000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21973293500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 21973293500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1616348000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 32457246500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34073594500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1616348000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 32457246500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34073594500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 837775 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 837775 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1476292 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1476292 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 21 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304010 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304010 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1477734 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1477734 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1090774 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1090774 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1477734 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1394784 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2872518 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1477734 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1394784 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2872518 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 303970 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 303970 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1477493 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1477493 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091052 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1091052 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1477493 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1395022 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2872515 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1477493 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1395022 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2872515 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.285714 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383711 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383711 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011063 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011063 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249571 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249571 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011063 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.278809 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.141070 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011063 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.278809 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.141070 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 55166.666667 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 55166.666667 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90003.527586 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90003.527586 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 99001.957426 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 99001.957426 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80680.278519 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80680.278519 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 99001.957426 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83476.979927 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84103.302848 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 99001.957426 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83476.979927 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84103.302848 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383729 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383729 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011079 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011079 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249510 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249510 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011079 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.278755 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.141075 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011079 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.278755 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.141075 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 55250 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 55250 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89881.457794 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89881.457794 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 98744.455984 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 98744.455984 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80716.507854 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80716.507854 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 98744.455984 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83465.545041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84082.712918 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 98744.455984 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83465.545041 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84082.712918 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 76716 # number of writebacks -system.cpu.l2cache.writebacks::total 76716 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 76723 # number of writebacks +system.cpu.l2cache.writebacks::total 76723 # number of writebacks system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116652 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116652 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16348 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16348 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272226 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272226 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16348 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388878 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405226 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16348 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388878 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405226 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116642 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116642 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16369 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16369 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272228 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272228 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16369 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388870 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405239 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16369 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388870 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405239 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 271000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9332571500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9332571500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1455004000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1455004000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19244147500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19244147500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1455004000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28576719000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30031723000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1455004000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28576719000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30031723000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447540500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447540500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447540500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447540500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 271500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9317533000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9317533000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1452658000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1452658000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19254021000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19254021000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1452658000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28571554000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30024212000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1452658000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28571554000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30024212000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447536000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447536000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447536000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447536000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383711 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383711 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011063 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249571 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249571 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278809 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141070 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278809 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141070 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 45166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 45166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80003.527586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80003.527586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 89001.957426 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 89001.957426 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70691.805706 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70691.805706 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 89001.957426 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73485.049296 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74111.046675 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 89001.957426 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73485.049296 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74111.046675 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208880.303030 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208880.303030 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87448.831028 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87448.831028 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5743946 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871549 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 999 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383729 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383729 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011079 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249510 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249510 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278755 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141075 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278755 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141075 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 45250 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 45250 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79881.457794 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79881.457794 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 88744.455984 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 88744.455984 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70727.555578 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70727.555578 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 88744.455984 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73473.278988 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74090.134464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 88744.455984 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73473.278988 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74090.134464 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208879.653680 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208879.653680 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87448.559174 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87448.559174 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5743935 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871442 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2378 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 998 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 998 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2575626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2575661 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 914380 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1477105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 819494 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 914498 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1476860 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 819632 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1090934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 242 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4432629 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217118 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8649747 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189109696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142929468 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 332039164 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 340242 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4923392 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3229178 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000972 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.031158 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 303970 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 303970 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477546 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 23 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4431899 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217835 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8649734 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189078592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142951868 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 332030460 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 340255 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4923648 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3229187 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001046 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032331 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3226040 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3138 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3225808 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3379 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3229178 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5199830000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3229187 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5199690500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 292383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2216814740 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2216461215 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2103909988 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2104266491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -971,7 +971,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51175 # Transaction distribution @@ -1002,46 +1002,46 @@ system.iobus.pkt_size_system.bridge.master::total 44348 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5417000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5413000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 803500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 807000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 181000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15637500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15127500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6005000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5984000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216245035 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216248283 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.299106 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.299538 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1735874546000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.299106 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081194 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081194 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1735874305000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.299538 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081221 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081221 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1050,14 +1050,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22024383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22024383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4948308652 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4948308652 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4970333035 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4970333035 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4970333035 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4970333035 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 29884383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29884383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4931902900 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4931902900 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4961787283 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4961787283 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4961787283 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4961787283 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1074,19 +1074,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 127308.572254 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 127308.572254 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119087.135445 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 119087.135445 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 119121.223128 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119121.223128 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 119121.223128 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119121.223128 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1402 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 172742.098266 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 172742.098266 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118692.310839 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118692.310839 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118916.411815 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118916.411815 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118916.411815 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118916.411815 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 893 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 13 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 107.846154 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 111.625000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1098,14 +1098,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13374383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13374383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2868251757 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2868251757 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2881626140 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2881626140 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2881626140 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2881626140 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 21234383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 21234383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2851851307 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2851851307 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2873085690 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2873085690 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2873085690 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2873085690 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1114,75 +1114,76 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 77308.572254 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 77308.572254 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69028.007244 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69028.007244 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69062.340084 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 69062.340084 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69062.340084 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 69062.340084 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 827498 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 381477 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 410 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 122742.098266 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 122742.098266 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68633.310238 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68633.310238 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68857.655842 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68857.655842 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68857.655842 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68857.655842 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 827515 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 381393 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 524 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295653 # Transaction distribution +system.membus.trans_dist::ReadResp 295677 # Transaction distribution system.membus.trans_dist::WriteReq 9623 # Transaction distribution system.membus.trans_dist::WriteResp 9623 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118228 # Transaction distribution -system.membus.trans_dist::CleanEvict 262245 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118235 # Transaction distribution +system.membus.trans_dist::CleanEvict 262254 # Transaction distribution system.membus.trans_dist::UpgradeReq 138 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 116520 # Transaction distribution -system.membus.trans_dist::ReadExResp 116520 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288747 # Transaction distribution -system.membus.trans_dist::BadAddressError 24 # Transaction distribution +system.membus.trans_dist::ReadExReq 116510 # Transaction distribution +system.membus.trans_dist::ReadExResp 116510 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288770 # Transaction distribution +system.membus.trans_dist::BadAddressError 23 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 127 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181947 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148837 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 46 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181989 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1265372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1265414 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30861180 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30818176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30862524 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33518908 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 434 # Total snoops (count) +system.membus.pkt_size::total 33520252 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 561 # Total snoops (count) system.membus.snoopTraffic 27584 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 463510 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001463 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.038218 # Request fanout histogram +system.membus.snoop_fanout::samples 463523 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001461 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038189 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 462832 99.85% 99.85% # Request fanout histogram -system.membus.snoop_fanout::1 678 0.15% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 462846 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 463510 # Request fanout histogram -system.membus.reqLayer0.occupancy 30461000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 463523 # Request fanout histogram +system.membus.reqLayer0.occupancy 29930000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319556082 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1319547835 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 29000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160064000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160176250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1081022 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1214,28 +1215,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index d900375a8..53cfb4ebd 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.907549 # Number of seconds simulated -sim_ticks 1907549438500 # Number of ticks simulated -final_tick 1907549438500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.909484 # Number of seconds simulated +sim_ticks 1909483951500 # Number of ticks simulated +final_tick 1909483951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 237406 # Simulator instruction rate (inst/s) -host_op_rate 237406 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7990338524 # Simulator tick rate (ticks/s) -host_mem_usage 342872 # Number of bytes of host memory used -host_seconds 238.73 # Real time elapsed on the host -sim_insts 56676315 # Number of instructions simulated -sim_ops 56676315 # Number of ops (including micro ops) simulated +host_inst_rate 164890 # Simulator instruction rate (inst/s) +host_op_rate 164890 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5556117262 # Simulator tick rate (ticks/s) +host_mem_usage 341236 # Number of bytes of host memory used +host_seconds 343.67 # Real time elapsed on the host +sim_insts 56668174 # Number of instructions simulated +sim_ops 56668174 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 857728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24440448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 121088 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24440064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 121024 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 888256 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26308480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 857728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 121088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 978816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7911424 # Number of bytes written to this memory -system.physmem.bytes_written::total 7911424 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13402 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 381882 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1892 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26307904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 857600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 121024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 978624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7910400 # Number of bytes written to this memory +system.physmem.bytes_written::total 7910400 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13400 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 381876 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1891 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 13879 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 411070 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123616 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123616 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 449649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12812485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 63478 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 465653 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 411061 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123600 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123600 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 449127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12799303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 63380 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 465181 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13791768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 449649 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 63478 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4147428 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4147428 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4147428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 449649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12812485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 63478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 465653 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13777494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 449127 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 63380 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512507 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4142690 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4142690 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4142690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 449127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12799303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 63380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 465181 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17939196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 411070 # Number of read requests accepted -system.physmem.writeReqs 123616 # Number of write requests accepted -system.physmem.readBursts 411070 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123616 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26300288 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue -system.physmem.bytesWritten 7909696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26308480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7911424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17920184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 411061 # Number of read requests accepted +system.physmem.writeReqs 123600 # Number of write requests accepted +system.physmem.readBursts 411061 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123600 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26300672 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue +system.physmem.bytesWritten 7909120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26307904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7910400 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26240 # Per bank write bursts -system.physmem.perBankRdBursts::1 25986 # Per bank write bursts -system.physmem.perBankRdBursts::2 25958 # Per bank write bursts -system.physmem.perBankRdBursts::3 25690 # Per bank write bursts -system.physmem.perBankRdBursts::4 25582 # Per bank write bursts -system.physmem.perBankRdBursts::5 25570 # Per bank write bursts -system.physmem.perBankRdBursts::6 25628 # Per bank write bursts -system.physmem.perBankRdBursts::7 25343 # Per bank write bursts +system.physmem.perBankRdBursts::0 26241 # Per bank write bursts +system.physmem.perBankRdBursts::1 25988 # Per bank write bursts +system.physmem.perBankRdBursts::2 25972 # Per bank write bursts +system.physmem.perBankRdBursts::3 25684 # Per bank write bursts +system.physmem.perBankRdBursts::4 25579 # Per bank write bursts +system.physmem.perBankRdBursts::5 25567 # Per bank write bursts +system.physmem.perBankRdBursts::6 25634 # Per bank write bursts +system.physmem.perBankRdBursts::7 25346 # Per bank write bursts system.physmem.perBankRdBursts::8 25590 # Per bank write bursts -system.physmem.perBankRdBursts::9 25698 # Per bank write bursts -system.physmem.perBankRdBursts::10 25929 # Per bank write bursts -system.physmem.perBankRdBursts::11 25525 # Per bank write bursts +system.physmem.perBankRdBursts::9 25694 # Per bank write bursts +system.physmem.perBankRdBursts::10 25928 # Per bank write bursts +system.physmem.perBankRdBursts::11 25514 # Per bank write bursts system.physmem.perBankRdBursts::12 26076 # Per bank write bursts -system.physmem.perBankRdBursts::13 25420 # Per bank write bursts -system.physmem.perBankRdBursts::14 25099 # Per bank write bursts -system.physmem.perBankRdBursts::15 25608 # Per bank write bursts -system.physmem.perBankWrBursts::0 8587 # Per bank write bursts +system.physmem.perBankRdBursts::13 25422 # Per bank write bursts +system.physmem.perBankRdBursts::14 25093 # Per bank write bursts +system.physmem.perBankRdBursts::15 25620 # Per bank write bursts +system.physmem.perBankWrBursts::0 8582 # Per bank write bursts system.physmem.perBankWrBursts::1 8090 # Per bank write bursts -system.physmem.perBankWrBursts::2 7940 # Per bank write bursts -system.physmem.perBankWrBursts::3 7436 # Per bank write bursts -system.physmem.perBankWrBursts::4 7275 # Per bank write bursts -system.physmem.perBankWrBursts::5 7415 # Per bank write bursts -system.physmem.perBankWrBursts::6 7544 # Per bank write bursts -system.physmem.perBankWrBursts::7 7156 # Per bank write bursts +system.physmem.perBankWrBursts::2 7941 # Per bank write bursts +system.physmem.perBankWrBursts::3 7423 # Per bank write bursts +system.physmem.perBankWrBursts::4 7276 # Per bank write bursts +system.physmem.perBankWrBursts::5 7412 # Per bank write bursts +system.physmem.perBankWrBursts::6 7548 # Per bank write bursts +system.physmem.perBankWrBursts::7 7160 # Per bank write bursts system.physmem.perBankWrBursts::8 7532 # Per bank write bursts -system.physmem.perBankWrBursts::9 7639 # Per bank write bursts -system.physmem.perBankWrBursts::10 7820 # Per bank write bursts -system.physmem.perBankWrBursts::11 7739 # Per bank write bursts -system.physmem.perBankWrBursts::12 8260 # Per bank write bursts -system.physmem.perBankWrBursts::13 7848 # Per bank write bursts -system.physmem.perBankWrBursts::14 7518 # Per bank write bursts -system.physmem.perBankWrBursts::15 7790 # Per bank write bursts +system.physmem.perBankWrBursts::9 7637 # Per bank write bursts +system.physmem.perBankWrBursts::10 7817 # Per bank write bursts +system.physmem.perBankWrBursts::11 7733 # Per bank write bursts +system.physmem.perBankWrBursts::12 8265 # Per bank write bursts +system.physmem.perBankWrBursts::13 7849 # Per bank write bursts +system.physmem.perBankWrBursts::14 7512 # Per bank write bursts +system.physmem.perBankWrBursts::15 7803 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 73 # Number of times write queue was full causing retry -system.physmem.totGap 1907545081500 # Total gap between requests +system.physmem.numWrRetry 80 # Number of times write queue was full causing retry +system.physmem.totGap 1909479571500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 411070 # Read request sizes (log2) +system.physmem.readPktSize::6 411061 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123616 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 316681 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 38865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25023 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 26 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123600 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 316679 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -159,206 +159,205 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7441 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 187 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.308940 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 323.701196 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.289256 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14473 22.48% 22.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11513 17.88% 40.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5038 7.82% 48.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2819 4.38% 52.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2271 3.53% 56.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1853 2.88% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1969 3.06% 62.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1608 2.50% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22844 35.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64388 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5502 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.686478 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2827.616380 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5499 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::45 370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 213 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64366 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 531.481590 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 324.184214 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.960810 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14447 22.45% 22.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11484 17.84% 40.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5025 7.81% 48.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2916 4.53% 52.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2241 3.48% 56.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1886 2.93% 59.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1937 3.01% 62.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1616 2.51% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22814 35.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64366 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5520 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.445833 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2823.039428 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5517 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5502 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5502 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.462559 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.761271 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.372868 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4982 90.55% 90.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 39 0.71% 91.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 171 3.11% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 6 0.11% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 5 0.09% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 13 0.24% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 3 0.05% 94.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 6 0.11% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 29 0.53% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 6 0.11% 95.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 149 2.71% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 8 0.15% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 14 0.25% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 3 0.05% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 12 0.22% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 2 0.04% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.02% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.04% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 11 0.20% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 6 0.11% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 14 0.25% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 8 0.15% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 5 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5520 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5520 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.387681 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.753213 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.953412 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4982 90.25% 90.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 46 0.83% 91.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 181 3.28% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 8 0.14% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 3 0.05% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 15 0.27% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 3 0.05% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 1 0.02% 94.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 37 0.67% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 6 0.11% 95.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 147 2.66% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 11 0.20% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 11 0.20% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.02% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 13 0.24% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 5 0.09% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.04% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 4 0.07% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.11% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 8 0.14% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 11 0.20% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 8 0.14% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 6 0.11% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5502 # Writes before turning the bus around for reads -system.physmem.totQLat 8174654750 # Total ticks spent queuing -system.physmem.totMemAccLat 15879817250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2054710000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19892.48 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5520 # Writes before turning the bus around for reads +system.physmem.totQLat 8180795500 # Total ticks spent queuing +system.physmem.totMemAccLat 15886070500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2054740000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19907.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38642.48 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.79 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.15 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.79 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.15 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38657.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.34 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.44 # Average write queue length when enqueuing -system.physmem.readRowHits 370634 # Number of row buffer hits during reads -system.physmem.writeRowHits 99508 # Number of row buffer hits during writes +system.physmem.avgRdQLen 2.22 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing +system.physmem.readRowHits 370615 # Number of row buffer hits during reads +system.physmem.writeRowHits 99546 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.50 # Row buffer hit rate for writes -system.physmem.avgGap 3567598.71 # Average gap between requests +system.physmem.writeRowHitRate 80.54 # Row buffer hit rate for writes +system.physmem.avgGap 3571383.68 # Average gap between requests system.physmem.pageHitRate 87.95 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229108320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 121773960 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1470818580 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 320732460 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3850104960.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4304249550 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 244489440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 8392475940 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 4645539360 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 448697608680 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 472278008880 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.583627 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1897458465500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 385946750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1635552000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1866968885000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 12097849250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8056520750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 18404684750 # Time in different power states -system.physmem_1.actEnergy 230629140 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122578500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1463307300 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 324402120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3763440720.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4252821870 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 240122400 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 8356841250 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 4387202880 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 448891199505 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 472033988085 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.455703 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1897589722250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 380622500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1598754000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1867843123750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 11424948500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7975953750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 18326036000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu0.branchPred.lookups 16746871 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14324468 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 462281 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10727156 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4756454 # Number of BTB hits +system.physmem_0.actEnergy 229044060 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 121739805 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1470918540 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 320675040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3850719600.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4272567240 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 246889440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 8425769640 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 4664365920 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 449143940805 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 472747584480 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.578716 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1899455525250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 389729500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1635812000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1868844860000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 12146835250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7989359750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 18477355000 # Time in different power states +system.physmem_1.actEnergy 230536320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122529165 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1463250180 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 324412560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3755450400.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4276202130 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 236380800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8298087360 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 4412246880 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 449354887095 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 472475862540 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.436414 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1899482388000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 371395250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1595272000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1869798792500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 11490281750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8030486500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 18197723500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu0.branchPred.lookups 16749334 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14325553 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 462257 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10374415 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4757954 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 44.340308 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 926491 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 34071 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 5119287 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 497756 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 4621531 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 206577 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 45.862384 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 926589 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 34524 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 4807269 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 496703 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 4310566 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 206845 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9412979 # DTB read hits -system.cpu0.dtb.read_misses 34328 # DTB read misses -system.cpu0.dtb.read_acv 621 # DTB read access violations -system.cpu0.dtb.read_accesses 567042 # DTB read accesses -system.cpu0.dtb.write_hits 5709982 # DTB write hits -system.cpu0.dtb.write_misses 8326 # DTB write misses -system.cpu0.dtb.write_acv 453 # DTB write access violations -system.cpu0.dtb.write_accesses 184750 # DTB write accesses -system.cpu0.dtb.data_hits 15122961 # DTB hits -system.cpu0.dtb.data_misses 42654 # DTB misses -system.cpu0.dtb.data_acv 1074 # DTB access violations -system.cpu0.dtb.data_accesses 751792 # DTB accesses -system.cpu0.itb.fetch_hits 1307701 # ITB hits -system.cpu0.itb.fetch_misses 6903 # ITB misses -system.cpu0.itb.fetch_acv 605 # ITB acv -system.cpu0.itb.fetch_accesses 1314604 # ITB accesses +system.cpu0.dtb.read_hits 9423503 # DTB read hits +system.cpu0.dtb.read_misses 34044 # DTB read misses +system.cpu0.dtb.read_acv 602 # DTB read access violations +system.cpu0.dtb.read_accesses 567323 # DTB read accesses +system.cpu0.dtb.write_hits 5707426 # DTB write hits +system.cpu0.dtb.write_misses 8375 # DTB write misses +system.cpu0.dtb.write_acv 432 # DTB write access violations +system.cpu0.dtb.write_accesses 185068 # DTB write accesses +system.cpu0.dtb.data_hits 15130929 # DTB hits +system.cpu0.dtb.data_misses 42419 # DTB misses +system.cpu0.dtb.data_acv 1034 # DTB access violations +system.cpu0.dtb.data_accesses 752391 # DTB accesses +system.cpu0.itb.fetch_hits 1309826 # ITB hits +system.cpu0.itb.fetch_misses 6979 # ITB misses +system.cpu0.itb.fetch_acv 608 # ITB acv +system.cpu0.itb.fetch_accesses 1316805 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -371,271 +370,272 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 12949 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6475 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 285376318.378378 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 440714536.369915 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6475 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 79500 # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 12955 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6478 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 285544950.833745 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 440803858.104390 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 6477 99.98% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6475 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 59737777000 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1847811661500 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 119482029 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 6478 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 59723759999 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849760191501 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 119453997 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25760123 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 73391497 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16746871 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6180701 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 86881424 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1333696 # Number of cycles fetch has spent squashing +system.cpu0.fetch.icacheStallCycles 25744550 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 73396662 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16749334 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6181246 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 86853986 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1333740 # Number of cycles fetch has spent squashing system.cpu0.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 31404 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 137910 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 424032 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 391 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8451225 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 316387 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 113902133 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.644338 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.954525 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.MiscStallCycles 29854 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 138979 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 426939 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8448706 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 314842 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 113861488 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.644614 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.955082 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 100270966 88.03% 88.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 886228 0.78% 88.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1867927 1.64% 90.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 772028 0.68% 91.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2612142 2.29% 93.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 579506 0.51% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 682297 0.60% 94.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 834861 0.73% 95.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5396178 4.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 100232411 88.03% 88.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 886423 0.78% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1866278 1.64% 90.45% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 772305 0.68% 91.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2608424 2.29% 93.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 580288 0.51% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 680998 0.60% 94.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 835244 0.73% 95.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5399117 4.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 113902133 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.140162 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.614247 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 20705856 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 82013409 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8738075 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1805880 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 638912 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 611998 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 28528 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 63750944 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 85334 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 638912 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 21566893 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 55682864 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17571842 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9616135 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 8825485 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 61313705 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 198555 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2000786 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 244905 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4945993 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 41348673 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 74029068 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 73897769 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 122571 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33810397 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7538276 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1420468 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 230583 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12282803 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9801073 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6065767 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1438850 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 936003 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 54214575 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1853218 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52616152 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 74253 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9353064 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 4027640 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1289091 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 113902133 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.461942 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.202978 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 113861488 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.140216 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.614435 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 20674409 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 82009104 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8737077 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1802336 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 638561 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 612096 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 28873 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 63730808 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 85670 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 638561 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 21537349 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 55655987 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17571911 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9607617 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 8850061 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 61287779 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 195487 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2001492 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 247198 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4966656 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 41332689 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 73998496 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 73867344 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 122420 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33806898 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7525791 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1421231 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 231053 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12310515 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9804371 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6066029 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1436076 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 935297 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 54210960 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1853678 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52617678 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 75373 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9354795 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 4029114 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1289525 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 113861488 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.462120 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.203620 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 92500805 81.21% 81.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9147500 8.03% 89.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3821730 3.36% 92.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2743420 2.41% 95.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2859412 2.51% 97.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1408857 1.24% 98.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 945269 0.83% 99.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 359735 0.32% 99.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 115405 0.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 92467205 81.21% 81.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9144132 8.03% 89.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3819872 3.35% 92.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2741139 2.41% 95.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2853722 2.51% 97.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1412384 1.24% 98.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 945124 0.83% 99.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 360447 0.32% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 117463 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 113902133 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 113861488 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 168885 16.81% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 486832 48.47% 65.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 300564 29.92% 95.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemRead 26620 2.65% 97.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemWrite 21571 2.15% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 167498 16.72% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 489097 48.82% 65.54% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 297116 29.66% 95.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemRead 26550 2.65% 97.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemWrite 21561 2.15% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2537 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 36110587 68.63% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 55774 0.11% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 25398 0.05% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9721676 18.48% 87.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5686986 10.81% 98.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemRead 122455 0.23% 98.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemWrite 110756 0.21% 98.52% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 778716 1.48% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2541 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 36104376 68.62% 68.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 55717 0.11% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 25404 0.05% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9732272 18.50% 87.27% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5684196 10.80% 98.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemRead 122332 0.23% 98.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemWrite 110816 0.21% 98.52% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 778757 1.48% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52616152 # Type of FU issued -system.cpu0.iq.rate 0.440369 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1004472 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019091 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 219643746 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 65164078 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50897823 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 569416 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 274599 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 257683 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 53310020 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 308067 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 606515 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52617678 # Type of FU issued +system.cpu0.iq.rate 0.440485 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1001822 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019040 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 219604859 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 65162997 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50893555 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 569180 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 274272 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 257685 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 53309029 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 307930 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 608555 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1936563 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4258 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18275 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 663361 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1940010 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3457 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18333 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 663404 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18355 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 359900 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18340 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 362661 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 638912 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 52175649 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1047801 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 59607584 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 159494 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9801073 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6065767 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1641866 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39898 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 807337 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18275 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 179860 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 504304 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 684164 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51934418 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9472740 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 681734 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 638561 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 52164612 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1031418 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 59600447 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 153776 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9804371 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6066029 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1643055 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39666 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 791016 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18333 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 179892 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 504278 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 684170 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51936356 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9483037 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 681322 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3539791 # number of nop insts executed -system.cpu0.iew.exec_refs 15207952 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8258466 # Number of branches executed -system.cpu0.iew.exec_stores 5735212 # Number of stores executed -system.cpu0.iew.exec_rate 0.434663 # Inst execution rate -system.cpu0.iew.wb_sent 51337506 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51155506 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26224773 # num instructions producing a value -system.cpu0.iew.wb_consumers 36250862 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.428144 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.723425 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 9849450 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 564127 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 611071 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 112190301 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.442089 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.364280 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 3535809 # number of nop insts executed +system.cpu0.iew.exec_refs 15215766 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8258108 # Number of branches executed +system.cpu0.iew.exec_stores 5732729 # Number of stores executed +system.cpu0.iew.exec_rate 0.434781 # Inst execution rate +system.cpu0.iew.wb_sent 51332154 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51151240 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26231692 # num instructions producing a value +system.cpu0.iew.wb_consumers 36261297 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.428209 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.723407 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 9848757 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 564153 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 610679 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 112148809 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.442210 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.364760 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 94635636 84.35% 84.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6985533 6.23% 90.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3776917 3.37% 93.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2005568 1.79% 95.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1565673 1.40% 97.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 565948 0.50% 97.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 418764 0.37% 98.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 453132 0.40% 98.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1783130 1.59% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 94602668 84.35% 84.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6980008 6.22% 90.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3776982 3.37% 93.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2002013 1.79% 95.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1561505 1.39% 97.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 569175 0.51% 97.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 418696 0.37% 98.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 452906 0.40% 98.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1784856 1.59% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 112190301 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 49598051 # Number of instructions committed -system.cpu0.commit.committedOps 49598051 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 112148809 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 49593272 # Number of instructions committed +system.cpu0.commit.committedOps 49593272 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13266916 # Number of memory references committed -system.cpu0.commit.loads 7864510 # Number of loads committed -system.cpu0.commit.membars 192309 # Number of memory barriers committed -system.cpu0.commit.branches 7509354 # Number of branches committed -system.cpu0.commit.fp_insts 248727 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 45907115 # Number of committed integer instructions. -system.cpu0.commit.function_calls 632192 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2885858 5.82% 5.82% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 32387672 65.30% 71.12% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 54445 0.11% 71.23% # Class of committed instruction +system.cpu0.commit.refs 13266986 # Number of memory references committed +system.cpu0.commit.loads 7864361 # Number of loads committed +system.cpu0.commit.membars 192313 # Number of memory barriers committed +system.cpu0.commit.branches 7507748 # Number of branches committed +system.cpu0.commit.fp_insts 248828 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 45902219 # Number of committed integer instructions. +system.cpu0.commit.function_calls 632222 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2885965 5.82% 5.82% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 32382704 65.30% 71.12% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 54404 0.11% 71.23% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.23% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 24929 0.05% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 24932 0.05% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.28% # Class of committed instruction @@ -663,324 +663,324 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.28% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7943636 16.02% 87.30% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5298998 10.68% 97.98% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemRead 113183 0.23% 98.21% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemWrite 109348 0.22% 98.43% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 778715 1.57% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7943457 16.02% 87.30% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5299157 10.69% 97.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemRead 113217 0.23% 98.21% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemWrite 109412 0.22% 98.43% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 778757 1.57% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 49598051 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1783130 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 169680194 # The number of ROB reads -system.cpu0.rob.rob_writes 120607262 # The number of ROB writes -system.cpu0.timesIdled 481372 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5579896 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3694980588 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 46714728 # Number of Instructions Simulated -system.cpu0.committedOps 46714728 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.557695 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.557695 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.390977 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.390977 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 68002319 # number of integer regfile reads -system.cpu0.int_regfile_writes 37262146 # number of integer regfile writes -system.cpu0.fp_regfile_reads 121389 # number of floating regfile reads -system.cpu0.fp_regfile_writes 130195 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1657828 # number of misc regfile reads -system.cpu0.misc_regfile_writes 782201 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1253317 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.016530 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10648438 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1253753 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.493250 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 49593272 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1784856 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 169631516 # The number of ROB reads +system.cpu0.rob.rob_writes 120597460 # The number of ROB writes +system.cpu0.timesIdled 479927 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5592509 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3698912124 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 46709842 # Number of Instructions Simulated +system.cpu0.committedOps 46709842 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.557362 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.557362 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.391028 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.391028 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 67996788 # number of integer regfile reads +system.cpu0.int_regfile_writes 37259313 # number of integer regfile writes +system.cpu0.fp_regfile_reads 121463 # number of floating regfile reads +system.cpu0.fp_regfile_writes 130119 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1657761 # number of misc regfile reads +system.cpu0.misc_regfile_writes 782234 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1252644 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.062362 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10655904 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1253074 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.503811 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 28164500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.016530 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988314 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988314 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 436 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 414 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.851562 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56881554 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56881554 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6768789 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6768789 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3521179 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3521179 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174329 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174329 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 179913 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 179913 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10289968 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10289968 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10289968 # number of overall hits -system.cpu0.dcache.overall_hits::total 10289968 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1553170 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1553170 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1684058 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1684058 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20354 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20354 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3039 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3039 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3237228 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3237228 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3237228 # number of overall misses -system.cpu0.dcache.overall_misses::total 3237228 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41477053500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 41477053500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85173031211 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 85173031211 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 394024000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 394024000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17098500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 17098500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 126650084711 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 126650084711 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 126650084711 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 126650084711 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8321959 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8321959 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5205237 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5205237 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194683 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 194683 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182952 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 182952 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13527196 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13527196 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13527196 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13527196 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186635 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.186635 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323531 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323531 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104549 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104549 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016611 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016611 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239313 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.239313 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239313 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.239313 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26704.773785 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26704.773785 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50576.067577 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50576.067577 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 19358.553601 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 19358.553601 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5626.357354 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5626.357354 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39123.004222 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39123.004222 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39123.004222 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39123.004222 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4484825 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 6096 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 108156 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 130 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.466262 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 46.892308 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 737739 # number of writebacks -system.cpu0.dcache.writebacks::total 737739 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 551343 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 551343 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432280 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1432280 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5686 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5686 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983623 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1983623 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983623 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1983623 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1001827 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1001827 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251778 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251778 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14668 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14668 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3039 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3039 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1253605 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1253605 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1253605 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1253605 # number of overall MSHR misses +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.062362 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988403 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988403 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.839844 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 56905298 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56905298 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 6776069 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6776069 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3521167 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3521167 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174528 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174528 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 179927 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 179927 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10297236 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10297236 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10297236 # number of overall hits +system.cpu0.dcache.overall_hits::total 10297236 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1551541 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1551541 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1684277 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1684277 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20385 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20385 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3031 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3031 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3235818 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3235818 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3235818 # number of overall misses +system.cpu0.dcache.overall_misses::total 3235818 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41541989000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 41541989000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84989668522 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 84989668522 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 383673500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 383673500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17049500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 17049500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 126531657522 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 126531657522 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 126531657522 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 126531657522 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8327610 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8327610 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5205444 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5205444 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194913 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 194913 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182958 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 182958 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13533054 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13533054 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13533054 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13533054 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186313 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.186313 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323561 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.323561 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104585 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104585 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016567 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016567 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239105 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.239105 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239105 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.239105 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26774.664028 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26774.664028 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50460.624067 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50460.624067 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18821.363748 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18821.363748 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5625.041241 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5625.041241 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39103.453137 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39103.453137 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4484959 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5749 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 107356 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 120 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.776510 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 47.908333 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 737573 # number of writebacks +system.cpu0.dcache.writebacks::total 737573 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 550277 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 550277 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432731 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1432731 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5546 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5546 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983008 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1983008 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983008 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1983008 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1001264 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1001264 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251546 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251546 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14839 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14839 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3031 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3031 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1252810 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1252810 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1252810 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1252810 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 6977 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9906 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9906 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16883 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16883 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31605979000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 31605979000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13230681248 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13230681248 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170838000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170838000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14059500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14059500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44836660248 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 44836660248 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44836660248 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 44836660248 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1556905500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1556905500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1556905500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1556905500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120384 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120384 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048370 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048370 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075343 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075343 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016611 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016611 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092673 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092673 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092673 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092673 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31548.340182 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31548.340182 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52548.996529 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52548.996529 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11646.986638 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11646.986638 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4626.357354 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4626.357354 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35766.178539 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35766.178539 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35766.178539 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35766.178539 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223148.272897 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223148.272897 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92217.348812 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92217.348812 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 894430 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.352767 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7502081 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 894941 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.382766 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 30333693500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.352767 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994830 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994830 # Average percentage of cache occupancy +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9910 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9910 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16887 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16887 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31631751000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 31631751000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13189939409 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13189939409 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 172118000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 172118000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14018500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14018500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44821690409 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 44821690409 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44821690409 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 44821690409 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1557150500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1557150500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1557150500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1557150500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120234 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120234 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048324 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048324 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.076131 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.076131 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016567 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016567 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092574 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092574 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31591.818941 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31591.818941 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52435.496525 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52435.496525 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11599.029584 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11599.029584 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4625.041241 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4625.041241 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223183.388276 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223183.388276 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92210.013620 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92210.013620 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 892272 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.350681 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7503325 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 892783 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.404422 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 30334536500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.350681 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994826 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994826 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 501 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9346457 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9346457 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 7502081 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7502081 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7502081 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7502081 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7502081 # number of overall hits -system.cpu0.icache.overall_hits::total 7502081 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 949140 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 949140 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 949140 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 949140 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 949140 # number of overall misses -system.cpu0.icache.overall_misses::total 949140 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13882658989 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13882658989 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13882658989 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13882658989 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13882658989 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13882658989 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8451221 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8451221 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8451221 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8451221 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8451221 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8451221 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112308 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.112308 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.112308 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.112308 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.112308 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.112308 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14626.566143 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14626.566143 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14626.566143 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14626.566143 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14626.566143 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14626.566143 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6715 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 9341754 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9341754 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 7503325 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7503325 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7503325 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7503325 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7503325 # number of overall hits +system.cpu0.icache.overall_hits::total 7503325 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 945376 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 945376 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 945376 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 945376 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 945376 # number of overall misses +system.cpu0.icache.overall_misses::total 945376 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13858102494 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13858102494 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13858102494 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13858102494 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13858102494 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13858102494 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8448701 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8448701 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8448701 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8448701 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8448701 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8448701 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111896 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.111896 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111896 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.111896 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111896 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.111896 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14658.826217 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14658.826217 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14658.826217 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14658.826217 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6578 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 267 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 245 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.149813 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.848980 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 894430 # number of writebacks -system.cpu0.icache.writebacks::total 894430 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53904 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 53904 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 53904 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 53904 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 53904 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 53904 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 895236 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 895236 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 895236 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 895236 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 895236 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 895236 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12277660991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12277660991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12277660991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12277660991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12277660991 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12277660991 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105930 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.105930 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.105930 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13714.440651 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13714.440651 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13714.440651 # average overall mshr miss latency -system.cpu1.branchPred.lookups 4438770 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3818546 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 113828 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2325021 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 880835 # Number of BTB hits +system.cpu0.icache.writebacks::writebacks 892272 # number of writebacks +system.cpu0.icache.writebacks::total 892272 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 52323 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 52323 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 52323 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 52323 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 52323 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 52323 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 893053 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 893053 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 893053 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 893053 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 893053 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 893053 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12259429995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12259429995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12259429995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12259429995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12259429995 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12259429995 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105703 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.105703 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.105703 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13727.550319 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency +system.cpu1.branchPred.lookups 4441555 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3820450 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 114047 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2322340 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 883836 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 37.885034 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 228893 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 8586 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 1265295 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 163281 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1102014 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 40695 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 38.057993 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 229553 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8671 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 1262341 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 163265 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1099076 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 40828 # Number of mispredicted indirect branches. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2431495 # DTB read hits -system.cpu1.dtb.read_misses 15697 # DTB read misses -system.cpu1.dtb.read_acv 126 # DTB read access violations -system.cpu1.dtb.read_accesses 432376 # DTB read accesses -system.cpu1.dtb.write_hits 1439190 # DTB write hits -system.cpu1.dtb.write_misses 3913 # DTB write misses -system.cpu1.dtb.write_acv 68 # DTB write access violations -system.cpu1.dtb.write_accesses 163232 # DTB write accesses -system.cpu1.dtb.data_hits 3870685 # DTB hits -system.cpu1.dtb.data_misses 19610 # DTB misses -system.cpu1.dtb.data_acv 194 # DTB access violations -system.cpu1.dtb.data_accesses 595608 # DTB accesses -system.cpu1.itb.fetch_hits 677547 # ITB hits -system.cpu1.itb.fetch_misses 3477 # ITB misses -system.cpu1.itb.fetch_acv 144 # ITB acv -system.cpu1.itb.fetch_accesses 681024 # ITB accesses +system.cpu1.dtb.read_hits 2431988 # DTB read hits +system.cpu1.dtb.read_misses 15687 # DTB read misses +system.cpu1.dtb.read_acv 78 # DTB read access violations +system.cpu1.dtb.read_accesses 432427 # DTB read accesses +system.cpu1.dtb.write_hits 1439876 # DTB write hits +system.cpu1.dtb.write_misses 3853 # DTB write misses +system.cpu1.dtb.write_acv 69 # DTB write access violations +system.cpu1.dtb.write_accesses 163205 # DTB write accesses +system.cpu1.dtb.data_hits 3871864 # DTB hits +system.cpu1.dtb.data_misses 19540 # DTB misses +system.cpu1.dtb.data_acv 147 # DTB access violations +system.cpu1.dtb.data_accesses 595632 # DTB accesses +system.cpu1.itb.fetch_hits 677957 # ITB hits +system.cpu1.itb.fetch_misses 3440 # ITB misses +system.cpu1.itb.fetch_acv 149 # ITB acv +system.cpu1.itb.fetch_accesses 681397 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -993,584 +993,584 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 5082 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2541 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 747256549.980323 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 396382548.008070 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2541 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state +system.cpu1.numPwrStateTransitions 5092 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2546 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 746545753.142184 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 396892720.756326 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2546 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 350000 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::max_value 975495000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2541 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 8770545000 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1898778893500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 17543632 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::total 2546 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 8778464000 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1900705487500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 17559475 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 7091057 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 17620667 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4438770 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1273009 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9220507 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 378986 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 26066 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 68380 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 52547 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1980567 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 84330 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 16648116 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.058418 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.465473 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 7089129 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 17628986 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4441555 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1276654 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9239971 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 379390 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 26991 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 67759 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 51232 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 58 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1981137 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 84838 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 16664835 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.057855 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.464288 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 13552832 81.41% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 195919 1.18% 82.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 328483 1.97% 84.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 235159 1.41% 85.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 403136 2.42% 88.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 149696 0.90% 89.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 175199 1.05% 90.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 211449 1.27% 91.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1396243 8.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 13565594 81.40% 81.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 195508 1.17% 82.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 331371 1.99% 84.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 236250 1.42% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 403775 2.42% 88.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 149802 0.90% 89.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 175422 1.05% 90.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 211560 1.27% 91.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1395553 8.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 16648116 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.253013 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.004391 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5799032 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 8189176 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2194913 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 283013 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 181981 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 153262 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7666 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 14395116 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 24052 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 181981 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5988192 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 920488 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6008083 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2289928 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1259442 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 13629732 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 4042 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 109065 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 36629 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 635484 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 9050413 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 16252880 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 16186853 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59441 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 7085651 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1964754 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 511413 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 53676 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2285701 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2541438 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1543271 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 322798 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 171550 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 11950332 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 586300 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 11472464 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 27528 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2575040 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1218372 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 432674 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 16648116 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.689115 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.415855 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 16664835 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.252943 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.003959 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5800433 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8202202 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2197206 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 282756 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 182237 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 153534 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7597 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 14400936 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 23892 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 182237 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5989487 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 906248 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6023778 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2292128 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1270955 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 13634993 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3736 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 109479 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 34532 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 648624 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 9050025 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 16251882 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 16185746 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59544 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 7082137 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1967880 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 511648 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 53659 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2285085 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2543631 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1545283 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 323334 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 171078 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 11953372 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 586667 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 11470583 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 27894 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2581702 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1224765 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 432970 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 16664835 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.688311 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.414763 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 11949949 71.78% 71.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2021085 12.14% 83.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 863131 5.18% 89.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 621327 3.73% 92.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 572760 3.44% 96.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 302852 1.82% 98.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 196760 1.18% 99.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 86740 0.52% 99.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 33512 0.20% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 11964424 71.79% 71.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2022081 12.13% 83.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 866450 5.20% 89.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 621081 3.73% 92.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 573042 3.44% 96.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 300412 1.80% 98.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 196836 1.18% 99.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 86957 0.52% 99.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 33552 0.20% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 16648116 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 16664835 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 33628 10.29% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 174409 53.35% 63.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 103464 31.65% 95.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemRead 7989 2.44% 97.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemWrite 7397 2.26% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 33610 10.34% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 173421 53.34% 63.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 102626 31.57% 95.25% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemRead 8052 2.48% 97.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemWrite 7405 2.28% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 7109835 61.97% 62.01% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 17232 0.15% 62.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 14002 0.12% 62.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2510604 21.88% 84.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1425191 12.42% 96.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemRead 45057 0.39% 97.01% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemWrite 43675 0.38% 97.39% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 299742 2.61% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7105969 61.95% 61.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 17120 0.15% 62.14% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 14007 0.12% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.26% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.28% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2511504 21.90% 84.18% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1426032 12.43% 96.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemRead 45143 0.39% 97.00% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemWrite 43776 0.38% 97.39% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 299906 2.61% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 11472464 # Type of FU issued -system.cpu1.iq.rate 0.653939 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 326887 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.028493 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 39721827 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 15008897 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 10951678 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 225631 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 107813 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 104885 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 11674105 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 120495 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 118360 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 11470583 # Type of FU issued +system.cpu1.iq.rate 0.653242 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 325114 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.028343 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 39732906 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 15018676 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 10950208 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 226102 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 108058 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 105069 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 11670188 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 120758 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 118257 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 553503 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1124 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 5247 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 178223 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 553253 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1093 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 5172 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 179987 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 530 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 100466 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 535 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 99855 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 181981 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 560519 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 287887 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 13187033 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 58459 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2541438 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1543271 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 532420 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 6842 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 279702 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 5247 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 45694 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 148663 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 194357 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 11283035 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2456415 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 189428 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 182237 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 561579 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 275117 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 13190679 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 58497 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2543631 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1545283 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 532703 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 6805 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 266988 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 5172 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 45989 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 148806 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 194795 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 11280251 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2456871 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 190331 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 650401 # number of nop insts executed -system.cpu1.iew.exec_refs 3906085 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1687752 # Number of branches executed -system.cpu1.iew.exec_stores 1449670 # Number of stores executed -system.cpu1.iew.exec_rate 0.643141 # Inst execution rate -system.cpu1.iew.wb_sent 11111703 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 11056563 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5287384 # num instructions producing a value -system.cpu1.iew.wb_consumers 7447136 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.630232 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.709989 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 2591726 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 153626 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 169211 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 16186649 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.645421 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.620431 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 650640 # number of nop insts executed +system.cpu1.iew.exec_refs 3907176 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1689156 # Number of branches executed +system.cpu1.iew.exec_stores 1450305 # Number of stores executed +system.cpu1.iew.exec_rate 0.642403 # Inst execution rate +system.cpu1.iew.wb_sent 11110028 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 11055277 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5286560 # num instructions producing a value +system.cpu1.iew.wb_consumers 7445661 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.629590 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.710019 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 2598878 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 153697 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 169517 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 16202334 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.644600 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.619525 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 12404611 76.63% 76.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1746252 10.79% 87.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 623750 3.85% 91.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 386653 2.39% 93.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 297145 1.84% 95.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 125489 0.78% 96.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 112472 0.69% 96.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 119580 0.74% 97.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 370697 2.29% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 12420063 76.66% 76.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1746761 10.78% 87.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 624490 3.85% 91.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 388127 2.40% 93.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 294767 1.82% 95.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 125393 0.77% 96.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 112323 0.69% 96.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 119344 0.74% 97.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 371066 2.29% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 16186649 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 10447204 # Number of instructions committed -system.cpu1.commit.committedOps 10447204 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 16202334 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 10444029 # Number of instructions committed +system.cpu1.commit.committedOps 10444029 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3352983 # Number of memory references committed -system.cpu1.commit.loads 1987935 # Number of loads committed -system.cpu1.commit.membars 48912 # Number of memory barriers committed -system.cpu1.commit.branches 1499265 # Number of branches committed -system.cpu1.commit.fp_insts 102779 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 9704534 # Number of committed integer instructions. -system.cpu1.commit.function_calls 163857 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 490367 4.69% 4.69% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 6221313 59.55% 64.24% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 16935 0.16% 64.41% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.41% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 13993 0.13% 64.54% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.54% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.54% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.54% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.54% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1992105 19.07% 83.63% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1323963 12.67% 96.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemRead 44742 0.43% 96.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemWrite 41669 0.40% 97.13% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 299742 2.87% 100.00% # Class of committed instruction +system.cpu1.commit.refs 3355674 # Number of memory references committed +system.cpu1.commit.loads 1990378 # Number of loads committed +system.cpu1.commit.membars 48933 # Number of memory barriers committed +system.cpu1.commit.branches 1499197 # Number of branches committed +system.cpu1.commit.fp_insts 102946 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 9701123 # Number of committed integer instructions. +system.cpu1.commit.function_calls 163891 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 490447 4.70% 4.70% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 6215282 59.51% 64.21% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 16829 0.16% 64.37% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.37% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 13998 0.13% 64.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.50% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.52% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1994471 19.10% 83.62% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1324148 12.68% 96.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemRead 44840 0.43% 96.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemWrite 41733 0.40% 97.13% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 299906 2.87% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 10447204 # Class of committed instruction -system.cpu1.commit.bw_lim_events 370697 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 28744557 # The number of ROB reads -system.cpu1.rob.rob_writes 26537349 # The number of ROB writes -system.cpu1.timesIdled 134728 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 895516 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3797555246 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 9961587 # Number of Instructions Simulated -system.cpu1.committedOps 9961587 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.761128 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.761128 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.567818 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.567818 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 14521611 # number of integer regfile reads -system.cpu1.int_regfile_writes 7909607 # number of integer regfile writes -system.cpu1.fp_regfile_reads 58779 # number of floating regfile reads -system.cpu1.fp_regfile_writes 57835 # number of floating regfile writes -system.cpu1.misc_regfile_reads 571518 # number of misc regfile reads -system.cpu1.misc_regfile_writes 244969 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 130966 # number of replacements -system.cpu1.dcache.tags.tagsinuse 487.964655 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3061418 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 131478 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.284641 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 49531315500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 487.964655 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.953056 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.953056 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 10444029 # Class of committed instruction +system.cpu1.commit.bw_lim_events 371066 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 28763808 # The number of ROB reads +system.cpu1.rob.rob_writes 26546353 # The number of ROB writes +system.cpu1.timesIdled 134909 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 894640 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3801408429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9958332 # Number of Instructions Simulated +system.cpu1.committedOps 9958332 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.763295 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.763295 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.567120 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.567120 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 14511646 # number of integer regfile reads +system.cpu1.int_regfile_writes 7905629 # number of integer regfile writes +system.cpu1.fp_regfile_reads 58867 # number of floating regfile reads +system.cpu1.fp_regfile_writes 57930 # number of floating regfile writes +system.cpu1.misc_regfile_reads 573957 # number of misc regfile reads +system.cpu1.misc_regfile_writes 245081 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 131073 # number of replacements +system.cpu1.dcache.tags.tagsinuse 488.756113 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3063603 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 131585 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.282312 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 49534380500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.756113 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954602 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.954602 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14512669 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14512669 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 1946433 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1946433 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1026063 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1026063 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40785 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 40785 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 37242 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 37242 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2972496 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2972496 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2972496 # number of overall hits -system.cpu1.dcache.overall_hits::total 2972496 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 241711 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 241711 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 292248 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 292248 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5308 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5308 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3094 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3094 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 533959 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 533959 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 533959 # number of overall misses -system.cpu1.dcache.overall_misses::total 533959 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3394927000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3394927000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12114051455 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 12114051455 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54394000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 54394000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17165000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 17165000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 15508978455 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 15508978455 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 15508978455 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 15508978455 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2188144 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2188144 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318311 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1318311 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 46093 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 46093 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40336 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 40336 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3506455 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3506455 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3506455 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3506455 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110464 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.110464 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221684 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.221684 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115158 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115158 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076706 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076706 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152279 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.152279 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152279 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.152279 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14045.397189 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14045.397189 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41451.272395 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41451.272395 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10247.550867 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10247.550867 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5547.834518 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5547.834518 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29045.260881 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 29045.260881 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29045.260881 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 29045.260881 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 715753 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 884 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 24925 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 28.716269 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 68 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 84601 # number of writebacks -system.cpu1.dcache.writebacks::total 84601 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148639 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 148639 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243827 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 243827 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 846 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 846 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 392466 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 392466 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 392466 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 392466 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93072 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 93072 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48421 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 48421 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4462 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4462 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3093 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3093 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 141493 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 141493 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 141493 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 141493 # number of overall MSHR misses +system.cpu1.dcache.tags.tag_accesses 14519091 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14519091 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 1948296 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1948296 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1026442 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1026442 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40668 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 40668 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 37243 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 37243 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2974738 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2974738 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2974738 # number of overall hits +system.cpu1.dcache.overall_hits::total 2974738 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 241303 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 241303 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 292103 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 292103 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5304 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5304 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3101 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3101 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 533406 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 533406 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 533406 # number of overall misses +system.cpu1.dcache.overall_misses::total 533406 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3375705500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3375705500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12203212844 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 12203212844 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54365500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 54365500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17261500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 17261500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15578918344 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15578918344 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15578918344 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15578918344 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2189599 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2189599 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318545 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1318545 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 45972 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 45972 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40344 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 40344 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3508144 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3508144 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3508144 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3508144 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110204 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.110204 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221534 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.221534 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115375 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115375 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076864 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076864 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152048 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.152048 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152048 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.152048 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13989.488320 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13989.488320 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41777.088370 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41777.088370 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10249.905732 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10249.905732 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5566.430184 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5566.430184 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 29206.492510 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 29206.492510 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 720965 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 386 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 24769 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 29.107554 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 20.315789 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 84598 # number of writebacks +system.cpu1.dcache.writebacks::total 84598 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148074 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 148074 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243671 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 243671 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 852 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 852 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 391745 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 391745 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 391745 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 391745 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93229 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 93229 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48432 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 48432 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4452 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4452 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3100 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3100 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 141661 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 141661 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 141661 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 141661 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 218 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3153 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3153 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3371 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3371 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1262526500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1262526500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1947214752 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1947214752 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40086500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40086500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14072000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14072000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3209741252 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3209741252 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3209741252 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3209741252 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41866500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41866500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41866500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41866500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042535 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042535 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.096804 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.096804 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076681 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076681 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040352 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.040352 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040352 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.040352 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13565.051788 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13565.051788 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40214.261416 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40214.261416 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8983.975796 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8983.975796 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4549.628193 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4549.628193 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22684.805976 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22684.805976 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22684.805976 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22684.805976 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192048.165138 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192048.165138 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12419.608425 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12419.608425 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 256896 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.782709 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1710963 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 257408 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.646891 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1882016787500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.782709 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919497 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.919497 # Average percentage of cache occupancy +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3157 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3157 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3375 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3375 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1262260500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1262260500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1962212693 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1962212693 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40045500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40045500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14161500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14161500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3224473193 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3224473193 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3224473193 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3224473193 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41860500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41860500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41860500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41860500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042578 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042578 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036731 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036731 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.096842 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.096842 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076839 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076839 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.040381 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.040381 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13539.354707 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13539.354707 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40514.797923 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40514.797923 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8994.946092 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8994.946092 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4568.225806 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4568.225806 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192020.642202 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192020.642202 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12403.111111 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12403.111111 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 256867 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.812016 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1711658 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 257379 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.650341 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1882992885500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.812016 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919555 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.919555 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 424 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2238053 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2238053 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 1710963 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1710963 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1710963 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1710963 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1710963 # number of overall hits -system.cpu1.icache.overall_hits::total 1710963 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 269604 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 269604 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 269604 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 269604 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 269604 # number of overall misses -system.cpu1.icache.overall_misses::total 269604 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3754413998 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3754413998 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3754413998 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3754413998 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3754413998 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3754413998 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1980567 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1980567 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1980567 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1980567 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1980567 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1980567 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.136125 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.136125 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.136125 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.136125 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.136125 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.136125 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13925.661333 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13925.661333 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13925.661333 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13925.661333 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13925.661333 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13925.661333 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 473 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 2238596 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2238596 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 1711658 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1711658 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1711658 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1711658 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1711658 # number of overall hits +system.cpu1.icache.overall_hits::total 1711658 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 269479 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 269479 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 269479 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 269479 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 269479 # number of overall misses +system.cpu1.icache.overall_misses::total 269479 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3760599998 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3760599998 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3760599998 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3760599998 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3760599998 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3760599998 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1981137 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1981137 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1981137 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1981137 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1981137 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1981137 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.136022 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.136022 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.136022 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.136022 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.136022 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.136022 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13955.076269 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13955.076269 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13955.076269 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13955.076269 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 535 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.261905 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.382979 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 256896 # number of writebacks -system.cpu1.icache.writebacks::total 256896 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12118 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 12118 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 12118 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 12118 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 12118 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 12118 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 257486 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 257486 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 257486 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 257486 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 257486 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 257486 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3368066498 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3368066498 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3368066498 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3368066498 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3368066498 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3368066498 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.130006 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.130006 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.130006 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13080.581072 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13080.581072 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13080.581072 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 256867 # number of writebacks +system.cpu1.icache.writebacks::total 256867 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12020 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 12020 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 12020 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 12020 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 12020 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 12020 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 257459 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 257459 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 257459 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 257459 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 257459 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 257459 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3369785998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3369785998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3369785998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3369785998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3369785998 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3369785998 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.129955 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.129955 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.129955 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13088.631580 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1583,12 +1583,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7374 # Transaction distribution system.iobus.trans_dist::ReadResp 7374 # Transaction distribution -system.iobus.trans_dist::WriteReq 54611 # Transaction distribution -system.iobus.trans_dist::WriteResp 54611 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11908 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 54619 # Transaction distribution +system.iobus.trans_dist::WriteResp 54619 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11924 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1597,11 +1597,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1814 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40508 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40524 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123970 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 123986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47696 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1610,50 +1610,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 73858 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 73922 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2735514 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12353502 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2735578 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12373500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 824500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 816500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13988000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14090000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2829000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2829500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6060500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6041501 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 89000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216282007 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216274759 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27449000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.490946 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.506657 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1714262123000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.490946 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.030684 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.030684 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1714262526000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.506657 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.031666 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.031666 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375579 # Number of tag accesses system.iocache.tags.data_accesses 375579 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses system.iocache.ReadReq_misses::total 179 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1662,14 +1662,14 @@ system.iocache.demand_misses::tsunami.ide 41731 # n system.iocache.demand_misses::total 41731 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses system.iocache.overall_misses::total 41731 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22774383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22774383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4918988624 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4918988624 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4941763007 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4941763007 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4941763007 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4941763007 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 22653383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22653383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4913989376 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4913989376 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4936642759 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4936642759 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4936642759 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4936642759 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1686,19 +1686,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 127231.189944 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 127231.189944 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118381.512899 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118381.512899 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118419.472502 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118419.472502 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118419.472502 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118419.472502 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1165 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126555.212291 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126555.212291 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118261.199846 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118261.199846 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118296.775994 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118296.775994 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 945 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 145.625000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 135 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks @@ -1710,14 +1710,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41731 system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13824383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13824383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2838948426 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2838948426 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2852772809 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2852772809 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2852772809 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2852772809 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13703383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13703383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2833958851 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2833958851 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2847662234 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2847662234 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2847662234 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2847662234 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1726,200 +1726,200 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 77231.189944 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 77231.189944 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68322.786533 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68322.786533 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68360.998035 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68360.998035 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68360.998035 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68360.998035 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 345941 # number of replacements -system.l2c.tags.tagsinuse 65423.095027 # Cycle average of tags in use -system.l2c.tags.total_refs 4335515 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 411463 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.536828 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 6416575000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 293.307825 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5315.079150 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58827.069962 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 210.319847 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 777.318243 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.004476 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081102 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.897630 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003209 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011861 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998277 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76555.212291 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76555.212291 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68202.706272 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68202.706272 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 345934 # number of replacements +system.l2c.tags.tagsinuse 65423.183339 # Cycle average of tags in use +system.l2c.tags.total_refs 4331268 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 411456 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.526686 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 6416563000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 293.472249 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5322.167822 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58815.337446 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 207.084290 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 785.121532 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.004478 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.081210 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.897451 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003160 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011980 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998279 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1694 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1843 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5673 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56180 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1689 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1849 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9122 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52734 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38390429 # Number of tag accesses -system.l2c.tags.data_accesses 38390429 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 822340 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 822340 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 875169 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 875169 # number of WritebackClean hits +system.l2c.tags.tag_accesses 38356372 # Number of tag accesses +system.l2c.tags.data_accesses 38356372 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 822171 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 822171 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 873935 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 873935 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 2863 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1494 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 4357 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 501 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 467 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 968 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 145988 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 30963 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 176951 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 881644 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 255533 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1137177 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 722233 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 84048 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 806281 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 881644 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 868221 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 255533 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 115011 # number of demand (read+write) hits -system.l2c.demand_hits::total 2120409 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 881644 # number of overall hits -system.l2c.overall_hits::cpu0.data 868221 # number of overall hits -system.l2c.overall_hits::cpu1.inst 255533 # number of overall hits -system.l2c.overall_hits::cpu1.data 115011 # number of overall hits -system.l2c.overall_hits::total 2120409 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 6 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11 # number of UpgradeReq misses +system.l2c.UpgradeReq_hits::cpu1.data 1523 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 4386 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 498 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 473 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 971 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 145860 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 30930 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 176790 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 879457 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 255503 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1134960 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 721850 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 84138 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 805988 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 879457 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 867710 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 255503 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 115068 # number of demand (read+write) hits +system.l2c.demand_hits::total 2117738 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 879457 # number of overall hits +system.l2c.overall_hits::cpu0.data 867710 # number of overall hits +system.l2c.overall_hits::cpu1.inst 255503 # number of overall hits +system.l2c.overall_hits::cpu1.data 115068 # number of overall hits +system.l2c.overall_hits::total 2117738 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 109595 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 12065 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121660 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 13405 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1909 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 15314 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 272577 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1964 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 274541 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 13405 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 382172 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1909 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 14029 # number of demand (read+write) misses -system.l2c.demand_misses::total 411515 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13405 # number of overall misses -system.l2c.overall_misses::cpu0.data 382172 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1909 # number of overall misses -system.l2c.overall_misses::cpu1.data 14029 # number of overall misses -system.l2c.overall_misses::total 411515 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 332000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 117000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 449000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 11349867000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1517430000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 12867297000 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1343054000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 191509000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1534563000 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 22206710000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 230127000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 22436837000 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1343054000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 33556577000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 191509000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1747557000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 36838697000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1343054000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 33556577000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 191509000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1747557000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 36838697000 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 822340 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 822340 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 875169 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 875169 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2869 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1499 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4368 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 501 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 468 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 969 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 255583 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 43028 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 298611 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 895049 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 257442 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1152491 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 994810 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 86012 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1080822 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 895049 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1250393 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 257442 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 129040 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2531924 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 895049 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1250393 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 257442 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 129040 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2531924 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.002091 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.003336 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.002518 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.002137 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.001032 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.428804 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.280399 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.407420 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.014977 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007415 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013288 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.273999 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.022834 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.254011 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014977 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.305642 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007415 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.108718 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.162531 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014977 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.305642 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007415 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.108718 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.162531 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 55333.333333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 23400 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 40818.181818 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 103561.905196 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 125771.239121 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 105764.400789 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 100190.525923 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 100319.015191 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 100206.543033 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 81469.493024 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 117172.606925 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 81724.904477 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 100190.525923 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 87804.907215 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 100319.015191 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 124567.467389 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 89519.694300 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 100190.525923 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 87804.907215 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 100319.015191 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 124567.467389 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 89519.694300 # average overall miss latency +system.l2c.ReadExReq_misses::cpu0.data 109487 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 12067 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 121554 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 13403 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 1908 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 15311 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 272678 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1963 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 274641 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 13403 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 382165 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1908 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 14030 # number of demand (read+write) misses +system.l2c.demand_misses::total 411506 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13403 # number of overall misses +system.l2c.overall_misses::cpu0.data 382165 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1908 # number of overall misses +system.l2c.overall_misses::cpu1.data 14030 # number of overall misses +system.l2c.overall_misses::total 411506 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 390000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 86500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 476500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 11308218500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1532406000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 12840624500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1352141000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 194316500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1546457500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 22230634500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 227734000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 22458368500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1352141000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 33538853000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 194316500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1760140000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 36845450500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1352141000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 33538853000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 194316500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1760140000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 36845450500 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 822171 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 822171 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 873935 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 873935 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2871 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1527 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4398 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 498 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 474 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 972 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 255347 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 42997 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 298344 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 892860 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 257411 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1150271 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 994528 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 86101 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1080629 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 892860 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1249875 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 257411 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 129098 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2529244 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 892860 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1249875 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 257411 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 129098 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2529244 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.002786 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.002620 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.002729 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.002110 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.001029 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.428777 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.280647 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.407429 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.015011 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007412 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013311 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.274178 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.022799 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.254149 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015011 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.305763 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007412 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.108677 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.162699 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015011 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.305763 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007412 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.108677 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.162699 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 48750 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 21625 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 39708.333333 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 103283.663814 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 126991.464324 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 105637.202396 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 100883.458927 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 101843.029350 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 101003.037032 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 81527.055721 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116013.245033 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 81773.546193 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 100883.458927 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 87760.137637 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 101843.029350 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 125455.452602 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 89538.063844 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 100883.458927 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 87760.137637 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 101843.029350 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 125455.452602 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 89538.063844 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 82096 # number of writebacks -system.l2c.writebacks::total 82096 # number of writebacks +system.l2c.writebacks::writebacks 82080 # number of writebacks +system.l2c.writebacks::total 82080 # number of writebacks system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 17 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits @@ -1929,249 +1929,251 @@ system.l2c.demand_mshr_hits::total 18 # nu system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 11 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 11 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 6 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 5 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses +system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 109595 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 12065 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 121660 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13404 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1892 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 15296 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272577 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1964 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 274541 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13404 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 382172 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1892 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 14029 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 411497 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13404 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 382172 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1892 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 14029 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 411497 # number of overall MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 109487 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 12067 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 121554 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13402 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1891 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 15293 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272678 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1963 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 274641 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13402 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 382165 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1891 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 14030 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 411488 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13402 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 382165 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1891 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 14030 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 411488 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::total 7195 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 9906 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3153 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 13059 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 16883 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3371 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 20254 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 272000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 95500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 367500 # number of UpgradeReq MSHR miss cycles +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 9910 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3157 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 13067 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 16887 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3375 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 20262 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 310000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 75000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 385000 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18500 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 18500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10253916501 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1396780000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 11650696501 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1208926000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 171260500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1380186500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19486691503 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 210487000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 19697178503 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1208926000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 29740608004 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 171260500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1607267000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 32728061504 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1208926000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 29740608004 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 171260500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1607267000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 32728061504 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1469664500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 39141500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1508806000 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1469664500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 39141500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1508806000 # number of overall MSHR uncacheable cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10213348500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1411735501 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 11625084001 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1218034000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 174078000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1392112000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19509738001 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 208104000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 19717842001 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1218034000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 29723086501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 174078000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1619839501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 32735038002 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1218034000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 29723086501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 174078000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1619839501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 32735038002 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1469912000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 39135500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1509047500 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1469912000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 39135500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1509047500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002091 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.003336 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.002518 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002137 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001032 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.428804 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.280399 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.407420 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014976 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007349 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013272 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273999 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022834 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254011 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014976 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.305642 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007349 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.108718 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.162523 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014976 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.305642 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007349 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.108718 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.162523 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 45333.333333 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19100 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 33409.090909 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002786 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.002620 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.002729 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002110 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.428777 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.280647 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.407429 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013295 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.274178 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022799 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254149 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.162692 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.162692 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 38750 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18750 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 32083.333333 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93561.900643 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 115771.239121 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 95764.396687 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 90231.858002 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71490.593495 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 107172.606925 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71745.854000 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77819.955423 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 114567.467389 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 79534.143637 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77819.955423 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 114567.467389 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 79534.143637 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210644.188046 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179548.165138 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209702.015288 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87049.961500 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11611.242955 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74494.223363 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 852108 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 399805 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 437 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93283.663814 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116991.422972 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 95637.198290 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 91029.359838 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71548.632457 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106013.245033 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71794.968708 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210679.661746 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179520.642202 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209735.580264 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87043.998342 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11595.703704 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74476.729839 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 852121 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 399760 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 540 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7195 # Transaction distribution -system.membus.trans_dist::ReadResp 297167 # Transaction distribution -system.membus.trans_dist::WriteReq 13059 # Transaction distribution -system.membus.trans_dist::WriteResp 13059 # Transaction distribution -system.membus.trans_dist::WritebackDirty 123616 # Transaction distribution -system.membus.trans_dist::CleanEvict 263125 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6609 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5164 # Transaction distribution +system.membus.trans_dist::ReadResp 297263 # Transaction distribution +system.membus.trans_dist::WriteReq 13067 # Transaction distribution +system.membus.trans_dist::WriteResp 13067 # Transaction distribution +system.membus.trans_dist::WritebackDirty 123600 # Transaction distribution +system.membus.trans_dist::CleanEvict 263134 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6631 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5160 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 121953 # Transaction distribution -system.membus.trans_dist::ReadExResp 121548 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 290016 # Transaction distribution -system.membus.trans_dist::BadAddressError 44 # Transaction distribution +system.membus.trans_dist::ReadExReq 121851 # Transaction distribution +system.membus.trans_dist::ReadExResp 121443 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 290113 # Transaction distribution +system.membus.trans_dist::BadAddressError 45 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40508 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179616 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 88 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1220212 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::InvalidateResp 134 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40524 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179612 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 90 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1220226 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1303657 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73858 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31561664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31635522 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1303671 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73922 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31560064 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31633986 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34293762 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 12507 # Total snoops (count) +system.membus.pkt_size::total 34292226 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 12662 # Total snoops (count) system.membus.snoopTraffic 28800 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 485548 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001427 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.037752 # Request fanout histogram +system.membus.snoop_fanout::samples 485569 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001425 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.037724 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 484855 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 693 0.14% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 484877 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 692 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 485548 # Request fanout histogram -system.membus.reqLayer0.occupancy 36350498 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 485569 # Request fanout histogram +system.membus.reqLayer0.occupancy 36441999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1353965073 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1353891077 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 55000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 56500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2179761000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2179677750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 960863 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1104580 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5108724 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2554049 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 343728 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1007 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5103299 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2546186 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 356313 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1076 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1008 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2263429 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13059 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13059 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 904436 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1151326 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 825788 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10854 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 6132 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 16986 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 300014 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 300014 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1152722 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1103559 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 44 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 238 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2684715 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3812301 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 771824 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 417816 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7686656 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114526656 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127297140 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32917632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13697806 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 288439234 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 382362 # Total snoops (count) -system.toL2Bus.snoopTraffic 6813696 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2939714 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.123574 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.329478 # Request fanout histogram +system.toL2Bus.trans_dist::ReadResp 2260964 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13067 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13067 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 904251 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1149139 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 825400 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10906 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 6131 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 17037 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 299755 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 299755 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1150512 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1103306 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 45 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2678185 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3810494 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 771737 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 418186 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7678602 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114248448 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127253332 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32913792 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13701358 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 288116930 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 382331 # Total snoops (count) +system.toL2Bus.snoopTraffic 6809920 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 2937042 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.126206 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.332589 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2576793 87.65% 87.65% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 362587 12.33% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 316 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 18 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2566846 87.40% 87.40% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 369740 12.59% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 436 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 20 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2939714 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4544765338 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2937042 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4539664918 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 301885 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 302885 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1344393906 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1341208229 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1911305093 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1910262297 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 387758410 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 387640565 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 217734513 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 217884535 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2203,142 +2205,142 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6475 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 176726 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 62785 40.28% 40.28% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6478 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 176731 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 62783 40.27% 40.27% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.08% 40.36% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1925 1.23% 41.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 181 0.12% 41.71% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 90860 58.29% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 155882 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 61770 49.18% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1927 1.24% 41.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 182 0.12% 41.71% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 90863 58.29% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 155886 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 61769 49.18% 49.18% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.10% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1925 1.53% 50.82% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 181 0.14% 50.96% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 61589 49.04% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1927 1.53% 50.82% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 182 0.14% 50.96% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 61587 49.04% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 125596 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862335551000 97.65% 97.65% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 64321000 0.00% 97.65% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 576343500 0.03% 97.68% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 87551500 0.00% 97.68% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 44167527000 2.32% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1907231294000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983834 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks::0 1864292107000 97.65% 97.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 64306500 0.00% 97.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 577089500 0.03% 97.68% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 88747000 0.00% 97.69% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 44160796000 2.31% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1909183046000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983849 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.677845 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.805712 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.677801 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.805691 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 293 0.18% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wripir 294 0.18% 0.18% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3349 2.05% 2.23% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3351 2.05% 2.23% # number of callpals executed system.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed -system.cpu0.kern.callpal::swpipl 149333 91.35% 93.61% # number of callpals executed -system.cpu0.kern.callpal::rdps 5683 3.48% 97.09% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed +system.cpu0.kern.callpal::swpipl 149332 91.35% 93.61% # number of callpals executed +system.cpu0.kern.callpal::rdps 5685 3.48% 97.09% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.09% # number of callpals executed system.cpu0.kern.callpal::wrusp 1 0.00% 97.09% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.09% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::rti 4311 2.64% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4313 2.64% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 303 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 163475 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6664 # number of protection mode switches +system.cpu0.kern.callpal::total 163481 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6669 # number of protection mode switches system.cpu0.kern.mode_switch::user 1070 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1070 system.cpu0.kern.mode_good::user 1070 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.160564 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.160444 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.276700 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1905216688000 99.91% 99.91% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1682440000 0.09% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.276522 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1907148784500 99.91% 99.91% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1683022000 0.09% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3350 # number of times the context was actually changed +system.cpu0.kern.swap_context 3352 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2541 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 62895 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 19560 37.60% 37.60% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1924 3.70% 41.30% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 293 0.56% 41.86% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 30244 58.14% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 52021 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 19198 47.61% 47.61% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1924 4.77% 52.38% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 293 0.73% 53.11% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 18906 46.89% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 40321 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1872948111000 98.19% 98.19% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 564456500 0.03% 98.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 141435000 0.01% 98.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 33894599000 1.78% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1907548601500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981493 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2546 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 62928 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 19570 37.60% 37.60% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 3.70% 41.30% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 294 0.56% 41.86% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 30260 58.14% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 52049 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 19207 47.61% 47.61% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 4.77% 52.39% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 294 0.73% 53.11% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 18913 46.89% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 40339 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1874881279000 98.19% 98.19% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 565111500 0.03% 98.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 141720000 0.01% 98.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 33895004500 1.78% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1909483115000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981451 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.625116 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.775091 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.625017 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.775020 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 181 0.33% 0.33% # number of callpals executed +system.cpu1.kern.callpal::wripir 182 0.33% 0.34% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1228 2.25% 2.59% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1230 2.25% 2.59% # number of callpals executed system.cpu1.kern.callpal::tbi 5 0.01% 2.60% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed -system.cpu1.kern.callpal::swpipl 46558 85.31% 87.92% # number of callpals executed -system.cpu1.kern.callpal::rdps 3077 5.64% 93.55% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.56% # number of callpals executed -system.cpu1.kern.callpal::wrusp 6 0.01% 93.57% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.57% # number of callpals executed +system.cpu1.kern.callpal::swpipl 46579 85.30% 87.91% # number of callpals executed +system.cpu1.kern.callpal::rdps 3079 5.64% 93.55% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed +system.cpu1.kern.callpal::wrusp 6 0.01% 93.56% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.56% # number of callpals executed system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed -system.cpu1.kern.callpal::rti 3246 5.95% 99.52% # number of callpals executed +system.cpu1.kern.callpal::rti 3250 5.95% 99.52% # number of callpals executed system.cpu1.kern.callpal::callsys 212 0.39% 99.91% # number of callpals executed system.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 54577 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1699 # number of protection mode switches -system.cpu1.kern.mode_switch::user 669 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2429 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 888 -system.cpu1.kern.mode_good::user 669 -system.cpu1.kern.mode_good::idle 219 -system.cpu1.kern.mode_switch_good::kernel 0.522660 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 54607 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1700 # number of protection mode switches +system.cpu1.kern.mode_switch::user 670 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2433 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 890 +system.cpu1.kern.mode_good::user 670 +system.cpu1.kern.mode_good::idle 220 +system.cpu1.kern.mode_switch_good::kernel 0.523529 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.090161 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.370231 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 5315508000 0.28% 0.28% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1058693000 0.06% 0.33% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1901174392500 99.67% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1229 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.090423 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.370602 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 5328500500 0.28% 0.28% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1057436000 0.06% 0.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1903097170500 99.67% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1231 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index bb54c4dfa..5af666630 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,113 +1,113 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.865012 # Number of seconds simulated -sim_ticks 1865011607500 # Number of ticks simulated -final_tick 1865011607500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.865010 # Number of seconds simulated +sim_ticks 1865009748000 # Number of ticks simulated +final_tick 1865009748000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 239114 # Simulator instruction rate (inst/s) -host_op_rate 239113 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8418978943 # Simulator tick rate (ticks/s) -host_mem_usage 338260 # Number of bytes of host memory used -host_seconds 221.52 # Real time elapsed on the host -sim_insts 52969539 # Number of instructions simulated -sim_ops 52969539 # Number of ops (including micro ops) simulated +host_inst_rate 235871 # Simulator instruction rate (inst/s) +host_op_rate 235870 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8303287371 # Simulator tick rate (ticks/s) +host_mem_usage 337912 # Number of bytes of host memory used +host_seconds 224.61 # Real time elapsed on the host +sim_insts 52979108 # Number of instructions simulated +sim_ops 52979108 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 962688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879872 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 962240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24880192 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25843520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 962688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 962688 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7514368 # Number of bytes written to this memory -system.physmem.bytes_written::total 7514368 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15042 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388748 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25843392 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 962240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 962240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7516224 # Number of bytes written to this memory +system.physmem.bytes_written::total 7516224 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15035 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388753 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403805 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117412 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117412 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 516183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13340331 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403803 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117441 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117441 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 515944 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13340516 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13857029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 516183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4029127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4029127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4029127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 516183 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13340331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13856974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 515944 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 515944 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4030126 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4030126 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4030126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 515944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13340516 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17886156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403805 # Number of read requests accepted -system.physmem.writeReqs 117412 # Number of write requests accepted -system.physmem.readBursts 403805 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117412 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25836672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue -system.physmem.bytesWritten 7513280 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25843520 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7514368 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17887100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403803 # Number of read requests accepted +system.physmem.writeReqs 117441 # Number of write requests accepted +system.physmem.readBursts 403803 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117441 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25835712 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue +system.physmem.bytesWritten 7515136 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25843392 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7516224 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25445 # Per bank write bursts -system.physmem.perBankRdBursts::1 25617 # Per bank write bursts -system.physmem.perBankRdBursts::2 25496 # Per bank write bursts -system.physmem.perBankRdBursts::3 25620 # Per bank write bursts -system.physmem.perBankRdBursts::4 25117 # Per bank write bursts -system.physmem.perBankRdBursts::5 25178 # Per bank write bursts -system.physmem.perBankRdBursts::6 24740 # Per bank write bursts -system.physmem.perBankRdBursts::7 24558 # Per bank write bursts -system.physmem.perBankRdBursts::8 25032 # Per bank write bursts -system.physmem.perBankRdBursts::9 25302 # Per bank write bursts -system.physmem.perBankRdBursts::10 25290 # Per bank write bursts -system.physmem.perBankRdBursts::11 25006 # Per bank write bursts -system.physmem.perBankRdBursts::12 24377 # Per bank write bursts -system.physmem.perBankRdBursts::13 25425 # Per bank write bursts -system.physmem.perBankRdBursts::14 25800 # Per bank write bursts -system.physmem.perBankRdBursts::15 25695 # Per bank write bursts -system.physmem.perBankWrBursts::0 7802 # Per bank write bursts -system.physmem.perBankWrBursts::1 7592 # Per bank write bursts -system.physmem.perBankWrBursts::2 7774 # Per bank write bursts -system.physmem.perBankWrBursts::3 7602 # Per bank write bursts -system.physmem.perBankWrBursts::4 7239 # Per bank write bursts -system.physmem.perBankWrBursts::5 7182 # Per bank write bursts -system.physmem.perBankWrBursts::6 6741 # Per bank write bursts -system.physmem.perBankWrBursts::7 6416 # Per bank write bursts -system.physmem.perBankWrBursts::8 7149 # Per bank write bursts -system.physmem.perBankWrBursts::9 6926 # Per bank write bursts -system.physmem.perBankWrBursts::10 7200 # Per bank write bursts -system.physmem.perBankWrBursts::11 7003 # Per bank write bursts -system.physmem.perBankWrBursts::12 6957 # Per bank write bursts -system.physmem.perBankWrBursts::13 7880 # Per bank write bursts -system.physmem.perBankWrBursts::14 8017 # Per bank write bursts +system.physmem.perBankRdBursts::0 25444 # Per bank write bursts +system.physmem.perBankRdBursts::1 25611 # Per bank write bursts +system.physmem.perBankRdBursts::2 25628 # Per bank write bursts +system.physmem.perBankRdBursts::3 25719 # Per bank write bursts +system.physmem.perBankRdBursts::4 25100 # Per bank write bursts +system.physmem.perBankRdBursts::5 25088 # Per bank write bursts +system.physmem.perBankRdBursts::6 24758 # Per bank write bursts +system.physmem.perBankRdBursts::7 24649 # Per bank write bursts +system.physmem.perBankRdBursts::8 24903 # Per bank write bursts +system.physmem.perBankRdBursts::9 25188 # Per bank write bursts +system.physmem.perBankRdBursts::10 25284 # Per bank write bursts +system.physmem.perBankRdBursts::11 25005 # Per bank write bursts +system.physmem.perBankRdBursts::12 24375 # Per bank write bursts +system.physmem.perBankRdBursts::13 25430 # Per bank write bursts +system.physmem.perBankRdBursts::14 25804 # Per bank write bursts +system.physmem.perBankRdBursts::15 25697 # Per bank write bursts +system.physmem.perBankWrBursts::0 7804 # Per bank write bursts +system.physmem.perBankWrBursts::1 7583 # Per bank write bursts +system.physmem.perBankWrBursts::2 7900 # Per bank write bursts +system.physmem.perBankWrBursts::3 7698 # Per bank write bursts +system.physmem.perBankWrBursts::4 7224 # Per bank write bursts +system.physmem.perBankWrBursts::5 7092 # Per bank write bursts +system.physmem.perBankWrBursts::6 6759 # Per bank write bursts +system.physmem.perBankWrBursts::7 6515 # Per bank write bursts +system.physmem.perBankWrBursts::8 7053 # Per bank write bursts +system.physmem.perBankWrBursts::9 6824 # Per bank write bursts +system.physmem.perBankWrBursts::10 7197 # Per bank write bursts +system.physmem.perBankWrBursts::11 7005 # Per bank write bursts +system.physmem.perBankWrBursts::12 6955 # Per bank write bursts +system.physmem.perBankWrBursts::13 7882 # Per bank write bursts +system.physmem.perBankWrBursts::14 8018 # Per bank write bursts system.physmem.perBankWrBursts::15 7915 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 50 # Number of times write queue was full causing retry -system.physmem.totGap 1865006319500 # Total gap between requests +system.physmem.numWrRetry 65 # Number of times write queue was full causing retry +system.physmem.totGap 1865004470500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403805 # Read request sizes (log2) +system.physmem.readPktSize::6 403803 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117412 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 36490 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117441 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314056 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36501 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -149,117 +149,115 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 298 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 103 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61234 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 544.625012 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 334.721385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.137572 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13321 21.75% 21.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10685 17.45% 39.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4509 7.36% 46.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2718 4.44% 51.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2169 3.54% 54.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1832 2.99% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1887 3.08% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1551 2.53% 63.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22562 36.85% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61234 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.280396 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2939.585639 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5154 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::39 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61362 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 543.503536 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 333.365701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.323842 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13476 21.96% 21.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10707 17.45% 39.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4479 7.30% 46.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2678 4.36% 51.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2195 3.58% 54.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1843 3.00% 57.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1874 3.05% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1552 2.53% 63.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22558 36.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61362 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.231977 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2938.731055 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5157 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.764204 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.942160 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.363230 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4631 89.80% 89.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 32 0.62% 90.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 183 3.55% 93.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 6 0.12% 94.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 4 0.08% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 9 0.17% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 9 0.17% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 4 0.08% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 32 0.62% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.10% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 155 3.01% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 14 0.27% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 9 0.17% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 9 0.17% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 4 0.08% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.02% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 8 0.16% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.12% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 10 0.19% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 10 0.19% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 4 0.08% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads -system.physmem.totQLat 7801574500 # Total ticks spent queuing -system.physmem.totMemAccLat 15370912000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018490000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19325.27 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.756589 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.921420 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.589297 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4641 89.94% 89.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 34 0.66% 90.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 173 3.35% 93.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 9 0.17% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 2 0.04% 94.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 16 0.31% 94.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 8 0.16% 94.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 3 0.06% 94.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 29 0.56% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.08% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 150 2.91% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 19 0.37% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 6 0.12% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 5 0.10% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 7 0.14% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 2 0.04% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.06% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 7 0.14% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.10% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 10 0.19% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 13 0.25% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 4 0.08% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.08% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 3 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads +system.physmem.totQLat 7817102750 # Total ticks spent queuing +system.physmem.totMemAccLat 15386159000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018415000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19364.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38075.27 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 38114.46 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s @@ -268,88 +266,88 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.96 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.64 # Average write queue length when enqueuing -system.physmem.readRowHits 364428 # Number of row buffer hits during reads -system.physmem.writeRowHits 95430 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.27 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.28 # Row buffer hit rate for writes -system.physmem.avgGap 3578176.31 # Average gap between requests -system.physmem.pageHitRate 88.25 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 214821180 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 114180165 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1440644940 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 304576560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3637439520.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4203799590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 238276320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 7970182890 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 4260887040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 438967517640 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 461353182075 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.372821 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1855132089750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 377139000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1545232000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1826595828250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 11096155750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7918821750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 17478430750 # Time in different power states -system.physmem_1.actEnergy 222396720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 118202865 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1441758780 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 308225340 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3641127360.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4165097730 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 227687040 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 8135120370 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 4246672320 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 438904577085 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 461412058890 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.404390 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1855277049250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 349511250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1546624000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1826382821500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 11059060000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7833171250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 17840419500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 19540652 # Number of BP lookups -system.cpu.branchPred.condPredicted 16609155 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 593501 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12781935 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5419166 # Number of BTB hits +system.physmem.avgRdQLen 1.99 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing +system.physmem.readRowHits 364427 # Number of row buffer hits during reads +system.physmem.writeRowHits 95317 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.16 # Row buffer hit rate for writes +system.physmem.avgGap 3577987.41 # Average gap between requests +system.physmem.pageHitRate 88.22 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 216106380 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 114863265 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1442258580 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 305761500 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3620229600.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4158564390 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 232346880 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 8004158310 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 4220231520 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 438996708360 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 461312299845 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.351146 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1855244620250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 361602000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1537874000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1826739481250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 10990187750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7827619250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 17552983750 # Time in different power states +system.physmem_1.actEnergy 222025440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 118005525 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1440038040 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 307191780 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3620229600.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4104344850 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 228211680 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8096599200 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 4247999520 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 438951182175 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 461336536560 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.364142 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1855407985250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 350582750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1537736000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1826594899250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 11062498750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7708202750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 17755828500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 19556212 # Number of BP lookups +system.cpu.branchPred.condPredicted 16618547 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 593854 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12802975 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5420040 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 42.397071 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1123794 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 42287 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6265125 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 563559 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5701566 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 264926 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 42.334223 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1126473 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 42524 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6261380 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 563797 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5697583 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 265016 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 11133148 # DTB read hits -system.cpu.dtb.read_misses 49550 # DTB read misses -system.cpu.dtb.read_acv 604 # DTB read access violations -system.cpu.dtb.read_accesses 995639 # DTB read accesses -system.cpu.dtb.write_hits 6779390 # DTB write hits -system.cpu.dtb.write_misses 12217 # DTB write misses -system.cpu.dtb.write_acv 419 # DTB write access violations -system.cpu.dtb.write_accesses 345330 # DTB write accesses -system.cpu.dtb.data_hits 17912538 # DTB hits -system.cpu.dtb.data_misses 61767 # DTB misses -system.cpu.dtb.data_acv 1023 # DTB access violations -system.cpu.dtb.data_accesses 1340969 # DTB accesses -system.cpu.itb.fetch_hits 1814760 # ITB hits -system.cpu.itb.fetch_misses 10379 # ITB misses -system.cpu.itb.fetch_acv 753 # ITB acv -system.cpu.itb.fetch_accesses 1825139 # ITB accesses +system.cpu.dtb.read_hits 11131129 # DTB read hits +system.cpu.dtb.read_misses 49734 # DTB read misses +system.cpu.dtb.read_acv 613 # DTB read access violations +system.cpu.dtb.read_accesses 995788 # DTB read accesses +system.cpu.dtb.write_hits 6783534 # DTB write hits +system.cpu.dtb.write_misses 12230 # DTB write misses +system.cpu.dtb.write_acv 435 # DTB write access violations +system.cpu.dtb.write_accesses 345368 # DTB write accesses +system.cpu.dtb.data_hits 17914663 # DTB hits +system.cpu.dtb.data_misses 61964 # DTB misses +system.cpu.dtb.data_acv 1048 # DTB access violations +system.cpu.dtb.data_accesses 1341156 # DTB accesses +system.cpu.itb.fetch_hits 1815343 # ITB hits +system.cpu.itb.fetch_misses 10369 # ITB misses +system.cpu.itb.fetch_acv 759 # ITB acv +system.cpu.itb.fetch_accesses 1825712 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -364,154 +362,154 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.numPwrStateTransitions 12878 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 6439 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 279577818.217114 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 438970116.286468 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 279575452.943004 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 438968142.754116 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 6439 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 62000 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 71000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 6439 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 64810036000 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1800201571500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 129626512 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 64823406500 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1800186341500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 129653253 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30190363 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85695972 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19540652 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7106519 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 91835709 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1682318 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 61 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 29737 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 207098 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 428060 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 576 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9928105 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 408572 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 123532763 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.693710 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.023135 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30226306 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85761758 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19556212 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7110310 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 91828962 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1682802 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 214 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 31116 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 206972 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 428466 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 497 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9929941 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 408418 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 123563934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.694068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.023639 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 107696719 87.18% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1032377 0.84% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2107068 1.71% 89.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 968796 0.78% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2908740 2.35% 92.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 664008 0.54% 93.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 809572 0.66% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1033225 0.84% 94.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6312258 5.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 107716203 87.17% 87.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1033964 0.84% 88.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2108086 1.71% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 968916 0.78% 90.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2910075 2.36% 92.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 665807 0.54% 93.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 808204 0.65% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1035117 0.84% 94.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6317562 5.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 123532763 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.150746 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.661099 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24222797 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86210181 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 10254650 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2038697 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 806437 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 738100 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 35530 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 74041720 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 113425 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 806437 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25231796 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 56630169 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20045874 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11215615 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9602870 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 71021126 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 199714 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2114917 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 266619 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5298821 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 47846131 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 85558708 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 85377795 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168460 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38170817 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9675306 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1730146 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 277278 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13907871 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 11664536 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7226725 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1727084 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1123210 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 62712842 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2208202 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 60540114 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 93631 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11951500 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5299174 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1546957 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 123532763 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.490073 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.235792 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 123563934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.150835 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.661470 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24256271 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86199481 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 10262767 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2038754 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 806660 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 739137 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 35567 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 74091152 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 113387 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 806660 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25262123 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 56608165 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20046193 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11227977 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9612814 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 71075345 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 200089 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2115758 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 264182 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5312560 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 47887128 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 85631010 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 85450068 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168489 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38179018 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 9708102 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1730208 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 277739 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13892500 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 11673351 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7232744 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1724750 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1099672 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 62753291 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2208700 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 60568136 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 94532 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11982878 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5316307 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1547451 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 123563934 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.490176 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.236204 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 98992964 80.13% 80.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10407106 8.42% 88.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4428528 3.58% 92.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3186499 2.58% 94.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3245157 2.63% 97.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1605158 1.30% 98.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1098083 0.89% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 432605 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 136663 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 99014105 80.13% 80.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10422330 8.43% 88.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4419921 3.58% 92.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3179961 2.57% 94.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3252538 2.63% 97.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1603803 1.30% 98.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1099991 0.89% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 433312 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 137973 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 123532763 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 123563934 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 207032 16.63% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 606591 48.74% 65.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 372500 29.93% 95.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 31949 2.57% 97.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 26498 2.13% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 206621 16.55% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 610635 48.92% 65.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 372589 29.85% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 31948 2.56% 97.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 26502 2.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7276 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 40915146 67.58% 67.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62152 0.10% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7279 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 40937281 67.59% 67.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62136 0.10% 67.70% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38560 0.06% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38562 0.06% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.77% # Type of FU issued @@ -535,97 +533,97 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 11521390 19.03% 86.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6745321 11.14% 97.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 156180 0.26% 98.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 141327 0.23% 98.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 11522525 19.02% 86.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6750152 11.14% 97.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 156092 0.26% 98.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 141347 0.23% 98.43% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 949126 1.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 60540114 # Type of FU issued -system.cpu.iq.rate 0.467035 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1244571 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020558 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 245211528 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 76534751 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 58316055 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 739664 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 359442 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 336937 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 61379259 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 398150 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 691177 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 60568136 # Type of FU issued +system.cpu.iq.rate 0.467155 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1248295 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020610 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 245303428 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 76606948 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 58345447 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 739604 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 359470 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 336798 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 61411065 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 398087 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 692317 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2573780 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3893 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 22128 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 849514 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2580830 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3930 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 22198 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 854795 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18020 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 462679 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17998 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 456632 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 806437 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 52697038 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1357053 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 68903527 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 198807 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 11664536 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7226725 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1959166 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 45872 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1108146 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 22128 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 230653 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 630212 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 860865 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 59685899 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 11215511 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 854214 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 806660 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 52694504 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1340713 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 68945664 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 202125 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 11673351 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7232744 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1959731 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 45749 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1091638 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 22198 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 229988 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 630611 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 860599 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 59710531 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 11213503 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 857604 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3982483 # number of nop insts executed -system.cpu.iew.exec_refs 18027322 # number of memory reference insts executed -system.cpu.iew.exec_branches 9384105 # Number of branches executed -system.cpu.iew.exec_stores 6811811 # Number of stores executed -system.cpu.iew.exec_rate 0.460445 # Inst execution rate -system.cpu.iew.wb_sent 58897557 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 58652992 # cumulative count of insts written-back -system.cpu.iew.wb_producers 29769052 # num instructions producing a value -system.cpu.iew.wb_consumers 41264413 # num instructions consuming a value -system.cpu.iew.wb_rate 0.452477 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.721422 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12552458 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 769809 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 121361631 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.462746 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.395074 # Number of insts commited each cycle +system.cpu.iew.exec_nop 3983673 # number of nop insts executed +system.cpu.iew.exec_refs 18029484 # number of memory reference insts executed +system.cpu.iew.exec_branches 9387402 # Number of branches executed +system.cpu.iew.exec_stores 6815981 # Number of stores executed +system.cpu.iew.exec_rate 0.460540 # Inst execution rate +system.cpu.iew.wb_sent 58927059 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 58682245 # cumulative count of insts written-back +system.cpu.iew.wb_producers 29779151 # num instructions producing a value +system.cpu.iew.wb_consumers 41279871 # num instructions consuming a value +system.cpu.iew.wb_rate 0.452609 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.721396 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 12584544 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661249 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 770143 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 121389515 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.462724 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.395132 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 101505032 83.64% 83.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7973925 6.57% 90.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4190958 3.45% 93.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2263923 1.87% 95.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1758393 1.45% 96.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 630847 0.52% 97.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 481222 0.40% 97.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 521755 0.43% 98.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2035576 1.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 101523124 83.63% 83.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7984339 6.58% 90.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4194668 3.46% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2261790 1.86% 95.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1754136 1.45% 96.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 633873 0.52% 97.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 481376 0.40% 97.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 513083 0.42% 98.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2043126 1.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 121361631 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56159642 # Number of instructions committed -system.cpu.commit.committedOps 56159642 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 121389515 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56169799 # Number of instructions committed +system.cpu.commit.committedOps 56169799 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15467967 # Number of memory references committed -system.cpu.commit.loads 9090756 # Number of loads committed -system.cpu.commit.membars 226364 # Number of memory barriers committed -system.cpu.commit.branches 8439956 # Number of branches committed +system.cpu.commit.refs 15470470 # Number of memory references committed +system.cpu.commit.loads 9092521 # Number of loads committed +system.cpu.commit.membars 226360 # Number of memory barriers committed +system.cpu.commit.branches 8440690 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52009640 # Number of committed integer instructions. -system.cpu.commit.function_calls 740476 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3197376 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36210459 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60672 0.11% 70.28% # Class of committed instruction +system.cpu.commit.int_insts 52019202 # Number of committed integer instructions. +system.cpu.commit.function_calls 740566 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3197964 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36217526 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60675 0.11% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction @@ -655,37 +653,37 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9172524 16.33% 86.69% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6245101 11.12% 97.81% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9174285 16.33% 86.69% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6245839 11.12% 97.81% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemRead 144596 0.26% 98.06% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemWrite 138067 0.25% 98.31% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 949126 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56159642 # Class of committed instruction -system.cpu.commit.bw_lim_events 2035576 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 187788618 # The number of ROB reads -system.cpu.rob.rob_writes 139599579 # The number of ROB writes -system.cpu.timesIdled 556181 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6093749 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3600396704 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52969539 # Number of Instructions Simulated -system.cpu.committedOps 52969539 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.447190 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.447190 # CPI: Total CPI of All Threads -system.cpu.ipc 0.408632 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.408632 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 77875050 # number of integer regfile reads -system.cpu.int_regfile_writes 42594378 # number of integer regfile writes -system.cpu.fp_regfile_reads 166655 # number of floating regfile reads -system.cpu.fp_regfile_writes 175866 # number of floating regfile writes -system.cpu.misc_regfile_reads 2002132 # number of misc regfile reads -system.cpu.misc_regfile_writes 939499 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1405977 # number of replacements +system.cpu.commit.op_class_0::total 56169799 # Class of committed instruction +system.cpu.commit.bw_lim_events 2043126 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 187851195 # The number of ROB reads +system.cpu.rob.rob_writes 139687376 # The number of ROB writes +system.cpu.timesIdled 556781 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6089319 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3600366244 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52979108 # Number of Instructions Simulated +system.cpu.committedOps 52979108 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.447252 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.447252 # CPI: Total CPI of All Threads +system.cpu.ipc 0.408622 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.408622 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 77910051 # number of integer regfile reads +system.cpu.int_regfile_writes 42617580 # number of integer regfile writes +system.cpu.fp_regfile_reads 166665 # number of floating regfile reads +system.cpu.fp_regfile_writes 175716 # number of floating regfile writes +system.cpu.misc_regfile_reads 2001313 # number of misc regfile reads +system.cpu.misc_regfile_writes 939513 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1405851 # number of replacements system.cpu.dcache.tags.tagsinuse 511.994060 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 12626898 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1406489 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.977602 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 12629128 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1406363 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.979992 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 28232500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.994060 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy @@ -695,506 +693,507 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 67141007 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 67141007 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 8018368 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 8018368 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4180367 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4180367 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 212226 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 212226 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215667 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215667 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 12198735 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 12198735 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 12198735 # number of overall hits -system.cpu.dcache.overall_hits::total 12198735 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1817070 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1817070 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1966374 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1966374 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23459 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23459 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 98 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 98 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3783444 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3783444 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3783444 # number of overall misses -system.cpu.dcache.overall_misses::total 3783444 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 45126424500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 45126424500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 92431305073 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 92431305073 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 416761500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 416761500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1368500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 1368500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137557729573 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137557729573 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137557729573 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137557729573 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9835438 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9835438 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6146741 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6146741 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235685 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 235685 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215765 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215765 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15982179 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15982179 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15982179 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15982179 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184747 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.184747 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319905 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.319905 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.099535 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.099535 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000454 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000454 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.236729 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.236729 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.236729 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.236729 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24834.719906 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24834.719906 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47005.963806 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47005.963806 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17765.527090 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17765.527090 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13964.285714 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13964.285714 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36357.807747 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36357.807747 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36357.807747 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36357.807747 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4938618 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4294 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 133157 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 67152661 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 67152661 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 8020035 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8020035 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4180765 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4180765 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 212398 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 212398 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215680 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215680 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 12200800 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 12200800 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 12200800 # number of overall hits +system.cpu.dcache.overall_hits::total 12200800 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1817327 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1817327 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1966706 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1966706 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23570 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23570 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 93 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 93 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3784033 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3784033 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3784033 # number of overall misses +system.cpu.dcache.overall_misses::total 3784033 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 45159601500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 45159601500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 92703832258 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 92703832258 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 420302500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 420302500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1299500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 1299500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 137863433758 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 137863433758 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 137863433758 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 137863433758 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9837362 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9837362 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147471 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147471 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235968 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 235968 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215773 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215773 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15984833 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15984833 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15984833 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15984833 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184737 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.184737 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319921 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.319921 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.099886 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.099886 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000431 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000431 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.236726 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.236726 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.236726 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.236726 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24849.463800 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24849.463800 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47136.599094 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47136.599094 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17832.095885 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17832.095885 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13973.118280 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13973.118280 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36432.936435 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36432.936435 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36432.936435 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36432.936435 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4933871 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2725 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 132268 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.088685 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 153.357143 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 844399 # number of writebacks -system.cpu.dcache.writebacks::total 844399 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 716933 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 716933 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1676859 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1676859 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6505 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6505 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2393792 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2393792 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2393792 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2393792 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100137 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1100137 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289515 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289515 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16954 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16954 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 98 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 98 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1389652 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1389652 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1389652 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1389652 # number of overall MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.302076 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 97.321429 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 844182 # number of writebacks +system.cpu.dcache.writebacks::total 844182 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717105 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 717105 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1677249 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1677249 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6763 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 6763 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2394354 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2394354 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2394354 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2394354 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100222 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1100222 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289457 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 289457 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16807 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16807 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 93 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 93 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1389679 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1389679 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1389679 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1389679 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33017901000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33017901000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14364764991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14364764991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 212848500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 212848500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1270500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1270500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47382665991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47382665991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47382665991 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47382665991 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535128000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535128000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535128000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535128000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111854 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111854 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047101 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047101 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071935 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071935 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000454 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000454 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086950 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.086950 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086950 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.086950 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30012.535711 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30012.535711 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49616.651956 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49616.651956 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12554.470921 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12554.470921 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12964.285714 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12964.285714 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34096.785376 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34096.785376 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34096.785376 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34096.785376 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221519.191919 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221519.191919 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92874.826063 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92874.826063 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1076759 # number of replacements -system.cpu.icache.tags.tagsinuse 509.003606 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8782144 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1077267 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.152245 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 30283847500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.003606 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994148 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994148 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33013560500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33013560500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14384695133 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14384695133 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 210983000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 210983000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1206500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1206500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47398255633 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47398255633 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47398255633 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47398255633 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535352000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535352000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535352000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535352000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111841 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111841 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047086 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047086 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071226 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071226 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000431 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000431 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086937 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.086937 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086937 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.086937 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30006.271916 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30006.271916 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49695.447452 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49695.447452 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12553.281371 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12553.281371 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12973.118280 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12973.118280 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34107.341072 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34107.341072 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34107.341072 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34107.341072 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221551.515152 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221551.515152 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92888.378002 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92888.378002 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1077480 # number of replacements +system.cpu.icache.tags.tagsinuse 509.004193 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8783075 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1077988 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.147656 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 30284131500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.004193 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994149 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994149 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11005677 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11005677 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 8782144 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8782144 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8782144 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8782144 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8782144 # number of overall hits -system.cpu.icache.overall_hits::total 8782144 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1145952 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1145952 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1145952 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1145952 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1145952 # number of overall misses -system.cpu.icache.overall_misses::total 1145952 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16332614990 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16332614990 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16332614990 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16332614990 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16332614990 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16332614990 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9928096 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9928096 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9928096 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9928096 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9928096 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9928096 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115425 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115425 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115425 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115425 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.115425 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.115425 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14252.442502 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14252.442502 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14252.442502 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14252.442502 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14252.442502 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14252.442502 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8348 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 11008225 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11008225 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 8783075 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8783075 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8783075 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8783075 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8783075 # number of overall hits +system.cpu.icache.overall_hits::total 8783075 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1146854 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1146854 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1146854 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1146854 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1146854 # number of overall misses +system.cpu.icache.overall_misses::total 1146854 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16347552990 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16347552990 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16347552990 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16347552990 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16347552990 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16347552990 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9929929 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9929929 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9929929 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9929929 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9929929 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9929929 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115495 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.115495 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.115495 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.115495 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.115495 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.115495 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14254.258162 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14254.258162 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14254.258162 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14254.258162 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14254.258162 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14254.258162 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8615 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 326 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 335 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 25.607362 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.716418 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1076759 # number of writebacks -system.cpu.icache.writebacks::total 1076759 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68371 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68371 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68371 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68371 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68371 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68371 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077581 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1077581 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1077581 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1077581 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1077581 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1077581 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14423902993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14423902993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14423902993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14423902993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14423902993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14423902993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108539 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108539 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108539 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.108539 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108539 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.108539 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13385.446656 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13385.446656 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13385.446656 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13385.446656 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13385.446656 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13385.446656 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.cpu.icache.writebacks::writebacks 1077480 # number of writebacks +system.cpu.icache.writebacks::total 1077480 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68558 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 68558 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 68558 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 68558 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 68558 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 68558 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1078296 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1078296 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1078296 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1078296 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1078296 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1078296 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14436755994 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14436755994 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14436755994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14436755994 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14436755994 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14436755994 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108591 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.108591 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.108591 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13388.490724 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13388.490724 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13388.490724 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13388.490724 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13388.490724 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13388.490724 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 338614 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65420.353665 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4559964 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65420.361718 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4561143 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 404136 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.283241 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6414398000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 255.266765 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5296.205124 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59868.881776 # Average occupied blocks per requestor +system.cpu.l2cache.tags.avg_refs 11.286159 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6414386000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 255.267028 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5315.608032 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59849.486658 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.003895 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080814 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.913527 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081110 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.913231 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998235 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 896 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5602 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58570 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 446 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5595 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58579 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40121077 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40121077 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 844399 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 844399 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1076079 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1076079 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 69 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 69 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 98 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 98 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185276 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185276 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1062141 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1062141 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 832063 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 832063 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1062141 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1017339 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2079480 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1062141 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1017339 # number of overall hits -system.cpu.l2cache.overall_hits::total 2079480 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 114725 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 114725 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15044 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 15044 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 274467 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 274467 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15044 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389192 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404236 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15044 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389192 # number of overall misses -system.cpu.l2cache.overall_misses::total 404236 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 418500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 418500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12044968500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12044968500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1516847000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1516847000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22392456000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 22392456000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1516847000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 34437424500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35954271500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1516847000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 34437424500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35954271500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 844399 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 844399 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1076079 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1076079 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 78 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 98 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 98 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 300001 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 300001 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1077185 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1077185 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1106530 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1106530 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1077185 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1406531 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2483716 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1077185 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1406531 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2483716 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.115385 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.115385 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382415 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.382415 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013966 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013966 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248043 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248043 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013966 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.276703 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.162755 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013966 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.276703 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.162755 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 46500 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 46500 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104989.919372 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104989.919372 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 100827.373039 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 100827.373039 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81585.239756 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81585.239756 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 100827.373039 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88484.410008 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 88943.764286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 100827.373039 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88484.410008 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 88943.764286 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 40130556 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40130556 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 844182 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 844182 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1076791 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1076791 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 68 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 68 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 93 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 93 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 185239 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 185239 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1062874 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1062874 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 831967 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 831967 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1062874 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1017206 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2080080 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1062874 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1017206 # number of overall hits +system.cpu.l2cache.overall_hits::total 2080080 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 7 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 114698 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 114698 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15038 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 15038 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 274508 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 274508 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15038 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389206 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404244 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15038 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389206 # number of overall misses +system.cpu.l2cache.overall_misses::total 404244 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 357500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 357500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12064669000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12064669000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1519815000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1519815000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22385224000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 22385224000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1519815000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 34449893000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35969708000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1519815000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 34449893000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35969708000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 844182 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 844182 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1076791 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1076791 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 75 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 75 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 93 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 93 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 299937 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 299937 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1077912 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1077912 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1106475 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1106475 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1077912 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1406412 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2484324 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1077912 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1406412 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2484324 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.093333 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.093333 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382407 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.382407 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013951 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013951 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248092 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248092 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013951 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.276737 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.162718 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013951 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.276737 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.162718 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 51071.428571 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 51071.428571 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105186.393834 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105186.393834 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101064.968746 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101064.968746 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81546.709021 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81546.709021 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101064.968746 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88513.262899 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 88980.190182 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101064.968746 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88513.262899 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 88980.190182 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 75900 # number of writebacks -system.cpu.l2cache.writebacks::total 75900 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75929 # number of writebacks +system.cpu.l2cache.writebacks::total 75929 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114725 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 114725 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15043 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15043 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274467 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274467 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15043 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389192 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404235 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15043 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389192 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404235 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114698 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 114698 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15037 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15037 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274508 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274508 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15037 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389206 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404243 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15037 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389206 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404243 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 328500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 328500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10897718500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10897718500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1366325500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1366325500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19653014500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19653014500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1366325500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 30550733000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31917058500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1366325500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 30550733000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31917058500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448486500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448486500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448486500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448486500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.115385 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.115385 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382415 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382415 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013965 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248043 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248043 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276703 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.162754 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276703 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.162754 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 36500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 36500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94989.919372 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94989.919372 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 90827.993086 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 90827.993086 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71604.289405 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71604.289405 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 90827.993086 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78497.844252 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78956.692271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 90827.993086 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78497.844252 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78956.692271 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209016.810967 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209016.810967 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87633.038901 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87633.038901 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4967024 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2483092 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2362 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 287500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 287500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10917688501 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10917688501 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1369353500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1369353500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19646288000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19646288000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1369353500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 30563976501 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31933330001 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1369353500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 30563976501 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31933330001 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448711500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448711500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448711500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448711500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.093333 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.093333 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382407 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382407 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013950 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248092 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248092 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276737 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.162718 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276737 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.162718 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 41071.428571 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 41071.428571 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95186.389484 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95186.389484 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 91065.604841 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 91065.604841 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71569.090883 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71569.090883 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 91065.604841 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78529.047602 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78995.381493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 91065.604841 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78529.047602 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78995.381493 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209049.278499 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209049.278499 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87646.651340 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87646.651340 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4968207 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2483449 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 5093 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 951 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 951 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2191157 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2191810 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 920299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1076759 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 824292 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 78 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 98 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 176 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 300001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 300001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1077581 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106690 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 40 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 237 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3231525 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252605 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7484130 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137852416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144111100 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 281963516 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 339563 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4892928 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2839828 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001278 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.035720 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 920111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1077480 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 824354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 75 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 93 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 299937 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 299937 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1078296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106636 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 47 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3233688 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252227 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7485915 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137945088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144089148 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 282034236 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 339553 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4894016 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2840416 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002130 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.046099 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2836200 99.87% 99.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3628 0.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2834367 99.79% 99.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 6049 0.21% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2839828 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4417734000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2840416 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4418829500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 292883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1617399440 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1618554275 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2121770107 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2121571625 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1208,7 +1207,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51151 # Transaction distribution @@ -1239,46 +1238,46 @@ system.iobus.pkt_size_system.bridge.master::total 44156 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5359000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5364500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 816500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 813500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 178500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14034000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14114000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2179500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6056500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6040500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 92500 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 88500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216222032 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216207792 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.265413 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.265392 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1714256790000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.265413 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.079088 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.079088 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1714257470000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.265392 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.079087 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.079087 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1287,14 +1286,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21932883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21932883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4939835149 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4939835149 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4961768032 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4961768032 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4961768032 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4961768032 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21940383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21940383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4930799409 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4930799409 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4952739792 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4952739792 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4952739792 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4952739792 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1311,19 +1310,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126779.670520 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126779.670520 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118883.210170 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118883.210170 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118915.950437 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118915.950437 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118915.950437 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118915.950437 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 2115 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126823.023121 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126823.023121 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118665.753971 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118665.753971 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118699.575602 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118699.575602 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118699.575602 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118699.575602 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1416 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 13 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 132.187500 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 108.923077 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1335,14 +1334,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13282883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13282883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2859804565 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2859804565 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2873087448 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2873087448 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2873087448 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2873087448 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13290383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13290383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2850780302 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2850780302 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2864070685 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2864070685 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2864070685 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2864070685 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1351,75 +1350,76 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76779.670520 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76779.670520 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68824.715176 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68824.715176 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68857.697975 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68857.697975 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68857.697975 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68857.697975 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 825525 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 380458 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 414 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76823.023121 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76823.023121 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68607.535185 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68607.535185 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68641.598203 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68641.598203 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68641.598203 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68641.598203 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 825546 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 380389 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 528 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 296573 # Transaction distribution +system.membus.trans_dist::ReadResp 296601 # Transaction distribution system.membus.trans_dist::WriteReq 9599 # Transaction distribution system.membus.trans_dist::WriteResp 9599 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117412 # Transaction distribution -system.membus.trans_dist::CleanEvict 262094 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117441 # Transaction distribution +system.membus.trans_dist::CleanEvict 262065 # Transaction distribution system.membus.trans_dist::UpgradeReq 137 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 114597 # Transaction distribution -system.membus.trans_dist::ReadExResp 114597 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289683 # Transaction distribution -system.membus.trans_dist::BadAddressError 40 # Transaction distribution +system.membus.trans_dist::ReadExReq 114568 # Transaction distribution +system.membus.trans_dist::ReadExResp 114568 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289718 # Transaction distribution +system.membus.trans_dist::BadAddressError 47 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 124 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145815 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 80 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178953 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 94 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178964 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1262378 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1262389 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30700160 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30744316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30746044 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33402044 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 438 # Total snoops (count) -system.membus.snoopTraffic 27840 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 462498 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001464 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.038232 # Request fanout histogram +system.membus.pkt_size::total 33403772 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 563 # Total snoops (count) +system.membus.snoopTraffic 27904 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 462504 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001466 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038259 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 461821 99.85% 99.85% # Request fanout histogram -system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 461826 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 678 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 462498 # Request fanout histogram -system.membus.reqLayer0.occupancy 28738500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 462504 # Request fanout histogram +system.membus.reqLayer0.occupancy 28800500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1313413567 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1313542061 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 48500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 57500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2137867250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2137882250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 917617 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1056521 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1451,29 +1451,29 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211030 # number of hwrei instructions executed @@ -1487,11 +1487,11 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.41% # nu system.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73303 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1819136783500 97.54% 97.54% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 67099500 0.00% 97.54% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 565538000 0.03% 97.57% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 45241360000 2.43% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1865010781000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1819124828000 97.54% 97.54% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 67368000 0.00% 97.54% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 565513500 0.03% 97.57% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 45251211500 2.43% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1865008921000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -1514,19 +1514,19 @@ system.cpu.kern.callpal::rti 5106 2.66% 99.64% # nu system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.callpal::total 191988 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches system.cpu.kern.mode_good::kernel 1908 system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326042 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326098 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.393971 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29668657000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2761122500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1832580993500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 29666586000 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2759246500 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832583080500 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |