diff options
| author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:52 -0500 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:52 -0500 |
| commit | 5fb00e1df6b2b7d9db472d0c25765263ed1b839f (patch) | |
| tree | 2f94ca554d9f92d1fe737ed98931856e43b52f6a /tests/long/fs/10.linux-boot/ref/alpha | |
| parent | e09e9fa279dec86b171b5e3efeb7057fa0d21cc9 (diff) | |
| download | gem5-5fb00e1df6b2b7d9db472d0c25765263ed1b839f.tar.xz | |
tests: Add CPU switching tests
This changeset adds a set of tests that stress the CPU switching
code. It adds the following test configurations:
* tsunami-switcheroo-full -- Alpha system (atomic, timing, O3)
* realview-switcheroo-atomic -- ARM system (atomic<->atomic)
* realview-switcheroo-timing -- ARM system (timing<->timing)
* realview-switcheroo-o3 -- ARM system (O3<->O3)
* realview-switcheroo-full -- ARM system (atomic, timing, O3)
Reference data is provided for the 10.linux-boot test case. All of the
tests trigger a CPU switch once per millisecond during the boot
process.
The in-order CPU model was not included in any of the tests as it does
not support CPU handover.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
5 files changed, 9181 insertions, 0 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini new file mode 100644 index 000000000..3b827b59e --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +full_system=true +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxAlphaSystem +children=bridge cpu0 cpu1 cpu2 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami +boot_cpu_frequency=500 +boot_osflags=root=/dev/hda1 console=ttyS0 +clock=1000 +console=/arm/scratch/sysexplr/dist/binaries/console +init_param=0 +kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux +load_addr_mask=1099511627775 +mem_mode=atomic +mem_ranges=0:134217727 +memories=system.physmem +num_work_ids=16 +pal=/arm/scratch/sysexplr/dist/binaries/ts_osfpal +readfile=tests/halt.sh +symbolfile= +system_rev=1024 +system_type=34 +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.bridge] +type=Bridge +clock=1000 +delay=50000 +ranges=8796093022208:18446744073709551615 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cpu0] +type=AtomicSimpleCPU +children=dcache dtb icache interrupts isa itb tracer +checker=Null +clock=500 +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +isa=system.cpu0.isa +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +switched_out=false +system=system +tracer=system.cpu0.tracer +width=1 +workload= +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +clock=500 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +size=32768 +system=system +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.slave[1] + +[system.cpu0.dtb] +type=AlphaTLB +size=64 + +[system.cpu0.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +clock=500 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +size=32768 +system=system +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.interrupts] +type=AlphaInterrupts + +[system.cpu0.isa] +type=AlphaISA + +[system.cpu0.itb] +type=AlphaTLB +size=48 + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu1] +type=TimingSimpleCPU +children=dtb interrupts isa itb tracer +checker=Null +clock=500 +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu1.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu1.interrupts +isa=system.cpu1.isa +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +switched_out=true +system=system +tracer=system.cpu1.tracer +workload= + +[system.cpu1.dtb] +type=AlphaTLB +size=64 + +[system.cpu1.interrupts] +type=AlphaInterrupts + +[system.cpu1.isa] +type=AlphaISA + +[system.cpu1.itb] +type=AlphaTLB +size=48 + +[system.cpu1.tracer] +type=ExeTracer + +[system.cpu2] +type=DerivO3CPU +children=dtb fuPool interrupts isa itb tracer +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu2.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu2.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +interrupts=system.cpu2.interrupts +isa=system.cpu2.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu2.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +store_set_clear_period=250000 +switched_out=true +system=system +tracer=system.cpu2.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload= + +[system.cpu2.dtb] +type=AlphaTLB +size=64 + +[system.cpu2.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 + +[system.cpu2.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu2.fuPool.FUList0.opList + +[system.cpu2.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu2.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 + +[system.cpu2.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu2.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu2.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 + +[system.cpu2.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu2.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu2.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu2.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 + +[system.cpu2.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu2.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu2.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu2.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu2.fuPool.FUList4.opList + +[system.cpu2.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu2.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 + +[system.cpu2.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu2.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu2.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu2.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu2.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu2.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu2.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu2.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu2.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu2.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu2.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu2.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu2.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu2.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu2.fuPool.FUList6] +type=FUDesc +children=opList +count=0 +opList=system.cpu2.fuPool.FUList6.opList + +[system.cpu2.fuPool.FUList6.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu2.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 + +[system.cpu2.fuPool.FUList7.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu2.fuPool.FUList7.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu2.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +opList=system.cpu2.fuPool.FUList8.opList + +[system.cpu2.fuPool.FUList8.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu2.interrupts] +type=AlphaInterrupts + +[system.cpu2.isa] +type=AlphaISA + +[system.cpu2.itb] +type=AlphaTLB +size=48 + +[system.cpu2.tracer] +type=ExeTracer + +[system.disk0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.disk0.image + +[system.disk0.image] +type=CowDiskImage +children=child +child=system.disk0.image.child +image_file= +read_only=false +table_size=65536 + +[system.disk0.image.child] +type=RawDiskImage +image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img +read_only=true + +[system.disk2] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.disk2.image + +[system.disk2.image] +type=CowDiskImage +children=child +child=system.disk2.image.child +image_file= +read_only=false +table_size=65536 + +[system.disk2.image.child] +type=RawDiskImage +image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img +read_only=true + +[system.intrctrl] +type=IntrControl +sys=system + +[system.iobus] +type=NoncoherentBus +block_size=64 +clock=1000 +header_cycles=1 +use_default_range=true +width=8 +default=system.tsunami.pciconfig.pio +master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side +slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma + +[system.iocache] +type=BaseCache +addr_ranges=0:134217727 +assoc=8 +block_size=64 +clock=1000 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +size=1024 +system=system +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[29] +mem_side=system.membus.slave[2] + +[system.l2c] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +size=4194304 +system=system +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.membus] +type=CoherentBus +children=badaddr_responder +block_size=64 +clock=1000 +header_cycles=1 +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.physmem.port +slave=system.system_port system.l2c.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.membus.default + +[system.physmem] +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 +conf_table_reported=false +in_addr_map=true +lines_per_rowbuffer=64 +mem_sched_policy=fcfs +null=false +page_policy=open +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 +zero=false +port=system.membus.master[1] + +[system.simple_disk] +type=SimpleDisk +children=disk +disk=system.simple_disk.disk +system=system + +[system.simple_disk.disk] +type=RawDiskImage +image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img +read_only=true + +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=8 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side + +[system.tsunami] +type=Tsunami +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +intrctrl=system.intrctrl +system=system + +[system.tsunami.backdoor] +type=AlphaBackdoor +clock=1000 +cpu=system.cpu0 +disk=system.simple_disk +pio_addr=8804682956800 +pio_latency=100000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.master[24] + +[system.tsunami.cchip] +type=TsunamiCChip +clock=1000 +pio_addr=8803072344064 +pio_latency=100000 +system=system +tsunami=system.tsunami +pio=system.iobus.master[0] + +[system.tsunami.ethernet] +type=NSGigE +BAR0=1 +BAR0LegacyIO=false +BAR0Size=256 +BAR1=0 +BAR1LegacyIO=false +BAR1Size=4096 +BAR2=0 +BAR2LegacyIO=false +BAR2Size=0 +BAR3=0 +BAR3LegacyIO=false +BAR3Size=0 +BAR4=0 +BAR4LegacyIO=false +BAR4Size=0 +BAR5=0 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=2 +Command=0 +DeviceID=34 +ExpansionROM=0 +HeaderType=0 +InterruptLine=30 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=52 +MinimumGrant=176 +ProgIF=0 +Revision=0 +Status=656 +SubClassCode=0 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=4107 +clock=2000 +config_latency=20000 +dma_data_free=false +dma_desc_free=false +dma_no_allocate=true +dma_read_delay=0 +dma_read_factor=0 +dma_write_delay=0 +dma_write_factor=0 +hardware_address=00:90:00:00:00:01 +intr_delay=10000000 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=30000 +platform=system.tsunami +rss=false +rx_delay=1000000 +rx_fifo_size=524288 +rx_filter=true +rx_thread=false +system=system +tx_delay=1000000 +tx_fifo_size=524288 +tx_thread=false +config=system.iobus.master[28] +dma=system.iobus.slave[2] +pio=system.iobus.master[27] + +[system.tsunami.fake_OROM] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8796093677568 +pio_latency=100000 +pio_size=393216 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[8] + +[system.tsunami.fake_ata0] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615848432 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[19] + +[system.tsunami.fake_ata1] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615848304 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[20] + +[system.tsunami.fake_pnp_addr] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615848569 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[9] + +[system.tsunami.fake_pnp_read0] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615848451 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[11] + +[system.tsunami.fake_pnp_read1] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615848515 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[12] + +[system.tsunami.fake_pnp_read2] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615848579 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[13] + +[system.tsunami.fake_pnp_read3] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615848643 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[14] + +[system.tsunami.fake_pnp_read4] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615848707 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[15] + +[system.tsunami.fake_pnp_read5] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615848771 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[16] + +[system.tsunami.fake_pnp_read6] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615848835 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[17] + +[system.tsunami.fake_pnp_read7] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615848899 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[18] + +[system.tsunami.fake_pnp_write] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615850617 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[10] + +[system.tsunami.fake_ppc] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615848891 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[7] + +[system.tsunami.fake_sm_chip] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615848816 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[2] + +[system.tsunami.fake_uart1] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615848696 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[3] + +[system.tsunami.fake_uart2] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615848936 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[4] + +[system.tsunami.fake_uart3] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615848680 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[5] + +[system.tsunami.fake_uart4] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=8804615848944 +pio_latency=100000 +pio_size=8 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[6] + +[system.tsunami.fb] +type=BadDevice +clock=1000 +devicename=FrameBuffer +pio_addr=8804615848912 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.tsunami.ide] +type=IdeController +BAR0=1 +BAR0LegacyIO=false +BAR0Size=8 +BAR1=1 +BAR1LegacyIO=false +BAR1Size=4 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=1 +Command=0 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=0 +MinimumGrant=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clock=1000 +config_latency=20000 +ctrl_offset=0 +disks=system.disk0 system.disk2 +io_shift=0 +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=30000 +platform=system.tsunami +system=system +config=system.iobus.master[26] +dma=system.iobus.slave[1] +pio=system.iobus.master[25] + +[system.tsunami.io] +type=TsunamiIO +clock=1000 +frequency=976562500 +pio_addr=8804615847936 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +tsunami=system.tsunami +year_is_bcd=false +pio=system.iobus.master[22] + +[system.tsunami.pchip] +type=TsunamiPChip +clock=1000 +pio_addr=8802535473152 +pio_latency=100000 +system=system +tsunami=system.tsunami +pio=system.iobus.master[1] + +[system.tsunami.pciconfig] +type=PciConfigAll +bus=0 +clock=1000 +pio_latency=30000 +platform=system.tsunami +size=16777216 +system=system +pio=system.iobus.default + +[system.tsunami.uart] +type=Uart8250 +clock=1000 +pio_addr=8804615848952 +pio_latency=100000 +platform=system.tsunami +system=system +terminal=system.terminal +pio=system.iobus.master[23] + diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr new file mode 100755 index 000000000..3c54e08bb --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr @@ -0,0 +1,9 @@ +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything +warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout new file mode 100755 index 000000000..94a2dd47e --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout @@ -0,0 +1,6245 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Dec 11 2012 16:31:37 +gem5 started Dec 11 2012 16:31:53 +gem5 executing on e103721-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 +info: Entering event queue @ 0. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1000000000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2000000000. Starting simulation... +switching cpus +info: Entering event queue @ 2000001000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 3000001000. Starting simulation... +info: Entering event queue @ 3000043000. Starting simulation... +switching cpus +info: Entering event queue @ 3000047500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 4000047500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 5000047500. Starting simulation... +switching cpus +info: Entering event queue @ 5000048000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 6000048000. Starting simulation... +info: Entering event queue @ 7452589500. Starting simulation... +info: Entering event queue @ 7452657000. Starting simulation... +switching cpus +info: Entering event queue @ 7452661500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 8452661500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 9452661500. Starting simulation... +info: Entering event queue @ 9452675500. Starting simulation... +switching cpus +info: Entering event queue @ 9452679000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 10452679000. Starting simulation... +switching cpus +info: Entering event queue @ 10452683500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 11452683500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 12452683500. Starting simulation... +switching cpus +info: Entering event queue @ 12452684500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 13452684500. Starting simulation... +switching cpus +info: Entering event queue @ 13452690000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 14452690000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 15452690000. Starting simulation... +switching cpus +info: Entering event queue @ 15452691000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 16452691000. Starting simulation... +switching cpus +info: Entering event queue @ 16452704500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 17452704500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 18452704500. Starting simulation... +switching cpus +info: Entering event queue @ 18452705500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 19452705500. Starting simulation... +info: Entering event queue @ 19452711000. Starting simulation... +switching cpus +info: Entering event queue @ 19452715500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 20452715500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 21452715500. Starting simulation... +switching cpus +info: Entering event queue @ 21452716000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 22452716000. Starting simulation... +info: Entering event queue @ 22452727500. Starting simulation... +switching cpus +info: Entering event queue @ 22452733000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 23452733000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 24452733000. Starting simulation... +switching cpus +info: Entering event queue @ 24452734000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 25452734000. Starting simulation... +switching cpus +info: Entering event queue @ 25452745500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 26452745500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 27452745500. Starting simulation... +switching cpus +info: Entering event queue @ 27452746500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 28452746500. Starting simulation... +info: Entering event queue @ 28452758500. Starting simulation... +info: Entering event queue @ 28452769000. Starting simulation... +switching cpus +info: Entering event queue @ 28452773500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 29452773500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 30452773500. Starting simulation... +switching cpus +info: Entering event queue @ 30452992500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 31452992500. Starting simulation... +switching cpus +info: Entering event queue @ 31452995500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 32452995500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 33452995500. Starting simulation... +switching cpus +info: Entering event queue @ 33452996500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 34452996500. Starting simulation... +switching cpus +info: Entering event queue @ 34452999500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 35452999500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 36452999500. Starting simulation... +switching cpus +info: Entering event queue @ 36453000500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 37453000500. Starting simulation... +switching cpus +info: Entering event queue @ 37453003500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 38453003500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 39453003500. Starting simulation... +switching cpus +info: Entering event queue @ 39453004500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 40453004500. Starting simulation... +switching cpus +info: Entering event queue @ 40453007500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 41453007500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 42453007500. Starting simulation... +switching cpus +info: Entering event queue @ 42453008500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 43453008500. Starting simulation... +switching cpus +info: Entering event queue @ 43945335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 44945335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 45945335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 46945335500. Starting simulation... +switching cpus +info: Entering event queue @ 47851585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 48851585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 49851585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 50851585500. Starting simulation... +switching cpus +info: Entering event queue @ 51757835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 52757835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 53757835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 54757835500. Starting simulation... +switching cpus +info: Entering event queue @ 55664085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 56664085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 57664085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 58664085500. Starting simulation... +switching cpus +info: Entering event queue @ 59570335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 60570335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 61570335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 62570335500. Starting simulation... +switching cpus +info: Entering event queue @ 63476585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 64476585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 65476585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 66476585500. Starting simulation... +switching cpus +info: Entering event queue @ 67382835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 68382835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 69382835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 70382835500. Starting simulation... +switching cpus +info: Entering event queue @ 71289085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 72289085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 73289085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 74289085500. Starting simulation... +switching cpus +info: Entering event queue @ 75195335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 76195335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 77195335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 78195335500. Starting simulation... +switching cpus +info: Entering event queue @ 79101585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 80101585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 81101585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 82101585500. Starting simulation... +switching cpus +info: Entering event queue @ 83007835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 84007835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 85007835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 86007835500. Starting simulation... +switching cpus +info: Entering event queue @ 86914085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 87914085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 88914085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 89914085500. Starting simulation... +switching cpus +info: Entering event queue @ 90820335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 91820335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 92820335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 93820335500. Starting simulation... +switching cpus +info: Entering event queue @ 94726585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 95726585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 96726585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 97726585500. Starting simulation... +switching cpus +info: Entering event queue @ 98632835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 99632835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 100632835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 101632835500. Starting simulation... +switching cpus +info: Entering event queue @ 102539085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 103539085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 104539085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 105539085500. Starting simulation... +switching cpus +info: Entering event queue @ 106445335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 107445335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 108445335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 109445335500. Starting simulation... +switching cpus +info: Entering event queue @ 110351585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 111351585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 112351585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 113351585500. Starting simulation... +switching cpus +info: Entering event queue @ 114257835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 115257835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 116257835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 117257835500. Starting simulation... +switching cpus +info: Entering event queue @ 118164085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 119164085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 120164085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 121164085500. Starting simulation... +switching cpus +info: Entering event queue @ 122070335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 123070335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 124070335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 125070335500. Starting simulation... +switching cpus +info: Entering event queue @ 125976585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 126976585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 127976585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 128976585500. Starting simulation... +switching cpus +info: Entering event queue @ 129882835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 130882835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 131882835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 132882835500. Starting simulation... +switching cpus +info: Entering event queue @ 133789085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 134789085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 135789085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 136789085500. Starting simulation... +switching cpus +info: Entering event queue @ 137695335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 138695335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 139695335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 140695335500. Starting simulation... +switching cpus +info: Entering event queue @ 141601585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 142601585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 143601585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 144601585500. Starting simulation... +switching cpus +info: Entering event queue @ 145507835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 146507835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 147507835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 148507835500. Starting simulation... +switching cpus +info: Entering event queue @ 149414085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 150414085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 151414085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 152414085500. Starting simulation... +switching cpus +info: Entering event queue @ 153320335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 154320335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 155320335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 156320335500. Starting simulation... +switching cpus +info: Entering event queue @ 157226585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 158226585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 159226585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 160226585500. Starting simulation... +switching cpus +info: Entering event queue @ 161132835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 162132835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 163132835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 164132835500. Starting simulation... +switching cpus +info: Entering event queue @ 165039085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 166039085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 167039085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 168039085500. Starting simulation... +switching cpus +info: Entering event queue @ 168945335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 169945335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 170945335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 171945335500. Starting simulation... +switching cpus +info: Entering event queue @ 172851585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 173851585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 174851585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 175851585500. Starting simulation... +switching cpus +info: Entering event queue @ 176757835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 177757835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 178757835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 179757835500. Starting simulation... +switching cpus +info: Entering event queue @ 180664085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 181664085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 182664085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 183664085500. Starting simulation... +switching cpus +info: Entering event queue @ 184570335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 185570335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 186570335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 187570335500. Starting simulation... +switching cpus +info: Entering event queue @ 188476585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 189476585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 190476585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 191476585500. Starting simulation... +switching cpus +info: Entering event queue @ 192382835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 193382835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 194382835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 195382835500. Starting simulation... +switching cpus +info: Entering event queue @ 196289085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 197289085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 198289085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 199289085500. Starting simulation... +switching cpus +info: Entering event queue @ 200195335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 201195335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 202195335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 203195335500. Starting simulation... +switching cpus +info: Entering event queue @ 204101585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 205101585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 206101585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 207101585500. Starting simulation... +switching cpus +info: Entering event queue @ 208007835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 209007835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 210007835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 211007835500. Starting simulation... +switching cpus +info: Entering event queue @ 211914085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 212914085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 213914085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 214914085500. Starting simulation... +switching cpus +info: Entering event queue @ 215820335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 216820335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 217820335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 218820335500. Starting simulation... +switching cpus +info: Entering event queue @ 219726585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 220726585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 221726585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 222726585500. Starting simulation... +switching cpus +info: Entering event queue @ 223632835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 224632835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 225632835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 226632835500. Starting simulation... +switching cpus +info: Entering event queue @ 227539085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 228539085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 229539085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 230539085500. Starting simulation... +switching cpus +info: Entering event queue @ 231445335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 232445335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 233445335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 234445335500. Starting simulation... +switching cpus +info: Entering event queue @ 235351585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 236351585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 237351585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 238351585500. Starting simulation... +switching cpus +info: Entering event queue @ 239257835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 240257835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 241257835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 242257835500. Starting simulation... +switching cpus +info: Entering event queue @ 243164085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 244164085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 245164085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 246164085500. Starting simulation... +switching cpus +info: Entering event queue @ 247070335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 248070335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 249070335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 250070335500. Starting simulation... +switching cpus +info: Entering event queue @ 250976585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 251976585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 252976585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 253976585500. Starting simulation... +switching cpus +info: Entering event queue @ 254882835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 255882835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 256882835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 257882835500. Starting simulation... +switching cpus +info: Entering event queue @ 258789085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 259789085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 260789085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 261789085500. Starting simulation... +switching cpus +info: Entering event queue @ 262695335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 263695335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 264695335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 265695335500. Starting simulation... +switching cpus +info: Entering event queue @ 266601585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 267601585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 268601585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 269601585500. Starting simulation... +switching cpus +info: Entering event queue @ 270507835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 271507835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 272507835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 273507835500. Starting simulation... +switching cpus +info: Entering event queue @ 274414085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 275414085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 276414085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 277414085500. Starting simulation... +switching cpus +info: Entering event queue @ 278320335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 279320335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 280320335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 281320335500. Starting simulation... +switching cpus +info: Entering event queue @ 282226585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 283226585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 284226585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 285226585500. Starting simulation... +switching cpus +info: Entering event queue @ 286132835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 287132835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 288132835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 289132835500. Starting simulation... +switching cpus +info: Entering event queue @ 290039085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 291039085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 292039085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 293039085500. Starting simulation... +switching cpus +info: Entering event queue @ 293945335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 294945335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 295945335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 296945335500. Starting simulation... +switching cpus +info: Entering event queue @ 297851585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 298851585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 299851585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 300851585500. Starting simulation... +switching cpus +info: Entering event queue @ 301757835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 302757835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 303757835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 304757835500. Starting simulation... +switching cpus +info: Entering event queue @ 304758059500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 305758059500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 306758059500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 307758059500. Starting simulation... +switching cpus +info: Entering event queue @ 308593773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 309593773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 310593773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 311593773000. Starting simulation... +switching cpus +info: Entering event queue @ 312500023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 313500023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 314500023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 315500023000. Starting simulation... +switching cpus +info: Entering event queue @ 316406273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 317406273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 318406273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 319406273000. Starting simulation... +switching cpus +info: Entering event queue @ 320312523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 321312523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 322312523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 323312523000. Starting simulation... +switching cpus +info: Entering event queue @ 324218773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 325218773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 326218773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 327218773000. Starting simulation... +switching cpus +info: Entering event queue @ 328125023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 329125023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 330125023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 331125023000. Starting simulation... +switching cpus +info: Entering event queue @ 332031273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 333031273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 334031273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 335031273000. Starting simulation... +switching cpus +info: Entering event queue @ 335937523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 336937523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 337937523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 338937523000. Starting simulation... +switching cpus +info: Entering event queue @ 339843773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 340843773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 341843773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 342843773000. Starting simulation... +switching cpus +info: Entering event queue @ 343750023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 344750023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 345750023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 346750023000. Starting simulation... +switching cpus +info: Entering event queue @ 347656273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 348656273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 349656273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 350656273000. Starting simulation... +switching cpus +info: Entering event queue @ 351562523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 352562523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 353562523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 354562523000. Starting simulation... +switching cpus +info: Entering event queue @ 355468773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 356468773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 357468773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 358468773000. Starting simulation... +switching cpus +info: Entering event queue @ 359375023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 360375023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 361375023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 362375023000. Starting simulation... +switching cpus +info: Entering event queue @ 363281273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 364281273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 365281273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 366281273000. Starting simulation... +switching cpus +info: Entering event queue @ 367187523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 368187523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 369187523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 370187523000. Starting simulation... +switching cpus +info: Entering event queue @ 371093773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 372093773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 373093773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 374093773000. Starting simulation... +switching cpus +info: Entering event queue @ 375000023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 376000023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 377000023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 378000023000. Starting simulation... +switching cpus +info: Entering event queue @ 378906273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 379906273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 380906273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 381906273000. Starting simulation... +switching cpus +info: Entering event queue @ 382812523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 383812523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 384812523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 385812523000. Starting simulation... +switching cpus +info: Entering event queue @ 386718773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 387718773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 388718773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 389718773000. Starting simulation... +switching cpus +info: Entering event queue @ 390625023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 391625023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 392625023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 393625023000. Starting simulation... +switching cpus +info: Entering event queue @ 394531273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 395531273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 396531273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 397531273000. Starting simulation... +switching cpus +info: Entering event queue @ 398437523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 399437523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 400437523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 401437523000. Starting simulation... +switching cpus +info: Entering event queue @ 402343773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 403343773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 404343773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 405343773000. Starting simulation... +switching cpus +info: Entering event queue @ 406250023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 407250023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 408250023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 409250023000. Starting simulation... +switching cpus +info: Entering event queue @ 410156273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 411156273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 412156273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 413156273000. Starting simulation... +switching cpus +info: Entering event queue @ 414062523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 415062523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 416062523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 417062523000. Starting simulation... +switching cpus +info: Entering event queue @ 417968773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 418968773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 419968773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 420968773000. Starting simulation... +switching cpus +info: Entering event queue @ 421875023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 422875023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 423875023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 424875023000. Starting simulation... +switching cpus +info: Entering event queue @ 425781273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 426781273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 427781273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 428781273000. Starting simulation... +switching cpus +info: Entering event queue @ 429687523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 430687523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 431687523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 432687523000. Starting simulation... +switching cpus +info: Entering event queue @ 433593773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 434593773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 435593773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 436593773000. Starting simulation... +switching cpus +info: Entering event queue @ 437500023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 438500023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 439500023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 440500023000. Starting simulation... +switching cpus +info: Entering event queue @ 441406273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 442406273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 443406273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 444406273000. Starting simulation... +switching cpus +info: Entering event queue @ 445312523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 446312523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 447312523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 448312523000. Starting simulation... +switching cpus +info: Entering event queue @ 449218773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 450218773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 451218773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 452218773000. Starting simulation... +switching cpus +info: Entering event queue @ 453125023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 454125023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 455125023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 456125023000. Starting simulation... +switching cpus +info: Entering event queue @ 457031273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 458031273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 459031273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 460031273000. Starting simulation... +switching cpus +info: Entering event queue @ 460937523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 461937523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 462937523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 463937523000. Starting simulation... +switching cpus +info: Entering event queue @ 464843773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 465843773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 466843773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 467843773000. Starting simulation... +switching cpus +info: Entering event queue @ 468750023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 469750023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 470750023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 471750023000. Starting simulation... +switching cpus +info: Entering event queue @ 472656273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 473656273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 474656273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 475656273000. Starting simulation... +switching cpus +info: Entering event queue @ 476562523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 477562523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 478562523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 479562523000. Starting simulation... +switching cpus +info: Entering event queue @ 480468773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 481468773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 482468773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 483468773000. Starting simulation... +switching cpus +info: Entering event queue @ 484375023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 485375023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 486375023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 487375023000. Starting simulation... +switching cpus +info: Entering event queue @ 488281273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 489281273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 490281273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 491281273000. Starting simulation... +switching cpus +info: Entering event queue @ 492187523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 493187523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 494187523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 495187523000. Starting simulation... +switching cpus +info: Entering event queue @ 496093773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 497093773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 498093773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 499093773000. Starting simulation... +switching cpus +info: Entering event queue @ 500000023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 501000023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 502000023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 503000023000. Starting simulation... +switching cpus +info: Entering event queue @ 503906273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 504906273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 505906273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 506906273000. Starting simulation... +switching cpus +info: Entering event queue @ 507812523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 508812523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 509812523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 510812523000. Starting simulation... +switching cpus +info: Entering event queue @ 511718773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 512718773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 513718773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 514718773000. Starting simulation... +switching cpus +info: Entering event queue @ 515625023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 516625023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 517625023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 518625023000. Starting simulation... +switching cpus +info: Entering event queue @ 519531273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 520531273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 521531273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 522531273000. Starting simulation... +switching cpus +info: Entering event queue @ 523437523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 524437523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 525437523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 526437523000. Starting simulation... +switching cpus +info: Entering event queue @ 527343773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 528343773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 529343773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 530343773000. Starting simulation... +switching cpus +info: Entering event queue @ 531250023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 532250023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 533250023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 534250023000. Starting simulation... +switching cpus +info: Entering event queue @ 535156273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 536156273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 537156273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 538156273000. Starting simulation... +switching cpus +info: Entering event queue @ 539062523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 540062523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 541062523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 542062523000. Starting simulation... +switching cpus +info: Entering event queue @ 542968773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 543968773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 544968773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 545968773000. Starting simulation... +switching cpus +info: Entering event queue @ 546875023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 547875023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 548875023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 549875023000. Starting simulation... +switching cpus +info: Entering event queue @ 550781273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 551781273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 552781273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 553781273000. Starting simulation... +switching cpus +info: Entering event queue @ 554687523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 555687523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 556687523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 557687523000. Starting simulation... +switching cpus +info: Entering event queue @ 558593773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 559593773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 560593773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 561593773000. Starting simulation... +switching cpus +info: Entering event queue @ 562500023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 563500023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 564500023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 565500023000. Starting simulation... +switching cpus +info: Entering event queue @ 566406273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 567406273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 568406273000. Starting simulation... +switching cpus +info: Entering event queue @ 568406301000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 569406301000. Starting simulation... +switching cpus +info: Entering event queue @ 570312523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 571312523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 572312523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 573312523000. Starting simulation... +switching cpus +info: Entering event queue @ 574218773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 575218773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 576218773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 577218773000. Starting simulation... +switching cpus +info: Entering event queue @ 578125023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 579125023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 580125023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 581125023000. Starting simulation... +switching cpus +info: Entering event queue @ 582031273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 583031273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 584031273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 585031273000. Starting simulation... +switching cpus +info: Entering event queue @ 585937523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 586937523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 587937523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 588937523000. Starting simulation... +switching cpus +info: Entering event queue @ 589843773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 590843773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 591843773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 592843773000. Starting simulation... +switching cpus +info: Entering event queue @ 593750023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 594750023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 595750023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 596750023000. Starting simulation... +switching cpus +info: Entering event queue @ 597656273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 598656273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 599656273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 600656273000. Starting simulation... +switching cpus +info: Entering event queue @ 601562523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 602562523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 603562523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 604562523000. Starting simulation... +switching cpus +info: Entering event queue @ 605468773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 606468773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 607468773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 608468773000. Starting simulation... +switching cpus +info: Entering event queue @ 609375023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 610375023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 611375023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 612375023000. Starting simulation... +switching cpus +info: Entering event queue @ 613281273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 614281273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 615281273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 616281273000. Starting simulation... +switching cpus +info: Entering event queue @ 617187523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 618187523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 619187523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 620187523000. Starting simulation... +switching cpus +info: Entering event queue @ 621093773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 622093773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 623093773000. Starting simulation... +switching cpus +info: Entering event queue @ 623093773500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 624093773500. Starting simulation... +switching cpus +info: Entering event queue @ 624216549000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 625216549000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 626216549000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 627216549000. Starting simulation... +switching cpus +info: Entering event queue @ 627929709000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 628929709000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 629929709000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 630929709000. Starting simulation... +switching cpus +info: Entering event queue @ 631835960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 632835960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 633835960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 634835960500. Starting simulation... +switching cpus +info: Entering event queue @ 635742210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 636742210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 637742210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 638742210500. Starting simulation... +switching cpus +info: Entering event queue @ 639648460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 640648460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 641648460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 642648460500. Starting simulation... +switching cpus +info: Entering event queue @ 643554710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 644554710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 645554710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 646554710500. Starting simulation... +switching cpus +info: Entering event queue @ 647460960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 648460960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 649460960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 650460960500. Starting simulation... +switching cpus +info: Entering event queue @ 651367210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 652367210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 653367210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 654367210500. Starting simulation... +switching cpus +info: Entering event queue @ 655273460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 656273460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 657273460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 658273460500. Starting simulation... +switching cpus +info: Entering event queue @ 659179710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 660179710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 661179710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 662179710500. Starting simulation... +switching cpus +info: Entering event queue @ 663085960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 664085960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 665085960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 666085960500. Starting simulation... +switching cpus +info: Entering event queue @ 666992210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 667992210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 668992210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 669992210500. Starting simulation... +switching cpus +info: Entering event queue @ 670898460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 671898460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 672898460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 673898460500. Starting simulation... +switching cpus +info: Entering event queue @ 674804710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 675804710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 676804710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 677804710500. Starting simulation... +switching cpus +info: Entering event queue @ 678710960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 679710960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 680710960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 681710960500. Starting simulation... +switching cpus +info: Entering event queue @ 682617210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 683617210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 684617210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 685617210500. Starting simulation... +switching cpus +info: Entering event queue @ 686523460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 687523460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 688523460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 689523460500. Starting simulation... +switching cpus +info: Entering event queue @ 690429710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 691429710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 692429710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 693429710500. Starting simulation... +switching cpus +info: Entering event queue @ 694335960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 695335960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 696335960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 697335960500. Starting simulation... +switching cpus +info: Entering event queue @ 698242210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 699242210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 700242210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 701242210500. Starting simulation... +switching cpus +info: Entering event queue @ 702148460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 703148460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 704148460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 705148460500. Starting simulation... +switching cpus +info: Entering event queue @ 706054710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 707054710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 708054710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 709054710500. Starting simulation... +switching cpus +info: Entering event queue @ 709960960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 710960960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 711960960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 712960960500. Starting simulation... +switching cpus +info: Entering event queue @ 713867210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 714867210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 715867210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 716867210500. Starting simulation... +switching cpus +info: Entering event queue @ 717773460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 718773460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 719773460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 720773460500. Starting simulation... +switching cpus +info: Entering event queue @ 721679710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 722679710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 723679710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 724679710500. Starting simulation... +switching cpus +info: Entering event queue @ 725585960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 726585960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 727585960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 728585960500. Starting simulation... +switching cpus +info: Entering event queue @ 729492210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 730492210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 731492210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 732492210500. Starting simulation... +switching cpus +info: Entering event queue @ 733398460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 734398460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 735398460500. Starting simulation... +switching cpus +info: Entering event queue @ 735398461500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 736398461500. Starting simulation... +switching cpus +info: Entering event queue @ 737304710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 738304710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 739304710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 740304710500. Starting simulation... +switching cpus +info: Entering event queue @ 741210960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 742210960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 743210960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 744210960500. Starting simulation... +switching cpus +info: Entering event queue @ 745117210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 746117210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 747117210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 748117210500. Starting simulation... +switching cpus +info: Entering event queue @ 749023460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 750023460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 751023460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 752023460500. Starting simulation... +switching cpus +info: Entering event queue @ 752929710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 753929710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 754929710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 755929710500. Starting simulation... +switching cpus +info: Entering event queue @ 756835960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 757835960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 758835960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 759835960500. Starting simulation... +switching cpus +info: Entering event queue @ 760742210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 761742210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 762742210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 763742210500. Starting simulation... +switching cpus +info: Entering event queue @ 764648460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 765648460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 766648460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 767648460500. Starting simulation... +switching cpus +info: Entering event queue @ 768554710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 769554710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 770554710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 771554710500. Starting simulation... +switching cpus +info: Entering event queue @ 772460960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 773460960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 774460960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 775460960500. Starting simulation... +switching cpus +info: Entering event queue @ 776367210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 777367210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 778367210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 779367210500. Starting simulation... +switching cpus +info: Entering event queue @ 780273460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 781273460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 782273460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 783273460500. Starting simulation... +switching cpus +info: Entering event queue @ 784179710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 785179710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 786179710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 787179710500. Starting simulation... +switching cpus +info: Entering event queue @ 788085960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 789085960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 790085960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 791085960500. Starting simulation... +switching cpus +info: Entering event queue @ 791992210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 792992210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 793992210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 794992210500. Starting simulation... +switching cpus +info: Entering event queue @ 795898460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 796898460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 797898460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 798898460500. Starting simulation... +switching cpus +info: Entering event queue @ 799804710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 800804710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 801804710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 802804710500. Starting simulation... +switching cpus +info: Entering event queue @ 803710960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 804710960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 805710960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 806710960500. Starting simulation... +switching cpus +info: Entering event queue @ 807617210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 808617210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 809617210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 810617210500. Starting simulation... +switching cpus +info: Entering event queue @ 811523460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 812523460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 813523460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 814523460500. Starting simulation... +switching cpus +info: Entering event queue @ 815429710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 816429710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 817429710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 818429710500. Starting simulation... +switching cpus +info: Entering event queue @ 819335960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 820335960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 821335960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 822335960500. Starting simulation... +switching cpus +info: Entering event queue @ 823242210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 824242210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 825242210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 826242210500. Starting simulation... +switching cpus +info: Entering event queue @ 827148460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 828148460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 829148460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 830148460500. Starting simulation... +switching cpus +info: Entering event queue @ 831054710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 832054710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 833054710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 834054710500. Starting simulation... +switching cpus +info: Entering event queue @ 834960960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 835960960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 836960960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 837960960500. Starting simulation... +switching cpus +info: Entering event queue @ 838867210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 839867210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 840867210500. Starting simulation... +switching cpus +info: Entering event queue @ 840867211500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 841867211500. Starting simulation... +switching cpus +info: Entering event queue @ 842773460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 843773460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 844773460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 845773460500. Starting simulation... +switching cpus +info: Entering event queue @ 846679710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 847679710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 848679710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 849679710500. Starting simulation... +switching cpus +info: Entering event queue @ 850585960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 851585960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 852585960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 853585960500. Starting simulation... +switching cpus +info: Entering event queue @ 854492210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 855492210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 856492210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 857492210500. Starting simulation... +switching cpus +info: Entering event queue @ 858398460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 859398460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 860398460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 861398460500. Starting simulation... +switching cpus +info: Entering event queue @ 862304710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 863304710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 864304710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 865304710500. Starting simulation... +switching cpus +info: Entering event queue @ 866210960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 867210960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 868210960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 869210960500. Starting simulation... +switching cpus +info: Entering event queue @ 870117210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 871117210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 872117210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 873117210500. Starting simulation... +switching cpus +info: Entering event queue @ 874023460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 875023460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 876023460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 877023460500. Starting simulation... +switching cpus +info: Entering event queue @ 877929710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 878929710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 879929710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 880929710500. Starting simulation... +switching cpus +info: Entering event queue @ 881835960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 882835960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 883835960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 884835960500. Starting simulation... +switching cpus +info: Entering event queue @ 885742210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 886742210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 887742210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 888742210500. Starting simulation... +switching cpus +info: Entering event queue @ 889648460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 890648460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 891648460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 892648460500. Starting simulation... +switching cpus +info: Entering event queue @ 893554710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 894554710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 895554710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 896554710500. Starting simulation... +switching cpus +info: Entering event queue @ 897460960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 898460960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 899460960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 900460960500. Starting simulation... +switching cpus +info: Entering event queue @ 901367210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 902367210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 903367210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 904367210500. Starting simulation... +switching cpus +info: Entering event queue @ 905273460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 906273460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 907273460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 908273460500. Starting simulation... +switching cpus +info: Entering event queue @ 909179710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 910179710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 911179710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 912179710500. Starting simulation... +switching cpus +info: Entering event queue @ 913085960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 914085960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 915085960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 916085960500. Starting simulation... +switching cpus +info: Entering event queue @ 916992210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 917992210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 918992210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 919992210500. Starting simulation... +switching cpus +info: Entering event queue @ 920898460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 921898460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 922898460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 923898460500. Starting simulation... +switching cpus +info: Entering event queue @ 924804710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 925804710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 926804710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 927804710500. Starting simulation... +switching cpus +info: Entering event queue @ 928710960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 929710960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 930710960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 931710960500. Starting simulation... +switching cpus +info: Entering event queue @ 932617210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 933617210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 934617210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 935617210500. Starting simulation... +switching cpus +info: Entering event queue @ 936523460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 937523460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 938523460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 939523460500. Starting simulation... +switching cpus +info: Entering event queue @ 940429710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 941429710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 942429710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 943429710500. Starting simulation... +switching cpus +info: Entering event queue @ 944335960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 945335960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 946335960500. Starting simulation... +switching cpus +info: Entering event queue @ 946335961500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 947335961500. Starting simulation... +switching cpus +info: Entering event queue @ 948242210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 949242210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 950242210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 951242210500. Starting simulation... +switching cpus +info: Entering event queue @ 952148460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 953148460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 954148460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 955148460500. Starting simulation... +switching cpus +info: Entering event queue @ 956054710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 957054710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 958054710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 959054710500. Starting simulation... +switching cpus +info: Entering event queue @ 959960960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 960960960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 961960960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 962960960500. Starting simulation... +switching cpus +info: Entering event queue @ 963867210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 964867210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 965867210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 966867210500. Starting simulation... +switching cpus +info: Entering event queue @ 967773460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 968773460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 969773460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 970773460500. Starting simulation... +switching cpus +info: Entering event queue @ 971679710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 972679710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 973679710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 974679710500. Starting simulation... +switching cpus +info: Entering event queue @ 975585960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 976585960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 977585960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 978585960500. Starting simulation... +switching cpus +info: Entering event queue @ 979492210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 980492210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 981492210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 982492210500. Starting simulation... +switching cpus +info: Entering event queue @ 983398460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 984398460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 985398460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 986398460500. Starting simulation... +switching cpus +info: Entering event queue @ 987304710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 988304710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 989304710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 990304710500. Starting simulation... +switching cpus +info: Entering event queue @ 991210960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 992210960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 993210960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 994210960500. Starting simulation... +switching cpus +info: Entering event queue @ 995117210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 996117210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 997117210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 998117210500. Starting simulation... +switching cpus +info: Entering event queue @ 999023460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1000023460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1001023460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1002023460500. Starting simulation... +switching cpus +info: Entering event queue @ 1002929710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1003929710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1004929710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1005929710500. Starting simulation... +switching cpus +info: Entering event queue @ 1006835960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1007835960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1008835960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1009835960500. Starting simulation... +switching cpus +info: Entering event queue @ 1010742210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1011742210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1012742210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1013742210500. Starting simulation... +switching cpus +info: Entering event queue @ 1014648460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1015648460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1016648460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1017648460500. Starting simulation... +switching cpus +info: Entering event queue @ 1018554710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1019554710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1020554710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1021554710500. Starting simulation... +switching cpus +info: Entering event queue @ 1022460960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1023460960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1024460960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1025460960500. Starting simulation... +switching cpus +info: Entering event queue @ 1026367210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1027367210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1028367210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1029367210500. Starting simulation... +switching cpus +info: Entering event queue @ 1030273460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1031273460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1032273460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1033273460500. Starting simulation... +switching cpus +info: Entering event queue @ 1034179710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1035179710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1036179710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1037179710500. Starting simulation... +switching cpus +info: Entering event queue @ 1038085960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1039085960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1040085960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1041085960500. Starting simulation... +switching cpus +info: Entering event queue @ 1041992210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1042992210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1043992210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1044992210500. Starting simulation... +switching cpus +info: Entering event queue @ 1045898460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1046898460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1047898460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1048898460500. Starting simulation... +switching cpus +info: Entering event queue @ 1049804710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1050804710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1051804710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1052804710500. Starting simulation... +switching cpus +info: Entering event queue @ 1053710960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1054710960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1055710960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1056710960500. Starting simulation... +switching cpus +info: Entering event queue @ 1057617210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1058617210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1059617210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1060617210500. Starting simulation... +switching cpus +info: Entering event queue @ 1061523460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1062523460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1063523460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1064523460500. Starting simulation... +switching cpus +info: Entering event queue @ 1065429710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1066429710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1067429710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1068429710500. Starting simulation... +switching cpus +info: Entering event queue @ 1069335960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1070335960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1071335960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1072335960500. Starting simulation... +switching cpus +info: Entering event queue @ 1073242210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1074242210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1075242210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1076242210500. Starting simulation... +switching cpus +info: Entering event queue @ 1077148460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1078148460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1079148460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1080148460500. Starting simulation... +switching cpus +info: Entering event queue @ 1081054710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1082054710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1083054710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1084054710500. Starting simulation... +switching cpus +info: Entering event queue @ 1084960960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1085960960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1086960960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1087960960500. Starting simulation... +switching cpus +info: Entering event queue @ 1088867210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1089867210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1090867210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1091867210500. Starting simulation... +switching cpus +info: Entering event queue @ 1092773460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1093773460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1094773460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1095773460500. Starting simulation... +switching cpus +info: Entering event queue @ 1096679710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1097679710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1098679710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1099679710500. Starting simulation... +switching cpus +info: Entering event queue @ 1100585960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1101585960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1102585960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1103585960500. Starting simulation... +switching cpus +info: Entering event queue @ 1104492210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1105492210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1106492210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1107492210500. Starting simulation... +switching cpus +info: Entering event queue @ 1108398460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1109398460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1110398460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1111398460500. Starting simulation... +switching cpus +info: Entering event queue @ 1112304710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1113304710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1114304710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1115304710500. Starting simulation... +switching cpus +info: Entering event queue @ 1116210960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1117210960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1118210960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1119210960500. Starting simulation... +switching cpus +info: Entering event queue @ 1120117210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1121117210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1122117210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1123117210500. Starting simulation... +switching cpus +info: Entering event queue @ 1124023460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1125023460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1126023460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1127023460500. Starting simulation... +switching cpus +info: Entering event queue @ 1127929710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1128929710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1129929710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1130929710500. Starting simulation... +switching cpus +info: Entering event queue @ 1131835960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1132835960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1133835960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1134835960500. Starting simulation... +switching cpus +info: Entering event queue @ 1135742210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1136742210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1137742210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1138742210500. Starting simulation... +switching cpus +info: Entering event queue @ 1139648460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1140648460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1141648460500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1142648460500. Starting simulation... +switching cpus +info: Entering event queue @ 1143554710500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1144554710500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1145554710500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1146554710500. Starting simulation... +switching cpus +info: Entering event queue @ 1147460960500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1148460960500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1149460960500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1150460960500. Starting simulation... +switching cpus +info: Entering event queue @ 1151367210500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1152367210500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1153367210500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1154367210500. Starting simulation... +switching cpus +info: Entering event queue @ 1155273460500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1156273460500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 1157273460500. Starting simulation... +switching cpus +info: Entering event queue @ 1157273461500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1158273461500. Starting simulation... +switching cpus +info: Entering event queue @ 1159361690000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1160361690000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1161361690000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1162361690000. Starting simulation... +switching cpus +info: Entering event queue @ 1162361693000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1163361693000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1164361693000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1165361693000. Starting simulation... +switching cpus +info: Entering event queue @ 1165361696000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1166361696000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1167361696000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1168361696000. Starting simulation... +switching cpus +info: Entering event queue @ 1168945335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1169945335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1170945335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1171945335500. Starting simulation... +switching cpus +info: Entering event queue @ 1172851585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1173851585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1174851585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1175851585500. Starting simulation... +switching cpus +info: Entering event queue @ 1176757835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1177757835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1178757835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1179757835500. Starting simulation... +switching cpus +info: Entering event queue @ 1180664085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1181664085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1182664085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1183664085500. Starting simulation... +switching cpus +info: Entering event queue @ 1184570335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1185570335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1186570335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1187570335500. Starting simulation... +switching cpus +info: Entering event queue @ 1188476585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1189476585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1190476585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1191476585500. Starting simulation... +switching cpus +info: Entering event queue @ 1192382835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1193382835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1194382835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1195382835500. Starting simulation... +switching cpus +info: Entering event queue @ 1196289085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1197289085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1198289085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1199289085500. Starting simulation... +switching cpus +info: Entering event queue @ 1200195335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1201195335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1202195335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1203195335500. Starting simulation... +switching cpus +info: Entering event queue @ 1204101585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1205101585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1206101585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1207101585500. Starting simulation... +switching cpus +info: Entering event queue @ 1208007835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1209007835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1210007835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1211007835500. Starting simulation... +switching cpus +info: Entering event queue @ 1211914085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1212914085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1213914085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1214914085500. Starting simulation... +switching cpus +info: Entering event queue @ 1215820335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1216820335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1217820335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1218820335500. Starting simulation... +switching cpus +info: Entering event queue @ 1219726585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1220726585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1221726585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1222726585500. Starting simulation... +switching cpus +info: Entering event queue @ 1223632835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1224632835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1225632835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1226632835500. Starting simulation... +switching cpus +info: Entering event queue @ 1227539085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1228539085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1229539085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1230539085500. Starting simulation... +switching cpus +info: Entering event queue @ 1231445335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1232445335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1233445335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1234445335500. Starting simulation... +switching cpus +info: Entering event queue @ 1235351585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1236351585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1237351585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1238351585500. Starting simulation... +switching cpus +info: Entering event queue @ 1239257835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1240257835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1241257835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1242257835500. Starting simulation... +switching cpus +info: Entering event queue @ 1243164085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1244164085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1245164085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1246164085500. Starting simulation... +switching cpus +info: Entering event queue @ 1247070335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1248070335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1249070335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1250070335500. Starting simulation... +switching cpus +info: Entering event queue @ 1250976585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1251976585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1252976585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1253976585500. Starting simulation... +switching cpus +info: Entering event queue @ 1254882835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1255882835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1256882835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1257882835500. Starting simulation... +switching cpus +info: Entering event queue @ 1258789085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1259789085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1260789085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1261789085500. Starting simulation... +switching cpus +info: Entering event queue @ 1262695335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1263695335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1264695335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1265695335500. Starting simulation... +switching cpus +info: Entering event queue @ 1266601585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1267601585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1268601585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1269601585500. Starting simulation... +switching cpus +info: Entering event queue @ 1270507835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1271507835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1272507835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1273507835500. Starting simulation... +switching cpus +info: Entering event queue @ 1274414085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1275414085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1276414085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1277414085500. Starting simulation... +switching cpus +info: Entering event queue @ 1278320335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1279320335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1280320335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1281320335500. Starting simulation... +switching cpus +info: Entering event queue @ 1282226585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1283226585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1284226585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1285226585500. Starting simulation... +switching cpus +info: Entering event queue @ 1286132835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1287132835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1288132835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1289132835500. Starting simulation... +switching cpus +info: Entering event queue @ 1290039085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1291039085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1292039085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1293039085500. Starting simulation... +switching cpus +info: Entering event queue @ 1293945335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1294945335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1295945335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1296945335500. Starting simulation... +switching cpus +info: Entering event queue @ 1297851585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1298851585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1299851585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1300851585500. Starting simulation... +switching cpus +info: Entering event queue @ 1301757835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1302757835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1303757835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1304757835500. Starting simulation... +switching cpus +info: Entering event queue @ 1305664085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1306664085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1307664085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1308664085500. Starting simulation... +switching cpus +info: Entering event queue @ 1309570335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1310570335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1311570335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1312570335500. Starting simulation... +switching cpus +info: Entering event queue @ 1313476585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1314476585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1315476585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1316476585500. Starting simulation... +switching cpus +info: Entering event queue @ 1317382835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1318382835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1319382835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1320382835500. Starting simulation... +switching cpus +info: Entering event queue @ 1321289085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1322289085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1323289085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1324289085500. Starting simulation... +switching cpus +info: Entering event queue @ 1325195335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1326195335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1327195335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1328195335500. Starting simulation... +switching cpus +info: Entering event queue @ 1329101585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1330101585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1331101585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1332101585500. Starting simulation... +switching cpus +info: Entering event queue @ 1333007835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1334007835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1335007835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1336007835500. Starting simulation... +switching cpus +info: Entering event queue @ 1336914085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1337914085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1338914085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1339914085500. Starting simulation... +switching cpus +info: Entering event queue @ 1340820335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1341820335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1342820335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1343820335500. Starting simulation... +switching cpus +info: Entering event queue @ 1344726585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1345726585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1346726585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1347726585500. Starting simulation... +switching cpus +info: Entering event queue @ 1348632835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1349632835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1350632835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1351632835500. Starting simulation... +switching cpus +info: Entering event queue @ 1352539085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1353539085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1354539085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1355539085500. Starting simulation... +switching cpus +info: Entering event queue @ 1356445335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1357445335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1358445335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1359445335500. Starting simulation... +switching cpus +info: Entering event queue @ 1360351585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1361351585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1362351585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1363351585500. Starting simulation... +switching cpus +info: Entering event queue @ 1364257835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1365257835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1366257835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1367257835500. Starting simulation... +switching cpus +info: Entering event queue @ 1368164085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1369164085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1370164085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1371164085500. Starting simulation... +switching cpus +info: Entering event queue @ 1372070335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1373070335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1374070335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1375070335500. Starting simulation... +switching cpus +info: Entering event queue @ 1375976585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1376976585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1377976585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1378976585500. Starting simulation... +switching cpus +info: Entering event queue @ 1379882835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1380882835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1381882835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1382882835500. Starting simulation... +switching cpus +info: Entering event queue @ 1383789085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1384789085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1385789085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1386789085500. Starting simulation... +switching cpus +info: Entering event queue @ 1387695335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1388695335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1389695335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1390695335500. Starting simulation... +switching cpus +info: Entering event queue @ 1391601585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1392601585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1393601585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1394601585500. Starting simulation... +switching cpus +info: Entering event queue @ 1395507835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1396507835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1397507835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1398507835500. Starting simulation... +switching cpus +info: Entering event queue @ 1399414085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1400414085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1401414085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1402414085500. Starting simulation... +switching cpus +info: Entering event queue @ 1403320335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1404320335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1405320335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1406320335500. Starting simulation... +switching cpus +info: Entering event queue @ 1407226585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1408226585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1409226585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1410226585500. Starting simulation... +switching cpus +info: Entering event queue @ 1411132835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1412132835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1413132835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1414132835500. Starting simulation... +switching cpus +info: Entering event queue @ 1415039085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1416039085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1417039085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1418039085500. Starting simulation... +switching cpus +info: Entering event queue @ 1418945335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1419945335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1420945335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1421945335500. Starting simulation... +switching cpus +info: Entering event queue @ 1422851585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1423851585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1424851585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1425851585500. Starting simulation... +switching cpus +info: Entering event queue @ 1426757835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1427757835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1428757835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1429757835500. Starting simulation... +switching cpus +info: Entering event queue @ 1430664085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1431664085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1432664085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1433664085500. Starting simulation... +switching cpus +info: Entering event queue @ 1434570335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1435570335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1436570335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1437570335500. Starting simulation... +switching cpus +info: Entering event queue @ 1438476585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1439476585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1440476585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1441476585500. Starting simulation... +switching cpus +info: Entering event queue @ 1442382835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1443382835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1444382835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1445382835500. Starting simulation... +switching cpus +info: Entering event queue @ 1446289085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1447289085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1448289085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1449289085500. Starting simulation... +switching cpus +info: Entering event queue @ 1450195335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1451195335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1452195335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1453195335500. Starting simulation... +switching cpus +info: Entering event queue @ 1454101585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1455101585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1456101585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1457101585500. Starting simulation... +switching cpus +info: Entering event queue @ 1458007835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1459007835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1460007835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1461007835500. Starting simulation... +switching cpus +info: Entering event queue @ 1461914085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1462914085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1463914085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1464914085500. Starting simulation... +switching cpus +info: Entering event queue @ 1465820335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1466820335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1467820335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1468820335500. Starting simulation... +switching cpus +info: Entering event queue @ 1469726585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1470726585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1471726585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1472726585500. Starting simulation... +switching cpus +info: Entering event queue @ 1473632835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1474632835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1475632835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1476632835500. Starting simulation... +switching cpus +info: Entering event queue @ 1477539085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1478539085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1479539085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1480539085500. Starting simulation... +switching cpus +info: Entering event queue @ 1481445335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1482445335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1483445335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1484445335500. Starting simulation... +switching cpus +info: Entering event queue @ 1485351585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1486351585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1487351585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1488351585500. Starting simulation... +switching cpus +info: Entering event queue @ 1489257835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1490257835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1491257835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1492257835500. Starting simulation... +switching cpus +info: Entering event queue @ 1493164085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1494164085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1495164085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1496164085500. Starting simulation... +switching cpus +info: Entering event queue @ 1497070335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1498070335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1499070335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1500070335500. Starting simulation... +switching cpus +info: Entering event queue @ 1500976585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1501976585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1502976585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1503976585500. Starting simulation... +switching cpus +info: Entering event queue @ 1504882835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1505882835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1506882835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1507882835500. Starting simulation... +switching cpus +info: Entering event queue @ 1508789085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1509789085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1510789085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1511789085500. Starting simulation... +switching cpus +info: Entering event queue @ 1512695335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1513695335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1514695335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1515695335500. Starting simulation... +switching cpus +info: Entering event queue @ 1516601585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1517601585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1518601585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1519601585500. Starting simulation... +switching cpus +info: Entering event queue @ 1520507835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1521507835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1522507835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1523507835500. Starting simulation... +switching cpus +info: Entering event queue @ 1524414085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1525414085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1526414085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1527414085500. Starting simulation... +switching cpus +info: Entering event queue @ 1528320335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1529320335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1530320335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1531320335500. Starting simulation... +switching cpus +info: Entering event queue @ 1532226585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1533226585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1534226585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1535226585500. Starting simulation... +switching cpus +info: Entering event queue @ 1536132835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1537132835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1538132835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1539132835500. Starting simulation... +switching cpus +info: Entering event queue @ 1540039085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1541039085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1542039085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1543039085500. Starting simulation... +switching cpus +info: Entering event queue @ 1543945335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1544945335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1545945335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1546945335500. Starting simulation... +switching cpus +info: Entering event queue @ 1547851585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1548851585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1549851585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1550851585500. Starting simulation... +switching cpus +info: Entering event queue @ 1551757835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1552757835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1553757835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1554757835500. Starting simulation... +switching cpus +info: Entering event queue @ 1555664085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1556664085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1557664085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1558664085500. Starting simulation... +switching cpus +info: Entering event queue @ 1559570335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1560570335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1561570335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1562570335500. Starting simulation... +switching cpus +info: Entering event queue @ 1563476585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1564476585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1565476585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1566476585500. Starting simulation... +switching cpus +info: Entering event queue @ 1567382835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1568382835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1569382835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1570382835500. Starting simulation... +switching cpus +info: Entering event queue @ 1571289085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1572289085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1573289085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1574289085500. Starting simulation... +switching cpus +info: Entering event queue @ 1575195335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1576195335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1577195335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1578195335500. Starting simulation... +switching cpus +info: Entering event queue @ 1579101585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1580101585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1581101585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1582101585500. Starting simulation... +switching cpus +info: Entering event queue @ 1583007835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1584007835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1585007835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1586007835500. Starting simulation... +switching cpus +info: Entering event queue @ 1586914085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1587914085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1588914085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1589914085500. Starting simulation... +switching cpus +info: Entering event queue @ 1590820335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1591820335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1592820335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1593820335500. Starting simulation... +switching cpus +info: Entering event queue @ 1594726585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1595726585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1596726585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1597726585500. Starting simulation... +switching cpus +info: Entering event queue @ 1598632835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1599632835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1600632835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1601632835500. Starting simulation... +switching cpus +info: Entering event queue @ 1602539085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1603539085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1604539085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1605539085500. Starting simulation... +switching cpus +info: Entering event queue @ 1606445335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1607445335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1608445335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1609445335500. Starting simulation... +switching cpus +info: Entering event queue @ 1610351585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1611351585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1612351585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1613351585500. Starting simulation... +switching cpus +info: Entering event queue @ 1614257835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1615257835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1616257835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1617257835500. Starting simulation... +switching cpus +info: Entering event queue @ 1618164085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1619164085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1620164085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1621164085500. Starting simulation... +switching cpus +info: Entering event queue @ 1622070335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1623070335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1624070335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1625070335500. Starting simulation... +switching cpus +info: Entering event queue @ 1625976585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1626976585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1627976585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1628976585500. Starting simulation... +switching cpus +info: Entering event queue @ 1629882835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1630882835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1631882835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1632882835500. Starting simulation... +switching cpus +info: Entering event queue @ 1633789085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1634789085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1635789085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1636789085500. Starting simulation... +switching cpus +info: Entering event queue @ 1637695335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1638695335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1639695335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1640695335500. Starting simulation... +switching cpus +info: Entering event queue @ 1641601585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1642601585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1643601585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1644601585500. Starting simulation... +switching cpus +info: Entering event queue @ 1645507835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1646507835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1647507835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1648507835500. Starting simulation... +switching cpus +info: Entering event queue @ 1649414085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1650414085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1651414085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1652414085500. Starting simulation... +switching cpus +info: Entering event queue @ 1653320335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1654320335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1655320335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1656320335500. Starting simulation... +switching cpus +info: Entering event queue @ 1657226585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1658226585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1659226585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1660226585500. Starting simulation... +switching cpus +info: Entering event queue @ 1661132835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1662132835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1663132835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1664132835500. Starting simulation... +switching cpus +info: Entering event queue @ 1665039085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1666039085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1667039085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1668039085500. Starting simulation... +switching cpus +info: Entering event queue @ 1668945335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1669945335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1670945335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1671945335500. Starting simulation... +switching cpus +info: Entering event queue @ 1672851585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1673851585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1674851585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1675851585500. Starting simulation... +switching cpus +info: Entering event queue @ 1676757835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1677757835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1678757835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1679757835500. Starting simulation... +switching cpus +info: Entering event queue @ 1680664085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1681664085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1682664085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1683664085500. Starting simulation... +switching cpus +info: Entering event queue @ 1684570335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1685570335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1686570335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1687570335500. Starting simulation... +switching cpus +info: Entering event queue @ 1688476585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1689476585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1690476585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1691476585500. Starting simulation... +switching cpus +info: Entering event queue @ 1692382835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1693382835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 1694382835500. Starting simulation... +switching cpus +info: Entering event queue @ 1694382836500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1695382836500. Starting simulation... +switching cpus +info: Entering event queue @ 1696289085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1697289085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1698289085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1699289085500. Starting simulation... +switching cpus +info: Entering event queue @ 1700195335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1701195335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1702195335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1703195335500. Starting simulation... +switching cpus +info: Entering event queue @ 1704101585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1705101585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 1706101585500. Starting simulation... +switching cpus +info: Entering event queue @ 1706101586500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1707101586500. Starting simulation... +switching cpus +info: Entering event queue @ 1708007835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1709007835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1710007835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1711007835500. Starting simulation... +switching cpus +info: Entering event queue @ 1711914085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1712914085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1713914085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1714914085500. Starting simulation... +switching cpus +info: Entering event queue @ 1715820335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1716820335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1717820335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1718820335500. Starting simulation... +switching cpus +info: Entering event queue @ 1719726585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1720726585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1721726585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1722726585500. Starting simulation... +switching cpus +info: Entering event queue @ 1723632835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1724632835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1725632835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1726632835500. Starting simulation... +switching cpus +info: Entering event queue @ 1727539085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1728539085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1729539085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1730539085500. Starting simulation... +switching cpus +info: Entering event queue @ 1731445335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1732445335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1733445335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1734445335500. Starting simulation... +switching cpus +info: Entering event queue @ 1735351585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1736351585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1737351585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1738351585500. Starting simulation... +switching cpus +info: Entering event queue @ 1739257835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1740257835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1741257835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1742257835500. Starting simulation... +switching cpus +info: Entering event queue @ 1743164085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1744164085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1745164085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1746164085500. Starting simulation... +switching cpus +info: Entering event queue @ 1747070335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1748070335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1749070335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1750070335500. Starting simulation... +switching cpus +info: Entering event queue @ 1750976585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1751976585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1752976585500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1753976585500. Starting simulation... +switching cpus +info: Entering event queue @ 1754882835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1755882835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 1756882835500. Starting simulation... +switching cpus +info: Entering event queue @ 1756882836500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1757882836500. Starting simulation... +switching cpus +info: Entering event queue @ 1758789085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1759789085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1760789085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1761789085500. Starting simulation... +switching cpus +info: Entering event queue @ 1762695335500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1763695335500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1764695335500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1765695335500. Starting simulation... +switching cpus +info: Entering event queue @ 1766601585500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1767601585500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 1768601585500. Starting simulation... +switching cpus +info: Entering event queue @ 1768601586500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1769601586500. Starting simulation... +switching cpus +info: Entering event queue @ 1770507835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1771507835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1772507835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1773507835500. Starting simulation... +switching cpus +info: Entering event queue @ 1774414085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1775414085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1776414085500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1777414085500. Starting simulation... +switching cpus +info: Entering event queue @ 1777414489000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1778414489000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1779414489000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1780414489000. Starting simulation... +switching cpus +info: Entering event queue @ 1781250023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1782250023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 1783250023000. Starting simulation... +switching cpus +info: Entering event queue @ 1783250024000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1784250024000. Starting simulation... +switching cpus +info: Entering event queue @ 1785156273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1786156273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1787156273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1788156273000. Starting simulation... +switching cpus +info: Entering event queue @ 1789062523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1790062523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1791062523000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1792062523000. Starting simulation... +switching cpus +info: Entering event queue @ 1792968773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1793968773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 1794968773000. Starting simulation... +switching cpus +info: Entering event queue @ 1794968774000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1795968774000. Starting simulation... +switching cpus +info: Entering event queue @ 1796875023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1797875023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1798875023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1799875023000. Starting simulation... +switching cpus +info: Entering event queue @ 1800781273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1801781273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1802781273000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1803781273000. Starting simulation... +switching cpus +info: Entering event queue @ 1804687523000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1805687523000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 1806687523000. Starting simulation... +switching cpus +info: Entering event queue @ 1806687524000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1807687524000. Starting simulation... +switching cpus +info: Entering event queue @ 1808593773000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1809593773000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1810593773000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1811593773000. Starting simulation... +switching cpus +info: Entering event queue @ 1812500023000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1813500023000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1814500023000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1815500023000. Starting simulation... +switching cpus +info: Entering event queue @ 1816406273000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1817406273000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 1818406273000. Starting simulation... +switching cpus +info: Entering event queue @ 1818406274000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1819406274000. Starting simulation... +switching cpus +info: Entering event queue @ 1819406280500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1820406280500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 1821406280500. Starting simulation... +switching cpus +info: Entering event queue @ 1821406281500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1822406281500. Starting simulation... +info: Entering event queue @ 1822406288500. Starting simulation... +switching cpus +info: Entering event queue @ 1822406293000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1823406293000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1824406293000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1825406293000. Starting simulation... +switching cpus +info: Entering event queue @ 1826171898000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1827171898000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1828171898000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1829171898000. Starting simulation... +info: Entering event queue @ 1829171911500. Starting simulation... +info: Entering event queue @ 1829171916500. Starting simulation... +switching cpus +info: Entering event queue @ 1829171921000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1830171921000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 1831171921000. Starting simulation... +switching cpus +info: Entering event queue @ 1831171922000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1832171922000. Starting simulation... +switching cpus +info: Entering event queue @ 1833007835500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1834007835500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1835007835500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1836007835500. Starting simulation... +switching cpus +info: Entering event queue @ 1836914085500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1837914085500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 1838914085500. Starting simulation... +switching cpus +info: Entering event queue @ 1838914086500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1839914086500. Starting simulation... +switching cpus +info: Entering event queue @ 1839914091000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1840914091000. Starting simulation... diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt new file mode 100644 index 000000000..1c485a623 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -0,0 +1,1554 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 1.841682 # Number of seconds simulated +sim_ticks 1841681669500 # Number of ticks simulated +final_tick 1841681669500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 340900 # Simulator instruction rate (inst/s) +host_op_rate 340900 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9082220288 # Simulator tick rate (ticks/s) +host_mem_usage 309920 # Number of bytes of host memory used +host_seconds 202.78 # Real time elapsed on the host +sim_insts 69127289 # Number of instructions simulated +sim_ops 69127289 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 474944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19316864 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 149888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2832832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 295936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2722176 # Number of bytes read from this memory +system.physmem.bytes_read::total 28444928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 474944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 149888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 295936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 920768 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7479680 # Number of bytes written to this memory +system.physmem.bytes_written::total 7479680 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7421 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 301826 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2342 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 44263 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4624 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 42534 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444452 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116870 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116870 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 257886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10488709 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1440145 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 81386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1538177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 160688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1478093 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15445084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 257886 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 81386 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 160688 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 499960 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4061332 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4061332 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4061332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 257886 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10488709 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1440145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 81386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1538177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 160688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1478093 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19506416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 111038 # Total number of read requests seen +system.physmem.writeReqs 46173 # Total number of write requests seen +system.physmem.cpureqs 157553 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 7106432 # Total number of bytes read from memory +system.physmem.bytesWritten 2955072 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 7106432 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2955072 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 7 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 41 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 7075 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6835 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6921 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6580 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 7013 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 7160 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 7199 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 7176 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 6821 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6547 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 6956 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 7030 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 7021 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 7068 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6779 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6850 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 3087 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2885 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2926 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2583 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2986 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 3014 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 3032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2994 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 2761 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2529 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 2745 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2938 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 3117 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 3088 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2763 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2725 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 141 # Number of times wr buffer was full causing retry +system.physmem.totGap 1840669582000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 111038 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # 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average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175767.095395 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 175767.095395 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. +system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_txs 395 # Number of DMA write transactions. +system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. +system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. +system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.cpu0.dtb.fetch_hits 0 # ITB hits +system.cpu0.dtb.fetch_misses 0 # ITB misses +system.cpu0.dtb.fetch_acv 0 # ITB acv +system.cpu0.dtb.fetch_accesses 0 # ITB accesses +system.cpu0.dtb.read_hits 4863195 # DTB read hits +system.cpu0.dtb.read_misses 5912 # DTB read misses +system.cpu0.dtb.read_acv 109 # DTB read access violations +system.cpu0.dtb.read_accesses 426831 # DTB read accesses +system.cpu0.dtb.write_hits 3494205 # DTB write hits +system.cpu0.dtb.write_misses 658 # DTB write misses +system.cpu0.dtb.write_acv 81 # DTB write access violations +system.cpu0.dtb.write_accesses 163149 # DTB write accesses +system.cpu0.dtb.data_hits 8357400 # DTB hits +system.cpu0.dtb.data_misses 6570 # DTB misses +system.cpu0.dtb.data_acv 190 # DTB access violations +system.cpu0.dtb.data_accesses 589980 # DTB accesses +system.cpu0.itb.fetch_hits 2736814 # ITB hits +system.cpu0.itb.fetch_misses 2973 # ITB misses +system.cpu0.itb.fetch_acv 97 # ITB acv +system.cpu0.itb.fetch_accesses 2739787 # ITB accesses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.read_acv 0 # DTB read access violations +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.write_acv 0 # DTB write access violations +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.data_hits 0 # DTB hits +system.cpu0.itb.data_misses 0 # DTB misses +system.cpu0.itb.data_acv 0 # DTB access violations +system.cpu0.itb.data_accesses 0 # DTB accesses +system.cpu0.numCycles 928581953 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 32231633 # Number of instructions committed +system.cpu0.committedOps 32231633 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 30115221 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 167520 # Number of float alu accesses +system.cpu0.num_func_calls 807051 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4228078 # number of instructions that are conditional controls +system.cpu0.num_int_insts 30115221 # number of integer instructions +system.cpu0.num_fp_insts 167520 # number of float instructions +system.cpu0.num_int_register_reads 41941415 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22024555 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 86513 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 88077 # number of times the floating registers were written +system.cpu0.num_mem_refs 8386802 # number of memory refs +system.cpu0.num_load_insts 4883995 # Number of load instructions +system.cpu0.num_store_insts 3502807 # Number of store instructions +system.cpu0.num_idle_cycles 214040611553.999786 # Number of idle cycles +system.cpu0.num_busy_cycles -213112029600.999786 # Number of busy cycles +system.cpu0.not_idle_fraction -229.502661 # Percentage of non-idle cycles +system.cpu0.idle_fraction 230.502661 # Percentage of idle cycles +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 6419 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211372 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74800 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105685 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182566 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73433 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73433 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148947 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818611622000 98.75% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39272500 0.00% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 363381500 0.02% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22666637000 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841680913000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694829 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815853 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed +system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed +system.cpu0.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed +system.cpu0.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed +system.cpu0.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed +system.cpu0.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed +system.cpu0.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed +system.cpu0.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed +system.cpu0.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed +system.cpu0.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed +system.cpu0.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed +system.cpu0.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed +system.cpu0.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed +system.cpu0.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed +system.cpu0.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed +system.cpu0.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed +system.cpu0.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed +system.cpu0.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed +system.cpu0.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed +system.cpu0.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed +system.cpu0.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 326 # number of syscalls executed +system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4175 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175309 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed +system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed +system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 192221 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1736 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1905 +system.cpu0.kern.mode_good::user 1736 +system.cpu0.kern.mode_good::idle 169 +system.cpu0.kern.mode_switch_good::kernel 0.321682 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.390689 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29776947000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2543344500 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809360618000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4176 # number of times the context was actually changed +system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR +system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +system.tsunami.ethernet.droppedPackets 0 # number of packets dropped +system.cpu0.icache.replacements 954146 # number of replacements +system.cpu0.icache.tagsinuse 511.198138 # Cycle average of tags in use +system.cpu0.icache.total_refs 41733941 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 954657 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 43.716163 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 10235539000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 257.559886 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 79.204756 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 174.433495 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.503047 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.154697 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.340690 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998434 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 31717072 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7719142 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2297727 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 41733941 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31717072 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7719142 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2297727 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 41733941 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31717072 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7719142 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2297727 # number of overall hits +system.cpu0.icache.overall_hits::total 41733941 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 521321 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 129232 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 321175 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 971728 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 521321 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 129232 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 321175 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 971728 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 521321 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 129232 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 321175 # number of overall misses +system.cpu0.icache.overall_misses::total 971728 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1794278000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4429709988 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6223987988 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1794278000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4429709988 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6223987988 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1794278000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4429709988 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6223987988 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32238393 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7848374 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2618902 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 42705669 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32238393 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7848374 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2618902 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 42705669 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32238393 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7848374 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2618902 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 42705669 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016171 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016466 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122637 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.022754 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016171 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016466 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122637 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.022754 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016171 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016466 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122637 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.022754 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13884.161818 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13792.200476 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6405.072189 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13884.161818 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13792.200476 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6405.072189 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13884.161818 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13792.200476 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6405.072189 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1920 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 179 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 117 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.410256 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 179 # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16896 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16896 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16896 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16896 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16896 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16896 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 129232 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 304279 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 433511 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 129232 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 304279 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 433511 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 129232 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 304279 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 433511 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1535814000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3651354490 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5187168490 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1535814000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3651354490 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5187168490 # 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number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2301660126 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3623191126 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24769500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 70346000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95115500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3275303000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6597259126 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9872562126 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3275303000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6597259126 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9872562126 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 289521000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 340019500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 629540500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 358537000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 415967500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 774504500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 648058000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 755987000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1404045000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086324 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088326 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041052 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053132 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045342 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021658 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102147 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.097682 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037926 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072034 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071711 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033139 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072034 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071711 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033139 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18853.343626 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16356.086510 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17062.663135 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27406.283700 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27093.973302 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27207.058038 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11218.070652 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12702.419646 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12279.305448 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21569.331577 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18980.494118 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19767.619803 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21569.331577 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18980.494118 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19767.619803 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dtb.fetch_hits 0 # ITB hits +system.cpu1.dtb.fetch_misses 0 # ITB misses +system.cpu1.dtb.fetch_acv 0 # ITB acv +system.cpu1.dtb.fetch_accesses 0 # ITB accesses +system.cpu1.dtb.read_hits 1219761 # DTB read hits +system.cpu1.dtb.read_misses 1488 # DTB read misses +system.cpu1.dtb.read_acv 40 # DTB read access violations +system.cpu1.dtb.read_accesses 143779 # DTB read accesses +system.cpu1.dtb.write_hits 929431 # DTB write hits +system.cpu1.dtb.write_misses 201 # DTB write misses +system.cpu1.dtb.write_acv 24 # DTB write access violations +system.cpu1.dtb.write_accesses 59743 # DTB write accesses +system.cpu1.dtb.data_hits 2149192 # DTB hits +system.cpu1.dtb.data_misses 1689 # DTB misses +system.cpu1.dtb.data_acv 64 # DTB access violations +system.cpu1.dtb.data_accesses 203522 # DTB accesses +system.cpu1.itb.fetch_hits 873235 # ITB hits +system.cpu1.itb.fetch_misses 756 # ITB misses +system.cpu1.itb.fetch_acv 43 # ITB acv +system.cpu1.itb.fetch_accesses 873991 # ITB accesses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.read_acv 0 # DTB read access violations +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.write_acv 0 # DTB write access violations +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.data_hits 0 # DTB hits +system.cpu1.itb.data_misses 0 # DTB misses +system.cpu1.itb.data_acv 0 # DTB access violations +system.cpu1.itb.data_accesses 0 # DTB accesses +system.cpu1.numCycles 953535739 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 7846620 # Number of instructions committed +system.cpu1.committedOps 7846620 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7299077 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45739 # Number of float alu accesses +system.cpu1.num_func_calls 212215 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 957639 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7299077 # number of integer instructions +system.cpu1.num_fp_insts 45739 # number of float instructions +system.cpu1.num_int_register_reads 10142741 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5309758 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24689 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24953 # number of times the floating registers were written +system.cpu1.num_mem_refs 2156913 # number of memory refs +system.cpu1.num_load_insts 1225031 # Number of load instructions +system.cpu1.num_store_insts 931882 # Number of store instructions +system.cpu1.num_idle_cycles -1658749274.077502 # Number of idle cycles +system.cpu1.num_busy_cycles 2612285013.077502 # Number of busy cycles +system.cpu1.not_idle_fraction 2.739577 # Percentage of non-idle cycles +system.cpu1.idle_fraction -1.739577 # Percentage of idle cycles +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed +system.cpu1.kern.mode_switch::kernel 0 # number of protection mode switches +system.cpu1.kern.mode_switch::user 0 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 0 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 0 +system.cpu1.kern.mode_good::user 0 +system.cpu1.kern.mode_good::idle 0 +system.cpu1.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::user nan # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::idle nan # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total nan # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode +system.cpu1.kern.swap_context 0 # number of times the context was actually changed +system.cpu2.dtb.fetch_hits 0 # ITB hits +system.cpu2.dtb.fetch_misses 0 # ITB misses +system.cpu2.dtb.fetch_acv 0 # ITB acv +system.cpu2.dtb.fetch_accesses 0 # ITB accesses +system.cpu2.dtb.read_hits 3234016 # DTB read hits +system.cpu2.dtb.read_misses 12170 # DTB read misses +system.cpu2.dtb.read_acv 136 # DTB read access violations +system.cpu2.dtb.read_accesses 218383 # DTB read accesses +system.cpu2.dtb.write_hits 2000862 # DTB write hits +system.cpu2.dtb.write_misses 2630 # DTB write misses +system.cpu2.dtb.write_acv 139 # DTB write access violations +system.cpu2.dtb.write_accesses 81465 # DTB write accesses +system.cpu2.dtb.data_hits 5234878 # DTB hits +system.cpu2.dtb.data_misses 14800 # DTB misses +system.cpu2.dtb.data_acv 275 # DTB access violations +system.cpu2.dtb.data_accesses 299848 # DTB accesses +system.cpu2.itb.fetch_hits 374542 # ITB hits +system.cpu2.itb.fetch_misses 5731 # ITB misses +system.cpu2.itb.fetch_acv 284 # ITB acv +system.cpu2.itb.fetch_accesses 380273 # ITB accesses +system.cpu2.itb.read_hits 0 # DTB read hits +system.cpu2.itb.read_misses 0 # DTB read misses +system.cpu2.itb.read_acv 0 # DTB read access violations +system.cpu2.itb.read_accesses 0 # DTB read accesses +system.cpu2.itb.write_hits 0 # DTB write hits +system.cpu2.itb.write_misses 0 # DTB write misses +system.cpu2.itb.write_acv 0 # DTB write access violations +system.cpu2.itb.write_accesses 0 # DTB write accesses +system.cpu2.itb.data_hits 0 # DTB hits +system.cpu2.itb.data_misses 0 # DTB misses +system.cpu2.itb.data_acv 0 # DTB access violations +system.cpu2.itb.data_accesses 0 # DTB accesses +system.cpu2.numCycles 30548805 # number of cpu cycles simulated +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.BPredUnit.lookups 8364028 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 7669410 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 129868 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 6711241 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 5709819 # Number of BTB hits +system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu2.BPredUnit.usedRAS 287796 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.RASInCorrect 15290 # Number of incorrect RAS predictions. +system.cpu2.fetch.icacheStallCycles 8565342 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 34820498 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8364028 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 5997615 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8085140 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 623390 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9684769 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 10169 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1946 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 65267 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 78430 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 219 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2618903 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 90402 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 26897224 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.294576 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.310232 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18812084 69.94% 69.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 275091 1.02% 70.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 443313 1.65% 72.61% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4200168 15.62% 88.23% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 736557 2.74% 90.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 167312 0.62% 91.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 197037 0.73% 92.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 432029 1.61% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1633633 6.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::total 26897224 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.273792 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.139832 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8682356 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9793254 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7488405 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 293704 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 393556 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 170875 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13042 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34420320 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 40663 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 393556 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 9037496 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2819097 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5808677 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7346220 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1246237 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33260279 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2326 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 233903 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 407997 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 22331754 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 41424509 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41259136 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 165373 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20496437 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1835317 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 510420 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 61593 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3691952 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3399315 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2093436 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 371907 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 254715 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 30727225 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 632539 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 30272118 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 35753 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2189784 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1100567 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 445757 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 26897224 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.125474 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.564893 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15350394 57.07% 57.07% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3115885 11.58% 68.65% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1557090 5.79% 74.44% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5021564 18.67% 93.11% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 911830 3.39% 96.50% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 491728 1.83% 98.33% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 288005 1.07% 99.40% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 142453 0.53% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18275 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 26897224 # Number of insts issued each cycle +system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 35285 14.01% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 14.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 113269 44.96% 58.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 103382 41.04% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 24555706 81.12% 81.12% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20320 0.07% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8506 0.03% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3366886 11.12% 92.35% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2024055 6.69% 99.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 292961 0.97% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::total 30272118 # Type of FU issued +system.cpu2.iq.rate 0.990943 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 251936 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.008322 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 87492046 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 33437480 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 29866501 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 237103 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 115982 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 112325 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 30398156 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 123442 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 190063 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu2.iew.lsq.thread0.squashedLoads 422258 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 952 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4004 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 162752 # Number of stores squashed +system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu2.iew.lsq.thread0.rescheduledLoads 4980 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 23112 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu2.iew.iewSquashCycles 393556 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2038103 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 212197 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32647760 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 228888 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3399315 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2093436 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 561709 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 150503 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2400 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4004 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 66845 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 130356 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 197201 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 30107405 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3254707 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 164713 # Number of squashed instructions skipped in execute +system.cpu2.iew.exec_swp 0 # number of swp insts executed +system.cpu2.iew.exec_nop 1287996 # number of nop insts executed +system.cpu2.iew.exec_refs 5262746 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6765344 # Number of branches executed +system.cpu2.iew.exec_stores 2008039 # Number of stores executed +system.cpu2.iew.exec_rate 0.985551 # Inst execution rate +system.cpu2.iew.wb_sent 30012235 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 29978826 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17295143 # num instructions producing a value +system.cpu2.iew.wb_consumers 20538847 # num instructions consuming a value +system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu2.iew.wb_rate 0.981342 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.842070 # average fanout of values written-back +system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu2.commit.commitSquashedInsts 2374409 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 186782 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 183048 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26503668 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.140514 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.850633 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16405527 61.90% 61.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2337415 8.82% 70.72% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1218938 4.60% 75.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4753611 17.94% 93.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 502619 1.90% 95.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 186793 0.70% 95.85% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 180491 0.68% 96.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 181897 0.69% 97.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 736377 2.78% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::total 26503668 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30227806 # Number of instructions committed +system.cpu2.commit.committedOps 30227806 # Number of ops (including micro ops) committed +system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu2.commit.refs 4907741 # Number of memory references committed +system.cpu2.commit.loads 2977057 # Number of loads committed +system.cpu2.commit.membars 65125 # Number of memory barriers committed +system.cpu2.commit.branches 6615814 # Number of branches committed +system.cpu2.commit.fp_insts 111064 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28762873 # Number of committed integer instructions. +system.cpu2.commit.function_calls 231817 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 736377 # number cycles where commit BW limit reached +system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu2.rob.rob_reads 58294713 # The number of ROB reads +system.cpu2.rob.rob_writes 65597739 # The number of ROB writes +system.cpu2.timesIdled 244101 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3651581 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745276463 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 29049036 # Number of Instructions Simulated +system.cpu2.committedOps 29049036 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 29049036 # Number of Instructions Simulated +system.cpu2.cpi 1.051629 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.051629 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.950906 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.950906 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 39585060 # number of integer regfile reads +system.cpu2.int_regfile_writes 21198431 # number of integer regfile writes +system.cpu2.fp_regfile_reads 68487 # number of floating regfile reads +system.cpu2.fp_regfile_writes 68830 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4557721 # number of misc regfile reads +system.cpu2.misc_regfile_writes 264115 # number of misc regfile writes +system.cpu2.kern.inst.arm 0 # number of arm instructions executed +system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed +system.cpu2.kern.mode_switch::kernel 0 # number of protection mode switches +system.cpu2.kern.mode_switch::user 0 # number of protection mode switches +system.cpu2.kern.mode_switch::idle 0 # number of protection mode switches +system.cpu2.kern.mode_good::kernel 0 +system.cpu2.kern.mode_good::user 0 +system.cpu2.kern.mode_good::idle 0 +system.cpu2.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches +system.cpu2.kern.mode_switch_good::user nan # fraction of useful protection mode switches +system.cpu2.kern.mode_switch_good::idle nan # fraction of useful protection mode switches +system.cpu2.kern.mode_switch_good::total nan # fraction of useful protection mode switches +system.cpu2.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode +system.cpu2.kern.mode_ticks::user 0 # number of ticks spent at the given mode +system.cpu2.kern.mode_ticks::idle 0 # number of ticks spent at the given mode +system.cpu2.kern.swap_context 0 # number of times the context was actually changed + +---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal new file mode 100644 index 000000000..8a879f578 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/system.terminal @@ -0,0 +1,108 @@ +M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 +
Got Configuration 623 +
memsize 8000000 pages 4000 +
First free page after ROM 0xFFFFFC0000018000 +
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 +
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 +
CPU Clock at 2000 MHz IntrClockFrequency=1024 +
Booting with 1 processor(s) +
KSP: 0x20043FE8 PTBR 0x20 +
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 +
Memory cluster 0 [0 - 392] +
Memory cluster 1 [392 - 15992] +
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 +
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 +
unix_boot_mem ends at FFFFFC0000076000 +
k_argc = 0 +
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) +
CallbackFixup 0 18000, t7=FFFFFC000070C000 +
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 +
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM +
Major Options: SMP LEGACY_START VERBOSE_MCHECK +
Command line: root=/dev/hda1 console=ttyS0 +
memcluster 0, usage 1, start 0, end 392 +
memcluster 1, usage 0, start 392, end 16384 +
freeing pages 1069:16384 +
reserving pages 1069:1070 +
4096K Bcache detected; load hit latency 6 cycles, load miss latency 32 cycles +
SMP: 1 CPUs probed -- cpu_present_mask = 1 +
Built 1 zonelists +
Kernel command line: root=/dev/hda1 console=ttyS0 +
PID hash table entries: 1024 (order: 10, 32768 bytes) +
Using epoch = 1900 +
Console: colour dummy device 80x25 +
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) +
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) +
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) +
Mount-cache hash table entries: 512 +
SMP mode deactivated. +
Brought up 1 CPUs +
SMP: Total of 1 processors activated (4002.20 BogoMIPS). +
NET: Registered protocol family 16 +
EISA bus registered +
pci: enabling save/restore of SRM state +
SCSI subsystem initialized +
srm_env: version 0.0.5 loaded successfully +
Installing knfsd (copyright (C) 1996 okir@monad.swb.de). +
Initializing Cryptographic API +
rtc: Standard PC (1900) epoch (1900) detected +
Real Time Clock Driver v1.12 +
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled +
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 +
io scheduler noop registered +
io scheduler anticipatory registered +
io scheduler deadline registered +
io scheduler cfq registered +
loop: loaded (max 8 devices) +
nbd: registered device at major 43 +
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. +
PCI: Setting latency timer of device 0000:00:01.0 to 64 +
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 +
eth0: enabling optical transceiver +
eth0: using 64 bit addressing. +
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg +
tun: Universal TUN/TAP device driver, 1.6 +
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> +
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 +
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx +
PIIX4: IDE controller at PCI slot 0000:00:00.0 +
PIIX4: chipset revision 0 +
PIIX4: 100% native mode on irq 31 +
PCI: Setting latency timer of device 0000:00:00.0 to 64 +
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA +
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA +
hda: M5 IDE Disk, ATA DISK drive +
hdb: M5 IDE Disk, ATA DISK drive +
ide0 at 0x8410-0x8417,0x8422 on irq 31 +
hda: max request size: 128KiB +
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) +
hda: cache flushes not supported +
hda: hda1 +
hdb: max request size: 128KiB +
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) +
hdb: cache flushes not supported +
hdb: unknown partition table +
mice: PS/2 mouse device common for all mice +
NET: Registered protocol family 2 +
IP route cache hash table entries: 4096 (order: 2, 32768 bytes) +
TCP established hash table entries: 16384 (order: 5, 262144 bytes) +
TCP bind hash table entries: 16384 (order: 5, 262144 bytes) +
TCP: Hash tables configured (established 16384 bind 16384) +
TCP reno registered +
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack +
ip_tables: (C) 2000-2002 Netfilter core team +
arp_tables: (C) 2002 David S. Miller +
TCP bic registered +
Initializing IPsec netlink socket +
NET: Registered protocol family 1 +
NET: Registered protocol family 17 +
NET: Registered protocol family 15 +
Bridge firewalling registered +
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com> +
All bugs added by David S. Miller <davem@redhat.com> +
VFS: Mounted root (ext2 filesystem) readonly. +
Freeing unused kernel memory: 224k freed +
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
+mounting filesystems...
+EXT2-fs warning: checktime reached, running e2fsck is recommended +
loading script...
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