diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2013-01-08 08:54:16 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2013-01-08 08:54:16 -0500 |
| commit | fbeced6135151cc70f83b95603589bcca53f3efc (patch) | |
| tree | cb8a877be1970b24d2eca0851fa5bfe5f5bca340 /tests/long/fs/10.linux-boot/ref/alpha | |
| parent | 25efbb5bdcc037826aac4ee2c9604dabb70e0ee5 (diff) | |
| download | gem5-fbeced6135151cc70f83b95603589bcca53f3efc.tar.xz | |
stats: update stats for previous six changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
3 files changed, 3579 insertions, 3579 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 4908ce50e..46b1b53be 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.897858 # Number of seconds simulated -sim_ticks 1897857556000 # Number of ticks simulated -final_tick 1897857556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.901720 # Number of seconds simulated +sim_ticks 1901719660500 # Number of ticks simulated +final_tick 1901719660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54087 # Simulator instruction rate (inst/s) -host_op_rate 54087 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1829896991 # Simulator tick rate (ticks/s) -host_mem_usage 335972 # Number of bytes of host memory used -host_seconds 1037.14 # Real time elapsed on the host -sim_insts 56096024 # Number of instructions simulated -sim_ops 56096024 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 762816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24264832 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 217920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 955136 # Number of bytes read from this memory -system.physmem.bytes_read::total 28851328 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 762816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 217920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 980736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7805952 # Number of bytes written to this memory -system.physmem.bytes_written::total 7805952 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11919 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 379138 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41416 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3405 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 14924 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450802 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121968 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121968 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 401935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12785381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1396640 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 114824 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 503271 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15202051 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 401935 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 114824 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516760 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4113034 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4113034 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4113034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 401935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12785381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1396640 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 114824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 503271 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19315085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450802 # Total number of read requests seen -system.physmem.writeReqs 121968 # Total number of write requests seen -system.physmem.cpureqs 580318 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28851328 # Total number of bytes read from memory -system.physmem.bytesWritten 7805952 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28851328 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7805952 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 52 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3354 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28275 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28002 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28406 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 28112 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28525 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28215 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27879 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27987 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28166 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28504 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28315 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 28066 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28252 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27814 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7745 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7549 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7802 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7514 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7914 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7617 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7286 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7435 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7648 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7558 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7984 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7855 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7634 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7769 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7378 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis +host_inst_rate 128809 # Simulator instruction rate (inst/s) +host_op_rate 128809 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4317556960 # Simulator tick rate (ticks/s) +host_mem_usage 340604 # Number of bytes of host memory used +host_seconds 440.46 # Real time elapsed on the host +sim_insts 56735321 # Number of instructions simulated +sim_ops 56735321 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24596992 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2651904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 118720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 533440 # Number of bytes read from this memory +system.physmem.bytes_read::total 28758656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 857600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 118720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 976320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7726912 # Number of bytes written to this memory +system.physmem.bytes_written::total 7726912 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13400 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 384328 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41436 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1855 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8335 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449354 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120733 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120733 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 450960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12934079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1394477 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 62428 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 280504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15122448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 450960 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 62428 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513388 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4063118 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4063118 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4063118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 450960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12934079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1394477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 62428 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 280504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19185566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 449354 # Total number of read requests seen +system.physmem.writeReqs 120733 # Total number of write requests seen +system.physmem.cpureqs 587676 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28758656 # Total number of bytes read from memory +system.physmem.bytesWritten 7726912 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28758656 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7726912 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4987 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28470 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27991 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28541 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28255 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28278 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27937 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28148 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28118 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28117 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28100 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27877 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27868 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27749 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7940 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7547 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7751 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7437 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7736 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7593 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7293 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7361 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7614 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7612 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7616 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7622 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7539 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7418 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7408 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7246 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 525 # Number of times wr buffer was full causing retry -system.physmem.totGap 1897852967000 # Total gap between requests +system.physmem.numWrRetry 393 # Number of times wr buffer was full causing retry +system.physmem.totGap 1901668058000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 450802 # Categorize read packet sizes +system.physmem.readPktSize::6 449354 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -107,7 +107,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 122493 # categorize write packet sizes +system.physmem.writePktSize::6 121126 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -116,33 +116,33 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 3354 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4987 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 322811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 31450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2029 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1950 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 322670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1563 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1228 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -152,225 +152,225 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5249 # 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Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31008.23 # Average memory access latency -system.physmem.avgRdBW 15.20 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.11 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.20 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.11 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 30379.84 # Average memory access latency +system.physmem.avgRdBW 15.12 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.06 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.12 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.06 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # 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average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 229001.511504 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 228537.006158 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 228537.006158 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 228537.006158 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 228537.006158 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 190616 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23021 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 22877 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.371921 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.332211 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41523 # number of writebacks -system.iocache.writebacks::total 41523 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 172 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 41520 # number of writebacks +system.iocache.writebacks::total 41520 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41724 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41724 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41724 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41724 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11872000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11872000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7377518046 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7377518046 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7389390046 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7389390046 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7389390046 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7389390046 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12298000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12298000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7352694535 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7352694535 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 7364992535 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7364992535 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7364992535 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7364992535 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -591,14 +591,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69023.255814 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 69023.255814 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177549.048084 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 177549.048084 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 177101.669207 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 177101.669207 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 177101.669207 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 177101.669207 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68703.910615 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68703.910615 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176951.639753 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176951.639753 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176487.324411 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176487.324411 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176487.324411 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176487.324411 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -616,22 +616,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7996955 # DTB read hits -system.cpu0.dtb.read_misses 29938 # DTB read misses -system.cpu0.dtb.read_acv 553 # DTB read access violations -system.cpu0.dtb.read_accesses 624438 # DTB read accesses -system.cpu0.dtb.write_hits 5309744 # DTB write hits -system.cpu0.dtb.write_misses 7955 # DTB write misses -system.cpu0.dtb.write_acv 319 # DTB write access violations -system.cpu0.dtb.write_accesses 207916 # DTB write accesses -system.cpu0.dtb.data_hits 13306699 # DTB hits -system.cpu0.dtb.data_misses 37893 # DTB misses -system.cpu0.dtb.data_acv 872 # DTB access violations -system.cpu0.dtb.data_accesses 832354 # DTB accesses -system.cpu0.itb.fetch_hits 944692 # ITB hits -system.cpu0.itb.fetch_misses 28693 # ITB misses -system.cpu0.itb.fetch_acv 988 # ITB acv -system.cpu0.itb.fetch_accesses 973385 # ITB accesses +system.cpu0.dtb.read_hits 8796431 # DTB read hits +system.cpu0.dtb.read_misses 31428 # DTB read misses +system.cpu0.dtb.read_acv 541 # DTB read access violations +system.cpu0.dtb.read_accesses 625134 # DTB read accesses +system.cpu0.dtb.write_hits 5759616 # DTB write hits +system.cpu0.dtb.write_misses 8293 # DTB write misses +system.cpu0.dtb.write_acv 340 # DTB write access violations +system.cpu0.dtb.write_accesses 208056 # DTB write accesses +system.cpu0.dtb.data_hits 14556047 # DTB hits +system.cpu0.dtb.data_misses 39721 # DTB misses +system.cpu0.dtb.data_acv 881 # DTB access violations +system.cpu0.dtb.data_accesses 833190 # DTB accesses +system.cpu0.itb.fetch_hits 984271 # ITB hits +system.cpu0.itb.fetch_misses 30098 # ITB misses +system.cpu0.itb.fetch_acv 957 # ITB acv +system.cpu0.itb.fetch_accesses 1014369 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -644,277 +644,277 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 92901317 # number of cpu cycles simulated +system.cpu0.numCycles 101814962 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 11220993 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 9498823 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 301088 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 7731310 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 4807164 # Number of BTB hits +system.cpu0.BPredUnit.lookups 12372868 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 10433314 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 330387 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 8151024 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5278103 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 696053 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 31347 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 22682478 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 57580156 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 11220993 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5503217 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10836671 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1573403 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 32658351 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 28974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 198560 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 186652 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 190 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6976582 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 207142 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 67595352 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.851836 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.189286 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 784011 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 32544 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 24931217 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 63627814 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12372868 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6062114 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11958171 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1721751 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 36639586 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31996 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 197160 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 291451 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 250 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7650026 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 223701 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 75155119 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.846620 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.185016 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 56758681 83.97% 83.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 707820 1.05% 85.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1385949 2.05% 87.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 615643 0.91% 87.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2401218 3.55% 91.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 457628 0.68% 92.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 501258 0.74% 92.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 784291 1.16% 94.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3982864 5.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 63196948 84.09% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 760434 1.01% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1555219 2.07% 87.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 695943 0.93% 88.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2597980 3.46% 91.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 515321 0.69% 92.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 570202 0.76% 93.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 825200 1.10% 94.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4437872 5.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 67595352 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.120784 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.619799 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 23783356 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 32156359 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9819480 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 864593 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 971563 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 447466 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 32236 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56434658 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 99123 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 971563 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 24717335 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12372612 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 16597679 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9220139 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3716022 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53261468 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6752 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 462341 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1402867 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 35633564 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 64862965 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 64519168 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 343797 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31292257 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4341299 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1345733 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 201778 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 10181749 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8375667 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5571987 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1008121 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 649590 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 47223004 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1661663 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 46145441 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 96356 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5312296 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2839377 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1124463 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 67595352 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.682672 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.326673 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 75155119 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.121523 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.624936 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26159678 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 36134055 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10861438 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 929510 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1070437 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 506952 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35177 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62384726 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 105081 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1070437 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27188236 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 14621537 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18000496 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10158555 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4115856 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 58951339 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6767 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 643786 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1455498 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 39478397 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 71801839 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 71417626 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 384213 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34623741 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4854648 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1439423 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 209577 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11309679 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9204846 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6035425 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1140474 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 743155 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52262338 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1790513 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 51072320 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 91453 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5903524 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3097982 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1211963 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 75155119 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.679559 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.328921 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 46917740 69.41% 69.41% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9524699 14.09% 83.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4257234 6.30% 89.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2757377 4.08% 93.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2128651 3.15% 97.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1105682 1.64% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 579516 0.86% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 281591 0.42% 99.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 42862 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 52460165 69.80% 69.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10326519 13.74% 83.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4642920 6.18% 89.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3073584 4.09% 93.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2437230 3.24% 97.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1208862 1.61% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 646282 0.86% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 308169 0.41% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 51388 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 67595352 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 75155119 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 67879 11.08% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.08% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 286167 46.73% 57.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 258352 42.19% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 82854 12.32% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 311669 46.35% 58.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 277938 41.33% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 31627354 68.54% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48263 0.10% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.65% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 14877 0.03% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8323640 18.04% 86.73% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5371898 11.64% 98.37% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 753768 1.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35204584 68.93% 68.94% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56105 0.11% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15686 0.03% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.08% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9153958 17.92% 87.01% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5827340 11.41% 98.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 808994 1.58% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 46145441 # Type of FU issued -system.cpu0.iq.rate 0.496715 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 612398 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013271 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 160102230 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 53968976 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 45199549 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 492757 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 238910 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 232575 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 46496253 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 257824 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 502915 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 51072320 # Type of FU issued +system.cpu0.iq.rate 0.501619 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 672462 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013167 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 177512873 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59702358 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50032811 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 550800 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 266343 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 260046 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 51452584 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 288424 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 541788 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1032397 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2215 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 11166 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 416538 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1120800 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2789 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12579 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 457772 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 13927 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 141497 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18421 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 147130 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 971563 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8614462 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 715502 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 51740003 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 598208 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8375667 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5571987 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1467274 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 578076 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5429 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 11166 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 147373 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 320873 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 468246 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 45797277 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8048095 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 348163 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1070437 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10393328 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 793846 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 57261563 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 642303 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9204846 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6035425 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1577054 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 582295 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5281 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12579 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 164111 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 347239 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 511350 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 50686887 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8851053 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 385432 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2855336 # number of nop insts executed -system.cpu0.iew.exec_refs 13377753 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7249094 # Number of branches executed -system.cpu0.iew.exec_stores 5329658 # Number of stores executed -system.cpu0.iew.exec_rate 0.492967 # Inst execution rate -system.cpu0.iew.wb_sent 45516467 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 45432124 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 22555336 # num instructions producing a value -system.cpu0.iew.wb_consumers 30242853 # num instructions consuming a value +system.cpu0.iew.exec_nop 3208712 # number of nop insts executed +system.cpu0.iew.exec_refs 14632506 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8068479 # Number of branches executed +system.cpu0.iew.exec_stores 5781453 # Number of stores executed +system.cpu0.iew.exec_rate 0.497833 # Inst execution rate +system.cpu0.iew.wb_sent 50383937 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 50292857 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25094352 # num instructions producing a value +system.cpu0.iew.wb_consumers 33818001 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.489036 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.745807 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.493963 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742041 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5732411 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 537200 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 438547 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 66623789 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.689159 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.608194 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6371688 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 578550 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 477828 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 74084682 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.685601 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.604018 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 49353923 74.08% 74.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7278183 10.92% 85.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3860099 5.79% 90.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2143933 3.22% 94.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1188584 1.78% 95.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 481737 0.72% 96.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 414393 0.62% 97.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 388678 0.58% 97.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1514259 2.27% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 55026515 74.28% 74.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7939418 10.72% 84.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4342581 5.86% 90.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2354466 3.18% 94.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1312338 1.77% 95.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 550007 0.74% 96.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 466229 0.63% 97.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 437204 0.59% 97.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1655924 2.24% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 66623789 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 45914377 # Number of instructions committed -system.cpu0.commit.committedOps 45914377 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 74084682 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50792559 # Number of instructions committed +system.cpu0.commit.committedOps 50792559 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 12498719 # Number of memory references committed -system.cpu0.commit.loads 7343270 # Number of loads committed -system.cpu0.commit.membars 179286 # Number of memory barriers committed -system.cpu0.commit.branches 6902899 # Number of branches committed -system.cpu0.commit.fp_insts 230540 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 42546523 # Number of committed integer instructions. -system.cpu0.commit.function_calls 573621 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1514259 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13661699 # Number of memory references committed +system.cpu0.commit.loads 8084046 # Number of loads committed +system.cpu0.commit.membars 197074 # Number of memory barriers committed +system.cpu0.commit.branches 7671683 # Number of branches committed +system.cpu0.commit.fp_insts 257823 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47034170 # Number of committed integer instructions. +system.cpu0.commit.function_calls 648346 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1655924 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 116563585 # The number of ROB reads -system.cpu0.rob.rob_writes 104266102 # The number of ROB writes -system.cpu0.timesIdled 937015 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25305965 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3702808960 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 43304295 # Number of Instructions Simulated -system.cpu0.committedOps 43304295 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 43304295 # Number of Instructions Simulated -system.cpu0.cpi 2.145314 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.145314 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.466132 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.466132 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 60234005 # number of integer regfile reads -system.cpu0.int_regfile_writes 32862786 # number of integer regfile writes -system.cpu0.fp_regfile_reads 114240 # number of floating regfile reads -system.cpu0.fp_regfile_writes 115409 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1567878 # number of misc regfile reads -system.cpu0.misc_regfile_writes 765605 # number of misc regfile writes +system.cpu0.rob.rob_reads 129398549 # The number of ROB reads +system.cpu0.rob.rob_writes 115399767 # The number of ROB writes +system.cpu0.timesIdled 1054205 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26659843 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3701617819 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47867129 # Number of Instructions Simulated +system.cpu0.committedOps 47867129 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 47867129 # Number of Instructions Simulated +system.cpu0.cpi 2.127033 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.127033 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.470138 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.470138 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 66695316 # number of integer regfile reads +system.cpu0.int_regfile_writes 36408183 # number of integer regfile writes +system.cpu0.fp_regfile_reads 127649 # number of floating regfile reads +system.cpu0.fp_regfile_writes 129302 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1695809 # number of misc regfile reads +system.cpu0.misc_regfile_writes 808592 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -946,245 +946,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 790851 # number of replacements -system.cpu0.icache.tagsinuse 510.328171 # Cycle average of tags in use -system.cpu0.icache.total_refs 6144778 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 791359 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.764843 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 20315369000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.328171 # Average occupied blocks per requestor +system.cpu0.icache.replacements 867960 # number of replacements +system.cpu0.icache.tagsinuse 510.328414 # Cycle average of tags in use +system.cpu0.icache.total_refs 6737923 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 868472 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.758365 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 20312098000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.328414 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.996735 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.996735 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6144778 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6144778 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6144778 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6144778 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6144778 # number of overall hits -system.cpu0.icache.overall_hits::total 6144778 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 831804 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 831804 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 831804 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 831804 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 831804 # number of overall misses -system.cpu0.icache.overall_misses::total 831804 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11563264492 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11563264492 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11563264492 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11563264492 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11563264492 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11563264492 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6976582 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6976582 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6976582 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6976582 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6976582 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6976582 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119228 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.119228 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119228 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.119228 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119228 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.119228 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13901.429293 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13901.429293 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13901.429293 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13901.429293 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13901.429293 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13901.429293 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2068 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1976 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 129 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.031008 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 988 # average number of cycles each access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 6737923 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6737923 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6737923 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6737923 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6737923 # number of overall hits +system.cpu0.icache.overall_hits::total 6737923 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 912101 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 912101 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 912101 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 912101 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 912101 # number of overall misses +system.cpu0.icache.overall_misses::total 912101 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12723011493 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12723011493 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12723011493 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12723011493 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12723011493 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12723011493 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7650024 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7650024 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7650024 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7650024 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7650024 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7650024 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119229 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.119229 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119229 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.119229 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119229 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.119229 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13949.125692 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13949.125692 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13949.125692 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13949.125692 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13949.125692 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13949.125692 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3314 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 438 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 144 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.013889 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 438 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40285 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 40285 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 40285 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 40285 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 40285 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 40285 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 791519 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 791519 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 791519 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 791519 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 791519 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 791519 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9521125993 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9521125993 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9521125993 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9521125993 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9521125993 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9521125993 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113454 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.113454 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113454 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.113454 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12028.929177 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12028.929177 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12028.929177 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12028.929177 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43445 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43445 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43445 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43445 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43445 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43445 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 868656 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 868656 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 868656 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 868656 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 868656 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 868656 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10487782996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10487782996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10487782996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10487782996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10487782996 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10487782996 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113549 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113549 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113549 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113549 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12073.574575 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12073.574575 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12073.574575 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12073.574575 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1122816 # number of replacements -system.cpu0.dcache.tagsinuse 467.302243 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9451134 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1123328 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.413512 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1274576 # number of replacements +system.cpu0.dcache.tagsinuse 505.658053 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10359284 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1275088 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.124368 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 21802000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 467.302243 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.912700 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.912700 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5816576 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5816576 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3291002 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3291002 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156681 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 156681 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 180603 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 180603 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9107578 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9107578 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9107578 # number of overall hits -system.cpu0.dcache.overall_hits::total 9107578 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1395487 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1395487 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1670757 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1670757 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 17192 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 17192 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 672 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 672 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3066244 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3066244 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3066244 # number of overall misses -system.cpu0.dcache.overall_misses::total 3066244 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31388896500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 31388896500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 67591367114 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 67591367114 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 251807000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 251807000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4104500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4104500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 98980263614 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 98980263614 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 98980263614 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 98980263614 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7212063 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7212063 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4961759 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4961759 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 173873 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 173873 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 181275 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 181275 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12173822 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12173822 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12173822 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12173822 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.193493 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.193493 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.336727 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.336727 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.098877 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.098877 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003707 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003707 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251872 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.251872 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251872 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.251872 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22493.148628 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 22493.148628 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40455.534296 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40455.534296 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.754304 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.754304 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6107.886905 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6107.886905 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 32280.622029 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32280.622029 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32280.622029 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2359081 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 46623 # number of cycles access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 505.658053 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.987613 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.987613 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6368256 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6368256 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3633863 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3633863 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 160621 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 160621 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 185111 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 185111 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10002119 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10002119 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10002119 # number of overall hits +system.cpu0.dcache.overall_hits::total 10002119 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1588144 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1588144 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1741180 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1741180 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20406 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20406 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2921 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2921 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3329324 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3329324 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3329324 # number of overall misses +system.cpu0.dcache.overall_misses::total 3329324 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34092049500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 34092049500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 69554473067 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 69554473067 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 288471000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 288471000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 21390500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 21390500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 103646522567 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 103646522567 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 103646522567 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 103646522567 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7956400 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7956400 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5375043 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5375043 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 181027 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 181027 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 188032 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 188032 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13331443 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13331443 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13331443 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13331443 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199606 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.199606 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323938 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.323938 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112724 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112724 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015535 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015535 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249735 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.249735 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249735 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.249735 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21466.598432 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21466.598432 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39946.744775 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 39946.744775 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14136.577477 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14136.577477 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7323.005820 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7323.005820 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31131.401620 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31131.401620 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31131.401620 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31131.401620 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2393556 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1763 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 48538 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 50.599082 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 131.285714 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 49.313033 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 251.857143 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 614637 # number of writebacks -system.cpu0.dcache.writebacks::total 614637 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 536909 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 536909 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1412908 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1412908 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3986 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3986 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1949817 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1949817 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1949817 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1949817 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 858578 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 858578 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257849 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 257849 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13206 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13206 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 672 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 672 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1116427 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1116427 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1116427 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1116427 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19432503500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19432503500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9843225787 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9843225787 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 161840000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 161840000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2760500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2760500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29275729287 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 29275729287 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29275729287 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 29275729287 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 998479000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 998479000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1684532498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1684532498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2683011498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2683011498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.119047 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.119047 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051967 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051967 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075952 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075952 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003707 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003707 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.091707 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091707 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.091707 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22633.358297 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22633.358297 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38174.380304 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38174.380304 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12255.035590 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12255.035590 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4107.886905 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4107.886905 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26222.699099 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26222.699099 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 749955 # number of writebacks +system.cpu0.dcache.writebacks::total 749955 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 587926 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 587926 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1468148 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1468148 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4517 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4517 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2056074 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2056074 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2056074 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2056074 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1000218 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1000218 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 273032 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 273032 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15889 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15889 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2921 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2921 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1273250 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1273250 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1273250 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1273250 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21325955000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21325955000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10169026713 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10169026713 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 181062500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 181062500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15548500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15548500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31494981713 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 31494981713 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31494981713 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 31494981713 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1455479000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1455479000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2128324998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2128324998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3583803998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3583803998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125712 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125712 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050796 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050796 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087771 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087771 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015535 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015535 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095507 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.095507 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095507 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.095507 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21321.306955 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21321.306955 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37244.816406 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37244.816406 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11395.462269 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.462269 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5323.005820 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5323.005820 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24735.897674 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24735.897674 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24735.897674 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24735.897674 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1196,22 +1196,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2657978 # DTB read hits -system.cpu1.dtb.read_misses 12789 # DTB read misses -system.cpu1.dtb.read_acv 27 # DTB read access violations -system.cpu1.dtb.read_accesses 325192 # DTB read accesses -system.cpu1.dtb.write_hits 1642917 # DTB write hits -system.cpu1.dtb.write_misses 2443 # DTB write misses +system.cpu1.dtb.read_hits 1943067 # DTB read hits +system.cpu1.dtb.read_misses 10795 # DTB read misses +system.cpu1.dtb.read_acv 23 # DTB read access violations +system.cpu1.dtb.read_accesses 324453 # DTB read accesses +system.cpu1.dtb.write_hits 1254400 # DTB write hits +system.cpu1.dtb.write_misses 2201 # DTB write misses system.cpu1.dtb.write_acv 63 # DTB write access violations -system.cpu1.dtb.write_accesses 132832 # DTB write accesses -system.cpu1.dtb.data_hits 4300895 # DTB hits -system.cpu1.dtb.data_misses 15232 # DTB misses -system.cpu1.dtb.data_acv 90 # DTB access violations -system.cpu1.dtb.data_accesses 458024 # DTB accesses -system.cpu1.itb.fetch_hits 468004 # ITB hits -system.cpu1.itb.fetch_misses 6860 # ITB misses -system.cpu1.itb.fetch_acv 223 # ITB acv -system.cpu1.itb.fetch_accesses 474864 # ITB accesses +system.cpu1.dtb.write_accesses 132933 # DTB write accesses +system.cpu1.dtb.data_hits 3197467 # DTB hits +system.cpu1.dtb.data_misses 12996 # DTB misses +system.cpu1.dtb.data_acv 86 # DTB access violations +system.cpu1.dtb.data_accesses 457386 # DTB accesses +system.cpu1.itb.fetch_hits 434450 # ITB hits +system.cpu1.itb.fetch_misses 7705 # ITB misses +system.cpu1.itb.fetch_acv 232 # ITB acv +system.cpu1.itb.fetch_accesses 442155 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1224,516 +1224,516 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 24425153 # number of cpu cycles simulated +system.cpu1.numCycles 16039611 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 3729082 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 3054181 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 119454 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 2320080 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 1316503 # Number of BTB hits +system.cpu1.BPredUnit.lookups 2617746 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 2161338 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 77903 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 1516620 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 873996 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 271618 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 12328 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 8114039 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 17895150 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3729082 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1588121 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 3257695 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 589472 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 9888414 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24413 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 65338 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 153630 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 457 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 2125845 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 78173 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 21892478 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.817411 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.179159 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 182212 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 8242 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 6032367 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 12375417 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2617746 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1056208 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2219979 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 406574 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 6282819 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 27064 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 67109 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 53469 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1501296 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 52568 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 14943285 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.828159 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.202626 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 18634783 85.12% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 188286 0.86% 85.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 405463 1.85% 87.83% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 257415 1.18% 89.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 494264 2.26% 91.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 174627 0.80% 92.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 196879 0.90% 92.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 233860 1.07% 94.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1306901 5.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12723306 85.14% 85.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 143447 0.96% 86.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 238457 1.60% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 178791 1.20% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 308600 2.07% 90.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 118341 0.79% 91.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 133550 0.89% 92.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 199066 1.33% 93.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 899727 6.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 21892478 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.152674 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.732653 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 8206589 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 10101487 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 3024410 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 183126 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 376865 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 172901 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 11788 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 17533822 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 34638 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 376865 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 8509918 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2827280 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6300792 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2835388 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1042233 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 16406070 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 208 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 240400 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 230284 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 10874634 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 19629751 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 19484062 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 145689 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 9164172 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1710462 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 526024 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 52355 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 3079996 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2820928 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1739172 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 303279 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 178063 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 14428831 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 617828 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 13962547 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 36109 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2150385 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1081456 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 443630 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 21892478 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.637778 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.318020 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 14943285 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.163205 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.771553 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5967965 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6534138 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2076282 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 111928 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 252971 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 114663 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7593 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 12129871 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22496 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 252971 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 6175430 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 499012 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5393527 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1978606 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 643737 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 11250530 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 66 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 56207 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 157985 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 7407591 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 13449617 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 13309138 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 140479 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6324692 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1082899 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 450684 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 43314 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1976964 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2055976 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1329039 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 193469 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 109268 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9879442 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 495628 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9611427 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 29957 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1443490 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 718060 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 356268 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 14943285 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.643194 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.319140 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 15854245 72.42% 72.42% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2672796 12.21% 84.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1184242 5.41% 90.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 847687 3.87% 93.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 726248 3.32% 97.23% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 300582 1.37% 98.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 191038 0.87% 99.47% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 101044 0.46% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 14596 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 10722627 71.76% 71.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1934278 12.94% 84.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 829364 5.55% 90.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 551304 3.69% 93.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 470726 3.15% 97.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 216087 1.45% 98.54% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 139402 0.93% 99.47% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 71218 0.48% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 8279 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 21892478 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 14943285 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 17685 7.13% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.13% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 130361 52.59% 59.73% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 99827 40.27% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3634 1.84% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 107033 54.32% 56.16% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 86373 43.84% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 9165178 65.64% 65.67% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 22201 0.16% 65.83% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.83% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10896 0.08% 65.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.90% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2775695 19.88% 85.80% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1670228 11.96% 97.76% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 313060 2.24% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5997328 62.40% 62.43% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16465 0.17% 62.61% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10793 0.11% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.72% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.74% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2032935 21.15% 83.89% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1277891 13.30% 97.18% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 270726 2.82% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 13962547 # Type of FU issued -system.cpu1.iq.rate 0.571646 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 247873 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.017753 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 49890568 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 17097827 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 13608739 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 210986 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 102380 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 99816 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 14096605 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 110289 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 133191 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9611427 # Type of FU issued +system.cpu1.iq.rate 0.599231 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 197040 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020501 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 34189984 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11721176 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 9344184 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 203152 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 99152 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 96176 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9699010 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 105931 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 93506 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 414475 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 850 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 3253 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 172072 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 286352 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1028 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1836 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 129863 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 4939 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 13663 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 382 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 9210 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 376865 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2193721 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 124101 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 15871795 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 185761 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2820928 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1739172 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 554609 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 45814 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2212 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 3253 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 57900 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 130435 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 188335 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 13825969 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2678414 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 136578 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 252971 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 330484 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 40597 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10884350 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 145943 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2055976 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1329039 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 449000 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 33362 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2246 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1836 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 35752 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 100142 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 135894 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 9521603 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1961135 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 89824 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 825136 # number of nop insts executed -system.cpu1.iew.exec_refs 4329493 # number of memory reference insts executed -system.cpu1.iew.exec_branches 2168898 # Number of branches executed -system.cpu1.iew.exec_stores 1651079 # Number of stores executed -system.cpu1.iew.exec_rate 0.566055 # Inst execution rate -system.cpu1.iew.wb_sent 13745874 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 13708555 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 6651311 # num instructions producing a value -system.cpu1.iew.wb_consumers 9340604 # num instructions consuming a value +system.cpu1.iew.exec_nop 509280 # number of nop insts executed +system.cpu1.iew.exec_refs 3223669 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1421889 # Number of branches executed +system.cpu1.iew.exec_stores 1262534 # Number of stores executed +system.cpu1.iew.exec_rate 0.593631 # Inst execution rate +system.cpu1.iew.wb_sent 9469121 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 9440360 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4419848 # num instructions producing a value +system.cpu1.iew.wb_consumers 6207573 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.561247 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.712086 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.588565 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.712009 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 2293261 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 174198 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 176022 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 21515613 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.628195 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.562431 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1489613 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 139360 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 127942 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 14690314 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.634143 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.577922 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 16491806 76.65% 76.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2174989 10.11% 86.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1058158 4.92% 91.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 548223 2.55% 94.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 352308 1.64% 95.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 166690 0.77% 96.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 160522 0.75% 97.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 129128 0.60% 97.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 433789 2.02% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 11205689 76.28% 76.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1626477 11.07% 87.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 606444 4.13% 91.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 368240 2.51% 93.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 264133 1.80% 95.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 104886 0.71% 96.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 108759 0.74% 97.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 107326 0.73% 97.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 298360 2.03% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 21515613 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 13515996 # Number of instructions committed -system.cpu1.commit.committedOps 13515996 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 14690314 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 9315763 # Number of instructions committed +system.cpu1.commit.committedOps 9315763 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3973553 # Number of memory references committed -system.cpu1.commit.loads 2406453 # Number of loads committed -system.cpu1.commit.membars 57533 # Number of memory barriers committed -system.cpu1.commit.branches 2017672 # Number of branches committed -system.cpu1.commit.fp_insts 98521 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 12496541 # Number of committed integer instructions. -system.cpu1.commit.function_calls 216490 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 433789 # number cycles where commit BW limit reached +system.cpu1.commit.refs 2968800 # Number of memory references committed +system.cpu1.commit.loads 1769624 # Number of loads committed +system.cpu1.commit.membars 44277 # Number of memory barriers committed +system.cpu1.commit.branches 1334383 # Number of branches committed +system.cpu1.commit.fp_insts 94889 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8635888 # Number of committed integer instructions. +system.cpu1.commit.function_calls 148923 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 298360 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 36803153 # The number of ROB reads -system.cpu1.rob.rob_writes 31994561 # The number of ROB writes -system.cpu1.timesIdled 237566 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2532675 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3770663279 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 12791729 # Number of Instructions Simulated -system.cpu1.committedOps 12791729 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 12791729 # Number of Instructions Simulated -system.cpu1.cpi 1.909449 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.909449 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.523711 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.523711 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 17892474 # number of integer regfile reads -system.cpu1.int_regfile_writes 9829261 # number of integer regfile writes -system.cpu1.fp_regfile_reads 54188 # number of floating regfile reads -system.cpu1.fp_regfile_writes 54153 # number of floating regfile writes -system.cpu1.misc_regfile_reads 592079 # number of misc regfile reads -system.cpu1.misc_regfile_writes 255780 # number of misc regfile writes -system.cpu1.icache.replacements 297472 # number of replacements -system.cpu1.icache.tagsinuse 505.689996 # Cycle average of tags in use -system.cpu1.icache.total_refs 1814153 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 297984 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 6.088089 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 42534295000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 505.689996 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.987676 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.987676 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1814153 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1814153 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1814153 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1814153 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1814153 # number of overall hits -system.cpu1.icache.overall_hits::total 1814153 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 311692 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 311692 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 311692 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 311692 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 311692 # number of overall misses -system.cpu1.icache.overall_misses::total 311692 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4307826496 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4307826496 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4307826496 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4307826496 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4307826496 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4307826496 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 2125845 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2125845 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 2125845 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2125845 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 2125845 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2125845 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146620 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.146620 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146620 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.146620 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146620 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.146620 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13820.779795 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13820.779795 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13820.779795 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13820.779795 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13820.779795 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13820.779795 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 806 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 423 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 43 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.744186 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 423 # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 25106022 # The number of ROB reads +system.cpu1.rob.rob_writes 21862282 # The number of ROB writes +system.cpu1.timesIdled 131003 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1096326 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3786825078 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8868192 # Number of Instructions Simulated +system.cpu1.committedOps 8868192 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 8868192 # Number of Instructions Simulated +system.cpu1.cpi 1.808668 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.808668 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.552893 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.552893 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 12288735 # number of integer regfile reads +system.cpu1.int_regfile_writes 6719305 # number of integer regfile writes +system.cpu1.fp_regfile_reads 52595 # number of floating regfile reads +system.cpu1.fp_regfile_writes 52295 # number of floating regfile writes +system.cpu1.misc_regfile_reads 519807 # number of misc regfile reads +system.cpu1.misc_regfile_writes 218837 # number of misc regfile writes +system.cpu1.icache.replacements 223384 # number of replacements +system.cpu1.icache.tagsinuse 470.911172 # Cycle average of tags in use +system.cpu1.icache.total_refs 1268764 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 223896 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.666756 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1876151234000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 470.911172 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.919748 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.919748 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1268764 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1268764 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1268764 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1268764 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1268764 # number of overall hits +system.cpu1.icache.overall_hits::total 1268764 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 232532 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 232532 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 232532 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 232532 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 232532 # number of overall misses +system.cpu1.icache.overall_misses::total 232532 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3191119498 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3191119498 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3191119498 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3191119498 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3191119498 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3191119498 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1501296 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1501296 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1501296 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1501296 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1501296 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1501296 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154888 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.154888 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154888 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.154888 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154888 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.154888 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13723.356347 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13723.356347 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13723.356347 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13723.356347 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13723.356347 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13723.356347 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 852 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 37.043478 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 13650 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 13650 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 13650 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 13650 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 13650 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 13650 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 298042 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 298042 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 298042 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 298042 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 298042 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 298042 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3567181997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3567181997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3567181997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3567181997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3567181997 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3567181997 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.140199 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.140199 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.140199 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.140199 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11968.722519 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11968.722519 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11968.722519 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11968.722519 # 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number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2651052998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2651052998 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2651052998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2651052998 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2651052998 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2651052998 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.149180 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.149180 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.149180 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.149180 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11836.960395 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11836.960395 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11836.960395 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11836.960395 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 296647 # 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miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149366 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149366 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.016605 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.016605 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.194344 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.194344 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.194344 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.194344 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15548.226016 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15548.226016 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39607.800536 # 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Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.962449 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.962449 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1604976 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1604976 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 940707 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 940707 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 33481 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 33481 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32051 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 32051 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2545683 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2545683 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2545683 # number of overall hits +system.cpu1.dcache.overall_hits::total 2545683 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 206048 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 206048 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 217271 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 217271 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5237 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5237 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3060 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3060 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 423319 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 423319 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 423319 # number of overall misses +system.cpu1.dcache.overall_misses::total 423319 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3148302000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3148302000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8860772084 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 8860772084 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54690000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 54690000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22134000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 22134000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12009074084 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12009074084 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12009074084 # 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miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.142580 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.142580 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.142580 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15279.459155 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15279.459155 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40782.120412 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 40782.120412 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10443.001719 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10443.001719 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7233.333333 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7233.333333 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28368.852057 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 28368.852057 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28368.852057 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 28368.852057 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 339060 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3910 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 86.716113 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 225448 # number of writebacks -system.cpu1.dcache.writebacks::total 225448 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 193837 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 193837 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 283225 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 283225 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1368 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1368 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 477062 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 477062 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 477062 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 477062 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 239425 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 239425 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58120 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 58120 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5667 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5667 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 718 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 718 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 297545 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 297545 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 297545 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 297545 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3123299000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3123299000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2029112304 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2029112304 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67015000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67015000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5152411304 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5152411304 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5152411304 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5152411304 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 486888000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 486888000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 925465000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 925465000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1412353000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1412353000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.096971 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.096971 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038320 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038320 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120321 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120321 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.016605 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.016605 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.074652 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.074652 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.074652 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13044.999478 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13044.999478 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34912.462216 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34912.462216 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11825.480854 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11825.480854 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5069.637883 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5069.637883 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17316.410304 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17316.410304 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 70825 # number of writebacks +system.cpu1.dcache.writebacks::total 70825 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 127864 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 127864 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 178553 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 178553 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 567 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 567 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 306417 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 306417 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 306417 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 306417 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 78184 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 78184 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 38718 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 38718 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4670 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4670 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3058 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3058 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 116902 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 116902 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 116902 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 116902 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 956868500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 956868500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1322831987 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1322831987 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38016500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38016500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16018000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16018000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2279700487 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2279700487 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2279700487 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2279700487 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30982500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30982500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 645432500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 645432500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 676415000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 676415000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043171 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043171 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033436 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033436 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120616 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120616 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087095 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087095 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039374 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.039374 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039374 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.039374 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12238.674153 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12238.674153 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34165.814014 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34165.814014 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8140.578158 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.578158 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5238.064094 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5238.064094 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19500.953679 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19500.953679 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19500.953679 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19500.953679 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1742,170 +1742,170 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 169372 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 58506 39.88% 39.88% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 135 0.09% 39.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1925 1.31% 41.28% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 41.29% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 86127 58.71% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 146709 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 57513 49.12% 49.12% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 135 0.12% 49.23% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1925 1.64% 50.88% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.01% 50.89% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 57499 49.11% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 117088 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1866028984500 98.32% 98.32% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63917500 0.00% 98.33% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 571228500 0.03% 98.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8802500 0.00% 98.36% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 31183758000 1.64% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1897856691000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983027 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6541 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 182292 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 64399 40.43% 40.43% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 137 0.09% 40.52% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1928 1.21% 41.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 188 0.12% 41.85% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 92618 58.15% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 159270 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 63397 49.20% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 137 0.11% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1928 1.50% 50.80% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 188 0.15% 50.95% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 63212 49.05% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 128862 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1866521704000 98.15% 98.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63425000 0.00% 98.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 571234500 0.03% 98.18% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 91794500 0.00% 98.19% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 34470644500 1.81% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1901718802500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984441 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.667607 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.798097 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.35% 3.35% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.13% 11.48% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.91% 13.40% # number of syscalls executed -system.cpu0.kern.syscall::6 29 13.88% 27.27% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.48% 27.75% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.31% 32.06% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.35% 35.41% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.91% 37.32% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.48% 37.80% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.44% 39.23% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.35% 42.58% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.96% 43.54% # number of syscalls executed -system.cpu0.kern.syscall::45 37 17.70% 61.24% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.44% 62.68% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.83% 66.51% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.31% 70.81% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.48% 71.29% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.39% 73.68% # number of syscalls executed -system.cpu0.kern.syscall::71 27 12.92% 86.60% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.44% 88.04% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.35% 91.39% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.48% 91.87% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.96% 92.82% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.35% 96.17% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.96% 97.13% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.96% 98.09% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.48% 98.56% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.48% 99.04% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.96% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 209 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.682502 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.809079 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed +system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed +system.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.50% 38.61% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.49% 40.10% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.47% 43.56% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.99% 44.55% # number of syscalls executed +system.cpu0.kern.syscall::45 34 16.83% 61.39% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.49% 62.87% # number of syscalls executed +system.cpu0.kern.syscall::48 8 3.96% 66.83% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.46% 71.29% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.50% 71.78% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.48% 74.26% # number of syscalls executed +system.cpu0.kern.syscall::71 25 12.38% 86.63% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.49% 88.12% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.97% 91.09% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.50% 91.58% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.99% 92.57% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.47% 96.04% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.99% 97.03% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.99% 98.02% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 202 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 100 0.06% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3082 1.99% 2.06% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.09% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed -system.cpu0.kern.callpal::swpipl 140299 90.69% 92.78% # number of callpals executed -system.cpu0.kern.callpal::rdps 6336 4.10% 96.88% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.88% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.88% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.01% 96.89% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.89% # number of callpals executed -system.cpu0.kern.callpal::rti 4335 2.80% 99.69% # number of callpals executed -system.cpu0.kern.callpal::callsys 342 0.22% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 154704 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6439 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1272 # number of protection mode switches +system.cpu0.kern.callpal::wripir 291 0.17% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3482 2.08% 2.25% # number of callpals executed +system.cpu0.kern.callpal::tbi 48 0.03% 2.28% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed +system.cpu0.kern.callpal::swpipl 152520 91.05% 93.34% # number of callpals executed +system.cpu0.kern.callpal::rdps 6170 3.68% 97.03% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.03% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.03% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.03% # number of callpals executed +system.cpu0.kern.callpal::rti 4499 2.69% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 333 0.20% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 167505 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7002 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1256 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1271 -system.cpu0.kern.mode_good::user 1272 +system.cpu0.kern.mode_good::kernel 1255 +system.cpu0.kern.mode_good::user 1256 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.197391 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.179235 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.329789 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1895973773500 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1882909500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.304069 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1899848666000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1870128500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3083 # number of times the context was actually changed +system.cpu0.kern.swap_context 3483 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3800 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 68195 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 23112 38.67% 38.67% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1924 3.22% 41.89% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 100 0.17% 42.06% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 34629 57.94% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 59765 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 22728 47.97% 47.97% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1924 4.06% 52.03% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 100 0.21% 52.24% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 22629 47.76% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 47381 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870052426500 98.55% 98.55% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533448500 0.03% 98.58% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 47034500 0.00% 98.58% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 26913191500 1.42% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1897546101000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.983385 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2459 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 57520 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 17961 36.86% 36.86% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1928 3.96% 40.82% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 291 0.60% 41.41% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 28549 58.59% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 48729 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 17586 47.40% 47.40% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1928 5.20% 52.60% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 291 0.78% 53.38% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 17296 46.62% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 37101 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1876762048000 98.70% 98.70% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 532687000 0.03% 98.73% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 132052500 0.01% 98.74% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 24006771500 1.26% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1901433559000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.979121 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.653470 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.792788 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.85% 0.85% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.11% 11.97% # number of syscalls executed -system.cpu1.kern.syscall::6 13 11.11% 23.08% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.85% 23.93% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.13% 29.06% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.56% 31.62% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.71% 33.33% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.56% 35.90% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.56% 38.46% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.42% 41.88% # number of syscalls executed -system.cpu1.kern.syscall::45 17 14.53% 56.41% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.56% 58.97% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.71% 60.68% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.85% 61.54% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.71% 63.25% # number of syscalls executed -system.cpu1.kern.syscall::71 27 23.08% 86.32% # number of syscalls executed -system.cpu1.kern.syscall::74 9 7.69% 94.02% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.85% 94.87% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.71% 96.58% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.56% 99.15% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.85% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 117 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.605836 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.761374 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed +system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed +system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.81% 23.39% # number of syscalls executed +system.cpu1.kern.syscall::17 6 4.84% 28.23% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.42% 30.65% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.61% 32.26% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.42% 34.68% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.42% 37.10% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.23% 40.32% # number of syscalls executed +system.cpu1.kern.syscall::45 20 16.13% 56.45% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.42% 58.87% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.61% 60.48% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.81% 61.29% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.61% 62.90% # number of syscalls executed +system.cpu1.kern.syscall::71 29 23.39% 86.29% # number of syscalls executed +system.cpu1.kern.syscall::74 10 8.06% 94.35% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.81% 95.16% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.61% 96.77% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.42% 99.19% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 124 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.03% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1165 1.89% 1.92% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 1.93% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 1.94% # number of callpals executed -system.cpu1.kern.callpal::swpipl 54867 89.09% 91.04% # number of callpals executed -system.cpu1.kern.callpal::rdps 2419 3.93% 94.96% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.96% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.97% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 94.97% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.98% # number of callpals executed -system.cpu1.kern.callpal::rti 2874 4.67% 99.64% # number of callpals executed -system.cpu1.kern.callpal::callsys 175 0.28% 99.93% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.07% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 188 0.37% 0.37% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1118 2.21% 2.58% # number of callpals executed +system.cpu1.kern.callpal::tbi 6 0.01% 2.60% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed +system.cpu1.kern.callpal::swpipl 43429 85.72% 88.33% # number of callpals executed +system.cpu1.kern.callpal::rdps 2596 5.12% 93.45% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.45% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.46% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.46% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.47% # number of callpals executed +system.cpu1.kern.callpal::rti 3081 6.08% 99.55% # number of callpals executed +system.cpu1.kern.callpal::callsys 184 0.36% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 61585 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1629 # number of protection mode switches -system.cpu1.kern.mode_switch::user 476 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 537 -system.cpu1.kern.mode_good::user 476 -system.cpu1.kern.mode_good::idle 61 -system.cpu1.kern.mode_switch_good::kernel 0.329650 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 50665 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1406 # number of protection mode switches +system.cpu1.kern.mode_switch::user 488 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2430 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 704 +system.cpu1.kern.mode_good::user 488 +system.cpu1.kern.mode_good::idle 216 +system.cpu1.kern.mode_switch_good::kernel 0.500711 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.029814 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.258733 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 37752222500 1.99% 1.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 817466500 0.04% 2.03% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1858966004500 97.97% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1166 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.088889 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.325624 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4780653500 0.25% 0.25% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 828450500 0.04% 0.29% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1895813783000 99.71% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1119 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 37f4b3f46..7d46ecd48 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.854350 # Number of seconds simulated -sim_ticks 1854349611000 # Number of ticks simulated -final_tick 1854349611000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.854344 # Number of seconds simulated +sim_ticks 1854344296500 # Number of ticks simulated +final_tick 1854344296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55480 # Simulator instruction rate (inst/s) -host_op_rate 55480 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1941178876 # Simulator tick rate (ticks/s) -host_mem_usage 331452 # Number of bytes of host memory used -host_seconds 955.27 # Real time elapsed on the host -sim_insts 52998188 # Number of instructions simulated -sim_ops 52998188 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 967168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24880448 # Number of bytes read from this memory +host_inst_rate 131278 # Simulator instruction rate (inst/s) +host_op_rate 131278 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4595190559 # Simulator tick rate (ticks/s) +host_mem_usage 336376 # Number of bytes of host memory used +host_seconds 403.54 # Real time elapsed on the host +sim_insts 52976017 # Number of instructions simulated +sim_ops 52976017 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 964864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879424 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28499904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 967168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 967168 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7518592 # Number of bytes written to this memory -system.physmem.bytes_written::total 7518592 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15112 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388757 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28496576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 964864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 964864 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7516416 # Number of bytes written to this memory +system.physmem.bytes_written::total 7516416 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15076 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388741 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445311 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117478 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117478 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 521567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13417345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1430306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15369218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 521567 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 521567 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4054571 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4054571 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4054571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 521567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13417345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1430306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19423789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445311 # Total number of read requests seen -system.physmem.writeReqs 117478 # Total number of write requests seen -system.physmem.cpureqs 564077 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28499904 # Total number of bytes read from memory -system.physmem.bytesWritten 7518592 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28499904 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7518592 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28171 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27744 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27861 # Track reads on a per bank basis +system.physmem.num_reads::total 445259 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117444 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117444 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 520326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13416831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1430310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15367468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 520326 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520326 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4053409 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4053409 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4053409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 520326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13416831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1430310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19420877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445259 # Total number of read requests seen +system.physmem.writeReqs 117444 # Total number of write requests seen +system.physmem.cpureqs 564803 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28496576 # Total number of bytes read from memory +system.physmem.bytesWritten 7516416 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28496576 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7516416 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 63 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 176 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28168 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27749 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27864 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 27384 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28325 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28126 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27859 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28323 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28119 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27841 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 27693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27840 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27508 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27634 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27843 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27857 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27753 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27753 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27902 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7651 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7405 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7296 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6891 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7793 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7560 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7306 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7181 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7405 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7055 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7397 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7475 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7357 # Track writes on a per bank basis +system.physmem.perBankRdReqs::8 27856 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27503 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27630 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27839 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27855 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27734 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27743 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27895 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7646 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7409 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7290 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6889 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7790 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7556 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7291 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7179 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7418 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7047 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7168 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7402 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7478 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7343 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 7210 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7329 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7328 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 554 # Number of times wr buffer was full causing retry -system.physmem.totGap 1854344226000 # Total gap between requests +system.physmem.numWrRetry 1365 # Number of times wr buffer was full causing retry +system.physmem.totGap 1854338900000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445311 # Categorize read packet sizes +system.physmem.readPktSize::6 445259 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -97,7 +97,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 118032 # categorize write packet sizes +system.physmem.writePktSize::6 118809 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -106,31 +106,31 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 175 # categorize neither packet sizes +system.physmem.neitherpktsize::6 176 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 331896 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 65179 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2875 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2427 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1797 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2003 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1654 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1778 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 888 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 331910 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 65137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1760 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1586 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1660 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1745 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1229 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -142,47 +142,47 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5066 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 6253510302 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13461286302 # Sum of mem lat for all requests -system.physmem.totBusLat 1781012000 # Total cycles spent in databus access -system.physmem.totBankLat 5426764000 # Total cycles spent in bank access -system.physmem.avgQLat 14044.85 # Average queueing delay per request -system.physmem.avgBankLat 12188.05 # Average bank access latency per request +system.physmem.totQLat 6228802493 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13434068493 # Sum of mem lat for all requests +system.physmem.totBusLat 1780784000 # Total cycles spent in databus access +system.physmem.totBankLat 5424482000 # Total cycles spent in bank access +system.physmem.avgQLat 13991.15 # Average queueing delay per request +system.physmem.avgBankLat 12184.48 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30232.89 # Average memory access latency +system.physmem.avgMemAccLat 30175.63 # Average memory access latency system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s @@ -190,21 +190,21 @@ system.physmem.avgConsumedWrBW 4.05 # Av system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 11.07 # Average write queue length over time -system.physmem.readRowHits 425296 # Number of row buffer hits during reads -system.physmem.writeRowHits 76454 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.08 # Row buffer hit rate for writes -system.physmem.avgGap 3294919.10 # Average gap between requests +system.physmem.avgWrQLen 11.37 # Average write queue length over time +system.physmem.readRowHits 425317 # Number of row buffer hits during reads +system.physmem.writeRowHits 76610 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 65.23 # Row buffer hit rate for writes +system.physmem.avgGap 3295413.21 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.265413 # Cycle average of tags in use +system.iocache.tagsinuse 1.265367 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1704469740000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.265413 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079088 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079088 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1704469917000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.265367 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079085 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079085 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -215,12 +215,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9494924806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9494924806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9515852804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9515852804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9515852804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9515852804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 9519862806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9519862806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9540790804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9540790804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9540790804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9540790804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -239,17 +239,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228507.046737 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 228507.046737 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 228061.181642 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228061.181642 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 228061.181642 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228061.181642 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 189089 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 229107.210387 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 229107.210387 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 228658.856896 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 228658.856896 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 228658.856896 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 228658.856896 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 189620 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 22862 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 22696 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.270886 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.354776 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -265,12 +265,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7332138561 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7332138561 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7344069561 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7344069561 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7344069561 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7344069561 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7357096000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7357096000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 7369027000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7369027000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7369027000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7369027000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -281,12 +281,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176456.934949 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176456.934949 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176011.253709 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176011.253709 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176011.253709 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176011.253709 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 177057.566423 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 177057.566423 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176609.394847 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176609.394847 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176609.394847 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176609.394847 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -304,22 +304,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9959916 # DTB read hits -system.cpu.dtb.read_misses 41524 # DTB read misses -system.cpu.dtb.read_acv 557 # DTB read access violations -system.cpu.dtb.read_accesses 942700 # DTB read accesses -system.cpu.dtb.write_hits 6603148 # DTB write hits -system.cpu.dtb.write_misses 10669 # DTB write misses -system.cpu.dtb.write_acv 409 # DTB write access violations -system.cpu.dtb.write_accesses 338186 # DTB write accesses -system.cpu.dtb.data_hits 16563064 # DTB hits -system.cpu.dtb.data_misses 52193 # DTB misses -system.cpu.dtb.data_acv 966 # DTB access violations -system.cpu.dtb.data_accesses 1280886 # DTB accesses -system.cpu.itb.fetch_hits 1308562 # ITB hits -system.cpu.itb.fetch_misses 36917 # ITB misses -system.cpu.itb.fetch_acv 1051 # ITB acv -system.cpu.itb.fetch_accesses 1345479 # ITB accesses +system.cpu.dtb.read_hits 9948747 # DTB read hits +system.cpu.dtb.read_misses 41658 # DTB read misses +system.cpu.dtb.read_acv 544 # DTB read access violations +system.cpu.dtb.read_accesses 942034 # DTB read accesses +system.cpu.dtb.write_hits 6596243 # DTB write hits +system.cpu.dtb.write_misses 10259 # DTB write misses +system.cpu.dtb.write_acv 405 # DTB write access violations +system.cpu.dtb.write_accesses 337916 # DTB write accesses +system.cpu.dtb.data_hits 16544990 # DTB hits +system.cpu.dtb.data_misses 51917 # DTB misses +system.cpu.dtb.data_acv 949 # DTB access violations +system.cpu.dtb.data_accesses 1279950 # DTB accesses +system.cpu.itb.fetch_hits 1308175 # ITB hits +system.cpu.itb.fetch_misses 37074 # ITB misses +system.cpu.itb.fetch_acv 1064 # ITB acv +system.cpu.itb.fetch_accesses 1345249 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -332,147 +332,147 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 108866981 # number of cpu cycles simulated +system.cpu.numCycles 108725026 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 13878911 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11630816 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 403232 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9482716 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5833581 # Number of BTB hits +system.cpu.BPredUnit.lookups 13851594 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11614390 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 401305 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9533712 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 5819078 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 911561 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 38998 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 28184398 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70994195 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13878911 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6745142 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13311939 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2031019 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37417570 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32583 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 255429 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 315513 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8617973 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 269432 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80827249 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.878345 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.221663 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 909714 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 39020 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 28116472 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70876145 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13851594 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6728792 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13285208 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2019522 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37381794 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 31979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 254614 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 318469 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 142 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8594512 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 267109 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80688804 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.878389 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.221787 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67515310 83.53% 83.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 859289 1.06% 84.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1709305 2.11% 86.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 824937 1.02% 87.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2774546 3.43% 91.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 565272 0.70% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 652347 0.81% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1007085 1.25% 93.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4919158 6.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67403596 83.54% 83.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 853020 1.06% 84.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1704381 2.11% 86.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 825297 1.02% 87.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2770281 3.43% 91.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 565024 0.70% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 647860 0.80% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1009692 1.25% 93.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4909653 6.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80827249 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.127485 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.652119 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29306094 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37119542 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12159527 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 975132 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1266953 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 590499 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43097 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69660736 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 130298 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1266953 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30443941 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13656496 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19805604 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11392846 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4261407 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65802441 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6765 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 504009 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1491914 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43932847 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79894315 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79415060 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479255 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38191269 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5741570 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1687796 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 244874 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12188114 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10482106 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6925475 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1313213 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 855117 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58302952 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2055207 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56888280 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 110464 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6988476 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3659625 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1390229 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80827249 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.703826 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.364551 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80688804 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.127400 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.651884 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29267449 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37052866 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12136986 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 973710 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1257792 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 584936 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42720 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69563521 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129851 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1257792 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30404358 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13652369 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19747652 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11366309 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4260322 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65705710 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6891 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 503348 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1491459 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43870153 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79781182 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79301924 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479258 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38177024 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5693121 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1683221 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 240085 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12184382 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10464940 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6914709 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1324795 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 859458 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58224316 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2050276 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56824991 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 109552 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6935340 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3625371 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1389407 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80688804 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.704249 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.364971 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56119293 69.43% 69.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10851228 13.43% 82.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5175866 6.40% 89.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3389461 4.19% 93.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2645582 3.27% 96.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1466047 1.81% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 750476 0.93% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 332850 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 96446 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56018871 69.43% 69.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10823549 13.41% 82.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5172467 6.41% 89.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3386571 4.20% 93.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2641337 3.27% 96.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1466438 1.82% 98.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 753039 0.93% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 331233 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 95299 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80827249 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80688804 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91026 11.51% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 373270 47.20% 58.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326472 41.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 89852 11.44% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 373396 47.53% 58.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 322395 41.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38768679 68.15% 68.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61732 0.11% 68.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38724808 68.15% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61690 0.11% 68.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.32% # Type of FU issued @@ -495,114 +495,114 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.32% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10391331 18.27% 86.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6681118 11.74% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 948891 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10379587 18.27% 86.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6673501 11.74% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948876 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56888280 # Type of FU issued -system.cpu.iq.rate 0.522549 # Inst issue rate -system.cpu.iq.fu_busy_cnt 790768 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013900 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194812399 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67023826 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55617934 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692641 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336620 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327880 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57310327 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361435 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 598219 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56824991 # Type of FU issued +system.cpu.iq.rate 0.522649 # Inst issue rate +system.cpu.iq.fu_busy_cnt 785643 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013826 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194541335 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66886966 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55559556 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692645 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336736 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327839 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57241937 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361411 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 597577 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1386761 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3497 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14147 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 544022 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1373561 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3601 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14111 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 537300 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17955 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 206298 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17953 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 206148 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1266953 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9965004 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 682330 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63888752 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 694377 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10482106 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6925475 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1810071 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 511236 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18909 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14147 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 204344 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411597 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 615941 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56420713 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10029634 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 467566 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1257792 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9964029 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 681966 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63803743 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 689880 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10464940 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6914709 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1805552 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 511141 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18669 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14111 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 204181 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411284 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 615465 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56359720 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10018596 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 465270 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3530593 # number of nop insts executed -system.cpu.iew.exec_refs 16658677 # number of memory reference insts executed -system.cpu.iew.exec_branches 8937468 # Number of branches executed -system.cpu.iew.exec_stores 6629043 # Number of stores executed -system.cpu.iew.exec_rate 0.518254 # Inst execution rate -system.cpu.iew.wb_sent 56060470 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55945814 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27785553 # num instructions producing a value -system.cpu.iew.wb_consumers 37633865 # num instructions consuming a value +system.cpu.iew.exec_nop 3529151 # number of nop insts executed +system.cpu.iew.exec_refs 16640307 # number of memory reference insts executed +system.cpu.iew.exec_branches 8921025 # Number of branches executed +system.cpu.iew.exec_stores 6621711 # Number of stores executed +system.cpu.iew.exec_rate 0.518369 # Inst execution rate +system.cpu.iew.wb_sent 56002392 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55887395 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27763328 # num instructions producing a value +system.cpu.iew.wb_consumers 37600496 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.513891 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738313 # average fanout of values written-back +system.cpu.iew.wb_rate 0.514025 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738377 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7580888 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 664978 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 571532 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79560296 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.706241 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.634825 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7517612 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660869 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 569940 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79431012 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.707112 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.636757 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58754657 73.85% 73.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8628270 10.84% 84.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4624578 5.81% 90.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2529268 3.18% 93.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1515738 1.91% 95.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 609533 0.77% 96.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 524421 0.66% 97.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 524312 0.66% 97.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1849519 2.32% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58662505 73.85% 73.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8598581 10.83% 84.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4616252 5.81% 90.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2527219 3.18% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1515396 1.91% 95.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 608578 0.77% 96.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 519366 0.65% 97.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 531746 0.67% 97.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1851369 2.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79560296 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56188709 # Number of instructions committed -system.cpu.commit.committedOps 56188709 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79431012 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56166586 # Number of instructions committed +system.cpu.commit.committedOps 56166586 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15476798 # Number of memory references committed -system.cpu.commit.loads 9095345 # Number of loads committed -system.cpu.commit.membars 226320 # Number of memory barriers committed -system.cpu.commit.branches 8447896 # Number of branches committed +system.cpu.commit.refs 15468788 # Number of memory references committed +system.cpu.commit.loads 9091379 # Number of loads committed +system.cpu.commit.membars 226331 # Number of memory barriers committed +system.cpu.commit.branches 8439881 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52034633 # Number of committed integer instructions. -system.cpu.commit.function_calls 740447 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1849519 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52016583 # Number of committed integer instructions. +system.cpu.commit.function_calls 740455 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1851369 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141230883 # The number of ROB reads -system.cpu.rob.rob_writes 128808067 # The number of ROB writes -system.cpu.timesIdled 1177683 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 28039732 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599825806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52998188 # Number of Instructions Simulated -system.cpu.committedOps 52998188 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52998188 # Number of Instructions Simulated -system.cpu.cpi 2.054164 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.054164 # CPI: Total CPI of All Threads -system.cpu.ipc 0.486816 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.486816 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73962724 # number of integer regfile reads -system.cpu.int_regfile_writes 40347354 # number of integer regfile writes -system.cpu.fp_regfile_reads 166024 # number of floating regfile reads -system.cpu.fp_regfile_writes 167429 # number of floating regfile writes -system.cpu.misc_regfile_reads 1994989 # number of misc regfile reads -system.cpu.misc_regfile_writes 947074 # number of misc regfile writes +system.cpu.rob.rob_reads 141014350 # The number of ROB reads +system.cpu.rob.rob_writes 128628080 # The number of ROB writes +system.cpu.timesIdled 1177475 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28036222 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599957129 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52976017 # Number of Instructions Simulated +system.cpu.committedOps 52976017 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52976017 # Number of Instructions Simulated +system.cpu.cpi 2.052344 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.052344 # CPI: Total CPI of All Threads +system.cpu.ipc 0.487248 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.487248 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73894396 # number of integer regfile reads +system.cpu.int_regfile_writes 40308039 # number of integer regfile writes +system.cpu.fp_regfile_reads 165978 # number of floating regfile reads +system.cpu.fp_regfile_writes 167424 # number of floating regfile writes +system.cpu.misc_regfile_reads 1987130 # number of misc regfile reads +system.cpu.misc_regfile_writes 938828 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -634,189 +634,189 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1012720 # number of replacements -system.cpu.icache.tagsinuse 510.299473 # Cycle average of tags in use -system.cpu.icache.total_refs 7548318 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1013228 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.449772 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20110483000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.299473 # Average occupied blocks per requestor +system.cpu.icache.replacements 1010112 # number of replacements +system.cpu.icache.tagsinuse 510.299453 # Cycle average of tags in use +system.cpu.icache.total_refs 7527432 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1010620 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.448331 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 20108875000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.299453 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.996679 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996679 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7548319 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7548319 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7548319 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7548319 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7548319 # number of overall hits -system.cpu.icache.overall_hits::total 7548319 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1069652 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1069652 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1069652 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1069652 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1069652 # number of overall misses -system.cpu.icache.overall_misses::total 1069652 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14542561994 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14542561994 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14542561994 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14542561994 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14542561994 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14542561994 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8617971 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8617971 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8617971 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8617971 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8617971 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8617971 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124119 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124119 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124119 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124119 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124119 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124119 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13595.601181 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13595.601181 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13595.601181 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13595.601181 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13595.601181 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13595.601181 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4808 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 32 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 175 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 27.474286 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 7527433 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7527433 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7527433 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7527433 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7527433 # number of overall hits +system.cpu.icache.overall_hits::total 7527433 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1067079 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1067079 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1067079 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1067079 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1067079 # number of overall misses +system.cpu.icache.overall_misses::total 1067079 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14519095993 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14519095993 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14519095993 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14519095993 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14519095993 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14519095993 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8594512 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8594512 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8594512 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8594512 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8594512 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8594512 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124158 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124158 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124158 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124158 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124158 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124158 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13606.392772 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13606.392772 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13606.392772 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13606.392772 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13606.392772 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13606.392772 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4279 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 166 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.777108 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1013449 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1013449 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11948814497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11948814497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11948814497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11948814497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11948814497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11948814497 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117597 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117597 # 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average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56239 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 56239 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 56239 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 56239 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 56239 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 56239 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010840 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1010840 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1010840 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1010840 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1010840 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1010840 # 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Cycle average of tags in use -system.cpu.l2cache.total_refs 2548619 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 403534 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.315748 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 338316 # number of replacements +system.cpu.l2cache.tagsinuse 65366.388920 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2545796 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 403484 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.309534 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 4043215002 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 54020.981996 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 5337.307261 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6006.672948 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15372384610 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16097576345 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 725191735 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15372384610 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16097576345 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333795500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333795500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882091500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882091500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3215887000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3215887000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014917 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248867 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136852 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.619048 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.619048 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383582 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383582 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014917 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277798 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167634 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014917 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277798 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167634 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48099.206407 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30135.610523 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31073.126568 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14231.615385 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14231.615385 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61694.142043 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61694.142043 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48099.206407 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39493.940946 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39814.836463 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48099.206407 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39493.940946 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39814.836463 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -898,161 +898,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1400783 # number of replacements +system.cpu.dcache.replacements 1400546 # number of replacements system.cpu.dcache.tagsinuse 511.995190 # Cycle average of tags in use -system.cpu.dcache.total_refs 11827578 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1401295 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 8.440463 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 11813976 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1401058 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 8.432182 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 21532000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.995190 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7213661 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7213661 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4203894 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4203894 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 190181 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 190181 # 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number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 70794455130 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 303687500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 303687500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 104919469647 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 104919469647 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 104919469647 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 104919469647 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9014786 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9014786 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147140 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147140 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 212866 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 212866 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 219615 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219615 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15161926 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15161926 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15161926 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15161926 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199797 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.199797 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316122 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316122 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.106569 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.106569 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 104612655630 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 104612655630 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 104612655630 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 104612655630 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9008542 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9008542 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147217 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147217 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208744 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 208744 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215494 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215494 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15155759 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15155759 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15155759 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15155759 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199876 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.199876 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316078 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316078 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108583 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108583 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.246959 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.246959 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.246959 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.246959 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18769.090430 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18769.090430 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36595.465344 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36595.465344 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13385.651311 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13385.651311 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.247007 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247007 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247007 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247007 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18781.764225 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18781.764225 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36435.699659 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36435.699659 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13398.372011 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13398.372011 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28020.586007 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28020.586007 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28020.586007 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28020.586007 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2640119 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 587 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 95652 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.601294 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 73.375000 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 27944.519378 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 27944.519378 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 27944.519378 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 27944.519378 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2603227 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 567 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 95613 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.226706 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 81 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840489 # number of writebacks -system.cpu.dcache.writebacks::total 840489 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717559 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 717559 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642936 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1642936 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5123 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5123 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2360495 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2360495 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2360495 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2360495 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083566 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083566 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300310 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300310 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17562 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17562 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 840422 # number of writebacks +system.cpu.dcache.writebacks::total 840422 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717194 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 717194 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642682 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1642682 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5172 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5172 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2359876 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2359876 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2359876 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2359876 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083393 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083393 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300315 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300315 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17494 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17494 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1383876 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1383876 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1383876 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1383876 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21170477000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21170477000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10817290277 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10817290277 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199800500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199800500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1383708 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1383708 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1383708 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1383708 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21171794000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21171794000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10766258774 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10766258774 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199318000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199318000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31987767277 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31987767277 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31987767277 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31987767277 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423886500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423886500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997350998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997350998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421237498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421237498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120199 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120199 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31938052774 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31938052774 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31938052774 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31938052774 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423872500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423872500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997246998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997246998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421119498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421119498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120263 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120263 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082503 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082503 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083806 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083806 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091273 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091273 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19537.782655 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19537.782655 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36020.413163 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36020.413163 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11376.864822 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11376.864822 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091299 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091299 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091299 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091299 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19542.118142 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19542.118142 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35849.886865 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35849.886865 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11393.506345 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11393.506345 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23114.619574 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23114.619574 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23114.619574 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23114.619574 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23081.497523 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23081.497523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23081.497523 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23081.497523 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1061,28 +1061,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6436 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 210973 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74651 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210969 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74649 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105545 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182205 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73284 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105543 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182201 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73282 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73284 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148577 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818516202000 98.07% 98.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64252000 0.00% 98.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 558035000 0.03% 98.10% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 35210286000 1.90% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1854348775000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_good::31 73282 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148573 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818511438500 98.07% 98.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 63990000 0.00% 98.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 557700000 0.03% 98.10% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 35210339500 1.90% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1854343468000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981688 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694339 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815439 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694333 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815435 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1121,7 +1121,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175092 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175088 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1130,7 +1130,7 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191934 # number of callpals executed +system.cpu.kern.callpal::total 191930 # number of callpals executed system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches system.cpu.kern.mode_switch::user 1741 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches @@ -1141,9 +1141,9 @@ system.cpu.kern.mode_switch_good::kernel 0.326778 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.394590 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29709775500 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2660669000 0.14% 1.75% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1821978322500 98.25% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 29685190500 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2663206500 0.14% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1821995063000 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 1c485a623..e61c2a067 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841682 # Number of seconds simulated -sim_ticks 1841681669500 # Number of ticks simulated -final_tick 1841681669500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841687 # Number of seconds simulated +sim_ticks 1841687115500 # Number of ticks simulated +final_tick 1841687115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 340900 # Simulator instruction rate (inst/s) -host_op_rate 340900 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9082220288 # Simulator tick rate (ticks/s) -host_mem_usage 309920 # Number of bytes of host memory used -host_seconds 202.78 # Real time elapsed on the host -sim_insts 69127289 # Number of instructions simulated -sim_ops 69127289 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 474944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19316864 # Number of bytes read from this memory +host_inst_rate 299654 # Simulator instruction rate (inst/s) +host_op_rate 299654 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8001020229 # Simulator tick rate (ticks/s) +host_mem_usage 317816 # Number of bytes of host memory used +host_seconds 230.18 # Real time elapsed on the host +sim_insts 68974794 # Number of instructions simulated +sim_ops 68974794 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 474496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19299136 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 149888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2832832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 295936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2722176 # Number of bytes read from this memory -system.physmem.bytes_read::total 28444928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 474944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 149888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 295936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 920768 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7479680 # Number of bytes written to this memory -system.physmem.bytes_written::total 7479680 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7421 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 301826 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 150016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2831040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 294592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2739200 # Number of bytes read from this memory +system.physmem.bytes_read::total 28440768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 474496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 150016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 294592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 919104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7474752 # Number of bytes written to this memory +system.physmem.bytes_written::total 7474752 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 301549 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2342 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 44263 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4624 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 42534 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444452 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116870 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116870 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 257886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10488709 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1440145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 81386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1538177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 160688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1478093 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15445084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 257886 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 81386 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 160688 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 499960 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4061332 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4061332 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4061332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 257886 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10488709 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1440145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 81386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1538177 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 160688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1478093 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19506416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 111038 # Total number of read requests seen -system.physmem.writeReqs 46173 # Total number of write requests seen -system.physmem.cpureqs 157553 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 7106432 # Total number of bytes read from memory -system.physmem.bytesWritten 2955072 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 7106432 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2955072 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 7 # Number of read reqs serviced by write Q +system.physmem.num_reads::cpu1.inst 2344 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 44235 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4603 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 42800 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444387 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116793 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116793 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 257642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10479053 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1440140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 81456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1537199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 159958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1487332 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15442779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 257642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 81456 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 159958 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 499055 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4058644 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4058644 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4058644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 257642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10479053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1440140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 81456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1537199 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 159958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1487332 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19501423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 111257 # Total number of read requests seen +system.physmem.writeReqs 46272 # Total number of write requests seen +system.physmem.cpureqs 157922 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 7120448 # Total number of bytes read from memory +system.physmem.bytesWritten 2961408 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 7120448 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2961408 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 8 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 41 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 7075 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6835 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6921 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6580 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7013 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 7160 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 7199 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 7200 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6995 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6907 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6539 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 7006 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 7093 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 7124 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 7176 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 6821 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 6956 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 7030 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 7021 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 7068 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6779 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6850 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 3087 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2885 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2926 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 2583 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 2986 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 3014 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 3032 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2994 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 2761 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2529 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 2745 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2938 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 3117 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 3088 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2763 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2725 # Track writes on a per bank basis +system.physmem.perBankRdReqs::8 6877 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6675 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 6909 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6929 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 7088 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 7137 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6752 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6842 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 3139 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2979 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2910 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 2542 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 2976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 2960 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 3003 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 2801 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 2642 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 2700 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 2850 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 3184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 3157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2742 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 2711 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 141 # Number of times wr buffer was full causing retry -system.physmem.totGap 1840669582000 # Total gap between requests +system.physmem.numWrRetry 191 # Number of times wr buffer was full causing retry +system.physmem.totGap 1840675056500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 111038 # Categorize read packet sizes +system.physmem.readPktSize::6 111257 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -117,7 +117,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 46314 # categorize write packet sizes +system.physmem.writePktSize::6 46463 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -129,27 +129,27 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 41 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 82621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10884 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1945 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 997 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 753 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 844 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 664 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 650 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 82762 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 10991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5832 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 985 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 747 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 800 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 662 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 53 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 742 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 511 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -162,243 +162,243 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1982 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 2005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 2007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 2004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 2002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 2001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 2012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 2011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 2007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 2006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 2005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 2003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1659441821 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 3549387821 # Sum of mem lat for all requests -system.physmem.totBusLat 444124000 # Total cycles spent in databus access -system.physmem.totBankLat 1445822000 # Total cycles spent in bank access -system.physmem.avgQLat 14945.75 # Average queueing delay per request -system.physmem.avgBankLat 13021.79 # Average bank access latency per request +system.physmem.totQLat 1656369284 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 3548083284 # Sum of mem lat for all requests +system.physmem.totBusLat 444996000 # Total cycles spent in databus access +system.physmem.totBankLat 1446718000 # Total cycles spent in bank access +system.physmem.avgQLat 14888.85 # Average queueing delay per request +system.physmem.avgBankLat 13004.32 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31967.54 # Average memory access latency -system.physmem.avgRdBW 3.86 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.86 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.60 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31893.17 # Average memory access latency +system.physmem.avgRdBW 3.87 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.61 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.87 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.61 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 0.18 # Average write queue length over time -system.physmem.readRowHits 102865 # Number of row buffer hits during reads -system.physmem.writeRowHits 29619 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.65 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 64.15 # Row buffer hit rate for writes -system.physmem.avgGap 11708274.75 # Average gap between requests -system.l2c.replacements 337510 # number of replacements -system.l2c.tagsinuse 65417.862524 # Cycle average of tags in use -system.l2c.total_refs 2476071 # Total number of references to valid blocks. -system.l2c.sampled_refs 402672 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.149102 # Average number of references to valid blocks. +system.physmem.avgWrQLen 0.16 # Average write queue length over time +system.physmem.readRowHits 103154 # Number of row buffer hits during reads +system.physmem.writeRowHits 29694 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.72 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 64.17 # 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number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 728366430 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1222975272 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1951341702 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 100921088 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1465219558 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 213196842 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2004686600 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 3784024088 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 100921088 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1465219558 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 213196842 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2004686600 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 3784024088 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 269964000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 317506000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 587470000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 337351500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 390944000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 728295500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 607315500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 708450000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1315765500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018140 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.219192 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015158 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.093752 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.027060 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.750000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.438183 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.206873 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.128294 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018140 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.287783 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015158 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.121062 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.040113 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018140 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.287783 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015158 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.121062 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.040113 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43055.071672 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 31807.525166 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 46316.932870 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 31019.059879 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 33132.342373 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 27375.666667 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 27375.666667 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34487.046875 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69102.456323 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 50268.991241 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43055.071672 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33085.389468 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 46316.932870 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 46730.380662 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40199.125568 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43055.071672 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33085.389468 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 46316.932870 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46730.380662 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40199.125568 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -509,14 +509,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.255489 # Cycle average of tags in use +system.iocache.tagsinuse 1.255760 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1693868794000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.255489 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.078468 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.078468 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1693868074000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.255760 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.078485 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.078485 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -527,12 +527,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 9177998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 9177998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 3943215289 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 3943215289 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 3952393287 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 3952393287 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 3952393287 # number of overall miss cycles -system.iocache.overall_miss_latency::total 3952393287 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 3948648289 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 3948648289 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 3957826287 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 3957826287 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 3957826287 # number of overall miss cycles +system.iocache.overall_miss_latency::total 3957826287 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -551,17 +551,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 53052.011561 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 94898.327132 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 94898.327132 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 94724.824134 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 94724.824134 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 94724.824134 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 94724.824134 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 78884 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 95029.078961 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 95029.078961 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 94855.033841 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 94855.033841 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 94855.033841 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 94855.033841 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 78872 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9633 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9708 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.188934 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.124433 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -577,12 +577,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 17349 system.iocache.overall_mshr_misses::total 17349 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5589000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 5589000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3043794338 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3043794338 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3049383338 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3049383338 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3049383338 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3049383338 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3049248779 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3049248779 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3054837779 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3054837779 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3054837779 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3054837779 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteReq accesses @@ -593,12 +593,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415794 system.iocache.overall_mshr_miss_rate::total 0.415794 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81000 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 81000 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176145.505671 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 176145.505671 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175767.095395 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 175767.095395 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175767.095395 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 175767.095395 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176461.156192 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176461.156192 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176081.490518 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176081.490518 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176081.490518 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176081.490518 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -616,22 +616,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4863195 # DTB read hits +system.cpu0.dtb.read_hits 4860289 # DTB read hits system.cpu0.dtb.read_misses 5912 # DTB read misses system.cpu0.dtb.read_acv 109 # DTB read access violations -system.cpu0.dtb.read_accesses 426831 # DTB read accesses -system.cpu0.dtb.write_hits 3494205 # DTB write hits -system.cpu0.dtb.write_misses 658 # DTB write misses +system.cpu0.dtb.read_accesses 426830 # DTB read accesses +system.cpu0.dtb.write_hits 3490049 # DTB write hits +system.cpu0.dtb.write_misses 657 # DTB write misses system.cpu0.dtb.write_acv 81 # DTB write access violations -system.cpu0.dtb.write_accesses 163149 # DTB write accesses -system.cpu0.dtb.data_hits 8357400 # DTB hits -system.cpu0.dtb.data_misses 6570 # DTB misses +system.cpu0.dtb.write_accesses 163148 # DTB write accesses +system.cpu0.dtb.data_hits 8350338 # DTB hits +system.cpu0.dtb.data_misses 6569 # DTB misses system.cpu0.dtb.data_acv 190 # DTB access violations -system.cpu0.dtb.data_accesses 589980 # DTB accesses -system.cpu0.itb.fetch_hits 2736814 # ITB hits +system.cpu0.dtb.data_accesses 589978 # DTB accesses +system.cpu0.itb.fetch_hits 2736650 # ITB hits system.cpu0.itb.fetch_misses 2973 # ITB misses system.cpu0.itb.fetch_acv 97 # ITB acv -system.cpu0.itb.fetch_accesses 2739787 # ITB accesses +system.cpu0.itb.fetch_accesses 2739623 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -644,51 +644,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928581953 # number of cpu cycles simulated +system.cpu0.numCycles 928580994 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32231633 # Number of instructions committed -system.cpu0.committedOps 32231633 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 30115221 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 167520 # Number of float alu accesses -system.cpu0.num_func_calls 807051 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4228078 # number of instructions that are conditional controls -system.cpu0.num_int_insts 30115221 # number of integer instructions -system.cpu0.num_fp_insts 167520 # number of float instructions -system.cpu0.num_int_register_reads 41941415 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22024555 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 86513 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 88077 # number of times the floating registers were written -system.cpu0.num_mem_refs 8386802 # number of memory refs -system.cpu0.num_load_insts 4883995 # Number of load instructions -system.cpu0.num_store_insts 3502807 # Number of store instructions -system.cpu0.num_idle_cycles 214040611553.999786 # Number of idle cycles -system.cpu0.num_busy_cycles -213112029600.999786 # Number of busy cycles -system.cpu0.not_idle_fraction -229.502661 # Percentage of non-idle cycles -system.cpu0.idle_fraction 230.502661 # Percentage of idle cycles +system.cpu0.committedInsts 32061485 # Number of instructions committed +system.cpu0.committedOps 32061485 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 29946926 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 167785 # Number of float alu accesses +system.cpu0.num_func_calls 806855 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4176537 # number of instructions that are conditional controls +system.cpu0.num_int_insts 29946926 # number of integer instructions +system.cpu0.num_fp_insts 167785 # number of float instructions +system.cpu0.num_int_register_reads 41669823 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21912533 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 86645 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 88213 # number of times the floating registers were written +system.cpu0.num_mem_refs 8379762 # number of memory refs +system.cpu0.num_load_insts 4881104 # Number of load instructions +system.cpu0.num_store_insts 3498658 # Number of store instructions +system.cpu0.num_idle_cycles 214035268696.310638 # Number of idle cycles +system.cpu0.num_busy_cycles -213106687702.310638 # Number of busy cycles +system.cpu0.not_idle_fraction -229.497146 # Percentage of non-idle cycles +system.cpu0.idle_fraction 230.497146 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6419 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211372 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74800 40.97% 40.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6422 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211380 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74799 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 205 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105685 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182566 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73433 49.30% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 105691 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182573 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73432 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 205 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73433 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148947 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818611622000 98.75% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39272500 0.00% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 363381500 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22666637000 1.23% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841680913000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::total 148948 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818622166500 98.75% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39746000 0.00% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 363817000 0.02% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22660629500 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841686359000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694829 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815853 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694790 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815827 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -724,33 +724,33 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4175 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175309 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175314 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192221 # number of callpals executed +system.cpu0.kern.callpal::total 192228 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1736 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1905 -system.cpu0.kern.mode_good::user 1736 -system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.321682 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1908 +system.cpu0.kern.mode_good::user 1738 +system.cpu0.kern.mode_good::idle 170 +system.cpu0.kern.mode_switch_good::kernel 0.322188 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.390689 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29776947000 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2543344500 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809360618000 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4176 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29768907500 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2544697000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809372751000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -782,372 +782,372 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 954146 # number of replacements -system.cpu0.icache.tagsinuse 511.198138 # Cycle average of tags in use -system.cpu0.icache.total_refs 41733941 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 954657 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 43.716163 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 10235539000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 257.559886 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 79.204756 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 174.433495 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.503047 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.154697 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.340690 # Average percentage of cache occupancy +system.cpu0.icache.replacements 953436 # number of replacements +system.cpu0.icache.tagsinuse 511.198067 # Cycle average of tags in use +system.cpu0.icache.total_refs 41560742 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 953947 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 43.567139 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 10234504000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 256.477356 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 79.519770 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 175.200941 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.500932 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.155312 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.342189 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998434 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 31717072 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7719142 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2297727 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 41733941 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31717072 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7719142 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2297727 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 41733941 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31717072 # 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number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32238393 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7848374 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2618902 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 42705669 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32238393 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7848374 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2618902 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 42705669 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32238393 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7848374 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2618902 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 42705669 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016171 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016466 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122637 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.022754 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016171 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016466 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122637 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.022754 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016171 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016466 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122637 # 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number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 179 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 117 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.410256 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 179 # average number of cycles each access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 31547031 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7721485 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2292226 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 41560742 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31547031 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7721485 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2292226 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 41560742 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31547031 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7721485 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2292226 # number of overall hits +system.cpu0.icache.overall_hits::total 41560742 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 521213 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 129218 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 320460 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 970891 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 521213 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 129218 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 320460 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 970891 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 521213 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 129218 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 320460 # number of overall misses +system.cpu0.icache.overall_misses::total 970891 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1794259500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4426264489 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6220523989 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1794259500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4426264489 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6220523989 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1794259500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4426264489 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6220523989 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32068244 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7850703 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2612686 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 42531633 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32068244 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7850703 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2612686 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 42531633 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32068244 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7850703 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2612686 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 42531633 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016253 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016459 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122655 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.022828 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016253 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016459 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122655 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.022828 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016253 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016459 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122655 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.022828 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13885.522915 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13812.221460 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6407.026112 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13885.522915 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13812.221460 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6407.026112 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13885.522915 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13812.221460 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6407.026112 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1940 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 125 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.520000 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16896 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16896 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16896 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16896 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16896 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16896 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 129232 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 304279 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 433511 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 129232 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 304279 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 433511 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 129232 # 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average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12000.021329 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11965.482975 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11884.161818 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12000.021329 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11965.482975 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11884.161818 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12000.021329 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11965.482975 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16767 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16767 # 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number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5184947491 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016459 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116238 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010179 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016459 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116238 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010179 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016459 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116238 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010179 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11885.522915 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12015.831748 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11976.936347 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11885.522915 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12015.831748 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11976.936347 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11885.522915 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12015.831748 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11976.936347 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1392176 # number of replacements +system.cpu0.dcache.replacements 1392058 # number of replacements system.cpu0.dcache.tagsinuse 511.997817 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13319375 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1392688 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.563790 # Average number of references to valid blocks. +system.cpu0.dcache.total_refs 13312306 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1392570 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.559524 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 250.475263 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 85.370425 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 176.152129 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.489209 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.166739 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.344047 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 249.308176 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 86.874382 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 175.815259 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.486930 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.169677 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.343389 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4041121 # 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number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8921890 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3367714 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 907554 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1873555 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6148823 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 125932 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21616 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 56694 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 204242 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125372 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3275303000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6597259126 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9872562126 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 289521000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 340019500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 629540500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 358537000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 415967500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 774504500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 648058000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 755987000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1404045000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086324 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088326 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041052 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053132 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045342 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021658 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102147 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.097682 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037926 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072034 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071711 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033139 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072034 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071711 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033139 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18853.343626 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16356.086510 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17062.663135 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27406.283700 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27093.973302 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27207.058038 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11218.070652 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12702.419646 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12279.305448 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 835817 # number of writebacks +system.cpu0.dcache.writebacks::total 835817 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 286842 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 286842 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 477332 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 477332 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1469 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1469 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 764174 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 764174 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 764174 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 764174 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 103484 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 263389 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 366873 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 48200 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 85309 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 133509 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2204 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5672 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7876 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 151684 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 348698 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 500382 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 151684 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 348698 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 500382 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1947142500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4307606000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6254748500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1320543000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2299251630 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3619794630 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24631000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 72250500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96881500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3267685500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6606857630 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9874543130 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3267685500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6606857630 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9874543130 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 288177500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 339273500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 627451000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357416500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 414861500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 772278000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 645594000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 754135000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1399729000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086179 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088589 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041134 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053154 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045410 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021712 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101943 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.101948 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.038763 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000038 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000010 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.071970 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071870 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033208 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.071970 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071870 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033208 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18815.879750 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16354.540243 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17048.811169 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27397.157676 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26952.040582 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27112.738692 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11175.589837 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12738.099436 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12300.850686 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21569.331577 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18980.494118 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19767.619803 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21569.331577 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18980.494118 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19767.619803 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21542.717096 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18947.219743 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19734.009477 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21542.717096 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18947.219743 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19734.009477 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1162,22 +1162,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1219761 # DTB read hits +system.cpu1.dtb.read_hits 1220100 # DTB read hits system.cpu1.dtb.read_misses 1488 # DTB read misses system.cpu1.dtb.read_acv 40 # DTB read access violations system.cpu1.dtb.read_accesses 143779 # DTB read accesses -system.cpu1.dtb.write_hits 929431 # DTB write hits +system.cpu1.dtb.write_hits 928690 # DTB write hits system.cpu1.dtb.write_misses 201 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 59743 # DTB write accesses -system.cpu1.dtb.data_hits 2149192 # DTB hits +system.cpu1.dtb.data_hits 2148790 # DTB hits system.cpu1.dtb.data_misses 1689 # DTB misses system.cpu1.dtb.data_acv 64 # DTB access violations system.cpu1.dtb.data_accesses 203522 # DTB accesses -system.cpu1.itb.fetch_hits 873235 # ITB hits +system.cpu1.itb.fetch_hits 872643 # ITB hits system.cpu1.itb.fetch_misses 756 # ITB misses system.cpu1.itb.fetch_acv 43 # ITB acv -system.cpu1.itb.fetch_accesses 873991 # ITB accesses +system.cpu1.itb.fetch_accesses 873399 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1190,28 +1190,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953535739 # number of cpu cycles simulated +system.cpu1.numCycles 953546573 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7846620 # Number of instructions committed -system.cpu1.committedOps 7846620 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7299077 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45739 # Number of float alu accesses -system.cpu1.num_func_calls 212215 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 957639 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7299077 # number of integer instructions -system.cpu1.num_fp_insts 45739 # number of float instructions -system.cpu1.num_int_register_reads 10142741 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5309758 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24689 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24953 # number of times the floating registers were written -system.cpu1.num_mem_refs 2156913 # number of memory refs -system.cpu1.num_load_insts 1225031 # Number of load instructions -system.cpu1.num_store_insts 931882 # Number of store instructions -system.cpu1.num_idle_cycles -1658749274.077502 # Number of idle cycles -system.cpu1.num_busy_cycles 2612285013.077502 # Number of busy cycles -system.cpu1.not_idle_fraction 2.739577 # Percentage of non-idle cycles -system.cpu1.idle_fraction -1.739577 # Percentage of idle cycles +system.cpu1.committedInsts 7848949 # Number of instructions committed +system.cpu1.committedOps 7848949 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7301756 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45390 # Number of float alu accesses +system.cpu1.num_func_calls 212250 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 958041 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7301756 # number of integer instructions +system.cpu1.num_fp_insts 45390 # number of float instructions +system.cpu1.num_int_register_reads 10145726 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5312805 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24524 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24770 # number of times the floating registers were written +system.cpu1.num_mem_refs 2156479 # number of memory refs +system.cpu1.num_load_insts 1225350 # Number of load instructions +system.cpu1.num_store_insts 931129 # Number of store instructions +system.cpu1.num_idle_cycles -1690648572.086683 # Number of idle cycles +system.cpu1.num_busy_cycles 2644195145.086683 # Number of busy cycles +system.cpu1.not_idle_fraction 2.773011 # Percentage of non-idle cycles +system.cpu1.idle_fraction -1.773011 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1233,22 +1233,22 @@ system.cpu2.dtb.fetch_hits 0 # IT system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3234016 # DTB read hits -system.cpu2.dtb.read_misses 12170 # DTB read misses -system.cpu2.dtb.read_acv 136 # DTB read access violations -system.cpu2.dtb.read_accesses 218383 # DTB read accesses -system.cpu2.dtb.write_hits 2000862 # DTB write hits -system.cpu2.dtb.write_misses 2630 # DTB write misses -system.cpu2.dtb.write_acv 139 # DTB write access violations -system.cpu2.dtb.write_accesses 81465 # DTB write accesses -system.cpu2.dtb.data_hits 5234878 # DTB hits -system.cpu2.dtb.data_misses 14800 # DTB misses -system.cpu2.dtb.data_acv 275 # DTB access violations -system.cpu2.dtb.data_accesses 299848 # DTB accesses -system.cpu2.itb.fetch_hits 374542 # ITB hits -system.cpu2.itb.fetch_misses 5731 # ITB misses -system.cpu2.itb.fetch_acv 284 # ITB acv -system.cpu2.itb.fetch_accesses 380273 # ITB accesses +system.cpu2.dtb.read_hits 3233315 # DTB read hits +system.cpu2.dtb.read_misses 12189 # DTB read misses +system.cpu2.dtb.read_acv 135 # DTB read access violations +system.cpu2.dtb.read_accesses 219207 # DTB read accesses +system.cpu2.dtb.write_hits 2006633 # DTB write hits +system.cpu2.dtb.write_misses 2635 # DTB write misses +system.cpu2.dtb.write_acv 145 # DTB write access violations +system.cpu2.dtb.write_accesses 81760 # DTB write accesses +system.cpu2.dtb.data_hits 5239948 # DTB hits +system.cpu2.dtb.data_misses 14824 # DTB misses +system.cpu2.dtb.data_acv 280 # DTB access violations +system.cpu2.dtb.data_accesses 300967 # DTB accesses +system.cpu2.itb.fetch_hits 374893 # ITB hits +system.cpu2.itb.fetch_misses 5781 # ITB misses +system.cpu2.itb.fetch_acv 261 # ITB acv +system.cpu2.itb.fetch_accesses 380674 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1261,278 +1261,278 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30548805 # number of cpu cycles simulated +system.cpu2.numCycles 30553382 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 8364028 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 7669410 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 129868 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 6711241 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 5709819 # Number of BTB hits +system.cpu2.BPredUnit.lookups 8367198 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 7675066 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 129021 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 6898028 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 5713360 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 287796 # Number of times the RAS was used to get a target. -system.cpu2.BPredUnit.RASInCorrect 15290 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 8565342 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 34820498 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8364028 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 5997615 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8085140 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 623390 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9684769 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 10169 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1946 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 65267 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 78430 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 219 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2618903 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 90402 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 26897224 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.294576 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.310232 # Number of instructions fetched each cycle (Total) +system.cpu2.BPredUnit.usedRAS 286292 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.RASInCorrect 15213 # Number of incorrect RAS predictions. +system.cpu2.fetch.icacheStallCycles 8548806 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 34839646 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8367198 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 5999652 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8085881 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 623525 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9702754 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 9910 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1956 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 65426 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 78066 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 227 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2612689 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 89635 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 26899441 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.295181 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.310992 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18812084 69.94% 69.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 275091 1.02% 70.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 443313 1.65% 72.61% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4200168 15.62% 88.23% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 736557 2.74% 90.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 167312 0.62% 91.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 197037 0.73% 92.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 432029 1.61% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1633633 6.07% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18813560 69.94% 69.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 273460 1.02% 70.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 442537 1.65% 72.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4198605 15.61% 88.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 738968 2.75% 90.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 167733 0.62% 91.58% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 196064 0.73% 92.31% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433736 1.61% 93.92% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1634778 6.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 26897224 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.273792 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.139832 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8682356 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9793254 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7488405 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 293704 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 393556 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 170875 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13042 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34420320 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40663 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 393556 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 9037496 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2819097 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5808677 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7346220 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1246237 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33260279 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2326 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 233903 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 407997 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 22331754 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41424509 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41259136 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 165373 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20496437 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1835317 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 510420 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 61593 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3691952 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3399315 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2093436 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 371907 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 254715 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30727225 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 632539 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30272118 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 35753 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2189784 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1100567 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 445757 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 26897224 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.125474 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.564893 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 26899441 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.273855 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.140288 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8679846 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9796545 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7488897 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 294076 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 394122 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 169250 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12966 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34438242 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 40605 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 394122 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 9036155 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2833856 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5793548 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7343930 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1251886 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33280862 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2342 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 235752 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 410323 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 22341851 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 41449381 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41284168 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 165213 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20505105 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1836746 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 509428 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 60335 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3708993 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3395949 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2096293 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 374269 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 256431 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 30745321 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 631973 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 30290863 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 30934 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2196077 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1091992 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 446408 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 26899441 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.126078 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.565187 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15350394 57.07% 57.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3115885 11.58% 68.65% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1557090 5.79% 74.44% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5021564 18.67% 93.11% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 911830 3.39% 96.50% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 491728 1.83% 98.33% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 288005 1.07% 99.40% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 142453 0.53% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18275 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15349062 57.06% 57.06% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3113388 11.57% 68.64% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1556519 5.79% 74.42% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5024470 18.68% 93.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 916558 3.41% 96.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 490691 1.82% 98.33% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 288280 1.07% 99.40% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 142124 0.53% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18349 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 26897224 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 26899441 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 35285 14.01% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 14.01% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 113269 44.96% 58.96% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 103382 41.04% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 35139 13.92% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.92% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 113314 44.90% 58.82% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 103925 41.18% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24555706 81.12% 81.12% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20320 0.07% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 24571272 81.12% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20288 0.07% 81.19% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8506 0.03% 81.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8510 0.03% 81.22% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.22% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.22% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.22% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3366886 11.12% 92.35% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2024055 6.69% 99.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 292961 0.97% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.23% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3364677 11.11% 92.33% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2029119 6.70% 99.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 293313 0.97% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30272118 # Type of FU issued -system.cpu2.iq.rate 0.990943 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 251936 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.008322 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 87492046 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33437480 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 29866501 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 237103 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 115982 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 112325 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30398156 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 123442 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 190063 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 30290863 # Type of FU issued +system.cpu2.iq.rate 0.991408 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 252378 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.008332 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 87527172 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 33461701 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 29889528 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 237307 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 115799 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 112442 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 30417117 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 123668 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 190380 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 422258 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 952 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4004 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 162752 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 417328 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 909 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4219 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 161835 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4980 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 23112 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5028 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 23504 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 393556 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2038103 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 212197 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32647760 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 228888 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3399315 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2093436 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 561709 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 150503 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2400 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4004 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 66845 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 130356 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197201 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30107405 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3254707 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 164713 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 394122 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2048539 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 212384 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32667767 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 225947 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3395949 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2096293 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 561038 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 149803 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2446 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4219 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 66256 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 130204 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 196460 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 30129770 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3254028 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 161093 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1287996 # number of nop insts executed -system.cpu2.iew.exec_refs 5262746 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6765344 # Number of branches executed -system.cpu2.iew.exec_stores 2008039 # Number of stores executed -system.cpu2.iew.exec_rate 0.985551 # Inst execution rate -system.cpu2.iew.wb_sent 30012235 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 29978826 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17295143 # num instructions producing a value -system.cpu2.iew.wb_consumers 20538847 # num instructions consuming a value +system.cpu2.iew.exec_nop 1290473 # number of nop insts executed +system.cpu2.iew.exec_refs 5267847 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6767321 # Number of branches executed +system.cpu2.iew.exec_stores 2013819 # Number of stores executed +system.cpu2.iew.exec_rate 0.986135 # Inst execution rate +system.cpu2.iew.wb_sent 30034994 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 30001970 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17305763 # num instructions producing a value +system.cpu2.iew.wb_consumers 20552521 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.981342 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.842070 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.981953 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.842026 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2374409 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 186782 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 183048 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26503668 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.140514 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.850633 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2377399 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 185565 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 182360 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26505319 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.141095 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.851284 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16405527 61.90% 61.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2337415 8.82% 70.72% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1218938 4.60% 75.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4753611 17.94% 93.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 502619 1.90% 95.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 186793 0.70% 95.85% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 180491 0.68% 96.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 181897 0.69% 97.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 736377 2.78% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16405167 61.89% 61.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2334119 8.81% 70.70% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1221930 4.61% 75.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4753276 17.93% 93.24% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 503631 1.90% 95.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 187421 0.71% 95.85% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 180293 0.68% 96.53% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 181960 0.69% 97.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 737522 2.78% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26503668 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30227806 # Number of instructions committed -system.cpu2.commit.committedOps 30227806 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26505319 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30245090 # Number of instructions committed +system.cpu2.commit.committedOps 30245090 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4907741 # Number of memory references committed -system.cpu2.commit.loads 2977057 # Number of loads committed -system.cpu2.commit.membars 65125 # Number of memory barriers committed -system.cpu2.commit.branches 6615814 # Number of branches committed -system.cpu2.commit.fp_insts 111064 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28762873 # Number of committed integer instructions. -system.cpu2.commit.function_calls 231817 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 736377 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4913079 # Number of memory references committed +system.cpu2.commit.loads 2978621 # Number of loads committed +system.cpu2.commit.membars 65145 # Number of memory barriers committed +system.cpu2.commit.branches 6616794 # Number of branches committed +system.cpu2.commit.fp_insts 111215 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28779164 # Number of committed integer instructions. +system.cpu2.commit.function_calls 231926 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 737522 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 58294713 # The number of ROB reads -system.cpu2.rob.rob_writes 65597739 # The number of ROB writes -system.cpu2.timesIdled 244101 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3651581 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745276463 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 29049036 # Number of Instructions Simulated -system.cpu2.committedOps 29049036 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 29049036 # Number of Instructions Simulated -system.cpu2.cpi 1.051629 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.051629 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.950906 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.950906 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39585060 # number of integer regfile reads -system.cpu2.int_regfile_writes 21198431 # number of integer regfile writes -system.cpu2.fp_regfile_reads 68487 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68830 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4557721 # number of misc regfile reads -system.cpu2.misc_regfile_writes 264115 # number of misc regfile writes +system.cpu2.rob.rob_reads 58315466 # The number of ROB reads +system.cpu2.rob.rob_writes 65639010 # The number of ROB writes +system.cpu2.timesIdled 244602 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3653941 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745271968 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 29064360 # Number of Instructions Simulated +system.cpu2.committedOps 29064360 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 29064360 # Number of Instructions Simulated +system.cpu2.cpi 1.051232 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.051232 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.951265 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.951265 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 39620111 # number of integer regfile reads +system.cpu2.int_regfile_writes 21211926 # number of integer regfile writes +system.cpu2.fp_regfile_reads 68528 # number of floating regfile reads +system.cpu2.fp_regfile_writes 68903 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4553685 # number of misc regfile reads +system.cpu2.misc_regfile_writes 261693 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed |