diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
| commit | 0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e (patch) | |
| tree | 45d559d0511bdca749a08a2f42eeafdcf25739cf /tests/long/fs/10.linux-boot/ref/alpha | |
| parent | 3de9def6c1ad38d6a5068b07512cbefffafcb758 (diff) | |
| download | gem5-0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e.tar.xz | |
stats: updates due to recent changesets including d0934b57735a
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
10 files changed, 5173 insertions, 5190 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini index a7c751a3c..db58f5ad6 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini @@ -141,7 +141,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -564,7 +564,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -613,7 +613,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -747,7 +747,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=0:134217727 assoc=8 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index b894ed506..96524a9ce 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,92 +1,92 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.886196 # Number of seconds simulated -sim_ticks 1886195993000 # Number of ticks simulated -final_tick 1886195993000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.887168 # Number of seconds simulated +sim_ticks 1887168480000 # Number of ticks simulated +final_tick 1887168480000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 256659 # Simulator instruction rate (inst/s) -host_op_rate 256659 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8626071053 # Simulator tick rate (ticks/s) -host_mem_usage 374008 # Number of bytes of host memory used -host_seconds 218.66 # Real time elapsed on the host -sim_insts 56121694 # Number of instructions simulated -sim_ops 56121694 # Number of ops (including micro ops) simulated +host_inst_rate 181674 # Simulator instruction rate (inst/s) +host_op_rate 181674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6108559174 # Simulator tick rate (ticks/s) +host_mem_usage 367844 # Number of bytes of host memory used +host_seconds 308.94 # Real time elapsed on the host +sim_insts 56125948 # Number of instructions simulated +sim_ops 56125948 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1049728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24850240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1049920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24850048 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 25900928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1049728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1049728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7553600 # Number of bytes written to this memory -system.physmem.bytes_written::total 7553600 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16402 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388285 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 1049920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1049920 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7553472 # Number of bytes written to this memory +system.physmem.bytes_written::total 7553472 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16405 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388282 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 404702 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118025 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118025 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 556532 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13174792 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::writebacks 118023 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118023 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 556347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13167901 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13731833 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 556532 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 556532 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4004674 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4004674 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4004674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 556532 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13174792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13724757 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 556347 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 556347 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4002542 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4002542 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4002542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 556347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13167901 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17736507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17727299 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 404702 # Number of read requests accepted -system.physmem.writeReqs 118025 # Number of write requests accepted +system.physmem.writeReqs 118023 # Number of write requests accepted system.physmem.readBursts 404702 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118025 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25894272 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue -system.physmem.bytesWritten 7551808 # Total number of bytes written to DRAM +system.physmem.writeBursts 118023 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25893824 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue +system.physmem.bytesWritten 7551936 # Total number of bytes written to DRAM system.physmem.bytesReadSys 25900928 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7553600 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytesWrittenSys 7553472 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 41706 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25487 # Per bank write bursts -system.physmem.perBankRdBursts::1 25728 # Per bank write bursts -system.physmem.perBankRdBursts::2 25822 # Per bank write bursts -system.physmem.perBankRdBursts::3 25769 # Per bank write bursts -system.physmem.perBankRdBursts::4 25085 # Per bank write bursts -system.physmem.perBankRdBursts::5 25016 # Per bank write bursts -system.physmem.perBankRdBursts::6 24650 # Per bank write bursts -system.physmem.perBankRdBursts::7 24524 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 41707 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25482 # Per bank write bursts +system.physmem.perBankRdBursts::1 25721 # Per bank write bursts +system.physmem.perBankRdBursts::2 25818 # Per bank write bursts +system.physmem.perBankRdBursts::3 25768 # Per bank write bursts +system.physmem.perBankRdBursts::4 25084 # Per bank write bursts +system.physmem.perBankRdBursts::5 25019 # Per bank write bursts +system.physmem.perBankRdBursts::6 24651 # Per bank write bursts +system.physmem.perBankRdBursts::7 24525 # Per bank write bursts system.physmem.perBankRdBursts::8 25293 # Per bank write bursts -system.physmem.perBankRdBursts::9 25190 # Per bank write bursts -system.physmem.perBankRdBursts::10 25398 # Per bank write bursts -system.physmem.perBankRdBursts::11 24986 # Per bank write bursts -system.physmem.perBankRdBursts::12 24522 # Per bank write bursts -system.physmem.perBankRdBursts::13 25563 # Per bank write bursts -system.physmem.perBankRdBursts::14 25828 # Per bank write bursts -system.physmem.perBankRdBursts::15 25737 # Per bank write bursts -system.physmem.perBankWrBursts::0 7820 # Per bank write bursts -system.physmem.perBankWrBursts::1 7688 # Per bank write bursts -system.physmem.perBankWrBursts::2 8067 # Per bank write bursts +system.physmem.perBankRdBursts::9 25189 # Per bank write bursts +system.physmem.perBankRdBursts::10 25397 # Per bank write bursts +system.physmem.perBankRdBursts::11 24988 # Per bank write bursts +system.physmem.perBankRdBursts::12 24521 # Per bank write bursts +system.physmem.perBankRdBursts::13 25565 # Per bank write bursts +system.physmem.perBankRdBursts::14 25830 # Per bank write bursts +system.physmem.perBankRdBursts::15 25740 # Per bank write bursts +system.physmem.perBankWrBursts::0 7815 # Per bank write bursts +system.physmem.perBankWrBursts::1 7682 # Per bank write bursts +system.physmem.perBankWrBursts::2 8062 # Per bank write bursts system.physmem.perBankWrBursts::3 7737 # Per bank write bursts system.physmem.perBankWrBursts::4 7196 # Per bank write bursts -system.physmem.perBankWrBursts::5 7011 # Per bank write bursts -system.physmem.perBankWrBursts::6 6646 # Per bank write bursts -system.physmem.perBankWrBursts::7 6392 # Per bank write bursts -system.physmem.perBankWrBursts::8 7401 # Per bank write bursts -system.physmem.perBankWrBursts::9 6804 # Per bank write bursts -system.physmem.perBankWrBursts::10 7278 # Per bank write bursts -system.physmem.perBankWrBursts::11 6972 # Per bank write bursts +system.physmem.perBankWrBursts::5 7012 # Per bank write bursts +system.physmem.perBankWrBursts::6 6647 # Per bank write bursts +system.physmem.perBankWrBursts::7 6398 # Per bank write bursts +system.physmem.perBankWrBursts::8 7404 # Per bank write bursts +system.physmem.perBankWrBursts::9 6806 # Per bank write bursts +system.physmem.perBankWrBursts::10 7277 # Per bank write bursts +system.physmem.perBankWrBursts::11 6969 # Per bank write bursts system.physmem.perBankWrBursts::12 7052 # Per bank write bursts -system.physmem.perBankWrBursts::13 8008 # Per bank write bursts -system.physmem.perBankWrBursts::14 7983 # Per bank write bursts -system.physmem.perBankWrBursts::15 7942 # Per bank write bursts +system.physmem.perBankWrBursts::13 8011 # Per bank write bursts +system.physmem.perBankWrBursts::14 7982 # Per bank write bursts +system.physmem.perBankWrBursts::15 7949 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 17 # Number of times write queue was full causing retry -system.physmem.totGap 1886187226500 # Total gap between requests +system.physmem.numWrRetry 29 # Number of times write queue was full causing retry +system.physmem.totGap 1887159671500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -100,10 +100,10 @@ system.physmem.writePktSize::2 0 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118025 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402327 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118023 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402323 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 2193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -148,188 +148,187 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63594 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 525.931377 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 320.890659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 414.200803 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14460 22.74% 22.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10997 17.29% 40.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4933 7.76% 47.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3625 5.70% 53.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2479 3.90% 57.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1827 2.87% 60.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1418 2.23% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1367 2.15% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22488 35.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63594 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5295 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.408121 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2902.928186 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5292 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 94 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.182842 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 320.768050 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 414.563237 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14483 22.79% 22.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10991 17.29% 40.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4893 7.70% 47.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3583 5.64% 53.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2419 3.81% 57.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1815 2.86% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1455 2.29% 62.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1407 2.21% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22517 35.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63563 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5279 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.639515 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2907.321691 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5276 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5295 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5295 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.284608 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.797942 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.673735 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4676 88.31% 88.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 227 4.29% 92.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 77 1.45% 94.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 16 0.30% 94.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 14 0.26% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 6 0.11% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 7 0.13% 94.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 9 0.17% 95.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 7 0.13% 95.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 34 0.64% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 171 3.23% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 10 0.19% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.02% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 5 0.09% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.04% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.08% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 4 0.08% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 8 0.15% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.04% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 7 0.13% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5295 # Writes before turning the bus around for reads -system.physmem.totQLat 2213284250 # Total ticks spent queuing -system.physmem.totMemAccLat 9799496750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2022990000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5470.33 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5279 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5279 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.352529 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.833418 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.552708 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4665 88.37% 88.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 223 4.22% 92.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 69 1.31% 93.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 13 0.25% 94.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 7 0.13% 94.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 8 0.15% 94.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 10 0.19% 94.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 11 0.21% 94.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 9 0.17% 95.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 33 0.63% 95.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 187 3.54% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 5 0.09% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 2 0.04% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.04% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 7 0.13% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.02% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.06% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 3 0.06% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.11% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.04% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 9 0.17% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5279 # Writes before turning the bus around for reads +system.physmem.totQLat 2194493000 # Total ticks spent queuing +system.physmem.totMemAccLat 9780574250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2022955000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5423.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24220.33 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24173.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.72 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.72 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.19 # Average write queue length when enqueuing -system.physmem.readRowHits 363516 # Number of row buffer hits during reads -system.physmem.writeRowHits 95485 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.85 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.90 # Row buffer hit rate for writes -system.physmem.avgGap 3608360.06 # Average gap between requests +system.physmem.avgWrQLen 21.87 # Average write queue length when enqueuing +system.physmem.readRowHits 363582 # Number of row buffer hits during reads +system.physmem.writeRowHits 95445 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.86 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.87 # Row buffer hit rate for writes +system.physmem.avgGap 3610234.20 # Average gap between requests system.physmem.pageHitRate 87.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 233845920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127594500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1576231800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 379449360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 123197134320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 60326866845 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1078799265750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1264640388495 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.471373 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1794467110750 # Time in different power states -system.physmem_0.memoryStateTime::REF 62984220000 # Time in different power states +system.physmem_0.actEnergy 233596440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127458375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1576130400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 379397520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 123260195760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 60352481790 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1079356093500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1265285353785 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.470116 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1795392967750 # Time in different power states +system.physmem_0.memoryStateTime::REF 63016460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28744633000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 28752031000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 246924720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134730750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579632600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385171200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 123197134320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61494025635 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1077775442250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1264813061475 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.562919 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1792762379750 # Time in different power states -system.physmem_1.memoryStateTime::REF 62984220000 # Time in different power states +system.physmem_1.actEnergy 246939840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134739000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579679400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385236000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 123260195760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61300664820 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1078524362250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1265431817070 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.547722 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1794008459000 # Time in different power states +system.physmem_1.memoryStateTime::REF 63016460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30449364000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30136553500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 15004879 # Number of BP lookups -system.cpu.branchPred.condPredicted 13013312 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 375549 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10036322 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5207234 # Number of BTB hits +system.cpu.branchPred.lookups 14997890 # Number of BP lookups +system.cpu.branchPred.condPredicted 13009268 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 370594 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9393435 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5198350 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 51.883887 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 808293 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 31321 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 55.340246 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 807960 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32049 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9242647 # DTB read hits -system.cpu.dtb.read_misses 17811 # DTB read misses +system.cpu.dtb.read_hits 9241004 # DTB read hits +system.cpu.dtb.read_misses 17472 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766734 # DTB read accesses -system.cpu.dtb.write_hits 6385782 # DTB write hits -system.cpu.dtb.write_misses 2309 # DTB write misses +system.cpu.dtb.read_accesses 766036 # DTB read accesses +system.cpu.dtb.write_hits 6386411 # DTB write hits +system.cpu.dtb.write_misses 2301 # DTB write misses system.cpu.dtb.write_acv 160 # DTB write access violations -system.cpu.dtb.write_accesses 298407 # DTB write accesses -system.cpu.dtb.data_hits 15628429 # DTB hits -system.cpu.dtb.data_misses 20120 # DTB misses +system.cpu.dtb.write_accesses 298419 # DTB write accesses +system.cpu.dtb.data_hits 15627415 # DTB hits +system.cpu.dtb.data_misses 19773 # DTB misses system.cpu.dtb.data_acv 371 # DTB access violations -system.cpu.dtb.data_accesses 1065141 # DTB accesses -system.cpu.itb.fetch_hits 4016387 # ITB hits -system.cpu.itb.fetch_misses 6834 # ITB misses -system.cpu.itb.fetch_acv 689 # ITB acv -system.cpu.itb.fetch_accesses 4023221 # ITB accesses +system.cpu.dtb.data_accesses 1064455 # DTB accesses +system.cpu.itb.fetch_hits 4013195 # ITB hits +system.cpu.itb.fetch_misses 6857 # ITB misses +system.cpu.itb.fetch_acv 677 # ITB acv +system.cpu.itb.fetch_accesses 4020052 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -342,39 +341,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 180216793 # number of cpu cycles simulated +system.cpu.numCycles 182043546 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56121694 # Number of instructions committed -system.cpu.committedOps 56121694 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2519198 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5577 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3592175193 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.211179 # CPI: cycles per instruction -system.cpu.ipc 0.311412 # IPC: instructions per cycle +system.cpu.committedInsts 56125948 # Number of instructions committed +system.cpu.committedOps 56125948 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2502558 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5565 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3594204473 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.243483 # CPI: cycles per instruction +system.cpu.ipc 0.308311 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211471 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74788 40.94% 40.94% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 133 0.07% 41.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105864 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182686 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73421 49.32% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73422 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148877 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1833775262000 97.22% 97.22% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 81341000 0.00% 97.23% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 679703500 0.04% 97.26% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 51658703500 2.74% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1886195010000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211461 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74782 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1902 1.04% 42.05% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105860 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182675 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73415 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1902 1.28% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73415 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148863 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1834747397000 97.22% 97.22% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 80828500 0.00% 97.23% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 680298500 0.04% 97.26% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 51658959000 2.74% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1887167483000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981720 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693550 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814934 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693510 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814906 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -413,8 +412,8 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4172 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175525 91.23% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175514 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6805 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed @@ -422,7 +421,7 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5127 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192408 # number of callpals executed +system.cpu.kern.callpal::total 192398 # number of callpals executed system.cpu.kern.mode_switch::kernel 5868 # number of protection mode switches system.cpu.kern.mode_switch::user 1739 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches @@ -433,92 +432,92 @@ system.cpu.kern.mode_switch_good::kernel 0.324983 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080114 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.393034 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36513483500 1.94% 1.94% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4123557000 0.22% 2.15% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1845557959500 97.85% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 36501486500 1.93% 1.93% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4115911000 0.22% 2.15% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1846550075500 97.85% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4173 # number of times the context was actually changed -system.cpu.tickCycles 84408299 # Number of cycles that the object actually ticked -system.cpu.idleCycles 95808494 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395428 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.981685 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13773051 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395940 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.866506 # Average number of references to valid blocks. +system.cpu.tickCycles 86269078 # Number of cycles that the object actually ticked +system.cpu.idleCycles 95774468 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395484 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.981722 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13771544 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395996 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.865031 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 90850500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.981685 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.981722 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63660654 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63660654 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7815445 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815445 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5575784 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5575784 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182800 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182800 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 198989 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 198989 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13391229 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13391229 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13391229 # number of overall hits -system.cpu.dcache.overall_hits::total 13391229 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201797 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201797 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 574153 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 574153 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17210 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17210 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1775950 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1775950 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1775950 # number of overall misses -system.cpu.dcache.overall_misses::total 1775950 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32866409500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32866409500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22318082000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22318082000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230873000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 230873000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 55184491500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 55184491500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 55184491500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 55184491500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9017242 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9017242 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6149937 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6149937 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200010 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200010 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 198989 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 198989 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15167179 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15167179 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15167179 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15167179 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133278 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133278 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093359 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093359 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086046 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086046 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117092 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117092 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117092 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117092 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27347.721371 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27347.721371 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38871.314789 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38871.314789 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13415.049390 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13415.049390 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31073.223627 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31073.223627 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31073.223627 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31073.223627 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63656757 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63656757 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7813939 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7813939 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5575873 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5575873 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182717 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182717 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 198981 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 198981 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13389812 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13389812 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13389812 # number of overall hits +system.cpu.dcache.overall_hits::total 13389812 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201834 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201834 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 574561 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 574561 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17285 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17285 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1776395 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1776395 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1776395 # number of overall misses +system.cpu.dcache.overall_misses::total 1776395 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32870602000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32870602000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22298477500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22298477500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232185000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 232185000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 55169079500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 55169079500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 55169079500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 55169079500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9015773 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9015773 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6150434 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6150434 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200002 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200002 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 198981 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 198981 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15166207 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15166207 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15166207 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15166207 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133303 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133303 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093418 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093418 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086424 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086424 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117128 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117128 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117128 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117128 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27350.367854 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27350.367854 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38809.591149 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38809.591149 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13432.745155 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13432.745155 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31056.763558 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31056.763558 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31056.763558 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31056.763558 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -527,129 +526,129 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838228 # number of writebacks -system.cpu.dcache.writebacks::total 838228 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127318 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127318 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269861 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269861 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838310 # number of writebacks +system.cpu.dcache.writebacks::total 838310 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127379 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 127379 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270264 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 270264 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 397179 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 397179 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 397179 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 397179 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074479 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074479 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304292 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304292 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17207 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17207 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378771 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378771 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378771 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378771 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16555 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 16555 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29864669500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29864669500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11367980000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11367980000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 213500500 # 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number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3493554500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3493554500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119158 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119158 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049479 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049479 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086031 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086031 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090905 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090905 # 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number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272179 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272179 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16403 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388713 # number of demand (read+write) MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116544 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116544 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16406 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16406 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272166 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272166 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16406 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388710 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 405116 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16403 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388713 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16406 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388710 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 405116 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9621 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9621 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16555 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16555 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 431000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 431000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7770532000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7770532000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1160467500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1160467500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17006826000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17006826000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1160467500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24777358000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25937825500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1160467500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24777358000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25937825500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364748500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364748500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1931469000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1931469000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3296217500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3296217500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9620 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9620 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16550 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16550 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 453499 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 453499 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7758089500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7758089500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1150653000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1150653000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17010167000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17010167000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1150653000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24768256500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25918909500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1150653000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24768256500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25918909500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363977000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363977000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1930958000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1930958000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3294935000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3294935000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382955 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382955 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011238 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249327 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249327 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278456 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141868 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278456 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141868 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 26937.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26937.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66680.385124 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66680.385124 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70747.271841 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70747.271841 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62483.975619 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62483.975619 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70747.271841 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63742.035898 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64025.675362 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70747.271841 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63742.035898 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64025.675362 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196819.800981 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196819.800981 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200755.534768 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200755.534768 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199107.067351 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199107.067351 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809524 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382982 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382982 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011239 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249303 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249303 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278443 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141862 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011239 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278443 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141862 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 26676.411765 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26676.411765 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66567.901393 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66567.901393 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70136.108741 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70136.108741 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62499.235761 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62499.235761 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70136.108741 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63719.113221 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63978.982563 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70136.108741 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63719.113221 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63978.982563 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196822.077922 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196822.077922 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200723.284823 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200723.284823 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199089.728097 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199089.728097 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 6934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2558426 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9621 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9621 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 956270 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2277118 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304302 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304302 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1459696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091829 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2558531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 956362 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2277135 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304307 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304307 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1459755 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091879 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4377747 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219297 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8597044 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93416704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143041221 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236457925 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 422839 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6149292 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4377903 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219455 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8597358 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93420352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143049956 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236470308 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422854 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6149527 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1.068727 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.252990 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.252989 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5726669 93.13% 93.13% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 422623 6.87% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5726891 93.13% 93.13% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 422636 6.87% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6149292 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3706373000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6149527 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3706565999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2189771045 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2189850563 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2105677995 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2105755497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -934,43 +933,43 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7107 # Transaction distribution -system.iobus.trans_dist::ReadResp 7107 # Transaction distribution -system.iobus.trans_dist::WriteReq 51173 # Transaction distribution -system.iobus.trans_dist::WriteResp 51173 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5104 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7103 # Transaction distribution +system.iobus.trans_dist::ReadResp 7103 # Transaction distribution +system.iobus.trans_dist::WriteReq 51172 # Transaction distribution +system.iobus.trans_dist::WriteResp 51172 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5096 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33110 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33100 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116560 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20416 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20384 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44357 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44324 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705965 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4712000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705932 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4707000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -984,7 +983,7 @@ system.iobus.reqLayer23.occupancy 13484000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) @@ -992,23 +991,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216063756 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216043265 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23489000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23480000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.294607 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.302220 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1729988854000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.294607 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.080913 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.080913 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1729987199000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.302220 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081389 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081389 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1024,8 +1023,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907200873 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4907200873 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908791382 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4908791382 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles @@ -1048,17 +1047,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118097.826170 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118097.826170 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118136.103725 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118136.103725 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1074,8 +1073,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829600873 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2829600873 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831191382 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2831191382 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles @@ -1090,61 +1089,61 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68097.826170 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68097.826170 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68136.103725 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68136.103725 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 6934 # Transaction distribution -system.membus.trans_dist::ReadResp 295673 # Transaction distribution -system.membus.trans_dist::WriteReq 9621 # Transaction distribution -system.membus.trans_dist::WriteResp 9621 # Transaction distribution -system.membus.trans_dist::Writeback 118025 # Transaction distribution -system.membus.trans_dist::CleanEvict 262175 # Transaction distribution -system.membus.trans_dist::UpgradeReq 156 # Transaction distribution -system.membus.trans_dist::UpgradeResp 156 # Transaction distribution -system.membus.trans_dist::ReadExReq 116394 # Transaction distribution -system.membus.trans_dist::ReadExResp 116394 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288755 # Transaction distribution +system.membus.trans_dist::ReadReq 6930 # Transaction distribution +system.membus.trans_dist::ReadResp 295659 # Transaction distribution +system.membus.trans_dist::WriteReq 9620 # Transaction distribution +system.membus.trans_dist::WriteResp 9620 # Transaction distribution +system.membus.trans_dist::Writeback 118023 # Transaction distribution +system.membus.trans_dist::CleanEvict 262178 # Transaction distribution +system.membus.trans_dist::UpgradeReq 157 # Transaction distribution +system.membus.trans_dist::UpgradeResp 157 # Transaction distribution +system.membus.trans_dist::ReadExReq 116404 # Transaction distribution +system.membus.trans_dist::ReadExResp 116404 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288745 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33110 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33100 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148635 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181774 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181767 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1306591 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44357 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30796800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30841157 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1306584 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44324 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30796672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30840996 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33498885 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33498724 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 843789 # Request fanout histogram +system.membus.snoop_fanout::samples 843798 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 843789 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 843798 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 843789 # Request fanout histogram -system.membus.reqLayer0.occupancy 29576000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 843798 # Request fanout histogram +system.membus.reqLayer0.occupancy 29290000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1318697936 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1318757186 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160007596 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160035845 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72031934 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 72019946 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 2b4d92c81..08ac5b1cf 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -166,7 +166,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -513,7 +513,7 @@ opLat=3 pipelined=false [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -671,7 +671,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu1.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -1018,7 +1018,7 @@ opLat=3 pipelined=false [system.cpu1.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -1151,7 +1151,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=0:134217727 assoc=8 @@ -1186,7 +1186,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index e5b1b4540..7571a76a8 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.907980 # Number of seconds simulated -sim_ticks 1907980084000 # Number of ticks simulated -final_tick 1907980084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.906957 # Number of seconds simulated +sim_ticks 1906956794000 # Number of ticks simulated +final_tick 1906956794000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 144634 # Simulator instruction rate (inst/s) -host_op_rate 144633 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4918211693 # Simulator tick rate (ticks/s) -host_mem_usage 381420 # Number of bytes of host memory used -host_seconds 387.94 # Real time elapsed on the host -sim_insts 56109384 # Number of instructions simulated -sim_ops 56109384 # Number of ops (including micro ops) simulated +host_inst_rate 101212 # Simulator instruction rate (inst/s) +host_op_rate 101212 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3411514986 # Simulator tick rate (ticks/s) +host_mem_usage 375140 # Number of bytes of host memory used +host_seconds 558.98 # Real time elapsed on the host +sim_insts 56575230 # Number of instructions simulated +sim_ops 56575230 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 744000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24138496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 236608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1227584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 862400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24773696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 117248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 514752 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26347648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 744000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 236608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 980608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7952896 # Number of bytes written to this memory -system.physmem.bytes_written::total 7952896 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11625 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 377164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3697 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 19181 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26269056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 862400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 117248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 979648 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7861568 # Number of bytes written to this memory +system.physmem.bytes_written::total 7861568 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13475 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387089 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1832 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8043 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 411682 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124264 # Number of write requests responded to by this memory -system.physmem.num_writes::total 124264 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 389941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12651335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 124010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 643395 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 410454 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122837 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122837 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 452239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12991220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 61484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 269934 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13809184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 389941 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 124010 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4168228 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4168228 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4168228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 389941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12651335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 124010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 643395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13775381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 452239 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 61484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513723 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4122573 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4122573 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4122573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 452239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12991220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 61484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 269934 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17977412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 411682 # Number of read requests accepted -system.physmem.writeReqs 124264 # Number of write requests accepted -system.physmem.readBursts 411682 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 124264 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26340672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue -system.physmem.bytesWritten 7951552 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26347648 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7952896 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17897953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410454 # Number of read requests accepted +system.physmem.writeReqs 122837 # Number of write requests accepted +system.physmem.readBursts 410454 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122837 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26260992 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue +system.physmem.bytesWritten 7860160 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26269056 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7861568 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 45002 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25908 # Per bank write bursts -system.physmem.perBankRdBursts::1 25789 # Per bank write bursts -system.physmem.perBankRdBursts::2 26010 # Per bank write bursts -system.physmem.perBankRdBursts::3 25614 # Per bank write bursts -system.physmem.perBankRdBursts::4 25643 # Per bank write bursts -system.physmem.perBankRdBursts::5 25797 # Per bank write bursts -system.physmem.perBankRdBursts::6 25922 # Per bank write bursts -system.physmem.perBankRdBursts::7 25550 # Per bank write bursts -system.physmem.perBankRdBursts::8 25897 # Per bank write bursts -system.physmem.perBankRdBursts::9 25701 # Per bank write bursts -system.physmem.perBankRdBursts::10 25484 # Per bank write bursts -system.physmem.perBankRdBursts::11 25508 # Per bank write bursts -system.physmem.perBankRdBursts::12 25696 # Per bank write bursts -system.physmem.perBankRdBursts::13 25817 # Per bank write bursts -system.physmem.perBankRdBursts::14 25547 # Per bank write bursts -system.physmem.perBankRdBursts::15 25690 # Per bank write bursts -system.physmem.perBankWrBursts::0 7970 # Per bank write bursts -system.physmem.perBankWrBursts::1 7556 # Per bank write bursts -system.physmem.perBankWrBursts::2 7711 # Per bank write bursts -system.physmem.perBankWrBursts::3 7606 # Per bank write bursts -system.physmem.perBankWrBursts::4 7633 # Per bank write bursts -system.physmem.perBankWrBursts::5 7951 # Per bank write bursts -system.physmem.perBankWrBursts::6 7934 # Per bank write bursts -system.physmem.perBankWrBursts::7 7815 # Per bank write bursts -system.physmem.perBankWrBursts::8 8060 # Per bank write bursts -system.physmem.perBankWrBursts::9 8044 # Per bank write bursts -system.physmem.perBankWrBursts::10 7565 # Per bank write bursts -system.physmem.perBankWrBursts::11 7446 # Per bank write bursts -system.physmem.perBankWrBursts::12 7634 # Per bank write bursts -system.physmem.perBankWrBursts::13 8000 # Per bank write bursts -system.physmem.perBankWrBursts::14 7754 # Per bank write bursts -system.physmem.perBankWrBursts::15 7564 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 46373 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 26161 # Per bank write bursts +system.physmem.perBankRdBursts::1 25973 # Per bank write bursts +system.physmem.perBankRdBursts::2 26108 # Per bank write bursts +system.physmem.perBankRdBursts::3 25765 # Per bank write bursts +system.physmem.perBankRdBursts::4 25066 # Per bank write bursts +system.physmem.perBankRdBursts::5 25574 # Per bank write bursts +system.physmem.perBankRdBursts::6 25905 # Per bank write bursts +system.physmem.perBankRdBursts::7 25241 # Per bank write bursts +system.physmem.perBankRdBursts::8 25825 # Per bank write bursts +system.physmem.perBankRdBursts::9 26325 # Per bank write bursts +system.physmem.perBankRdBursts::10 25290 # Per bank write bursts +system.physmem.perBankRdBursts::11 25205 # Per bank write bursts +system.physmem.perBankRdBursts::12 25472 # Per bank write bursts +system.physmem.perBankRdBursts::13 25390 # Per bank write bursts +system.physmem.perBankRdBursts::14 25632 # Per bank write bursts +system.physmem.perBankRdBursts::15 25396 # Per bank write bursts +system.physmem.perBankWrBursts::0 8442 # Per bank write bursts +system.physmem.perBankWrBursts::1 7958 # Per bank write bursts +system.physmem.perBankWrBursts::2 8052 # Per bank write bursts +system.physmem.perBankWrBursts::3 7723 # Per bank write bursts +system.physmem.perBankWrBursts::4 7027 # Per bank write bursts +system.physmem.perBankWrBursts::5 7199 # Per bank write bursts +system.physmem.perBankWrBursts::6 7428 # Per bank write bursts +system.physmem.perBankWrBursts::7 6815 # Per bank write bursts +system.physmem.perBankWrBursts::8 7536 # Per bank write bursts +system.physmem.perBankWrBursts::9 7897 # Per bank write bursts +system.physmem.perBankWrBursts::10 7294 # Per bank write bursts +system.physmem.perBankWrBursts::11 7366 # Per bank write bursts +system.physmem.perBankWrBursts::12 7733 # Per bank write bursts +system.physmem.perBankWrBursts::13 8096 # Per bank write bursts +system.physmem.perBankWrBursts::14 8387 # Per bank write bursts +system.physmem.perBankWrBursts::15 7862 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 18 # Number of times write queue was full causing retry -system.physmem.totGap 1907975777500 # Total gap between requests +system.physmem.numWrRetry 17 # Number of times write queue was full causing retry +system.physmem.totGap 1906952476500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 411682 # Read request sizes (log2) +system.physmem.readPktSize::6 410454 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124264 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 38583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122837 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25010 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,204 +158,187 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 46 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65129 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.524774 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 320.940318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.518091 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14691 22.56% 22.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11476 17.62% 40.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5283 8.11% 48.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3332 5.12% 53.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2563 3.94% 57.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1696 2.60% 59.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1442 2.21% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1386 2.13% 64.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23260 35.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65129 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5620 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 73.233096 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2814.761745 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5617 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.098216 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.146393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.677441 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14983 23.10% 23.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11330 17.47% 40.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5177 7.98% 48.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3304 5.09% 53.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2428 3.74% 57.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1616 2.49% 59.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1474 2.27% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1311 2.02% 64.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23234 35.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64857 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5518 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.361182 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2842.300525 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5515 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5620 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5620 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.107295 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.769658 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.265728 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4863 86.53% 86.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 151 2.69% 89.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 190 3.38% 92.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 20 0.36% 92.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 26 0.46% 93.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 52 0.93% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.25% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.12% 94.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 2 0.04% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.04% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.11% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.12% 95.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 8 0.14% 95.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.09% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.05% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.05% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 8 0.14% 95.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 8 0.14% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 26 0.46% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 16 0.28% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 144 2.56% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.21% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.04% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.02% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.07% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.04% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.04% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.05% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 6 0.11% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.05% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 7 0.12% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 2 0.04% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 5 0.09% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-243 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5620 # Writes before turning the bus around for reads -system.physmem.totQLat 4128600500 # Total ticks spent queuing -system.physmem.totMemAccLat 11845594250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2057865000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10031.27 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5518 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5518 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.257158 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.834122 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.444866 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4906 88.91% 88.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 212 3.84% 92.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 76 1.38% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 18 0.33% 94.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 5 0.09% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 9 0.16% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 6 0.11% 94.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 17 0.31% 95.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 11 0.20% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 35 0.63% 95.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 173 3.14% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 8 0.14% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 1 0.02% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.02% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 6 0.11% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 2 0.04% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.04% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.11% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.09% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.04% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 5 0.09% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 6 0.11% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 4 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5518 # Writes before turning the bus around for reads +system.physmem.totQLat 4043689250 # Total ticks spent queuing +system.physmem.totMemAccLat 11737339250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2051640000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9854.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28781.27 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.81 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.17 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28604.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.21 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.72 # Average write queue length when enqueuing -system.physmem.readRowHits 370844 # Number of row buffer hits during reads -system.physmem.writeRowHits 99842 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.10 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.35 # Row buffer hit rate for writes -system.physmem.avgGap 3560014.96 # Average gap between requests -system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 245019600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133691250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1608188400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 402589440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124619576640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 57486510675 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1094357699250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1278853275255 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.267627 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1820391723000 # Time in different power states -system.physmem_0.memoryStateTime::REF 63711440000 # Time in different power states +system.physmem.avgRdQLen 2.27 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.58 # Average write queue length when enqueuing +system.physmem.readRowHits 369741 # Number of row buffer hits during reads +system.physmem.writeRowHits 98545 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.22 # Row buffer hit rate for writes +system.physmem.avgGap 3575819.72 # Average gap between requests +system.physmem.pageHitRate 87.83 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 242910360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132540375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1605185400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392973120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124552955280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 57318973425 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1093892654250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1278138192210 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.251160 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1819616623000 # Time in different power states +system.physmem_0.memoryStateTime::REF 63677380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23872193000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23660103250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 247287600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134928750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1601652000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 402194160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124619576640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 57648050955 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1094215997250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1278869687355 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.276229 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1820158780750 # Time in different power states -system.physmem_1.memoryStateTime::REF 63711440000 # Time in different power states +system.physmem_1.actEnergy 247408560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134994750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1595373000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 402868080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124552955280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 57679570530 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1093576349250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1278189519450 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.278071 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1819088073250 # Time in different power states +system.physmem_1.memoryStateTime::REF 63677380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 24103898000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 24188666750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 11788808 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10301623 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 235567 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 7623393 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4144660 # Number of BTB hits +system.cpu0.branchPred.lookups 16421216 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14369135 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 322041 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10416019 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5388507 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 54.367655 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 590548 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 12472 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 51.732884 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 814349 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 18392 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7021210 # DTB read hits -system.cpu0.dtb.read_misses 28922 # DTB read misses +system.cpu0.dtb.read_hits 9282981 # DTB read hits +system.cpu0.dtb.read_misses 32197 # DTB read misses system.cpu0.dtb.read_acv 549 # DTB read access violations -system.cpu0.dtb.read_accesses 680178 # DTB read accesses -system.cpu0.dtb.write_hits 4516223 # DTB write hits -system.cpu0.dtb.write_misses 6969 # DTB write misses -system.cpu0.dtb.write_acv 383 # DTB write access violations -system.cpu0.dtb.write_accesses 234540 # DTB write accesses -system.cpu0.dtb.data_hits 11537433 # DTB hits -system.cpu0.dtb.data_misses 35891 # DTB misses -system.cpu0.dtb.data_acv 932 # DTB access violations -system.cpu0.dtb.data_accesses 914718 # DTB accesses -system.cpu0.itb.fetch_hits 1192769 # ITB hits -system.cpu0.itb.fetch_misses 29243 # ITB misses -system.cpu0.itb.fetch_acv 632 # ITB acv -system.cpu0.itb.fetch_accesses 1222012 # ITB accesses +system.cpu0.dtb.read_accesses 681404 # DTB read accesses +system.cpu0.dtb.write_hits 5956980 # DTB write hits +system.cpu0.dtb.write_misses 7300 # DTB write misses +system.cpu0.dtb.write_acv 382 # DTB write access violations +system.cpu0.dtb.write_accesses 235779 # DTB write accesses +system.cpu0.dtb.data_hits 15239961 # DTB hits +system.cpu0.dtb.data_misses 39497 # DTB misses +system.cpu0.dtb.data_acv 931 # DTB access violations +system.cpu0.dtb.data_accesses 917183 # DTB accesses +system.cpu0.itb.fetch_hits 1451467 # ITB hits +system.cpu0.itb.fetch_misses 20802 # ITB misses +system.cpu0.itb.fetch_acv 603 # ITB acv +system.cpu0.itb.fetch_accesses 1472269 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -368,598 +351,598 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 94258709 # number of cpu cycles simulated +system.cpu0.numCycles 115722397 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 18560589 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 53027757 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 11788808 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4735208 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 69979824 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 806070 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 422 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 25803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1456351 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 296845 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 178 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6342869 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 170274 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 90723047 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.584501 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.854201 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 26666578 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 71121267 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16421216 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6202856 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 81967119 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1079386 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 563 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 29093 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 971886 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 464461 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8198819 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 234916 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 110639677 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.642819 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.946891 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 80634947 88.88% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 672953 0.74% 89.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1448081 1.60% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 584574 0.64% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2111688 2.33% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 463915 0.51% 94.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 450869 0.50% 95.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 614781 0.68% 95.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3741239 4.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 97354556 87.99% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 847860 0.77% 88.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1824694 1.65% 90.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 789927 0.71% 91.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2609447 2.36% 93.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 576925 0.52% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 654110 0.59% 94.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 850099 0.77% 95.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5132059 4.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 90723047 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.125069 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.562577 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 14977569 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 67686915 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6257157 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1423439 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 377966 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 370983 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 25389 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 46677806 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 79994 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 377966 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 15660908 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 46083028 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14369152 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6948168 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7283823 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 45068314 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 191995 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1547824 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 115834 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4229403 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 30289226 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 55138176 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 55047778 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 82793 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 26689501 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 3599717 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1126936 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 168790 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 10038208 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7066684 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 4739993 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1073845 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 760534 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 40346624 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1418133 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 39715880 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 51531 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 4979263 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2318512 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 978590 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 90723047 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.437771 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.168840 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 110639677 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.141902 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.614585 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 21680681 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 78105435 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8575313 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1774700 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 503547 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 522363 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 36577 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62219552 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 111460 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 503547 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 22526069 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 50558199 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 19082823 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9419071 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 8549966 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 60053732 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 197896 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2013708 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 145060 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4631346 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 40115150 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72965738 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72822559 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 133404 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 35357429 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4757713 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1490349 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 215164 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12632454 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9363221 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6214194 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1348186 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 960020 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 53527289 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1914294 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52757497 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 50335 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6507909 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2851663 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1318911 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 110639677 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.476841 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.213091 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 74240349 81.83% 81.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7278177 8.02% 89.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3014429 3.32% 93.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2002130 2.21% 95.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2057446 2.27% 97.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1059416 1.17% 98.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 709655 0.78% 99.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 273899 0.30% 99.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 87546 0.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 88942477 80.39% 80.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9398072 8.49% 88.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3917958 3.54% 92.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2747278 2.48% 94.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2855598 2.58% 97.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1392573 1.26% 98.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 913992 0.83% 99.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 361366 0.33% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 110363 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 90723047 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 110639677 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 128942 17.20% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 17.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 362987 48.42% 65.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 257779 34.38% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 181613 18.32% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 474655 47.88% 66.21% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 334992 33.79% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3788 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 27155018 68.37% 68.38% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 40485 0.10% 68.48% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.48% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 25259 0.06% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.55% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7282480 18.34% 86.89% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 4576355 11.52% 98.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 630612 1.59% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 36170574 68.56% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57549 0.11% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.68% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 28793 0.05% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9634233 18.26% 87.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6027526 11.42% 98.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 833151 1.58% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 39715880 # Type of FU issued -system.cpu0.iq.rate 0.421350 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 749708 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018877 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 170597233 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 46586090 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 38643243 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 358812 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 172505 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 165745 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 40269961 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 191839 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 469267 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52757497 # Type of FU issued +system.cpu0.iq.rate 0.455897 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 991260 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018789 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 216609620 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61691492 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 51347656 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 586645 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 275208 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 269627 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 53428897 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 316072 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 584424 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 864378 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3380 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 14864 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 401917 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1070558 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2876 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 17548 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 473318 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 11804 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 365714 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18682 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 412098 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 377966 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 43619498 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 675796 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 44202753 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 88904 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7066684 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 4739993 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1257449 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 23012 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 538948 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 14864 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 117466 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 265776 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 383242 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 39342618 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7067139 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 373261 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 503547 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 47448039 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 802619 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 58859222 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 120684 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9363221 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6214194 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1691778 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39350 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 562336 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 17548 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 158131 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 358107 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 516238 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 52248436 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9338690 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 509060 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2437996 # number of nop insts executed -system.cpu0.iew.exec_refs 11599884 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6171265 # Number of branches executed -system.cpu0.iew.exec_stores 4532745 # Number of stores executed -system.cpu0.iew.exec_rate 0.417390 # Inst execution rate -system.cpu0.iew.wb_sent 38908729 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 38808988 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 20149850 # num instructions producing a value -system.cpu0.iew.wb_consumers 27578035 # num instructions consuming a value +system.cpu0.iew.exec_nop 3417639 # number of nop insts executed +system.cpu0.iew.exec_refs 15316719 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8298030 # Number of branches executed +system.cpu0.iew.exec_stores 5978029 # Number of stores executed +system.cpu0.iew.exec_rate 0.451498 # Inst execution rate +system.cpu0.iew.wb_sent 51729756 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51617283 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26562977 # num instructions producing a value +system.cpu0.iew.wb_consumers 36791821 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.411728 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.730649 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.446044 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.721980 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5183738 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 439543 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 349838 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 89803768 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.433386 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.354442 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6839384 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 595383 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 473671 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 109429659 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.474443 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.410223 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 76032999 84.67% 84.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5542678 6.17% 90.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2869062 3.19% 94.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1578965 1.76% 95.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1284314 1.43% 97.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 412798 0.46% 97.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 324191 0.36% 98.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 314453 0.35% 98.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1444308 1.61% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 91094862 83.25% 83.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7261881 6.64% 89.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3995871 3.65% 93.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2069124 1.89% 95.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1633444 1.49% 96.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 582030 0.53% 97.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 441609 0.40% 97.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 443115 0.40% 98.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1907723 1.74% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 89803768 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 38919724 # Number of instructions committed -system.cpu0.commit.committedOps 38919724 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 109429659 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51918164 # Number of instructions committed +system.cpu0.commit.committedOps 51918164 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 10540382 # Number of memory references committed -system.cpu0.commit.loads 6202306 # Number of loads committed -system.cpu0.commit.membars 144405 # Number of memory barriers committed -system.cpu0.commit.branches 5839773 # Number of branches committed -system.cpu0.commit.fp_insts 162063 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 36166381 # Number of committed integer instructions. -system.cpu0.commit.function_calls 471449 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2138002 5.49% 5.49% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 25394964 65.25% 70.74% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 39484 0.10% 70.84% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.84% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 24801 0.06% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 6346711 16.31% 87.22% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 4343267 11.16% 98.38% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 630612 1.62% 100.00% # Class of committed instruction +system.cpu0.commit.refs 14033539 # Number of memory references committed +system.cpu0.commit.loads 8292663 # Number of loads committed +system.cpu0.commit.membars 202804 # Number of memory barriers committed +system.cpu0.commit.branches 7846921 # Number of branches committed +system.cpu0.commit.fp_insts 266538 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 48077974 # Number of committed integer instructions. +system.cpu0.commit.function_calls 666824 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2988262 5.76% 5.76% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 33767854 65.04% 70.80% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 56339 0.11% 70.90% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.90% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 28331 0.05% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.96% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8495467 16.36% 87.33% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5746879 11.07% 98.40% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 833149 1.60% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 38919724 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1444308 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 132264444 # The number of ROB reads -system.cpu0.rob.rob_writes 89122078 # The number of ROB writes -system.cpu0.timesIdled 337516 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3535662 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3721701460 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 36785489 # Number of Instructions Simulated -system.cpu0.committedOps 36785489 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.562388 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.562388 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.390261 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.390261 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 51878765 # number of integer regfile reads -system.cpu0.int_regfile_writes 28204778 # number of integer regfile writes -system.cpu0.fp_regfile_reads 81728 # number of floating regfile reads -system.cpu0.fp_regfile_writes 81429 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1387632 # number of misc regfile reads -system.cpu0.misc_regfile_writes 636485 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 898491 # number of replacements -system.cpu0.dcache.tags.tagsinuse 481.994698 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 8012262 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 899003 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.912386 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 26393500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.994698 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.941396 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.941396 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 51918164 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1907723 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 166079481 # The number of ROB reads +system.cpu0.rob.rob_writes 118719518 # The number of ROB writes +system.cpu0.timesIdled 511712 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5082720 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3698191192 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48933669 # Number of Instructions Simulated +system.cpu0.committedOps 48933669 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.364883 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.364883 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.422854 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.422854 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 68649325 # number of integer regfile reads +system.cpu0.int_regfile_writes 37335516 # number of integer regfile writes +system.cpu0.fp_regfile_reads 132501 # number of floating regfile reads +system.cpu0.fp_regfile_writes 134063 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1824055 # number of misc regfile reads +system.cpu0.misc_regfile_writes 833586 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1296864 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.135915 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10665502 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1297376 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.220826 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 26097500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.135915 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988547 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988547 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 236 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 43230678 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 43230678 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5046736 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5046736 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 2679789 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 2679789 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129628 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 129628 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149296 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149296 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7726525 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 7726525 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7726525 # number of overall hits -system.cpu0.dcache.overall_hits::total 7726525 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1067598 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1067598 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1496200 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1496200 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12202 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12202 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 769 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 769 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2563798 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2563798 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2563798 # number of overall misses -system.cpu0.dcache.overall_misses::total 2563798 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 32014122500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 32014122500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 69455032918 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 69455032918 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 190587000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 190587000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5445000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5445000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 101469155418 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 101469155418 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 101469155418 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 101469155418 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6114334 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6114334 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4175989 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4175989 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 141830 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 141830 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 150065 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 150065 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10290323 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10290323 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10290323 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10290323 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.174606 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.174606 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.358286 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.358286 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086033 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086033 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.005124 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.005124 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249147 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.249147 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249147 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.249147 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29987.057394 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 29987.057394 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46420.955031 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 46420.955031 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15619.324701 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15619.324701 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7080.624187 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7080.624187 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39577.671649 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39577.671649 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39577.671649 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39577.671649 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4094264 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5021 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 103728 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 39.471155 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 53.414894 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 57664711 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 57664711 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6558537 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6558537 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3738792 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3738792 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 165967 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 165967 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191452 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 191452 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10297329 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10297329 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10297329 # number of overall hits +system.cpu0.dcache.overall_hits::total 10297329 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1618045 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1618045 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1793563 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1793563 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21339 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21339 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2425 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2425 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3411608 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3411608 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3411608 # number of overall misses +system.cpu0.dcache.overall_misses::total 3411608 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39371994500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 39371994500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77781772548 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 77781772548 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 331348500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 331348500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20480000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 20480000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 117153767048 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 117153767048 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 117153767048 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 117153767048 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8176582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8176582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5532355 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5532355 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 187306 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 187306 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 193877 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 193877 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13708937 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13708937 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13708937 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13708937 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197888 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197888 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324195 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.324195 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113926 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113926 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.012508 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.012508 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248860 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248860 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248860 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248860 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24333.065211 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 24333.065211 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43367.181720 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43367.181720 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15527.836356 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15527.836356 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8445.360825 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8445.360825 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34339.750361 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34339.750361 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34339.750361 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34339.750361 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4364063 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4809 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 121083 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 97 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.041913 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 49.577320 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 426068 # number of writebacks -system.cpu0.dcache.writebacks::total 426068 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 384761 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 384761 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1282051 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1282051 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3514 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3514 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1666812 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1666812 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1666812 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1666812 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 682837 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 682837 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 214149 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 214149 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8688 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8688 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 769 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 769 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 896986 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 896986 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 896986 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 896986 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 4777 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 4777 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 8020 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 8020 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 12797 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 12797 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25205904500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25205904500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10851652245 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10851652245 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 107603000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 107603000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4676000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4676000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36057556745 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 36057556745 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36057556745 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 36057556745 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1013290500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1013290500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1707574498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1707574498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2720864998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2720864998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.111678 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.111678 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051281 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051281 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061256 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061256 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.005124 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.005124 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.087168 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.087168 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.087168 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.087168 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36913.501319 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36913.501319 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 50673.373422 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 50673.373422 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12385.244015 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12385.244015 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6080.624187 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6080.624187 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40198.572492 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 40198.572492 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 40198.572492 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 40198.572492 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 212118.589073 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212118.589073 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 212914.525935 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212914.525935 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212617.410174 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212617.410174 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 766891 # number of writebacks +system.cpu0.dcache.writebacks::total 766891 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 594303 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 594303 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1523628 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1523628 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5200 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5200 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2117931 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2117931 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2117931 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2117931 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1023742 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1023742 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 269935 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 269935 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16139 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16139 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2425 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2425 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1293677 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1293677 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1293677 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1293677 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7035 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7035 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10024 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10024 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17059 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17059 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 29563027500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 29563027500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12280270109 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12280270109 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188351000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188351000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 18055000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 18055000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 41843297609 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 41843297609 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 41843297609 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 41843297609 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1480741500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1480741500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2153066498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2153066498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3633807998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3633807998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125204 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125204 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048792 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048792 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086164 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086164 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.012508 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.012508 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094367 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.094367 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094367 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.094367 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28877.419799 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28877.419799 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45493.434008 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45493.434008 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11670.549600 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11670.549600 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7445.360825 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7445.360825 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32344.470536 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32344.470536 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32344.470536 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32344.470536 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210482.089552 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210482.089552 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214791.151038 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214791.151038 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 213014.127323 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 213014.127323 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 615978 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.684225 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 5692804 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 616490 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.234220 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 28149663500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.684225 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993524 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.993524 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 927295 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.382377 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7224199 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 927807 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.786317 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 28149280500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.382377 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994887 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994887 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 430 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 427 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 6959538 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 6959538 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5692804 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5692804 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5692804 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5692804 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5692804 # number of overall hits -system.cpu0.icache.overall_hits::total 5692804 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 650065 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 650065 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 650065 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 650065 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 650065 # number of overall misses -system.cpu0.icache.overall_misses::total 650065 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9309214992 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9309214992 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9309214992 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9309214992 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9309214992 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9309214992 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6342869 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6342869 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6342869 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6342869 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6342869 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6342869 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.102488 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.102488 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.102488 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.102488 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.102488 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.102488 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14320.437175 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14320.437175 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14320.437175 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14320.437175 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14320.437175 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14320.437175 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3481 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 9126911 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9126911 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7224199 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7224199 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7224199 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7224199 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7224199 # number of overall hits +system.cpu0.icache.overall_hits::total 7224199 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 974618 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 974618 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 974618 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 974618 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 974618 # number of overall misses +system.cpu0.icache.overall_misses::total 974618 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13621983991 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13621983991 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13621983991 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13621983991 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13621983991 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13621983991 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8198817 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8198817 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8198817 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8198817 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8198817 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8198817 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118873 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.118873 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118873 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.118873 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118873 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.118873 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13976.741647 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13976.741647 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13976.741647 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13976.741647 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13976.741647 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13976.741647 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5225 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 166 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 203 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.969880 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.738916 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33396 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 33396 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 33396 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 33396 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 33396 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 33396 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 616669 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 616669 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 616669 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 616669 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 616669 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 616669 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8251915495 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8251915495 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8251915495 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8251915495 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8251915495 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8251915495 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.097222 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.097222 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.097222 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13381.433954 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13381.433954 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13381.433954 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 46524 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 46524 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 46524 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 46524 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 46524 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 46524 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 928094 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 928094 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 928094 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 928094 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 928094 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 928094 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12135046494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12135046494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12135046494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12135046494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12135046494 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12135046494 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113199 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.113199 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113199 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.113199 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13075.234291 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13075.234291 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13075.234291 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13075.234291 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7710185 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6710334 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 163097 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4502045 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 2070765 # Number of BTB hits +system.cpu1.branchPred.lookups 3314305 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2896651 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 61906 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1740825 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 779195 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 45.996097 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 394984 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 11166 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 44.760099 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 157645 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 4636 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 4026297 # DTB read hits -system.cpu1.dtb.read_misses 14233 # DTB read misses -system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 293572 # DTB read accesses -system.cpu1.dtb.write_hits 2497972 # DTB write hits -system.cpu1.dtb.write_misses 2408 # DTB write misses -system.cpu1.dtb.write_acv 37 # DTB write access violations -system.cpu1.dtb.write_accesses 109195 # DTB write accesses -system.cpu1.dtb.data_hits 6524269 # DTB hits -system.cpu1.dtb.data_misses 16641 # DTB misses -system.cpu1.dtb.data_acv 43 # DTB access violations -system.cpu1.dtb.data_accesses 402767 # DTB accesses -system.cpu1.itb.fetch_hits 750930 # ITB hits -system.cpu1.itb.fetch_misses 5383 # ITB misses -system.cpu1.itb.fetch_acv 53 # ITB acv -system.cpu1.itb.fetch_accesses 756313 # ITB accesses +system.cpu1.dtb.read_hits 1755656 # DTB read hits +system.cpu1.dtb.read_misses 9508 # DTB read misses +system.cpu1.dtb.read_acv 5 # DTB read access violations +system.cpu1.dtb.read_accesses 286377 # DTB read accesses +system.cpu1.dtb.write_hits 1073642 # DTB write hits +system.cpu1.dtb.write_misses 1995 # DTB write misses +system.cpu1.dtb.write_acv 40 # DTB write access violations +system.cpu1.dtb.write_accesses 108795 # DTB write accesses +system.cpu1.dtb.data_hits 2829298 # DTB hits +system.cpu1.dtb.data_misses 11503 # DTB misses +system.cpu1.dtb.data_acv 45 # DTB access violations +system.cpu1.dtb.data_accesses 395172 # DTB accesses +system.cpu1.itb.fetch_hits 497795 # ITB hits +system.cpu1.itb.fetch_misses 4809 # ITB misses +system.cpu1.itb.fetch_acv 84 # ITB acv +system.cpu1.itb.fetch_accesses 502604 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -972,564 +955,563 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 34369930 # number of cpu cycles simulated +system.cpu1.numCycles 13378620 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 13361598 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 30714280 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7710185 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2465749 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 18120966 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 547594 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 46 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 23797 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 211021 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 198154 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 3304195 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 117193 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 32189433 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.954173 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.349586 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 5528968 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 12732566 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3314305 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 936840 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 6841586 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 246622 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 24765 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 177717 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 60433 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1438917 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 48462 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 12756788 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.998101 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.406721 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 26750456 83.10% 83.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 307184 0.95% 84.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 618506 1.92% 85.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 382121 1.19% 87.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 801179 2.49% 89.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 249293 0.77% 90.43% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 334783 1.04% 91.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 403446 1.25% 92.72% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 2342465 7.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 10526481 82.52% 82.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 138708 1.09% 83.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 230541 1.81% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 169879 1.33% 86.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 284565 2.23% 88.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 115144 0.90% 89.88% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 131557 1.03% 90.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 159487 1.25% 92.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1000426 7.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 32189433 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.224329 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.893638 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 11124412 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16339992 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 3934359 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 534571 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 256098 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 250042 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 17822 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 25897409 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 55799 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 256098 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 11423416 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 4918911 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 9329125 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 4131002 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2130879 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 24789451 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 5724 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 540758 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 43054 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 820253 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 16289258 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 29487961 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 29391972 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 88964 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 13777657 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2511601 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 753305 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 82405 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 4252225 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 4127805 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 2629581 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 507300 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 331297 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 21789875 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 948507 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 21283611 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 28389 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 3414486 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1484281 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 680406 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 32189433 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.661199 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.387208 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 12756788 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.247731 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.951710 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 4581654 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6264793 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1608431 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 184437 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 117472 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 99495 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 5921 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 10317942 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 18589 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 117472 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 4714026 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 446929 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 4987547 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1661018 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 829794 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 9788331 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3632 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 64825 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 14992 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 371131 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 6443318 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 11674537 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 11622438 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 46696 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5463726 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 979592 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 407944 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 36440 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1686696 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1800249 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1144526 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 213224 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 121752 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 8623787 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 466284 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 8415044 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 20175 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1448509 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 669329 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 345933 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 12756788 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.659652 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.379213 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 23533399 73.11% 73.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 3630192 11.28% 84.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1573878 4.89% 89.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1186258 3.69% 92.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 1178148 3.66% 96.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 546160 1.70% 98.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 337865 1.05% 99.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 151957 0.47% 99.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 51576 0.16% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 9236176 72.40% 72.40% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1557417 12.21% 84.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 656816 5.15% 89.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 459502 3.60% 93.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 405096 3.18% 96.54% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 217416 1.70% 98.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 137120 1.07% 99.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 62655 0.49% 99.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 24590 0.19% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 32189433 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 12756788 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 80499 16.46% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 16.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 246874 50.47% 66.92% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 161807 33.08% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 22931 9.91% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 125391 54.21% 64.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 82988 35.88% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 14071465 66.11% 66.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 30174 0.14% 66.27% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.27% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 13456 0.06% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.34% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 4194422 19.71% 86.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 2532925 11.90% 97.95% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 435892 2.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5217804 62.01% 62.05% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 14291 0.17% 62.22% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.22% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10471 0.12% 62.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.36% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1829208 21.74% 84.10% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1094853 13.01% 97.11% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 243140 2.89% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 21283611 # Type of FU issued -system.cpu1.iq.rate 0.619251 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 489180 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.022984 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 74907239 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 25989017 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 20583813 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 366985 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 171482 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 168729 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 21571772 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 197501 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 207443 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 8415044 # Type of FU issued +system.cpu1.iq.rate 0.628992 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 231310 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.027488 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 29661025 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 10457474 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8106737 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 177336 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 85037 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 82464 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 8548271 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 94565 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 87834 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 572592 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1888 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 7837 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 247159 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 257024 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 716 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4046 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 124034 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 7441 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 131088 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 425 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 63290 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 256098 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 4050515 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 319306 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 24169619 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 59065 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 4127805 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 2629581 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 846465 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 33159 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 202940 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 7837 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 80858 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 187737 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 268595 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 21021510 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 4051663 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 262101 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 117472 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 288545 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 130999 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 9554579 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 24166 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1800249 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1144526 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 424658 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4139 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 125975 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4046 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 28597 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 88577 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 117174 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 8309020 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1771054 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 106024 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 1431237 # number of nop insts executed -system.cpu1.iew.exec_refs 6560061 # number of memory reference insts executed -system.cpu1.iew.exec_branches 3322997 # Number of branches executed -system.cpu1.iew.exec_stores 2508398 # Number of stores executed -system.cpu1.iew.exec_rate 0.611625 # Inst execution rate -system.cpu1.iew.wb_sent 20805592 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 20752542 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 10210202 # num instructions producing a value -system.cpu1.iew.wb_consumers 14612629 # num instructions consuming a value +system.cpu1.iew.exec_nop 464508 # number of nop insts executed +system.cpu1.iew.exec_refs 2851870 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1230259 # Number of branches executed +system.cpu1.iew.exec_stores 1080816 # Number of stores executed +system.cpu1.iew.exec_rate 0.621067 # Inst execution rate +system.cpu1.iew.wb_sent 8217653 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8189201 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 3916216 # num instructions producing a value +system.cpu1.iew.wb_consumers 5553340 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.603799 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.698725 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.612111 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.705200 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 3582987 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 268101 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 243613 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 31565232 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.650241 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.623237 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1470840 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 120351 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 107539 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 12487025 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.642311 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.620138 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 24282945 76.93% 76.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2976975 9.43% 86.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1587723 5.03% 91.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 771361 2.44% 93.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 532421 1.69% 95.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 258990 0.82% 96.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 207817 0.66% 97.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 189047 0.60% 97.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 757953 2.40% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 9576588 76.69% 76.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1351659 10.82% 87.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 487280 3.90% 91.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 294734 2.36% 93.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 217151 1.74% 95.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 92181 0.74% 96.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 81385 0.65% 96.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 96065 0.77% 97.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 289982 2.32% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 31565232 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 20524993 # Number of instructions committed -system.cpu1.commit.committedOps 20524993 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 12487025 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8020551 # Number of instructions committed +system.cpu1.commit.committedOps 8020551 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 5937635 # Number of memory references committed -system.cpu1.commit.loads 3555213 # Number of loads committed -system.cpu1.commit.membars 92415 # Number of memory barriers committed -system.cpu1.commit.branches 3082130 # Number of branches committed -system.cpu1.commit.fp_insts 166998 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 18893824 # Number of committed integer instructions. -system.cpu1.commit.function_calls 318960 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 1204616 5.87% 5.87% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 12808497 62.40% 68.27% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 29745 0.14% 68.42% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 68.42% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 13451 0.07% 68.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 68.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 68.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 68.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.01% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.49% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 3647628 17.77% 86.26% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 2383405 11.61% 97.88% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 435892 2.12% 100.00% # Class of committed instruction +system.cpu1.commit.refs 2563717 # Number of memory references committed +system.cpu1.commit.loads 1543225 # Number of loads committed +system.cpu1.commit.membars 37500 # Number of memory barriers committed +system.cpu1.commit.branches 1142801 # Number of branches committed +system.cpu1.commit.fp_insts 80747 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 7435629 # Number of committed integer instructions. +system.cpu1.commit.function_calls 128494 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 382508 4.77% 4.77% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 4766897 59.43% 64.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 14118 0.18% 64.38% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.38% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 10465 0.13% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.53% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1580725 19.71% 84.24% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1020940 12.73% 96.97% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 243139 3.03% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 20524993 # Class of committed instruction -system.cpu1.commit.bw_lim_events 757953 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 54833276 # The number of ROB reads -system.cpu1.rob.rob_writes 48835744 # The number of ROB writes -system.cpu1.timesIdled 276866 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2180497 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3780899978 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 19323895 # Number of Instructions Simulated -system.cpu1.committedOps 19323895 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.778623 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.778623 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.562233 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.562233 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 27142723 # number of integer regfile reads -system.cpu1.int_regfile_writes 14810250 # number of integer regfile writes -system.cpu1.fp_regfile_reads 88193 # number of floating regfile reads -system.cpu1.fp_regfile_writes 88824 # number of floating regfile writes -system.cpu1.misc_regfile_reads 1272248 # number of misc regfile reads -system.cpu1.misc_regfile_writes 377130 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 561653 # number of replacements -system.cpu1.dcache.tags.tagsinuse 496.197725 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4717582 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 561970 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 8.394722 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 37149185000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 496.197725 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.969136 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.969136 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 317 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.619141 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 24916279 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 24916279 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2844065 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2844065 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1751257 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1751257 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 62172 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 62172 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 69860 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 69860 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4595322 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4595322 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4595322 # number of overall hits -system.cpu1.dcache.overall_hits::total 4595322 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 792097 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 792097 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 552973 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 552973 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14160 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14160 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 786 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 786 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1345070 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1345070 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1345070 # number of overall misses -system.cpu1.dcache.overall_misses::total 1345070 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 10154789500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 10154789500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 16820667860 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 16820667860 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 217520000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 217520000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6395000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 6395000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 26975457360 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 26975457360 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 26975457360 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 26975457360 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3636162 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3636162 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2304230 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2304230 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 76332 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 76332 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 70646 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 70646 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 5940392 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 5940392 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 5940392 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 5940392 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.217839 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.217839 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.239982 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.239982 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.185505 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.185505 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.011126 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.011126 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.226428 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.226428 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.226428 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.226428 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12820.133771 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12820.133771 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30418.606080 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 30418.606080 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15361.581921 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15361.581921 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8136.132316 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8136.132316 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20055.058369 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20055.058369 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20055.058369 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20055.058369 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 765854 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 810 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 36939 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 18 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.732938 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 45 # average number of cycles each access was blocked +system.cpu1.commit.op_class_0::total 8020551 # Class of committed instruction +system.cpu1.commit.bw_lim_events 289982 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 21604416 # The number of ROB reads +system.cpu1.rob.rob_writes 19248787 # The number of ROB writes +system.cpu1.timesIdled 107122 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 621832 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3799884834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 7641561 # Number of Instructions Simulated +system.cpu1.committedOps 7641561 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.750771 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.750771 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.571177 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.571177 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 10694286 # number of integer regfile reads +system.cpu1.int_regfile_writes 5846668 # number of integer regfile writes +system.cpu1.fp_regfile_reads 46070 # number of floating regfile reads +system.cpu1.fp_regfile_writes 45105 # number of floating regfile writes +system.cpu1.misc_regfile_reads 889333 # number of misc regfile reads +system.cpu1.misc_regfile_writes 191018 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 88757 # number of replacements +system.cpu1.dcache.tags.tagsinuse 491.801602 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2280391 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 89062 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 25.604534 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1034185237500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.801602 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.960550 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.960550 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 305 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 305 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.595703 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 10633162 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 10633162 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1420631 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1420631 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 810208 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 810208 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 27933 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 27933 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 26395 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 26395 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2230839 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2230839 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2230839 # number of overall hits +system.cpu1.dcache.overall_hits::total 2230839 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 166361 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 166361 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 175617 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 175617 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4254 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4254 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2523 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2523 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 341978 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 341978 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 341978 # number of overall misses +system.cpu1.dcache.overall_misses::total 341978 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2085855500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2085855500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6615792667 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 6615792667 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 40341500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 40341500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21053500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 21053500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8701648167 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8701648167 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8701648167 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8701648167 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1586992 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1586992 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 985825 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 985825 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 32187 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 32187 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 28918 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 28918 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2572817 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2572817 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2572817 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2572817 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.104828 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.104828 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.178142 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.178142 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.132165 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.132165 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087247 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087247 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132920 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.132920 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132920 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.132920 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12538.127927 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12538.127927 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37671.709840 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 37671.709840 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9483.192290 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9483.192290 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8344.629409 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8344.629409 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25445.052509 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 25445.052509 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25445.052509 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 25445.052509 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 379425 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 575 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 15060 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 25.194223 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 47.916667 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 435263 # number of writebacks -system.cpu1.dcache.writebacks::total 435263 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 332265 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 332265 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 455576 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 455576 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 2707 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 2707 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 787841 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 787841 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 787841 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 787841 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 459832 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 459832 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 97397 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 97397 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11453 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11453 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 786 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 786 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 557229 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 557229 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 557229 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 557229 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2425 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2425 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4340 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4340 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6765 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6765 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5761115500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5761115500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2818212839 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2818212839 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 135759000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 135759000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5609000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5609000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8579328339 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8579328339 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8579328339 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8579328339 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 499447000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 499447000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 957710500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 957710500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1457157500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1457157500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.126461 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.126461 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.042269 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.042269 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.150042 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.150042 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.011126 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.011126 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.093803 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.093803 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.093803 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.093803 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12528.739844 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12528.739844 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28935.314630 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28935.314630 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11853.575482 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11853.575482 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7136.132316 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7136.132316 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15396.413932 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15396.413932 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15396.413932 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15396.413932 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 205957.525773 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205957.525773 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220670.622120 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 220670.622120 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 215396.526238 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 215396.526238 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 56462 # number of writebacks +system.cpu1.dcache.writebacks::total 56462 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 100117 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 100117 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 144305 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 144305 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 473 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 473 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 244422 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 244422 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 244422 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 244422 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 66244 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 66244 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 31312 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 31312 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 3781 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 3781 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2522 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2522 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 97556 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 97556 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 97556 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 97556 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 158 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2884 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2884 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3042 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3042 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 801271000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 801271000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1099670460 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1099670460 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 31948000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 31948000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 18531500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 18531500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1900941460 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1900941460 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1900941460 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1900941460 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29727000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29727000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 636171000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 636171000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 665898000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 665898000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.041742 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.041742 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031762 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.031762 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117470 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117470 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087212 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087212 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.037918 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.037918 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.037918 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.037918 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12095.752068 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12095.752068 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35119.777082 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35119.777082 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8449.616504 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8449.616504 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7347.938144 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7347.938144 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19485.643733 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19485.643733 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19485.643733 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19485.643733 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188145.569620 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188145.569620 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220586.338419 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 220586.338419 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 218901.380671 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 218901.380671 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 499853 # number of replacements -system.cpu1.icache.tags.tagsinuse 504.618896 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 2783346 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 500364 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.562642 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 48744804500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.618896 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.985584 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.985584 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 3804626 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 3804626 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 2783351 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 2783351 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 2783351 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 2783351 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 2783351 # number of overall hits -system.cpu1.icache.overall_hits::total 2783351 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 520843 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 520843 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 520843 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 520843 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 520843 # number of overall misses -system.cpu1.icache.overall_misses::total 520843 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7005360499 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7005360499 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7005360499 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7005360499 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7005360499 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7005360499 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 3304194 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 3304194 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 3304194 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 3304194 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 3304194 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 3304194 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.157631 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.157631 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.157631 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.157631 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.157631 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.157631 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13450.042525 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13450.042525 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13450.042525 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13450.042525 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13450.042525 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13450.042525 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1720 # number of cycles access was blocked +system.cpu1.icache.tags.replacements 200477 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.242239 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1230816 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 200989 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.123798 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1882066156500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.242239 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918442 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.918442 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 1639971 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1639971 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1230816 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1230816 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1230816 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1230816 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1230816 # number of overall hits +system.cpu1.icache.overall_hits::total 1230816 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 208101 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 208101 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 208101 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 208101 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 208101 # number of overall misses +system.cpu1.icache.overall_misses::total 208101 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2838828500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2838828500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2838828500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2838828500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2838828500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2838828500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1438917 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1438917 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1438917 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1438917 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1438917 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1438917 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.144623 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.144623 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.144623 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.144623 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.144623 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.144623 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13641.589901 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13641.589901 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13641.589901 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13641.589901 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13641.589901 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13641.589901 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 462 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 65 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 30 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 26.461538 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.400000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 20411 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 20411 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 20411 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 20411 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 20411 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 20411 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 500432 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 500432 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 500432 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 500432 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 500432 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 500432 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6297993499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6297993499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6297993499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6297993499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6297993499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6297993499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.151454 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.151454 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.151454 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12585.113460 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12585.113460 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12585.113460 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7047 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 7047 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 7047 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 7047 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 7047 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 7047 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 201054 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 201054 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 201054 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 201054 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 201054 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 201054 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2552554500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2552554500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2552554500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2552554500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2552554500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2552554500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.139726 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.139726 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.139726 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.139726 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12695.865290 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12695.865290 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12695.865290 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12695.865290 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1543,45 +1525,45 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7377 # Transaction distribution -system.iobus.trans_dist::ReadResp 7377 # Transaction distribution -system.iobus.trans_dist::WriteReq 53912 # Transaction distribution -system.iobus.trans_dist::WriteResp 53912 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10518 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7371 # Transaction distribution +system.iobus.trans_dist::ReadResp 7371 # Transaction distribution +system.iobus.trans_dist::WriteReq 54460 # Transaction distribution +system.iobus.trans_dist::WriteResp 54460 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11610 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122578 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40202 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 123662 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 46440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1872 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 68315 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2729939 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 9868000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 72634 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2734282 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 10965000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 350000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1593,7 +1575,7 @@ system.iobus.reqLayer23.occupancy 13505000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) @@ -1601,52 +1583,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216085248 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216128229 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26764000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27294000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41701 # number of replacements -system.iocache.tags.tagsinuse 0.804902 # Cycle average of tags in use +system.iocache.tags.replacements 41698 # number of replacements +system.iocache.tags.tagsinuse 0.504095 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41717 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711319254000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.804902 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.050306 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.050306 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1711315950000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.504095 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.031506 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.031506 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375543 # Number of tag accesses -system.iocache.tags.data_accesses 375543 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.tags.tag_accesses 375570 # Number of tag accesses +system.iocache.tags.data_accesses 375570 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses +system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses -system.iocache.demand_misses::total 175 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 175 # number of overall misses -system.iocache.overall_misses::total 175 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 25392883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 25392883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907312365 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4907312365 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 25392883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 25392883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 25392883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 25392883 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 178 # number of demand (read+write) misses +system.iocache.demand_misses::total 178 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 178 # number of overall misses +system.iocache.overall_misses::total 178 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22218883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22218883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907321346 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4907321346 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22218883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22218883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22218883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22218883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 178 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 178 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 178 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 178 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1655,14 +1637,14 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 145102.188571 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 145102.188571 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118100.509362 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118100.509362 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 145102.188571 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 145102.188571 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 145102.188571 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 145102.188571 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124825.185393 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124825.185393 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118100.725501 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118100.725501 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 124825.185393 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124825.185393 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 124825.185393 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124825.185393 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1671,24 +1653,24 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41526 # 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number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 16642883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16642883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829712365 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2829712365 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 16642883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16642883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 16642883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16642883 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 178 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 178 # 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number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1697,195 +1679,195 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 95102.188571 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 95102.188571 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68100.509362 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68100.509362 # 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Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1375.831057 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 575.898345 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.815486 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.064295 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.086796 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.020994 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008788 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996358 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2225 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5965 # 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average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 203974.959547 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200730.913495 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 203265.262380 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 201607.350987 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941541 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.813312 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.903382 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.877805 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.933673 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.905422 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.417765 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.271097 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.404665 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014525 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.009113 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013561 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.267774 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.013890 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.253541 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014525 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.299603 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009113 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.093081 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.163785 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014525 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.299603 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009113 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.093081 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.163785 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20846.420745 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20682.634731 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20802.540107 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20803.977273 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20786.885246 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20795.264624 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78686.950306 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99977.129554 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 79960.958820 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 73309.513209 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 73993.449782 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73391.363993 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63027.600114 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81423.900119 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63084.099931 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73309.513209 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67661.174174 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73993.449782 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98060.972615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68476.578575 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73309.513209 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67661.174174 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73993.449782 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98060.972615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68476.578575 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197982.089552 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175645.569620 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197491.450021 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203275.039904 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 208450.589459 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 204431.399132 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201092.268011 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 206746.712689 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 201947.987662 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7202 # Transaction distribution -system.membus.trans_dist::ReadResp 296546 # Transaction distribution -system.membus.trans_dist::WriteReq 12360 # Transaction distribution -system.membus.trans_dist::WriteResp 12360 # Transaction distribution -system.membus.trans_dist::Writeback 124264 # Transaction distribution -system.membus.trans_dist::CleanEvict 262871 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5279 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1481 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3452 # Transaction distribution -system.membus.trans_dist::ReadExReq 122900 # Transaction distribution -system.membus.trans_dist::ReadExResp 122774 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289774 # Transaction distribution -system.membus.trans_dist::BadAddressError 430 # Transaction distribution +system.membus.trans_dist::ReadReq 7193 # Transaction distribution +system.membus.trans_dist::ReadResp 296434 # Transaction distribution +system.membus.trans_dist::WriteReq 12908 # Transaction distribution +system.membus.trans_dist::WriteResp 12908 # Transaction distribution +system.membus.trans_dist::Writeback 122837 # Transaction distribution +system.membus.trans_dist::CleanEvict 263082 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9353 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 4872 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4824 # Transaction distribution +system.membus.trans_dist::ReadExReq 122000 # Transaction distribution +system.membus.trans_dist::ReadExResp 121659 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289315 # Transaction distribution +system.membus.trans_dist::BadAddressError 74 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39124 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179542 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 860 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1219526 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1344359 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68315 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31641920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31710235 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2658624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34368859 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3872 # Total snoops (count) -system.membus.snoop_fanout::samples 867863 # Request fanout histogram +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40202 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1184934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 148 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1225284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1350114 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 72634 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31472384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31545018 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 34203258 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 10191 # Total snoops (count) +system.membus.snoop_fanout::samples 873294 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 867863 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 873294 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 867863 # Request fanout histogram -system.membus.reqLayer0.occupancy 35224999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 873294 # Request fanout histogram +system.membus.reqLayer0.occupancy 36159500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1361324691 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1354680439 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 531000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 95500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2190703579 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2187139696 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 72073655 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 72110882 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 7202 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2275897 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12360 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12360 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 985613 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1602095 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 5338 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1555 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 6893 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 317171 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 317171 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1117101 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1152039 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 430 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 7193 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2235424 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12908 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12908 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 946207 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1643079 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 9387 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 4947 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 14334 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302784 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302784 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1129148 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1099173 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 74 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1728214 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2704934 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1334787 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1622621 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7390556 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39458944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 84672718 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32025024 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 62527373 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 218684059 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 464381 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5618153 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.076464 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.265739 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2591178 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3901537 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 531442 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 279415 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7303572 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 59378176 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 131958120 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 12865536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 9234898 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213436730 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 458492 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5507130 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.077786 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.267834 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 5188566 92.35% 92.35% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 429587 7.65% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 5078755 92.22% 92.22% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 428375 7.78% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5618153 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3461836914 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 5507130 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3369225418 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 240000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 925515973 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1363977262 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1393343588 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1972546779 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 751744303 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 301679801 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 856189885 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 151036436 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2174,32 +2152,32 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4815 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 139340 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 45519 38.89% 38.89% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 133 0.11% 39.01% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1927 1.65% 40.65% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 40.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 69446 59.33% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 117041 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 44932 48.88% 48.88% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 133 0.14% 49.02% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1927 2.10% 51.12% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.02% 51.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 44917 48.86% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 91925 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1870471244000 98.03% 98.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 61392000 0.00% 98.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 548913500 0.03% 98.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8511500 0.00% 98.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 36889187000 1.93% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1907979248000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.987104 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6502 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 187776 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 66469 40.53% 40.53% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.61% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1926 1.17% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 149 0.09% 41.88% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 95308 58.12% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 163983 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 65388 49.23% 49.23% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1926 1.45% 50.77% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 149 0.11% 50.89% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 65239 49.11% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 132833 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864137851500 97.75% 97.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 61127000 0.00% 97.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 545976000 0.03% 97.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 68164000 0.00% 97.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 42142829000 2.21% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1906955947500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983737 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.646790 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.785409 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684507 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810041 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed @@ -2231,60 +2209,60 @@ system.cpu0.kern.syscall::144 2 0.89% 99.11% # nu system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 225 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 104 0.08% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.09% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.09% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.09% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2293 1.85% 1.93% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.04% 1.97% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 1.98% # number of callpals executed -system.cpu0.kern.callpal::swpipl 110963 89.30% 91.28% # number of callpals executed -system.cpu0.kern.callpal::rdps 6296 5.07% 96.35% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.35% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.35% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.36% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.36% # number of callpals executed -system.cpu0.kern.callpal::rti 4002 3.22% 99.58% # number of callpals executed -system.cpu0.kern.callpal::callsys 382 0.31% 99.89% # number of callpals executed -system.cpu0.kern.callpal::imb 138 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 124254 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5723 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1342 # number of protection mode switches +system.cpu0.kern.callpal::wripir 249 0.14% 0.14% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.15% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.15% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.15% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3603 2.09% 2.23% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.26% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed +system.cpu0.kern.callpal::swpipl 157157 91.07% 93.34% # number of callpals executed +system.cpu0.kern.callpal::rdps 6335 3.67% 97.01% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.01% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.02% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 97.02% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.02% # number of callpals executed +system.cpu0.kern.callpal::rti 4619 2.68% 99.70% # number of callpals executed +system.cpu0.kern.callpal::callsys 382 0.22% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 172559 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7164 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1343 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1341 -system.cpu0.kern.mode_good::user 1342 +system.cpu0.kern.mode_good::kernel 1342 +system.cpu0.kern.mode_good::user 1343 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.234318 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.187326 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.379759 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1905987592000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1991648000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.315622 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1904989354500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1966585000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2294 # number of times the context was actually changed +system.cpu0.kern.swap_context 3604 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3855 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 98215 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 36112 40.36% 40.36% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 2.15% 42.52% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 104 0.12% 42.63% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 51325 57.37% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 89466 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 35322 48.67% 48.67% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 2.65% 51.33% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 104 0.14% 51.47% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 35218 48.53% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 72569 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870768654000 98.07% 98.07% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 540231000 0.03% 98.10% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 48911000 0.00% 98.10% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 36277143500 1.90% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1907634939500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978124 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2444 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 51472 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 15731 36.02% 36.02% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 4.41% 40.43% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 249 0.57% 41.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 25763 59.00% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 43668 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 15435 47.07% 47.07% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 5.87% 52.93% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 249 0.76% 53.69% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 15186 46.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 32795 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1874760769500 98.33% 98.33% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 538410500 0.03% 98.36% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 114320500 0.01% 98.36% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 31218212000 1.64% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1906631712500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981184 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.686176 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.811135 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.589450 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.751008 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed @@ -2300,35 +2278,35 @@ system.cpu1.kern.syscall::74 10 9.90% 97.03% # nu system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 101 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1949 2.12% 2.14% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 2.14% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.15% # number of callpals executed -system.cpu1.kern.callpal::swpipl 84230 91.49% 93.64% # number of callpals executed -system.cpu1.kern.callpal::rdps 2466 2.68% 96.32% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 96.32% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.00% 96.32% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 96.33% # number of callpals executed -system.cpu1.kern.callpal::rti 3206 3.48% 99.81% # number of callpals executed -system.cpu1.kern.callpal::callsys 133 0.14% 99.95% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.05% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 149 0.33% 0.33% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu1.kern.callpal::swpctx 911 2.02% 2.35% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 2.36% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 2.38% # number of callpals executed +system.cpu1.kern.callpal::swpipl 38628 85.51% 87.88% # number of callpals executed +system.cpu1.kern.callpal::rdps 2426 5.37% 93.25% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.25% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.26% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.27% # number of callpals executed +system.cpu1.kern.callpal::rti 2865 6.34% 99.61% # number of callpals executed +system.cpu1.kern.callpal::callsys 133 0.29% 99.90% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 92064 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2331 # number of protection mode switches +system.cpu1.kern.callpal::total 45176 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1151 # number of protection mode switches system.cpu1.kern.mode_switch::user 395 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 461 +system.cpu1.kern.mode_switch::idle 2341 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 568 system.cpu1.kern.mode_good::user 395 -system.cpu1.kern.mode_good::idle 66 -system.cpu1.kern.mode_switch_good::kernel 0.197769 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 173 +system.cpu1.kern.mode_switch_good::kernel 0.493484 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.032132 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.192887 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 42837305000 2.25% 2.25% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 697376000 0.04% 2.28% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1863790118000 97.72% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1950 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.073900 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.292256 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 3648998000 0.19% 0.19% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 689386500 0.04% 0.23% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1901995153000 99.77% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 912 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 3eacf4507..2be1ffca4 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -166,7 +166,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -513,7 +513,7 @@ opLat=3 pipelined=false [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -562,7 +562,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -696,7 +696,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=0:134217727 assoc=8 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 156f5647f..275b5ad07 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,111 +1,111 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.861005 # Number of seconds simulated -sim_ticks 1861005347500 # Number of ticks simulated -final_tick 1861005347500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.860990 # Number of seconds simulated +sim_ticks 1860990273000 # Number of ticks simulated +final_tick 1860990273000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149955 # Simulator instruction rate (inst/s) -host_op_rate 149955 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5267476367 # Simulator tick rate (ticks/s) -host_mem_usage 376564 # Number of bytes of host memory used -host_seconds 353.30 # Real time elapsed on the host -sim_insts 52979113 # Number of instructions simulated -sim_ops 52979113 # Number of ops (including micro ops) simulated +host_inst_rate 102674 # Simulator instruction rate (inst/s) +host_op_rate 102674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3606509618 # Simulator tick rate (ticks/s) +host_mem_usage 370916 # Number of bytes of host memory used +host_seconds 516.01 # Real time elapsed on the host +sim_insts 52980740 # Number of instructions simulated +sim_ops 52980740 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 965824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 964096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24880000 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25846272 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 965824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 965824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7524416 # Number of bytes written to this memory -system.physmem.bytes_written::total 7524416 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15091 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388742 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25845056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 964096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 964096 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7523456 # Number of bytes written to this memory +system.physmem.bytes_written::total 7523456 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388750 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403848 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117569 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117569 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13368843 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403829 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117554 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117554 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518055 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13369226 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13888338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518980 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518980 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4043200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4043200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4043200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13368843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13887797 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518055 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518055 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4042716 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4042716 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4042716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13369226 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17931538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403848 # Number of read requests accepted -system.physmem.writeReqs 117569 # Number of write requests accepted -system.physmem.readBursts 403848 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117569 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25839488 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue -system.physmem.bytesWritten 7523328 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25846272 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7524416 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17930514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403829 # Number of read requests accepted +system.physmem.writeReqs 117554 # Number of write requests accepted +system.physmem.readBursts 403829 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117554 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25837696 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue +system.physmem.bytesWritten 7522048 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25845056 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7523456 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 41759 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25651 # Per bank write bursts -system.physmem.perBankRdBursts::1 25422 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 41890 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25640 # Per bank write bursts +system.physmem.perBankRdBursts::1 25420 # Per bank write bursts system.physmem.perBankRdBursts::2 25567 # Per bank write bursts -system.physmem.perBankRdBursts::3 25497 # Per bank write bursts -system.physmem.perBankRdBursts::4 25384 # Per bank write bursts -system.physmem.perBankRdBursts::5 24734 # Per bank write bursts -system.physmem.perBankRdBursts::6 24943 # Per bank write bursts -system.physmem.perBankRdBursts::7 25079 # Per bank write bursts -system.physmem.perBankRdBursts::8 24928 # Per bank write bursts -system.physmem.perBankRdBursts::9 25027 # Per bank write bursts -system.physmem.perBankRdBursts::10 25572 # Per bank write bursts -system.physmem.perBankRdBursts::11 24872 # Per bank write bursts -system.physmem.perBankRdBursts::12 24489 # Per bank write bursts +system.physmem.perBankRdBursts::3 25490 # Per bank write bursts +system.physmem.perBankRdBursts::4 25392 # Per bank write bursts +system.physmem.perBankRdBursts::5 24736 # Per bank write bursts +system.physmem.perBankRdBursts::6 24946 # Per bank write bursts +system.physmem.perBankRdBursts::7 25069 # Per bank write bursts +system.physmem.perBankRdBursts::8 24934 # Per bank write bursts +system.physmem.perBankRdBursts::9 25024 # Per bank write bursts +system.physmem.perBankRdBursts::10 25571 # Per bank write bursts +system.physmem.perBankRdBursts::11 24874 # Per bank write bursts +system.physmem.perBankRdBursts::12 24488 # Per bank write bursts system.physmem.perBankRdBursts::13 25240 # Per bank write bursts system.physmem.perBankRdBursts::14 25741 # Per bank write bursts -system.physmem.perBankRdBursts::15 25596 # Per bank write bursts -system.physmem.perBankWrBursts::0 7944 # Per bank write bursts -system.physmem.perBankWrBursts::1 7514 # Per bank write bursts -system.physmem.perBankWrBursts::2 7965 # Per bank write bursts -system.physmem.perBankWrBursts::3 7518 # Per bank write bursts -system.physmem.perBankWrBursts::4 7330 # Per bank write bursts -system.physmem.perBankWrBursts::5 6666 # Per bank write bursts -system.physmem.perBankWrBursts::6 6776 # Per bank write bursts -system.physmem.perBankWrBursts::7 6716 # Per bank write bursts -system.physmem.perBankWrBursts::8 7141 # Per bank write bursts -system.physmem.perBankWrBursts::9 6711 # Per bank write bursts -system.physmem.perBankWrBursts::10 7422 # Per bank write bursts -system.physmem.perBankWrBursts::11 6968 # Per bank write bursts -system.physmem.perBankWrBursts::12 7145 # Per bank write bursts +system.physmem.perBankRdBursts::15 25582 # Per bank write bursts +system.physmem.perBankWrBursts::0 7942 # Per bank write bursts +system.physmem.perBankWrBursts::1 7515 # Per bank write bursts +system.physmem.perBankWrBursts::2 7958 # Per bank write bursts +system.physmem.perBankWrBursts::3 7515 # Per bank write bursts +system.physmem.perBankWrBursts::4 7335 # Per bank write bursts +system.physmem.perBankWrBursts::5 6671 # Per bank write bursts +system.physmem.perBankWrBursts::6 6772 # Per bank write bursts +system.physmem.perBankWrBursts::7 6705 # Per bank write bursts +system.physmem.perBankWrBursts::8 7147 # Per bank write bursts +system.physmem.perBankWrBursts::9 6708 # Per bank write bursts +system.physmem.perBankWrBursts::10 7414 # Per bank write bursts +system.physmem.perBankWrBursts::11 6974 # Per bank write bursts +system.physmem.perBankWrBursts::12 7148 # Per bank write bursts system.physmem.perBankWrBursts::13 7857 # Per bank write bursts -system.physmem.perBankWrBursts::14 8054 # Per bank write bursts -system.physmem.perBankWrBursts::15 7825 # Per bank write bursts +system.physmem.perBankWrBursts::14 8057 # Per bank write bursts +system.physmem.perBankWrBursts::15 7814 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 23 # Number of times write queue was full causing retry -system.physmem.totGap 1860999975500 # Total gap between requests +system.physmem.numWrRetry 22 # Number of times write queue was full causing retry +system.physmem.totGap 1860985018500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403848 # Read request sizes (log2) +system.physmem.readPktSize::6 403829 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117569 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 36182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28364 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117554 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28406 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 24147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 73 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -148,116 +148,128 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 173 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 41 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61779 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 540.028683 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 331.823835 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.833229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13638 22.08% 22.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10412 16.85% 38.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4989 8.08% 47.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3229 5.23% 52.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2263 3.66% 55.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1516 2.45% 58.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1526 2.47% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1289 2.09% 62.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22917 37.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61779 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5213 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.447919 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2924.392219 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5210 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::60 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61694 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 540.722923 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 331.893410 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.338201 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13637 22.10% 22.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10472 16.97% 39.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4852 7.86% 46.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3164 5.13% 52.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2278 3.69% 55.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1550 2.51% 58.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1469 2.38% 60.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1300 2.11% 62.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22972 37.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61694 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5210 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.486564 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2926.418549 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5207 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5213 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5213 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.549779 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.928650 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.456391 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4618 88.59% 88.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 208 3.99% 92.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 74 1.42% 94.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 17 0.33% 94.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 8 0.15% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 5 0.10% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 10 0.19% 94.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 10 0.19% 94.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 7 0.13% 95.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 32 0.61% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 168 3.22% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 10 0.19% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 5 0.10% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 2 0.04% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.04% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.06% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.04% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 5 0.10% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 3 0.06% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 4 0.08% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 12 0.23% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5213 # Writes before turning the bus around for reads -system.physmem.totQLat 3805918000 # Total ticks spent queuing -system.physmem.totMemAccLat 11376080500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018710000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9426.61 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5210 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5210 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.558925 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.942347 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.343325 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4470 85.80% 85.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 144 2.76% 88.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 197 3.78% 92.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 15 0.29% 92.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 22 0.42% 93.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 47 0.90% 93.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 16 0.31% 94.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.02% 94.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 3 0.06% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.12% 94.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.10% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 4 0.08% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.04% 94.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.06% 94.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 10 0.19% 94.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 6 0.12% 95.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 10 0.19% 95.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 18 0.35% 95.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 17 0.33% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 156 2.99% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 8 0.15% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.13% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.06% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.06% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.06% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 3 0.06% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 2 0.04% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.04% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 4 0.08% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 11 0.21% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5210 # Writes before turning the bus around for reads +system.physmem.totQLat 3803541750 # Total ticks spent queuing +system.physmem.totMemAccLat 11373179250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018570000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9421.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28176.61 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28171.38 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s @@ -266,72 +278,72 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.30 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing -system.physmem.readRowHits 364169 # Number of row buffer hits during reads -system.physmem.writeRowHits 95345 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.20 # Row buffer hit rate for reads +system.physmem.avgRdQLen 2.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.35 # Average write queue length when enqueuing +system.physmem.readRowHits 364213 # Number of row buffer hits during reads +system.physmem.writeRowHits 95338 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.22 # Row buffer hit rate for reads system.physmem.writeRowHitRate 81.10 # Row buffer hit rate for writes -system.physmem.avgGap 3569120.25 # Average gap between requests -system.physmem.pageHitRate 88.15 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 232515360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 126868500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577760600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 378619920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 56250477360 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1067257263000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1247374938900 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.271455 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1775312455750 # Time in different power states -system.physmem_0.memoryStateTime::REF 62142860000 # Time in different power states +system.physmem.avgGap 3569324.31 # Average gap between requests +system.physmem.pageHitRate 88.16 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 231343560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 126229125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577628000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 378516240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 121550417040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 56189479095 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1067301426750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1247355039810 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.266370 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1775383293000 # Time in different power states +system.physmem_0.memoryStateTime::REF 62142340000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23544343000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23458453250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 234533880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 127969875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1571380200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 383117040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 55982569095 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1067492278500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1247343282750 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.254439 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1775708219250 # Time in different power states -system.physmem_1.memoryStateTime::REF 62142860000 # Time in different power states +system.physmem_1.actEnergy 235063080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 128258625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1571294400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 383091120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 121550417040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 55921872645 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1067536177500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1247326174410 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.250855 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1775778508500 # Time in different power states +system.physmem_1.memoryStateTime::REF 62142340000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23148593250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23063881500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17721018 # Number of BP lookups -system.cpu.branchPred.condPredicted 15408782 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 378784 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12470436 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5897235 # Number of BTB hits +system.cpu.branchPred.lookups 17952495 # Number of BP lookups +system.cpu.branchPred.condPredicted 15650737 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 369298 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11540660 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5852648 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 47.289726 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 918220 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21032 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 50.713287 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 911814 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21176 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10294388 # DTB read hits -system.cpu.dtb.read_misses 42024 # DTB read misses -system.cpu.dtb.read_acv 506 # DTB read access violations -system.cpu.dtb.read_accesses 968687 # DTB read accesses -system.cpu.dtb.write_hits 6648521 # DTB write hits -system.cpu.dtb.write_misses 9456 # DTB write misses -system.cpu.dtb.write_acv 408 # DTB write access violations -system.cpu.dtb.write_accesses 343243 # DTB write accesses -system.cpu.dtb.data_hits 16942909 # DTB hits -system.cpu.dtb.data_misses 51480 # DTB misses -system.cpu.dtb.data_acv 914 # DTB access violations -system.cpu.dtb.data_accesses 1311930 # DTB accesses -system.cpu.itb.fetch_hits 1769476 # ITB hits -system.cpu.itb.fetch_misses 36155 # ITB misses -system.cpu.itb.fetch_acv 662 # ITB acv -system.cpu.itb.fetch_accesses 1805631 # ITB accesses +system.cpu.dtb.read_hits 10266725 # DTB read hits +system.cpu.dtb.read_misses 41420 # DTB read misses +system.cpu.dtb.read_acv 529 # DTB read access violations +system.cpu.dtb.read_accesses 965767 # DTB read accesses +system.cpu.dtb.write_hits 6642195 # DTB write hits +system.cpu.dtb.write_misses 9809 # DTB write misses +system.cpu.dtb.write_acv 405 # DTB write access violations +system.cpu.dtb.write_accesses 342270 # DTB write accesses +system.cpu.dtb.data_hits 16908920 # DTB hits +system.cpu.dtb.data_misses 51229 # DTB misses +system.cpu.dtb.data_acv 934 # DTB access violations +system.cpu.dtb.data_accesses 1308037 # DTB accesses +system.cpu.itb.fetch_hits 1768997 # ITB hits +system.cpu.itb.fetch_misses 27603 # ITB misses +system.cpu.itb.fetch_acv 655 # ITB acv +system.cpu.itb.fetch_accesses 1796600 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -344,691 +356,692 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 122272854 # number of cpu cycles simulated +system.cpu.numCycles 122250725 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29542399 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 77951342 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17721018 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6815455 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 84318662 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1251172 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1032 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 27002 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1751503 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 450615 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 220 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9037094 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 274713 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116717019 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.667866 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.979948 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29590872 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78035312 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17952495 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6764462 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 84736015 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1230846 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3604 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1246103 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 463506 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 270 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8988072 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 271207 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 116683770 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.668776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.983888 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 102159840 87.53% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 935001 0.80% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1975635 1.69% 90.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 907890 0.78% 90.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2798283 2.40% 93.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 634657 0.54% 93.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 731012 0.63% 94.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1008696 0.86% 95.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5566005 4.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 102162821 87.56% 87.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 926771 0.79% 88.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1955000 1.68% 90.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 905545 0.78% 90.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2771139 2.37% 93.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 614884 0.53% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 724459 0.62% 94.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1009032 0.86% 95.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5614119 4.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116717019 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.144930 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.637520 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24051579 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 80690981 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9487535 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1903773 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 583150 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 586842 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42848 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68182155 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 134674 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 583150 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24974215 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50913599 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20868972 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10381558 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8995523 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65764072 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 201455 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2078667 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 157006 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4811107 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43858088 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79749030 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79568293 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168286 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38179356 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5678724 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1691117 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 241700 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13523739 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10414999 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6951257 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1489090 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1076371 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58557437 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2137330 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57550552 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 58383 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7715649 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3482179 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1476201 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116717019 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.493078 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.231262 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 116683770 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.146850 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.638322 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24065548 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 80700938 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9436968 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1906955 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 573360 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 582340 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42404 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68029803 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 132508 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 573360 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24987085 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50897393 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20868454 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10337136 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9020340 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65614260 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 203152 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2087104 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 150571 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4833262 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43733220 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79561709 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79380946 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168313 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38180223 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5552989 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1689330 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239361 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13544094 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10376074 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6949198 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1492318 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1087072 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58452380 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2137932 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57496742 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 57057 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7609567 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3401604 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1476871 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116683770 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.492757 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.231576 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 93076852 79.75% 79.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10193735 8.73% 88.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4312708 3.70% 92.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3021195 2.59% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3081764 2.64% 97.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1495449 1.28% 98.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1007889 0.86% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 403235 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 124192 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 93080109 79.77% 79.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10182698 8.73% 88.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4288903 3.68% 92.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3018996 2.59% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3082938 2.64% 97.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1488362 1.28% 98.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1011835 0.87% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 404754 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125175 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116717019 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116683770 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 208462 18.43% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547266 48.38% 66.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 375475 33.19% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 209669 18.63% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 542046 48.17% 66.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 373622 33.20% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39056911 67.87% 67.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61891 0.11% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38552 0.07% 68.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10704988 18.60% 86.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6728388 11.69% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 948900 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39037181 67.89% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61834 0.11% 68.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38554 0.07% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10676723 18.57% 86.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6722717 11.69% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948811 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57550552 # Type of FU issued -system.cpu.iq.rate 0.470673 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1131203 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019656 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 232294841 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68093775 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55871823 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 712867 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336544 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 329026 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58291729 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 382740 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 634925 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57496742 # Type of FU issued +system.cpu.iq.rate 0.470318 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1125337 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019572 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 232146820 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67882277 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55834928 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 712827 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336508 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328971 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58232105 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 382688 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 634703 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1322411 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3516 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20331 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 573217 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1283936 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3373 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19308 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 571381 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18302 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 483316 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18194 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 477327 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 583150 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 47678109 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 871068 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64398227 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 142430 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10414999 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6951257 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1888726 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 44438 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 623782 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20331 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 186400 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411798 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 598198 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56961347 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10364061 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 589204 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 573360 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 47668673 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 853294 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64278853 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 140556 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10376074 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6949198 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1890343 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 43583 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 606693 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19308 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 178271 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 409117 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 587388 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56911436 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10335818 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 585305 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3703460 # number of nop insts executed -system.cpu.iew.exec_refs 17037134 # number of memory reference insts executed -system.cpu.iew.exec_branches 8968929 # Number of branches executed -system.cpu.iew.exec_stores 6673073 # Number of stores executed -system.cpu.iew.exec_rate 0.465854 # Inst execution rate -system.cpu.iew.wb_sent 56337909 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56200849 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28756133 # num instructions producing a value -system.cpu.iew.wb_consumers 39912635 # num instructions consuming a value +system.cpu.iew.exec_nop 3688541 # number of nop insts executed +system.cpu.iew.exec_refs 17002933 # number of memory reference insts executed +system.cpu.iew.exec_branches 8971597 # Number of branches executed +system.cpu.iew.exec_stores 6667115 # Number of stores executed +system.cpu.iew.exec_rate 0.465530 # Inst execution rate +system.cpu.iew.wb_sent 56299831 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56163899 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28741573 # num instructions producing a value +system.cpu.iew.wb_consumers 39917507 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.459635 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.720477 # average fanout of values written-back +system.cpu.iew.wb_rate 0.459416 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.720024 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8112704 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661129 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 547326 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 115294268 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.487187 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.430320 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7990103 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661061 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 538190 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 115283305 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.487246 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.430050 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 95501177 82.83% 82.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7867272 6.82% 89.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4280982 3.71% 93.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2233083 1.94% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1745854 1.51% 96.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 611445 0.53% 97.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 482985 0.42% 97.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 468960 0.41% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2102510 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 95489644 82.83% 82.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7861367 6.82% 89.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4279666 3.71% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2238986 1.94% 95.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1753667 1.52% 96.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 610357 0.53% 97.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 475106 0.41% 97.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 479497 0.42% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2095015 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 115294268 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56169836 # Number of instructions committed -system.cpu.commit.committedOps 56169836 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 115283305 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56171345 # Number of instructions committed +system.cpu.commit.committedOps 56171345 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470628 # Number of memory references committed -system.cpu.commit.loads 9092588 # Number of loads committed -system.cpu.commit.membars 226333 # Number of memory barriers committed -system.cpu.commit.branches 8440353 # Number of branches committed +system.cpu.commit.refs 15469955 # Number of memory references committed +system.cpu.commit.loads 9092138 # Number of loads committed +system.cpu.commit.membars 226307 # Number of memory barriers committed +system.cpu.commit.branches 8441356 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52019375 # Number of committed integer instructions. -system.cpu.commit.function_calls 740552 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3197996 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36217639 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60667 0.11% 70.28% # Class of committed instruction +system.cpu.commit.int_insts 52021098 # Number of committed integer instructions. +system.cpu.commit.function_calls 740502 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3197878 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36220066 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60657 0.11% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9318921 16.59% 86.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6383992 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 948900 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9318445 16.59% 86.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6383767 11.36% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 948811 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56169836 # Class of committed instruction -system.cpu.commit.bw_lim_events 2102510 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 177224791 # The number of ROB reads -system.cpu.rob.rob_writes 129983616 # The number of ROB writes -system.cpu.timesIdled 573073 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5555835 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599737842 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52979113 # Number of Instructions Simulated -system.cpu.committedOps 52979113 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.307945 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.307945 # CPI: Total CPI of All Threads -system.cpu.ipc 0.433286 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.433286 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74622251 # number of integer regfile reads -system.cpu.int_regfile_writes 40551917 # number of integer regfile writes -system.cpu.fp_regfile_reads 167069 # number of floating regfile reads -system.cpu.fp_regfile_writes 167545 # number of floating regfile writes -system.cpu.misc_regfile_reads 2028916 # number of misc regfile reads -system.cpu.misc_regfile_writes 939321 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1404299 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994455 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11844191 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1404811 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.431163 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 26393500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994455 # Average occupied blocks per requestor +system.cpu.commit.op_class_0::total 56171345 # Class of committed instruction +system.cpu.commit.bw_lim_events 2095015 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 177100105 # The number of ROB reads +system.cpu.rob.rob_writes 129718981 # The number of ROB writes +system.cpu.timesIdled 575678 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5566955 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599729822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52980740 # Number of Instructions Simulated +system.cpu.committedOps 52980740 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.307456 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.307456 # CPI: Total CPI of All Threads +system.cpu.ipc 0.433378 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.433378 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74560962 # number of integer regfile reads +system.cpu.int_regfile_writes 40515010 # number of integer regfile writes +system.cpu.fp_regfile_reads 167029 # number of floating regfile reads +system.cpu.fp_regfile_writes 167528 # number of floating regfile writes +system.cpu.misc_regfile_reads 2030483 # number of misc regfile reads +system.cpu.misc_regfile_writes 939256 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1402429 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994497 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11825966 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1402941 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.429411 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 26175500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994497 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 412 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63926076 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63926076 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7252822 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7252822 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4188714 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4188714 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186644 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186644 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215706 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215706 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11441536 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11441536 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11441536 # number of overall hits -system.cpu.dcache.overall_hits::total 11441536 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1804157 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1804157 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1958890 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1958890 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23354 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23354 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 29 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3763047 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3763047 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3763047 # number of overall misses -system.cpu.dcache.overall_misses::total 3763047 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 41750233000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 41750233000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 80527676066 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 80527676066 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 377889000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 377889000 # 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number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30575992000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30575992000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12635842717 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12635842717 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 226273500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 226273500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 469500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 469500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43211834717 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 43211834717 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43211834717 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 43211834717 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1451037500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1451037500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2035928998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2035928998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3486966498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3486966498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121007 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121007 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047305 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047305 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086682 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086682 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000134 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000134 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091208 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091208 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091208 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091208 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27898.770213 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27898.770213 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43450.061438 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43450.061438 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12430.560897 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12430.560897 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16189.655172 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16189.655172 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31159.946435 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31159.946435 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31159.946435 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31159.946435 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209384.920635 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209384.920635 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212142.231739 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212142.231739 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210986.053004 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210986.053004 # average overall mshr uncacheable latency +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9596 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 9596 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16526 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 16526 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30550296500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30550296500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12634151241 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12634151241 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 226327000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 226327000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 457000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 457000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43184447741 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 43184447741 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43184447741 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 43184447741 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450758000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450758000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2035709998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2035709998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3486467998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3486467998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121105 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121105 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047291 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047291 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086658 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086658 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091219 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091219 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091219 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091219 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27918.094771 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27918.094771 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43458.441655 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43458.441655 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12471.181397 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12471.181397 # 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average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212141.517090 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210968.655331 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210968.655331 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1035158 # number of replacements -system.cpu.icache.tags.tagsinuse 509.238634 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7947846 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1035666 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.674140 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 28148361500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.238634 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994607 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994607 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1038549 # number of replacements +system.cpu.icache.tags.tagsinuse 509.170339 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7895321 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1039057 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.598545 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 28146856500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.170339 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994473 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994473 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10073023 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10073023 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7947847 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7947847 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7947847 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7947847 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7947847 # number of overall hits -system.cpu.icache.overall_hits::total 7947847 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1089244 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1089244 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1089244 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1089244 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1089244 # number of overall misses -system.cpu.icache.overall_misses::total 1089244 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15223822993 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15223822993 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15223822993 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15223822993 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15223822993 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15223822993 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9037091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9037091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9037091 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9037091 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9037091 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9037091 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120530 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.120530 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.120530 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.120530 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.120530 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.120530 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13976.503881 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13976.503881 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13976.503881 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13976.503881 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13976.503881 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13976.503881 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5247 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10027494 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10027494 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7895322 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7895322 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7895322 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7895322 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7895322 # number of overall hits +system.cpu.icache.overall_hits::total 7895322 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1092746 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1092746 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1092746 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1092746 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1092746 # number of overall misses +system.cpu.icache.overall_misses::total 1092746 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15273300993 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15273300993 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15273300993 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15273300993 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15273300993 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15273300993 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8988068 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8988068 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8988068 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8988068 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8988068 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8988068 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121577 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.121577 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.121577 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.121577 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.121577 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.121577 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13976.990987 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13976.990987 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13976.990987 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13976.990987 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13976.990987 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13976.990987 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6859 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 192 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 220 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 27.328125 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.177273 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53312 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 53312 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 53312 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 53312 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 53312 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 53312 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035932 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1035932 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1035932 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1035932 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1035932 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1035932 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13551519997 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13551519997 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13551519997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13551519997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13551519997 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13551519997 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114631 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114631 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114631 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114631 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114631 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114631 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13081.476387 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13081.476387 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13081.476387 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13081.476387 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13081.476387 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13081.476387 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53320 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 53320 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 53320 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 53320 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 53320 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 53320 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1039426 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1039426 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1039426 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1039426 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1039426 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1039426 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13594657497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13594657497 # 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number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364412500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364412500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1925547500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1925547500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3289960000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3289960000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9596 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9596 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16526 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16526 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2195000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2195000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 124000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 124000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9147908500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9147908500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1108373500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1108373500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17263967500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17263967500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1108373500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26411876000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27520249500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1108373500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26411876000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27520249500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364133000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364133000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1925339500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1925339500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3289472500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3289472500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.646341 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.646341 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.206897 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.206897 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382611 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382611 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014571 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014571 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248213 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248213 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014571 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277067 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165671 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014571 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277067 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165671 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 23594.339623 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23594.339623 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 20750 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20750 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79278.696764 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79278.696764 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73289.027299 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73289.027299 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63057.724049 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63057.724049 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73289.027299 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67866.912352 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68069.291418 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73289.027299 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67866.912352 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68069.291418 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196884.920635 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196884.920635 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200640.564760 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200640.564760 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199065.771162 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199065.771162 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.771654 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.771654 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383114 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383114 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014498 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248597 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248597 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277502 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.165595 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014498 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277502 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.165595 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22397.959184 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22397.959184 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 20666.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20666.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79200.613837 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79200.613837 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73572.751411 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73572.751411 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63044.224891 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63044.224891 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73572.751411 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67837.212528 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68050.873254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73572.751411 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67837.212528 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68050.873254 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196844.588745 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196844.588745 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200639.797832 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200639.797832 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199048.317802 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199048.317802 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2146205 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 960354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1857372 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 82 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 301625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1035932 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1103445 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 85 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2147969 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9596 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9596 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 959201 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1860011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 127 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 155 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301485 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301485 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1039426 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101712 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 82 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3106451 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4246137 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7352588 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66287680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143898860 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 210186540 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 422109 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5318690 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.079299 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.270205 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3116681 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4240614 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7357295 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66503296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143706404 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 210209700 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422216 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5321857 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.079248 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.270126 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4896924 92.07% 92.07% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 421766 7.93% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4900109 92.08% 92.08% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 421748 7.92% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5318690 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3296022500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5321857 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3296477500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1555343104 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1560615042 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2119169250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2116394230 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1187,9 +1200,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51149 # Transaction distribution -system.iobus.trans_dist::WriteResp 51149 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51148 # Transaction distribution +system.iobus.trans_dist::WriteResp 51148 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5048 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1201,11 +1214,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33054 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33052 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116504 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20200 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116502 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20192 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1217,11 +1230,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44140 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44132 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705748 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4661000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705740 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4659000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1243,23 +1256,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 216065006 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216075504 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23456000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.259177 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.259061 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711311931000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.259177 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078699 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078699 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1711310965000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.259061 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078691 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078691 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1275,8 +1288,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4909206123 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4909206123 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908771621 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4908771621 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles @@ -1299,17 +1312,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118146.084978 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118146.084978 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118135.628153 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118135.628153 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 18 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1325,8 +1338,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831606123 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2831606123 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831171621 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2831171621 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles @@ -1341,60 +1354,60 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68146.084978 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68146.084978 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68135.628153 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68135.628153 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295956 # Transaction distribution -system.membus.trans_dist::WriteReq 9597 # Transaction distribution -system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117569 # Transaction distribution -system.membus.trans_dist::CleanEvict 261797 # Transaction distribution -system.membus.trans_dist::UpgradeReq 204 # Transaction distribution +system.membus.trans_dist::ReadResp 295925 # Transaction distribution +system.membus.trans_dist::WriteReq 9596 # Transaction distribution +system.membus.trans_dist::WriteResp 9596 # Transaction distribution +system.membus.trans_dist::Writeback 117554 # Transaction distribution +system.membus.trans_dist::CleanEvict 261799 # Transaction distribution +system.membus.trans_dist::UpgradeReq 335 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 210 # Transaction distribution -system.membus.trans_dist::ReadExReq 115254 # Transaction distribution -system.membus.trans_dist::ReadExResp 115254 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289111 # Transaction distribution -system.membus.trans_dist::BadAddressError 85 # Transaction distribution +system.membus.trans_dist::UpgradeResp 341 # Transaction distribution +system.membus.trans_dist::ReadExReq 115266 # Transaction distribution +system.membus.trans_dist::ReadExResp 115266 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289077 # Transaction distribution +system.membus.trans_dist::BadAddressError 82 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179422 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33052 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146409 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 164 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179625 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1304239 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30712960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30757100 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1304442 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44132 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30710784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30754916 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33414828 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33412644 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 842203 # Request fanout histogram +system.membus.snoop_fanout::samples 842297 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 842203 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 842297 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 842203 # Request fanout histogram -system.membus.reqLayer0.occupancy 29160500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 842297 # Request fanout histogram +system.membus.reqLayer0.occupancy 28891000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1313577675 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1313747676 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 109500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 109000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2139558790 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2139659662 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 72030935 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1430,28 +1443,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 210978 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74652 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210955 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74645 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105547 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182209 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73285 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1878 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105533 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182187 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73278 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73285 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148580 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817522630000 97.66% 97.66% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 62579500 0.00% 97.67% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 533633500 0.03% 97.70% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 42885651500 2.30% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1861004494500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981688 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1878 1.26% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73278 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148565 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817526707500 97.66% 97.66% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 62603000 0.00% 97.67% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 536431500 0.03% 97.70% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 42863705000 2.30% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860989447000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981687 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694335 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815437 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694361 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815453 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1490,29 +1503,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175094 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175074 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5103 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191938 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1907 -system.cpu.kern.mode_good::user 1737 +system.cpu.kern.callpal::total 191916 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5848 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.325983 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326436 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393886 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29174464500 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2684090500 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1829145931500 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394259 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29189899500 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2667621500 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1829131918000 98.29% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini index d49d26c09..df18f1206 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini @@ -98,7 +98,7 @@ dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -138,7 +138,7 @@ eventq_index=0 size=64 [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -750,7 +750,7 @@ master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=0:134217727 assoc=8 @@ -785,7 +785,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr index ae9247519..1b889d7a1 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr @@ -7,10 +7,6 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 8155, Bank: 7 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -19,8 +15,6 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 11185, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -54,6 +48,6 @@ Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 11369, Bank: 3 +Command: 0, Timestamp: 11394, Bank: 3 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout index 29e1e9099..930df34c1 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 07:55:25 -gem5 started Apr 22 2015 08:35:45 -gem5 executing on phenom -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full +gem5 compiled Sep 14 2015 20:54:01 +gem5 started Sep 14 2015 20:54:31 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full Global frequency set at 1000000000000 ticks per second 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 8b67c053c..296ab434c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841548 # Number of seconds simulated -sim_ticks 1841548033500 # Number of ticks simulated -final_tick 1841548033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841535 # Number of seconds simulated +sim_ticks 1841535479500 # Number of ticks simulated +final_tick 1841535479500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 218310 # Simulator instruction rate (inst/s) -host_op_rate 218310 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5702515722 # Simulator tick rate (ticks/s) -host_mem_usage 375536 # Number of bytes of host memory used -host_seconds 322.94 # Real time elapsed on the host -sim_insts 70500110 # Number of instructions simulated -sim_ops 70500110 # Number of ops (including micro ops) simulated +host_inst_rate 156573 # Simulator instruction rate (inst/s) +host_op_rate 156573 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3970842510 # Simulator tick rate (ticks/s) +host_mem_usage 369896 # Number of bytes of host memory used +host_seconds 463.76 # Real time elapsed on the host +sim_insts 72613172 # Number of instructions simulated +sim_ops 72613172 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 465600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20057408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2156416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 307456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2656704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 466112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20058112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2156288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 305728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2656832 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25791680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 465600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 307456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 920192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7484672 # Number of bytes written to this memory -system.physmem.bytes_written::total 7484672 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 313397 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2299 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 33694 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4804 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41511 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25791040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 466112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 305728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 918848 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7482432 # Number of bytes written to this memory +system.physmem.bytes_written::total 7482432 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7283 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 313408 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 33692 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4777 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41513 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 402995 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116948 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116948 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 252831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10891602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1170980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 166955 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1442647 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 402985 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116913 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116913 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 253111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10892058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79829 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1170919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 166018 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1442726 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14005434 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 252831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79898 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 166955 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 499684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4064337 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4064337 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4064337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 252831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10891602 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1170980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 166955 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1442647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 14005182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 253111 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79829 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 166018 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498958 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4063148 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4063148 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4063148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 253111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10892058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1170919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 166018 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1442726 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18069771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 82323 # Number of read requests accepted -system.physmem.writeReqs 47461 # Number of write requests accepted -system.physmem.readBursts 82323 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 47461 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5267264 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1408 # Total number of bytes read from write queue -system.physmem.bytesWritten 3035584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5268672 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 3037504 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 22 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 18068331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 82294 # Number of read requests accepted +system.physmem.writeReqs 47398 # Number of write requests accepted +system.physmem.readBursts 82294 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 47398 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5265472 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1344 # Total number of bytes read from write queue +system.physmem.bytesWritten 3032512 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5266816 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 3033472 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 21 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 17348 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 4998 # Per bank write bursts -system.physmem.perBankRdBursts::1 5047 # Per bank write bursts -system.physmem.perBankRdBursts::2 4951 # Per bank write bursts -system.physmem.perBankRdBursts::3 4902 # Per bank write bursts -system.physmem.perBankRdBursts::4 5135 # Per bank write bursts -system.physmem.perBankRdBursts::5 5137 # Per bank write bursts -system.physmem.perBankRdBursts::6 5321 # Per bank write bursts -system.physmem.perBankRdBursts::7 5238 # Per bank write bursts -system.physmem.perBankRdBursts::8 5355 # Per bank write bursts -system.physmem.perBankRdBursts::9 4827 # Per bank write bursts -system.physmem.perBankRdBursts::10 5539 # Per bank write bursts -system.physmem.perBankRdBursts::11 5124 # Per bank write bursts -system.physmem.perBankRdBursts::12 4881 # Per bank write bursts -system.physmem.perBankRdBursts::13 5044 # Per bank write bursts -system.physmem.perBankRdBursts::14 5631 # Per bank write bursts -system.physmem.perBankRdBursts::15 5171 # Per bank write bursts -system.physmem.perBankWrBursts::0 2712 # Per bank write bursts -system.physmem.perBankWrBursts::1 2869 # Per bank write bursts -system.physmem.perBankWrBursts::2 2967 # Per bank write bursts -system.physmem.perBankWrBursts::3 2927 # Per bank write bursts -system.physmem.perBankWrBursts::4 2992 # Per bank write bursts -system.physmem.perBankWrBursts::5 2769 # Per bank write bursts -system.physmem.perBankWrBursts::6 3293 # Per bank write bursts -system.physmem.perBankWrBursts::7 2918 # Per bank write bursts -system.physmem.perBankWrBursts::8 3398 # Per bank write bursts -system.physmem.perBankWrBursts::9 2634 # Per bank write bursts -system.physmem.perBankWrBursts::10 3325 # Per bank write bursts -system.physmem.perBankWrBursts::11 2913 # Per bank write bursts -system.physmem.perBankWrBursts::12 2642 # Per bank write bursts -system.physmem.perBankWrBursts::13 2800 # Per bank write bursts -system.physmem.perBankWrBursts::14 3388 # Per bank write bursts -system.physmem.perBankWrBursts::15 2884 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 17325 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5126 # Per bank write bursts +system.physmem.perBankRdBursts::1 5048 # Per bank write bursts +system.physmem.perBankRdBursts::2 4814 # Per bank write bursts +system.physmem.perBankRdBursts::3 4971 # Per bank write bursts +system.physmem.perBankRdBursts::4 5248 # Per bank write bursts +system.physmem.perBankRdBursts::5 5169 # Per bank write bursts +system.physmem.perBankRdBursts::6 5184 # Per bank write bursts +system.physmem.perBankRdBursts::7 5149 # Per bank write bursts +system.physmem.perBankRdBursts::8 5417 # Per bank write bursts +system.physmem.perBankRdBursts::9 4756 # Per bank write bursts +system.physmem.perBankRdBursts::10 5535 # Per bank write bursts +system.physmem.perBankRdBursts::11 5117 # Per bank write bursts +system.physmem.perBankRdBursts::12 4885 # Per bank write bursts +system.physmem.perBankRdBursts::13 5047 # Per bank write bursts +system.physmem.perBankRdBursts::14 5632 # Per bank write bursts +system.physmem.perBankRdBursts::15 5175 # Per bank write bursts +system.physmem.perBankWrBursts::0 2819 # Per bank write bursts +system.physmem.perBankWrBursts::1 2870 # Per bank write bursts +system.physmem.perBankWrBursts::2 2836 # Per bank write bursts +system.physmem.perBankWrBursts::3 2977 # Per bank write bursts +system.physmem.perBankWrBursts::4 3104 # Per bank write bursts +system.physmem.perBankWrBursts::5 2797 # Per bank write bursts +system.physmem.perBankWrBursts::6 3160 # Per bank write bursts +system.physmem.perBankWrBursts::7 2831 # Per bank write bursts +system.physmem.perBankWrBursts::8 3459 # Per bank write bursts +system.physmem.perBankWrBursts::9 2567 # Per bank write bursts +system.physmem.perBankWrBursts::10 3319 # Per bank write bursts +system.physmem.perBankWrBursts::11 2907 # Per bank write bursts +system.physmem.perBankWrBursts::12 2644 # Per bank write bursts +system.physmem.perBankWrBursts::13 2801 # Per bank write bursts +system.physmem.perBankWrBursts::14 3392 # Per bank write bursts +system.physmem.perBankWrBursts::15 2900 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1840536161000 # Total gap between requests +system.physmem.totGap 1840523607000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 82323 # Read request sizes (log2) +system.physmem.readPktSize::6 82294 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 47461 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 64278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5619 # What read queue length does an incoming req see +system.physmem.writePktSize::6 47398 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 64239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7821 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5630 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 4551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -153,140 +153,137 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 26 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21805 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 380.777253 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 217.097266 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 378.211296 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7203 33.03% 33.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4880 22.38% 55.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 2010 9.22% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1038 4.76% 69.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 857 3.93% 73.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 538 2.47% 75.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 425 1.95% 77.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 372 1.71% 79.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4482 20.55% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21805 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2075 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 39.654458 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 980.113813 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2073 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21780 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 380.991001 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 216.949703 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 378.684450 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7216 33.13% 33.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4887 22.44% 55.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1962 9.01% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1034 4.75% 69.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 848 3.89% 73.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 523 2.40% 75.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 452 2.08% 77.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 368 1.69% 79.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4490 20.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21780 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2078 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 39.592397 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 979.363215 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2076 99.90% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2075 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.858313 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.353134 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.870235 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 34 1.64% 1.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.34% 1.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 2 0.10% 2.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 5 0.24% 2.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1736 83.66% 85.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 36 1.73% 87.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 80 3.86% 91.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 17 0.82% 92.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 12 0.58% 92.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 17 0.82% 93.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 5 0.24% 94.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.05% 94.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.05% 94.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.10% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 3 0.14% 94.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.05% 94.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.19% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.05% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.10% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.05% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.14% 94.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 9 0.43% 95.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.19% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 65 3.13% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.14% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.14% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.05% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 2 0.10% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.05% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.05% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.05% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.10% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.10% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.10% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.05% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 3 0.14% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.05% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 4 0.19% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2075 # Writes before turning the bus around for reads -system.physmem.totQLat 914891250 # Total ticks spent queuing -system.physmem.totMemAccLat 2458035000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 411505000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11116.41 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2078 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2078 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.802214 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.584158 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.825875 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 29 1.40% 1.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 6 0.29% 1.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.05% 1.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 6 0.29% 2.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1724 82.96% 84.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 39 1.88% 86.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 91 4.38% 91.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 19 0.91% 92.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 9 0.43% 92.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 19 0.91% 93.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 4 0.19% 93.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 2 0.10% 93.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.14% 93.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.05% 93.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 2 0.10% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.14% 94.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.05% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.14% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 4 0.19% 94.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 8 0.38% 95.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.19% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 76 3.66% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 6 0.29% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.10% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.05% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.14% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.10% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.05% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.05% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.05% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.10% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 2 0.10% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2078 # Writes before turning the bus around for reads +system.physmem.totQLat 922774500 # Total ticks spent queuing +system.physmem.totMemAccLat 2465393250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 411365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11216.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29866.41 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29966.01 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.86 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.65 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.86 # Average system read bandwidth in MiByte/s @@ -295,63 +292,63 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 2.86 # Average write queue length when enqueuing -system.physmem.readRowHits 70476 # Number of row buffer hits during reads -system.physmem.writeRowHits 37451 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.91 # Row buffer hit rate for writes -system.physmem.avgGap 14181533.63 # Average gap between requests -system.physmem.pageHitRate 83.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 81194400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 44195250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 317686200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 151936560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89056992960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 35637705585 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 799850646000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 925140356955 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.881529 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1309035077000 # Time in different power states -system.physmem_0.memoryStateTime::REF 45530160000 # Time in different power states +system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing +system.physmem.avgWrQLen 16.09 # Average write queue length when enqueuing +system.physmem.readRowHits 70442 # Number of row buffer hits during reads +system.physmem.writeRowHits 37434 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.98 # Row buffer hit rate for writes +system.physmem.avgGap 14191496.83 # Average gap between requests +system.physmem.pageHitRate 83.19 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 81065880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 44121000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 317530200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 151593120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 35745647625 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 800947233750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 926343167415 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.792687 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1308857547000 # Time in different power states +system.physmem_0.memoryStateTime::REF 45529640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9110965500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9287627500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 83651400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 45474000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 324261600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 155416320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89056992960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35441943930 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 803933138250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 929040878460 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.556246 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1309294919000 # Time in different power states -system.physmem_1.memoryStateTime::REF 45530160000 # Time in different power states +system.physmem_1.actEnergy 83590920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 45449250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 324199200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 155448720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35447161140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 801537520500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 926649345570 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.749891 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1309278655250 # Time in different power states +system.physmem_1.memoryStateTime::REF 45529640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8868165750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8857363000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4775602 # DTB read hits -system.cpu0.dtb.read_misses 5966 # DTB read misses +system.cpu0.dtb.read_hits 4774172 # DTB read hits +system.cpu0.dtb.read_misses 5959 # DTB read misses system.cpu0.dtb.read_acv 109 # DTB read access violations -system.cpu0.dtb.read_accesses 428378 # DTB read accesses -system.cpu0.dtb.write_hits 3387346 # DTB write hits -system.cpu0.dtb.write_misses 667 # DTB write misses +system.cpu0.dtb.read_accesses 427834 # DTB read accesses +system.cpu0.dtb.write_hits 3388527 # DTB write hits +system.cpu0.dtb.write_misses 664 # DTB write misses system.cpu0.dtb.write_acv 80 # DTB write access violations -system.cpu0.dtb.write_accesses 163776 # DTB write accesses -system.cpu0.dtb.data_hits 8162948 # DTB hits -system.cpu0.dtb.data_misses 6633 # DTB misses +system.cpu0.dtb.write_accesses 164366 # DTB write accesses +system.cpu0.dtb.data_hits 8162699 # DTB hits +system.cpu0.dtb.data_misses 6623 # DTB misses system.cpu0.dtb.data_acv 189 # DTB access violations -system.cpu0.dtb.data_accesses 592154 # DTB accesses -system.cpu0.itb.fetch_hits 2717036 # ITB hits -system.cpu0.itb.fetch_misses 3019 # ITB misses +system.cpu0.dtb.data_accesses 592200 # DTB accesses +system.cpu0.itb.fetch_hits 2715643 # ITB hits +system.cpu0.itb.fetch_misses 3015 # ITB misses system.cpu0.itb.fetch_acv 97 # ITB acv -system.cpu0.itb.fetch_accesses 2720055 # ITB accesses +system.cpu0.itb.fetch_accesses 2718658 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -364,67 +361,67 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 930055234 # number of cpu cycles simulated +system.cpu0.numCycles 928469977 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31475732 # Number of instructions committed -system.cpu0.committedOps 31475732 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 29412106 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 162586 # Number of float alu accesses -system.cpu0.num_func_calls 792411 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4104277 # number of instructions that are conditional controls -system.cpu0.num_int_insts 29412106 # number of integer instructions -system.cpu0.num_fp_insts 162586 # number of float instructions -system.cpu0.num_int_register_reads 40967178 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21562005 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 84110 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 85570 # number of times the floating registers were written -system.cpu0.num_mem_refs 8192042 # number of memory refs -system.cpu0.num_load_insts 4796241 # Number of load instructions -system.cpu0.num_store_insts 3395801 # Number of store instructions -system.cpu0.num_idle_cycles 907058327.289346 # Number of idle cycles -system.cpu0.num_busy_cycles 22996906.710654 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024726 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975274 # Percentage of idle cycles -system.cpu0.Branches 5151040 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1559860 4.95% 4.95% # Class of executed instruction -system.cpu0.op_class::IntAlu 21040910 66.83% 71.79% # Class of executed instruction -system.cpu0.op_class::IntMult 31347 0.10% 71.89% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.89% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12827 0.04% 71.93% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1598 0.01% 71.93% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.93% # Class of executed instruction -system.cpu0.op_class::MemRead 4926196 15.65% 87.58% # Class of executed instruction -system.cpu0.op_class::MemWrite 3398883 10.80% 98.38% # Class of executed instruction -system.cpu0.op_class::IprAccess 510933 1.62% 100.00% # Class of executed instruction +system.cpu0.committedInsts 30414467 # Number of instructions committed +system.cpu0.committedOps 30414467 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 28351523 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 162419 # Number of float alu accesses +system.cpu0.num_func_calls 792250 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3751370 # number of instructions that are conditional controls +system.cpu0.num_int_insts 28351523 # number of integer instructions +system.cpu0.num_fp_insts 162419 # number of float instructions +system.cpu0.num_int_register_reads 39201854 # number of times the integer registers were read +system.cpu0.num_int_register_writes 20853832 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 84043 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 85470 # number of times the floating registers were written +system.cpu0.num_mem_refs 8191763 # number of memory refs +system.cpu0.num_load_insts 4794790 # Number of load instructions +system.cpu0.num_store_insts 3396973 # Number of store instructions +system.cpu0.num_idle_cycles 905786099.867998 # Number of idle cycles +system.cpu0.num_busy_cycles 22683877.132002 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024431 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975569 # Percentage of idle cycles +system.cpu0.Branches 4797930 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1559380 5.13% 5.13% # Class of executed instruction +system.cpu0.op_class::IntAlu 19980835 65.68% 70.81% # Class of executed instruction +system.cpu0.op_class::IntMult 31353 0.10% 70.91% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 70.91% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12822 0.04% 70.95% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 70.95% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 70.95% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 70.95% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1598 0.01% 70.96% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.96% # Class of executed instruction +system.cpu0.op_class::MemRead 4924664 16.19% 87.15% # Class of executed instruction +system.cpu0.op_class::MemWrite 3400050 11.18% 98.32% # Class of executed instruction +system.cpu0.op_class::IprAccess 510577 1.68% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 31482554 # Class of executed instruction +system.cpu0.op_class::total 30421279 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6422 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211358 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211362 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl @@ -435,11 +432,11 @@ system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # nu system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818800243000 98.76% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38808500 0.00% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 357216000 0.02% 98.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22351032000 1.21% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841547299500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1818807757000 98.77% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38797500 0.00% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 357175000 0.02% 98.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22331016000 1.21% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841534745500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -503,429 +500,429 @@ system.cpu0.kern.mode_switch_good::kernel 0.321851 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.390894 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29750547000 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2575384000 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809221366500 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 29743380000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2567925500 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809223438000 98.25% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1393348 # number of replacements +system.cpu0.dcache.tags.replacements 1392924 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13255372 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393860 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.509830 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 13249026 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393436 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.508170 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 177.816582 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 164.221248 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 169.959986 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.347298 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.320745 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.331953 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 177.335991 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 163.453449 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 171.208376 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.346359 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.319245 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.334391 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63362265 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63362265 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 3956098 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1080024 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2536463 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7572585 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3101293 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 830391 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1367001 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5298685 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113681 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19703 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51298 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184682 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122268 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21809 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55240 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199317 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7057391 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1910415 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3903464 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12871270 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7057391 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1910415 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3903464 # number of overall hits -system.cpu0.dcache.overall_hits::total 12871270 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 706776 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 97332 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 562527 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1366635 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 162364 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 44132 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 644654 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 851150 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9134 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2235 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7668 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19037 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 10 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 869140 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 141464 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1207181 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2217785 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 869140 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 141464 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1207181 # number of overall misses -system.cpu0.dcache.overall_misses::total 2217785 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2268250000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8231829500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 10500079500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1752940000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19634310548 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 21387250548 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 29559000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 124972000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 154531000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 170500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 170500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4021190000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 27866140048 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 31887330048 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4021190000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 27866140048 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 31887330048 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4662874 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1177356 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3098990 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8939220 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3263657 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 874523 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2011655 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6149835 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 122815 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21938 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58966 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203719 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 122268 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21809 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55250 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.tags.tag_accesses 63330121 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63330121 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 3955641 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1077876 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2532941 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7566458 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3102475 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 828519 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1367883 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5298877 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113517 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19685 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51083 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184285 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122198 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21798 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55320 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199316 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7058116 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1906395 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3900824 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12865335 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7058116 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1906395 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3900824 # number of overall hits +system.cpu0.dcache.overall_hits::total 12865335 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 705857 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 97562 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 561486 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1364905 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 162429 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 43967 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 644644 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 851040 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9228 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2243 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7808 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19279 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 11 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 868286 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 141529 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1206130 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2215945 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 868286 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 141529 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1206130 # number of overall misses +system.cpu0.dcache.overall_misses::total 2215945 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2272668500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8215053500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 10487722000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1750811500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19626601777 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 21377413277 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 29663000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 127096500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 156759500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 184000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 184000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 4023480000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 27841655277 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 31865135277 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 4023480000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 27841655277 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 31865135277 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4661498 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1175438 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 3094427 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8931363 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3264904 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 872486 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2012527 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6149917 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 122745 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21928 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58891 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203564 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 122198 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21798 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55331 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 199327 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 7926531 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2051879 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5110645 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15089055 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 7926531 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2051879 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5110645 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15089055 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151575 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082670 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181519 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.152881 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049749 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050464 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.320460 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.138402 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.074372 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.101878 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.093447 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000181 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000050 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109649 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.068944 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.236209 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.146980 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109649 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.068944 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.236209 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.146980 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23304.257593 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14633.661140 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 7683.163025 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39720.384302 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30457.129791 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25127.475237 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13225.503356 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16297.861242 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8117.402952 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 17050 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 17050 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28425.535825 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23083.646983 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14378.007809 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28425.535825 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 23083.646983 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14378.007809 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1019885 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1764 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 60259 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 7926402 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 2047924 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 5106954 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15081280 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 7926402 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 2047924 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 5106954 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15081280 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151423 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083001 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181451 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.152822 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049750 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050393 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.320316 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.138382 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075180 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.102289 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.132584 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094707 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000199 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000055 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109544 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069109 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.236174 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.146933 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109544 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069109 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.236174 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.146933 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23294.607532 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14630.914217 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 7683.847594 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39821.036232 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30445.644072 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 25119.163937 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13224.699064 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16277.727971 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8131.101198 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16727.272727 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16727.272727 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28428.661264 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23083.461382 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14379.930584 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28428.661264 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 23083.461382 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14379.930584 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1023083 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1722 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 60080 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 18 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.925024 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 98 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.028678 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 95.666667 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835740 # number of writebacks -system.cpu0.dcache.writebacks::total 835740 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 292598 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 292598 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 548626 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 548626 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1690 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1690 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 841224 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 841224 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 841224 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 841224 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 97332 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 269929 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 367261 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 44132 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 96028 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 140160 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2235 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5978 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8213 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 10 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 141464 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 365957 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 507421 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 141464 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 365957 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 507421 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1108 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1559 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2667 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1387 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.writebacks::writebacks 835650 # number of writebacks +system.cpu0.dcache.writebacks::total 835650 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 291568 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 291568 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 548541 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 548541 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1641 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1641 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 840109 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 840109 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 840109 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 840109 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 97562 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 269918 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 367480 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43967 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 96103 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 140070 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2243 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6167 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8410 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 11 # 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number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2128 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3515 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2495 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3687 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6182 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170918000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4426676000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6597594000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1708808000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3106661815 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4815469815 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 27324000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 74701500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102025500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 160500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 160500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3879726000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7533337815 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11413063815 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3879726000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7533337815 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11413063815 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 226454500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 334463500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 560918000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298425500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 450956500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 749382000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 524880000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 785420000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1310300000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082670 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087102 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041084 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050464 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047736 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022791 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101878 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.101380 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040315 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000181 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.068944 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071607 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033628 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.068944 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071607 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033628 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22304.257593 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16399.408733 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17964.319653 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38720.384302 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32351.624682 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34356.947881 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12225.503356 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12496.068919 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12422.440034 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 16050 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16050 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27425.535825 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20585.308697 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22492.296959 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27425.535825 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20585.308697 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22492.296959 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 204381.317690 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 214537.203335 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210317.960255 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 215158.976208 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211915.648496 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 213195.448080 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 210372.745491 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 213024.138866 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 211954.060175 # average overall mshr uncacheable latency +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3514 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2493 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3686 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6179 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2175106500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4426228500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6601335000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1706844500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3108596312 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4815440812 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 27420000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 77097500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104517500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 173000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 173000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3881951000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7534824812 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11416775812 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3881951000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7534824812 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11416775812 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 226227500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 334192500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 560420000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298200000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 450969000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 749169000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 524427500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 785161500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1309589000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083001 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087227 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041145 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050393 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047752 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022776 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.102289 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.104719 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.041314 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000199 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000055 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069109 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071671 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033654 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069109 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071671 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033654 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22294.607532 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16398.419150 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17963.793948 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38821.036232 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32346.506477 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34378.816392 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12224.699064 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12501.621534 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12427.764566 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 15727.272727 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15727.272727 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27428.661264 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20585.771887 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22493.893827 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27428.661264 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20585.771887 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22493.893827 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 204360.885276 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 214500.962773 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210288.930582 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 215151.515152 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211921.522556 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 213195.503699 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 210360.008022 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 213011.801411 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 211941.899984 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 965393 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.914113 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 41264625 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 965904 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 42.721249 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10188445500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 146.904249 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 135.394605 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 228.615259 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.286922 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.264443 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.446514 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997879 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 963177 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.919668 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 40183368 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 963688 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 41.697487 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10187899500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 148.948748 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 136.141622 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 225.829298 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.290916 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.265902 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.441073 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997890 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43213951 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43213951 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 30975792 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7803098 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2485735 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 41264625 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30975792 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7803098 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2485735 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 41264625 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 30975792 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7803098 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2485735 # number of overall hits -system.cpu0.icache.overall_hits::total 41264625 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 506762 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 129019 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 347436 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 983217 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 506762 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 129019 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 347436 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 983217 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 506762 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 129019 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 347436 # number of overall misses -system.cpu0.icache.overall_misses::total 983217 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1839982500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4838575988 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6678558488 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1839982500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4838575988 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6678558488 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1839982500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4838575988 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6678558488 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 31482554 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7932117 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2833171 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 42247842 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 31482554 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7932117 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2833171 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 42247842 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 31482554 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7932117 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2833171 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 42247842 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016097 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016265 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122631 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.023273 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016097 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016265 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122631 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023273 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016097 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016265 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122631 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023273 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14261.329727 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13926.524563 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6792.557989 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14261.329727 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13926.524563 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6792.557989 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14261.329727 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13926.524563 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6792.557989 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3935 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 42127818 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 42127818 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29914547 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7792823 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2475998 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 40183368 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29914547 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7792823 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2475998 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 40183368 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29914547 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7792823 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2475998 # number of overall hits +system.cpu0.icache.overall_hits::total 40183368 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 506732 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 128884 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 344958 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 980574 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 506732 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 128884 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 344958 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 980574 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 506732 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 128884 # 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number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 459347 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1710963500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4315526491 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6026489991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1710963500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4315526491 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6026489991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1710963500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4315526491 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6026489991 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016265 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116593 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010873 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016265 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116593 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010873 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016265 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116593 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010873 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13261.329727 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13064.367813 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13119.689453 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13261.329727 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13064.367813 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13119.689453 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13261.329727 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13064.367813 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13119.689453 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16698 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16698 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16698 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16698 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16698 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16698 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 128884 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 328260 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 457144 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 128884 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 328260 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 457144 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 128884 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 328260 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 457144 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1711275000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4293223488 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6004498488 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1711275000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4293223488 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6004498488 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1711275000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4293223488 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6004498488 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016270 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116365 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011105 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016270 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116365 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011105 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016270 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116365 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011105 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13277.637255 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13078.728715 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13134.807605 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13277.637255 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13078.728715 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13134.807605 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13277.637255 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13078.728715 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13134.807605 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1196955 # DTB read hits +system.cpu1.dtb.read_hits 1195033 # DTB read hits system.cpu1.dtb.read_misses 1325 # DTB read misses system.cpu1.dtb.read_acv 35 # DTB read access violations system.cpu1.dtb.read_accesses 141268 # DTB read accesses -system.cpu1.dtb.write_hits 896481 # DTB write hits +system.cpu1.dtb.write_hits 894434 # DTB write hits system.cpu1.dtb.write_misses 169 # DTB write misses system.cpu1.dtb.write_acv 22 # DTB write access violations -system.cpu1.dtb.write_accesses 57742 # DTB write accesses -system.cpu1.dtb.data_hits 2093436 # DTB hits +system.cpu1.dtb.write_accesses 56923 # DTB write accesses +system.cpu1.dtb.data_hits 2089467 # DTB hits system.cpu1.dtb.data_misses 1494 # DTB misses system.cpu1.dtb.data_acv 57 # DTB access violations -system.cpu1.dtb.data_accesses 199010 # DTB accesses -system.cpu1.itb.fetch_hits 858438 # ITB hits +system.cpu1.dtb.data_accesses 198191 # DTB accesses +system.cpu1.itb.fetch_hits 856224 # ITB hits system.cpu1.itb.fetch_misses 659 # ITB misses system.cpu1.itb.fetch_acv 35 # ITB acv -system.cpu1.itb.fetch_accesses 859097 # ITB accesses +system.cpu1.itb.fetch_accesses 856883 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -938,64 +935,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953273349 # number of cpu cycles simulated +system.cpu1.numCycles 953248779 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7930565 # Number of instructions committed -system.cpu1.committedOps 7930565 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7389333 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45920 # Number of float alu accesses -system.cpu1.num_func_calls 207460 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1022605 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7389333 # number of integer instructions -system.cpu1.num_fp_insts 45920 # number of float instructions -system.cpu1.num_int_register_reads 10362144 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5369975 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24736 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 25085 # number of times the floating registers were written -system.cpu1.num_mem_refs 2100568 # number of memory refs -system.cpu1.num_load_insts 1201762 # Number of load instructions -system.cpu1.num_store_insts 898806 # Number of store instructions -system.cpu1.num_idle_cycles 922154358.750069 # Number of idle cycles -system.cpu1.num_busy_cycles 31118990.249931 # Number of busy cycles -system.cpu1.not_idle_fraction 0.032644 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.967356 # Percentage of idle cycles -system.cpu1.Branches 1296677 # Number of branches fetched -system.cpu1.op_class::No_OpClass 410840 5.18% 5.18% # Class of executed instruction -system.cpu1.op_class::IntAlu 5240708 66.07% 71.25% # Class of executed instruction -system.cpu1.op_class::IntMult 8731 0.11% 71.36% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 71.36% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5176 0.07% 71.42% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 71.42% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 71.42% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 71.42% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 71.43% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.43% # Class of executed instruction -system.cpu1.op_class::MemRead 1230901 15.52% 86.95% # Class of executed instruction -system.cpu1.op_class::MemWrite 900034 11.35% 98.30% # Class of executed instruction -system.cpu1.op_class::IprAccess 134916 1.70% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7920155 # Number of instructions committed +system.cpu1.committedOps 7920155 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7379126 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45865 # Number of float alu accesses +system.cpu1.num_func_calls 207333 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1021718 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7379126 # number of integer instructions +system.cpu1.num_fp_insts 45865 # number of float instructions +system.cpu1.num_int_register_reads 10346831 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5362502 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24725 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 25053 # number of times the floating registers were written +system.cpu1.num_mem_refs 2096589 # number of memory refs +system.cpu1.num_load_insts 1199833 # Number of load instructions +system.cpu1.num_store_insts 896756 # Number of store instructions +system.cpu1.num_idle_cycles 922000099.418594 # Number of idle cycles +system.cpu1.num_busy_cycles 31248679.581406 # Number of busy cycles +system.cpu1.not_idle_fraction 0.032781 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.967219 # Percentage of idle cycles +system.cpu1.Branches 1295631 # Number of branches fetched +system.cpu1.op_class::No_OpClass 410705 5.18% 5.18% # Class of executed instruction +system.cpu1.op_class::IntAlu 5234650 66.08% 71.26% # Class of executed instruction +system.cpu1.op_class::IntMult 8605 0.11% 71.37% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 71.37% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5163 0.07% 71.44% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 71.44% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 71.44% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 71.44% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::MemRead 1228944 15.51% 86.96% # Class of executed instruction +system.cpu1.op_class::MemWrite 897985 11.34% 98.30% # Class of executed instruction +system.cpu1.op_class::IprAccess 134844 1.70% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7932116 # Class of executed instruction +system.cpu1.op_class::total 7921706 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1013,35 +1010,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 10402334 # Number of BP lookups -system.cpu2.branchPred.condPredicted 9657881 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 126933 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 8330137 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6272162 # Number of BTB hits +system.cpu2.branchPred.lookups 11475270 # Number of BP lookups +system.cpu2.branchPred.condPredicted 10735483 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 123474 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 9110272 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 7311084 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 75.294824 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 302639 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7723 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.250996 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 301261 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7742 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3549115 # DTB read hits -system.cpu2.dtb.read_misses 12776 # DTB read misses -system.cpu2.dtb.read_acv 157 # DTB read access violations -system.cpu2.dtb.read_accesses 225358 # DTB read accesses -system.cpu2.dtb.write_hits 2157791 # DTB write hits -system.cpu2.dtb.write_misses 2831 # DTB write misses -system.cpu2.dtb.write_acv 142 # DTB write access violations -system.cpu2.dtb.write_accesses 84650 # DTB write accesses -system.cpu2.dtb.data_hits 5706906 # DTB hits -system.cpu2.dtb.data_misses 15607 # DTB misses -system.cpu2.dtb.data_acv 299 # DTB access violations -system.cpu2.dtb.data_accesses 310008 # DTB accesses -system.cpu2.itb.fetch_hits 538598 # ITB hits -system.cpu2.itb.fetch_misses 5991 # ITB misses -system.cpu2.itb.fetch_acv 159 # ITB acv -system.cpu2.itb.fetch_accesses 544589 # ITB accesses +system.cpu2.dtb.read_hits 3542926 # DTB read hits +system.cpu2.dtb.read_misses 12527 # DTB read misses +system.cpu2.dtb.read_acv 162 # DTB read access violations +system.cpu2.dtb.read_accesses 225242 # DTB read accesses +system.cpu2.dtb.write_hits 2156991 # DTB write hits +system.cpu2.dtb.write_misses 2860 # DTB write misses +system.cpu2.dtb.write_acv 147 # DTB write access violations +system.cpu2.dtb.write_accesses 84372 # DTB write accesses +system.cpu2.dtb.data_hits 5699917 # DTB hits +system.cpu2.dtb.data_misses 15387 # DTB misses +system.cpu2.dtb.data_acv 309 # DTB access violations +system.cpu2.dtb.data_accesses 309614 # DTB accesses +system.cpu2.itb.fetch_hits 534150 # ITB hits +system.cpu2.itb.fetch_misses 5562 # ITB misses +system.cpu2.itb.fetch_acv 158 # ITB acv +system.cpu2.itb.fetch_accesses 539712 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1054,304 +1051,304 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30759536 # number of cpu cycles simulated +system.cpu2.numCycles 31796057 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9338114 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 39735788 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 10402334 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6574801 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 19282744 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 413720 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 277 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 9678 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1944 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 234903 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 108900 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 473 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2833173 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 93993 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 29183655 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.361577 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.367035 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9294739 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 42846452 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 11475270 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 7612345 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 20400927 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 406592 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 934 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9632 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1958 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 201207 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 109893 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 558 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2820959 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 91095 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 30222906 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.417681 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.345063 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20063773 68.75% 68.75% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 307542 1.05% 69.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 477296 1.64% 71.44% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4654234 15.95% 87.39% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 859104 2.94% 90.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 198525 0.68% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 235442 0.81% 91.82% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 432653 1.48% 93.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1955086 6.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 20065674 66.39% 66.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 304778 1.01% 67.40% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 474119 1.57% 68.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 5709833 18.89% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 849889 2.81% 90.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 195244 0.65% 91.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 232616 0.77% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433559 1.43% 93.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1957194 6.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 29183655 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.338182 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.291820 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7672062 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 13049396 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7739525 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 528158 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 193789 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 177139 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13443 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36353966 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 42512 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 193789 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7950274 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4574250 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6325048 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7961138 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2178432 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35523870 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 60190 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 394243 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 57916 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1115509 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 23763436 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 44289897 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 44229633 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56339 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 21842362 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1921074 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 535035 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63809 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3839801 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3528507 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2250963 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 468940 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 330687 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32977065 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 683079 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32678030 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 15337 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2566331 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1147551 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 488786 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 29183655 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.119737 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.624192 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 30222906 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.360902 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.347540 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7641311 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 13078900 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8781400 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 530431 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 190274 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 176731 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13389 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 39469462 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 42545 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 190274 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7916618 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4614900 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6334560 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 9009266 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2156706 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 38654408 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 61763 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 395728 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 57668 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1091797 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 25842385 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 48471958 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 48411597 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56430 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 23967156 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1875229 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 535043 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63361 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3828496 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3518120 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2250866 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 468779 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 334709 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 36116015 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 683906 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 35834403 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 15167 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2521371 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1120007 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 489344 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 30222906 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.185670 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.632890 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17436459 59.75% 59.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2753806 9.44% 69.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1377159 4.72% 73.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5375832 18.42% 92.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1030141 3.53% 95.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 601956 2.06% 97.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 392573 1.35% 99.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 169204 0.58% 99.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 46525 0.16% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17428882 57.67% 57.67% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2748935 9.10% 66.76% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1369590 4.53% 71.29% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 6435558 21.29% 92.59% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1033977 3.42% 96.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 595062 1.97% 97.98% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 394555 1.31% 99.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 169710 0.56% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 46637 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 29183655 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 30222906 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 85386 21.51% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 184726 46.54% 68.05% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 126802 31.95% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 86081 21.74% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 183352 46.31% 68.05% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 126504 31.95% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 26465043 80.99% 80.99% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21101 0.06% 81.06% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.06% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20515 0.06% 81.12% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.12% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.12% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.12% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.13% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3679518 11.26% 92.39% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2182790 6.68% 99.07% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 305379 0.93% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 29630335 82.69% 82.69% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21208 0.06% 82.75% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.75% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20533 0.06% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.81% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3671135 10.24% 93.06% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2181666 6.09% 99.15% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 305842 0.85% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32678030 # Type of FU issued -system.cpu2.iq.rate 1.062371 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 396914 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.012146 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 94697637 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 36112111 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 32047154 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 254329 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 120282 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 117366 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32936079 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 136409 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206083 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 35834403 # Type of FU issued +system.cpu2.iq.rate 1.127008 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 395937 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.011049 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 102047941 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39206340 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 35210799 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 254875 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 120668 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 117568 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36091226 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 136658 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206130 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 440040 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1257 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6058 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 180485 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 426126 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1149 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5847 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 179431 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5073 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 225988 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5057 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 224722 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 193789 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3993186 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 173385 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 35054322 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 55127 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3528507 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2250963 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 608084 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 13021 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 119091 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6058 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 64339 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 136180 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 200519 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 32475558 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3570784 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 202472 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 190274 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4003128 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 196899 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 38192826 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 53825 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3518120 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2250866 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 608609 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 12914 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 142416 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5847 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 60692 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 135198 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 195890 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 35634663 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3564372 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 199740 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1394178 # number of nop insts executed -system.cpu2.iew.exec_refs 5736169 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7344406 # Number of branches executed -system.cpu2.iew.exec_stores 2165385 # Number of stores executed -system.cpu2.iew.exec_rate 1.055788 # Inst execution rate -system.cpu2.iew.wb_sent 32207740 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 32164520 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18733989 # num instructions producing a value -system.cpu2.iew.wb_consumers 22461298 # num instructions consuming a value +system.cpu2.iew.exec_nop 1392905 # number of nop insts executed +system.cpu2.iew.exec_refs 5729004 # number of memory reference insts executed +system.cpu2.iew.exec_branches 8402054 # Number of branches executed +system.cpu2.iew.exec_stores 2164632 # Number of stores executed +system.cpu2.iew.exec_rate 1.120726 # Inst execution rate +system.cpu2.iew.wb_sent 35371199 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 35328367 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 20848782 # num instructions producing a value +system.cpu2.iew.wb_consumers 24577214 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.045676 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.834056 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.111093 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.848297 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2690484 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 194293 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 182480 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 28713100 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.125605 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.869287 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2641573 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 194562 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 179155 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 29759977 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.193046 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.869762 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18196306 63.37% 63.37% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2254505 7.85% 71.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1188955 4.14% 75.37% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5110402 17.80% 93.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 563606 1.96% 95.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 199238 0.69% 95.82% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 165515 0.58% 96.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 164290 0.57% 96.97% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 870283 3.03% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18187552 61.11% 61.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2254342 7.58% 68.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1186941 3.99% 72.68% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6165862 20.72% 93.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 562678 1.89% 95.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 198394 0.67% 95.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 165216 0.56% 96.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 166703 0.56% 97.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 872289 2.93% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 28713100 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32319619 # Number of instructions committed -system.cpu2.commit.committedOps 32319619 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 29759977 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 35505021 # Number of instructions committed +system.cpu2.commit.committedOps 35505021 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5158945 # Number of memory references committed -system.cpu2.commit.loads 3088467 # Number of loads committed -system.cpu2.commit.membars 68233 # Number of memory barriers committed -system.cpu2.commit.branches 7171529 # Number of branches committed -system.cpu2.commit.fp_insts 115750 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 30796114 # Number of committed integer instructions. -system.cpu2.commit.function_calls 241665 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1228262 3.80% 3.80% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 25515212 78.95% 82.75% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20642 0.06% 82.81% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 82.81% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20078 0.06% 82.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 82.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 82.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 82.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1228 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 82.88% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3156700 9.77% 92.64% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2072118 6.41% 99.06% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 305379 0.94% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5163429 # Number of memory references committed +system.cpu2.commit.loads 3091994 # Number of loads committed +system.cpu2.commit.membars 68344 # Number of memory barriers committed +system.cpu2.commit.branches 8230032 # Number of branches committed +system.cpu2.commit.fp_insts 115972 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 33980571 # Number of committed integer instructions. +system.cpu2.commit.function_calls 241816 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1228927 3.46% 3.46% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 28694755 80.82% 84.28% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20756 0.06% 84.34% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 84.34% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20096 0.06% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1228 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 84.40% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3160338 8.90% 93.30% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2073079 5.84% 99.14% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 305842 0.86% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 32319619 # Class of committed instruction -system.cpu2.commit.bw_lim_events 870283 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 62775514 # The number of ROB reads -system.cpu2.rob.rob_writes 70489103 # The number of ROB writes -system.cpu2.timesIdled 177769 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1575881 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745050657 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 31093813 # Number of Instructions Simulated -system.cpu2.committedOps 31093813 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.989249 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.989249 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.010867 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.010867 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42649325 # number of integer regfile reads -system.cpu2.int_regfile_writes 22654905 # number of integer regfile writes -system.cpu2.fp_regfile_reads 71051 # number of floating regfile reads -system.cpu2.fp_regfile_writes 71293 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5005090 # number of misc regfile reads -system.cpu2.misc_regfile_writes 273836 # number of misc regfile writes +system.cpu2.commit.op_class_0::total 35505021 # Class of committed instruction +system.cpu2.commit.bw_lim_events 872289 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 66956679 # The number of ROB reads +system.cpu2.rob.rob_writes 76754434 # The number of ROB writes +system.cpu2.timesIdled 177058 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1573151 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1744013124 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 34278550 # Number of Instructions Simulated +system.cpu2.committedOps 34278550 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.927579 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.927579 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.078075 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.078075 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 46864030 # number of integer regfile reads +system.cpu2.int_regfile_writes 24760821 # number of integer regfile writes +system.cpu2.fp_regfile_reads 71108 # number of floating regfile reads +system.cpu2.fp_regfile_writes 71427 # number of floating regfile writes +system.cpu2.misc_regfile_reads 6062934 # number of misc regfile reads +system.cpu2.misc_regfile_writes 274246 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1406,7 +1403,7 @@ system.iobus.reqLayer1.occupancy 105000 # La system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5370000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5366000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 1863000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) @@ -1416,21 +1413,21 @@ system.iobus.reqLayer27.occupancy 7000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 89820170 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 89821669 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 8849000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 8844000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 17468000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254241 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254132 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693892852000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254241 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078390 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078390 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1693892766000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254132 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078383 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078383 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1446,8 +1443,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 9418962 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 9418962 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 2040792208 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2040792208 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 2040972707 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2040972707 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 9418962 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 9418962 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 9418962 # number of overall miss cycles @@ -1470,8 +1467,8 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54444.867052 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 54444.867052 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 49114.175202 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 49114.175202 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 49118.519133 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 49118.519133 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 54444.867052 # average overall miss latency system.iocache.demand_avg_miss_latency::total 54444.867052 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 54444.867052 # average overall miss latency @@ -1496,8 +1493,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 70 system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5918962 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 5918962 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1176792208 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1176792208 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1176972707 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1176972707 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 5918962 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 5918962 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 5918962 # number of overall MSHR miss cycles @@ -1512,219 +1509,219 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 84556.600000 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68101.400926 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68101.400926 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68111.846470 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68111.846470 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 84556.600000 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 84556.600000 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 337481 # number of replacements -system.l2c.tags.tagsinuse 65419.198683 # Cycle average of tags in use -system.l2c.tags.total_refs 4010491 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402643 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.960414 # Average number of references to valid blocks. +system.l2c.tags.replacements 337470 # number of replacements +system.l2c.tags.tagsinuse 65419.393999 # Cycle average of tags in use +system.l2c.tags.total_refs 4005329 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402632 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.947866 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54563.896309 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2274.571035 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2764.017947 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 537.574504 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 599.716909 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2426.240023 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2253.181956 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.832579 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.034707 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042176 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008203 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009151 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.037021 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.034381 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998218 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54633.992785 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2282.515139 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2705.284872 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 536.585010 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 602.481810 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2408.251048 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2250.283336 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.833649 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.034828 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041279 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008188 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009193 # 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number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 165398000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 349071000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 514469000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 1012748000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1095055000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 2107803000 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 165398000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2200978000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 349071000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 3042928500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5758375500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 165398000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2200978000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 349071000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 3042928500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5758375500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 212390000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 314717500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 527107500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 282261000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 426497000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 708758000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 494651000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 741214500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1235865500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.709677 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.511628 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.200000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.407287 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.255964 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.140765 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017819 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014546 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.007353 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.158376 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.061563 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.030004 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017819 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.234819 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014546 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.111891 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.034942 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017819 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.234819 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014546 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.111891 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034942 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 27590.909091 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 27590.909091 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 20750 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20750 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66107.210415 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 78998.458105 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 73561.744762 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71104.175729 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72187.031640 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71836.547937 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 64133.584882 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 64582.773456 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 64366.404985 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71104.175729 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65184.882791 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72187.031640 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73120.359022 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 69762.500152 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71104.175729 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65184.882791 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72187.031640 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73120.359022 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 69762.500152 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191881.317690 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 202037.203335 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197817.960255 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203658.976208 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200415.648496 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201695.448080 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 198428.657315 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 201101.301871 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 200022.646393 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.523810 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408930 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.255830 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.140797 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017822 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014554 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.007340 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.157938 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.061492 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.030003 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017822 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.234693 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014554 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.111785 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034964 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017822 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.234693 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014554 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.111785 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034964 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 34272.727273 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 34272.727273 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 21000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 21000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66089.882641 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 79053.307630 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 73584.633614 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72006.094906 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73073.267741 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72726.745830 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 64248.429867 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 64555.503154 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 64407.596407 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72006.094906 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65229.624800 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73073.267741 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73142.045045 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 69867.087686 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72006.094906 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65229.624800 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73073.267741 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73142.045045 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69867.087686 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191860.885276 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 202000.962773 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197788.930582 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203651.515152 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200421.522556 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201695.503699 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 198415.964701 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 201089.120998 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 200010.600421 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7144 # Transaction distribution -system.membus.trans_dist::ReadResp 294958 # Transaction distribution +system.membus.trans_dist::ReadResp 294907 # Transaction distribution system.membus.trans_dist::WriteReq 9810 # Transaction distribution system.membus.trans_dist::WriteResp 9810 # Transaction distribution -system.membus.trans_dist::Writeback 116948 # Transaction distribution -system.membus.trans_dist::CleanEvict 262295 # Transaction distribution -system.membus.trans_dist::UpgradeReq 165 # Transaction distribution +system.membus.trans_dist::Writeback 116913 # Transaction distribution +system.membus.trans_dist::CleanEvict 262319 # Transaction distribution +system.membus.trans_dist::UpgradeReq 141 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 167 # Transaction distribution -system.membus.trans_dist::ReadExReq 115610 # Transaction distribution -system.membus.trans_dist::ReadExResp 115610 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 287819 # Transaction distribution -system.membus.trans_dist::BadAddressError 5 # Transaction distribution +system.membus.trans_dist::UpgradeResp 143 # Transaction distribution +system.membus.trans_dist::ReadExReq 115651 # Transaction distribution +system.membus.trans_dist::ReadExResp 115651 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 287769 # Transaction distribution +system.membus.trans_dist::BadAddressError 6 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1144349 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1178267 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1144270 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1178190 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125023 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 125023 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1303290 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1303213 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30629632 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30675200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30626752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30672320 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33339520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33336640 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 157 # Total snoops (count) -system.membus.snoop_fanout::samples 841413 # Request fanout histogram +system.membus.snoop_fanout::samples 841369 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 841413 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 841369 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 841413 # Request fanout histogram -system.membus.reqLayer0.occupancy 11052000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 841369 # Request fanout histogram +system.membus.reqLayer0.occupancy 11017000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 394258327 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 393892331 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 7000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 441332932 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 441141955 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 29902743 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2064402 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2061814 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 883212 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1574760 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 43 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 53 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302767 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302767 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 966109 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1091169 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 5 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 883059 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1572257 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 33 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 44 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302698 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302698 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 963876 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1090815 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 17280 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2897413 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4214892 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7112305 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61827200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142743552 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 204570752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 141567 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4877075 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.028983 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.167759 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2890767 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4213603 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7104370 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61685760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142710656 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 204396416 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 141516 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4871742 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.029009 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.167832 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 4735723 97.10% 97.10% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 141352 2.90% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4730418 97.10% 97.10% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 141324 2.90% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4877075 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1372572500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4871742 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1371248000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 82500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 689392754 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 686121188 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 777864461 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 778360963 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |