diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/long/fs/10.linux-boot/ref/alpha | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
4 files changed, 5410 insertions, 5359 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 2bd7abaa8..b894ed506 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.887179 # Number of seconds simulated -sim_ticks 1887179292000 # Number of ticks simulated -final_tick 1887179292000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.886196 # Number of seconds simulated +sim_ticks 1886195993000 # Number of ticks simulated +final_tick 1886195993000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 271909 # Simulator instruction rate (inst/s) -host_op_rate 271909 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9140545464 # Simulator tick rate (ticks/s) -host_mem_usage 373988 # Number of bytes of host memory used -host_seconds 206.46 # Real time elapsed on the host -sim_insts 56138893 # Number of instructions simulated -sim_ops 56138893 # Number of ops (including micro ops) simulated +host_inst_rate 256659 # Simulator instruction rate (inst/s) +host_op_rate 256659 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8626071053 # Simulator tick rate (ticks/s) +host_mem_usage 374008 # Number of bytes of host memory used +host_seconds 218.66 # Real time elapsed on the host +sim_insts 56121694 # Number of instructions simulated +sim_ops 56121694 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1052544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1049728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24850240 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25912448 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1052544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1052544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7556224 # Number of bytes written to this memory -system.physmem.bytes_written::total 7556224 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16446 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388421 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25900928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1049728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1049728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7553600 # Number of bytes written to this memory +system.physmem.bytes_written::total 7553600 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16402 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388285 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404882 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118066 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118066 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 557734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13172540 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404702 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118025 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118025 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 556532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13174792 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13730782 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 557734 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557734 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4003978 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4003978 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4003978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 557734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13172540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13731833 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 556532 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 556532 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4004674 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4004674 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4004674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 556532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13174792 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17734760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404882 # Number of read requests accepted -system.physmem.writeReqs 159618 # Number of write requests accepted -system.physmem.readBursts 404882 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159618 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25905920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue -system.physmem.bytesWritten 8528320 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25912448 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10215552 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 26335 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write +system.physmem.bw_total::total 17736507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404702 # Number of read requests accepted +system.physmem.writeReqs 118025 # Number of write requests accepted +system.physmem.readBursts 404702 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118025 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25894272 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue +system.physmem.bytesWritten 7551808 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25900928 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7553600 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 41706 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25487 # Per bank write bursts -system.physmem.perBankRdBursts::1 25681 # Per bank write bursts -system.physmem.perBankRdBursts::2 25706 # Per bank write bursts -system.physmem.perBankRdBursts::3 25753 # Per bank write bursts -system.physmem.perBankRdBursts::4 25164 # Per bank write bursts -system.physmem.perBankRdBursts::5 25107 # Per bank write bursts -system.physmem.perBankRdBursts::6 24789 # Per bank write bursts -system.physmem.perBankRdBursts::7 24544 # Per bank write bursts -system.physmem.perBankRdBursts::8 25200 # Per bank write bursts -system.physmem.perBankRdBursts::9 25299 # Per bank write bursts -system.physmem.perBankRdBursts::10 25393 # Per bank write bursts -system.physmem.perBankRdBursts::11 24991 # Per bank write bursts -system.physmem.perBankRdBursts::12 24525 # Per bank write bursts -system.physmem.perBankRdBursts::13 25570 # Per bank write bursts -system.physmem.perBankRdBursts::14 25834 # Per bank write bursts +system.physmem.perBankRdBursts::1 25728 # Per bank write bursts +system.physmem.perBankRdBursts::2 25822 # Per bank write bursts +system.physmem.perBankRdBursts::3 25769 # Per bank write bursts +system.physmem.perBankRdBursts::4 25085 # Per bank write bursts +system.physmem.perBankRdBursts::5 25016 # Per bank write bursts +system.physmem.perBankRdBursts::6 24650 # Per bank write bursts +system.physmem.perBankRdBursts::7 24524 # Per bank write bursts +system.physmem.perBankRdBursts::8 25293 # Per bank write bursts +system.physmem.perBankRdBursts::9 25190 # Per bank write bursts +system.physmem.perBankRdBursts::10 25398 # Per bank write bursts +system.physmem.perBankRdBursts::11 24986 # Per bank write bursts +system.physmem.perBankRdBursts::12 24522 # Per bank write bursts +system.physmem.perBankRdBursts::13 25563 # Per bank write bursts +system.physmem.perBankRdBursts::14 25828 # Per bank write bursts system.physmem.perBankRdBursts::15 25737 # Per bank write bursts -system.physmem.perBankWrBursts::0 8901 # Per bank write bursts -system.physmem.perBankWrBursts::1 8465 # Per bank write bursts -system.physmem.perBankWrBursts::2 9022 # Per bank write bursts -system.physmem.perBankWrBursts::3 8725 # Per bank write bursts -system.physmem.perBankWrBursts::4 8062 # Per bank write bursts -system.physmem.perBankWrBursts::5 8096 # Per bank write bursts -system.physmem.perBankWrBursts::6 7614 # Per bank write bursts -system.physmem.perBankWrBursts::7 7482 # Per bank write bursts -system.physmem.perBankWrBursts::8 8269 # Per bank write bursts -system.physmem.perBankWrBursts::9 7671 # Per bank write bursts -system.physmem.perBankWrBursts::10 8104 # Per bank write bursts -system.physmem.perBankWrBursts::11 7830 # Per bank write bursts -system.physmem.perBankWrBursts::12 8200 # Per bank write bursts -system.physmem.perBankWrBursts::13 9100 # Per bank write bursts -system.physmem.perBankWrBursts::14 8920 # Per bank write bursts -system.physmem.perBankWrBursts::15 8794 # Per bank write bursts +system.physmem.perBankWrBursts::0 7820 # Per bank write bursts +system.physmem.perBankWrBursts::1 7688 # Per bank write bursts +system.physmem.perBankWrBursts::2 8067 # Per bank write bursts +system.physmem.perBankWrBursts::3 7737 # Per bank write bursts +system.physmem.perBankWrBursts::4 7196 # Per bank write bursts +system.physmem.perBankWrBursts::5 7011 # Per bank write bursts +system.physmem.perBankWrBursts::6 6646 # Per bank write bursts +system.physmem.perBankWrBursts::7 6392 # Per bank write bursts +system.physmem.perBankWrBursts::8 7401 # Per bank write bursts +system.physmem.perBankWrBursts::9 6804 # Per bank write bursts +system.physmem.perBankWrBursts::10 7278 # Per bank write bursts +system.physmem.perBankWrBursts::11 6972 # Per bank write bursts +system.physmem.perBankWrBursts::12 7052 # Per bank write bursts +system.physmem.perBankWrBursts::13 8008 # Per bank write bursts +system.physmem.perBankWrBursts::14 7983 # Per bank write bursts +system.physmem.perBankWrBursts::15 7942 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 50 # Number of times write queue was full causing retry -system.physmem.totGap 1887170570500 # Total gap between requests +system.physmem.numWrRetry 17 # Number of times write queue was full causing retry +system.physmem.totGap 1886187226500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404882 # Read request sizes (log2) +system.physmem.readPktSize::6 404702 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 159618 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118025 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -148,201 +148,188 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 78 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64763 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.696185 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 324.957517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.417041 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14664 22.64% 22.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11016 17.01% 39.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5432 8.39% 48.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3093 4.78% 52.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2464 3.80% 56.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1908 2.95% 59.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1486 2.29% 61.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1430 2.21% 64.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23270 35.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64763 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4906 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 82.503669 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3015.330482 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 4903 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63594 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 525.931377 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 320.890659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 414.200803 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14460 22.74% 22.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10997 17.29% 40.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4933 7.76% 47.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3625 5.70% 53.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2479 3.90% 57.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1827 2.87% 60.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1418 2.23% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1367 2.15% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22488 35.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63594 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5295 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.408121 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2902.928186 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5292 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4906 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4906 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.161639 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.352681 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 61.394400 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 4666 95.11% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 49 1.00% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 4 0.08% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 5 0.10% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 7 0.14% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 1 0.02% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 2 0.04% 96.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 7 0.14% 96.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 21 0.43% 97.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 22 0.45% 97.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 9 0.18% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 10 0.20% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 3 0.06% 97.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 2 0.04% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.04% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.06% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 2 0.04% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 2 0.04% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 3 0.06% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 19 0.39% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 9 0.18% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 5 0.10% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 13 0.26% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 3 0.06% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.02% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 1 0.02% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 3 0.06% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 5 0.10% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 3 0.06% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 8 0.16% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.04% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 3 0.06% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::656-671 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 3 0.06% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 3 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::816-831 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4906 # Writes before turning the bus around for reads -system.physmem.totQLat 2145475500 # Total ticks spent queuing -system.physmem.totMemAccLat 9735100500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023900000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5300.35 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5295 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5295 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.284608 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.797942 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.673735 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4676 88.31% 88.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 227 4.29% 92.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 77 1.45% 94.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 16 0.30% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 14 0.26% 94.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 6 0.11% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 7 0.13% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 9 0.17% 95.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 7 0.13% 95.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 34 0.64% 95.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 171 3.23% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 10 0.19% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.02% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.09% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.04% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.08% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 4 0.08% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 8 0.15% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.04% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 7 0.13% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5295 # Writes before turning the bus around for reads +system.physmem.totQLat 2213284250 # Total ticks spent queuing +system.physmem.totMemAccLat 9799496750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2022990000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5470.33 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24050.35 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24220.33 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.52 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.41 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing -system.physmem.readRowHits 363650 # Number of row buffer hits during reads -system.physmem.writeRowHits 109622 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.25 # Row buffer hit rate for writes -system.physmem.avgGap 3343083.38 # Average gap between requests -system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 239016960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 130416000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577401800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 430058160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 60604997490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1079143932000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1265387035290 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.518464 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1795039940480 # Time in different power states -system.physmem_0.memoryStateTime::REF 63016980000 # Time in different power states +system.physmem.avgWrQLen 24.19 # Average write queue length when enqueuing +system.physmem.readRowHits 363516 # Number of row buffer hits during reads +system.physmem.writeRowHits 95485 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.90 # Row buffer hit rate for writes +system.physmem.avgGap 3608360.06 # Average gap between requests +system.physmem.pageHitRate 87.83 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 233845920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127594500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1576231800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 379449360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 123197134320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 60326866845 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1078799265750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1264640388495 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.471373 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1794467110750 # Time in different power states +system.physmem_0.memoryStateTime::REF 62984220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 29120110770 # Time in different power states +system.physmem_0.memoryStateTime::ACT 28744633000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250591320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136731375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579882200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 433434240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61665698520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1078213500750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1265541051285 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.600071 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1793490285480 # Time in different power states -system.physmem_1.memoryStateTime::REF 63016980000 # Time in different power states +system.physmem_1.actEnergy 246924720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134730750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579632600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385171200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 123197134320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61494025635 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1077775442250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1264813061475 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.562919 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1792762379750 # Time in different power states +system.physmem_1.memoryStateTime::REF 62984220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30669779520 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30449364000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 15009390 # Number of BP lookups -system.cpu.branchPred.condPredicted 13017239 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 373223 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9937559 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5199343 # Number of BTB hits +system.cpu.branchPred.lookups 15004879 # Number of BP lookups +system.cpu.branchPred.condPredicted 13013312 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 375549 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10036322 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5207234 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.320122 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 808599 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32086 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 51.883887 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 808293 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 31321 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9244571 # DTB read hits -system.cpu.dtb.read_misses 17796 # DTB read misses +system.cpu.dtb.read_hits 9242647 # DTB read hits +system.cpu.dtb.read_misses 17811 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766653 # DTB read accesses -system.cpu.dtb.write_hits 6387559 # DTB write hits -system.cpu.dtb.write_misses 2314 # DTB write misses +system.cpu.dtb.read_accesses 766734 # DTB read accesses +system.cpu.dtb.write_hits 6385782 # DTB write hits +system.cpu.dtb.write_misses 2309 # DTB write misses system.cpu.dtb.write_acv 160 # DTB write access violations -system.cpu.dtb.write_accesses 298430 # DTB write accesses -system.cpu.dtb.data_hits 15632130 # DTB hits -system.cpu.dtb.data_misses 20110 # DTB misses +system.cpu.dtb.write_accesses 298407 # DTB write accesses +system.cpu.dtb.data_hits 15628429 # DTB hits +system.cpu.dtb.data_misses 20120 # DTB misses system.cpu.dtb.data_acv 371 # DTB access violations -system.cpu.dtb.data_accesses 1065083 # DTB accesses -system.cpu.itb.fetch_hits 4016391 # ITB hits -system.cpu.itb.fetch_misses 6902 # ITB misses -system.cpu.itb.fetch_acv 656 # ITB acv -system.cpu.itb.fetch_accesses 4023293 # ITB accesses +system.cpu.dtb.data_accesses 1065141 # DTB accesses +system.cpu.itb.fetch_hits 4016387 # ITB hits +system.cpu.itb.fetch_misses 6834 # ITB misses +system.cpu.itb.fetch_acv 689 # ITB acv +system.cpu.itb.fetch_accesses 4023221 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -355,39 +342,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 180739367 # number of cpu cycles simulated +system.cpu.numCycles 180216793 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56138893 # Number of instructions committed -system.cpu.committedOps 56138893 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2514465 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5513 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593619217 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.219504 # CPI: cycles per instruction -system.cpu.ipc 0.310607 # IPC: instructions per cycle +system.cpu.committedInsts 56121694 # Number of instructions committed +system.cpu.committedOps 56121694 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2519198 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5577 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3592175193 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.211179 # CPI: cycles per instruction +system.cpu.ipc 0.311412 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211474 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74790 40.94% 40.94% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211471 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74788 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 133 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105866 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182688 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73423 49.32% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105864 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182686 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73421 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73423 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148878 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1834553179500 97.21% 97.21% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 80704500 0.00% 97.22% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 676355500 0.04% 97.25% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 51868058000 2.75% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1887178297500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_good::31 73422 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148877 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1833775262000 97.22% 97.22% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 81341000 0.00% 97.23% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 679703500 0.04% 97.26% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 51658703500 2.74% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1886195010000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693547 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814930 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693550 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814934 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -426,112 +413,112 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4172 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175529 91.23% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6805 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175525 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5127 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192412 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5872 # number of protection mode switches +system.cpu.kern.callpal::total 192408 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5868 # number of protection mode switches system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2092 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches system.cpu.kern.mode_good::kernel 1907 system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.324762 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324983 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080306 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393074 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36563872500 1.94% 1.94% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4128201000 0.22% 2.16% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1846486214000 97.84% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080114 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.393034 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 36513483500 1.94% 1.94% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4123557000 0.22% 2.15% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1845557959500 97.85% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4173 # number of times the context was actually changed -system.cpu.tickCycles 84425844 # Number of cycles that the object actually ticked -system.cpu.idleCycles 96313523 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395605 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.981737 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13777018 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1396117 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.868097 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 90985250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.981737 # Average occupied blocks per requestor +system.cpu.tickCycles 84408299 # Number of cycles that the object actually ticked +system.cpu.idleCycles 95808494 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395428 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.981685 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13773051 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395940 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.866506 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 90850500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.981685 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63673578 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63673578 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7816852 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7816852 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5578390 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5578390 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182745 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182745 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 198996 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 198996 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13395242 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13395242 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13395242 # number of overall hits -system.cpu.dcache.overall_hits::total 13395242 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201883 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201883 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 573228 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573228 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17271 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17271 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1775111 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1775111 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1775111 # number of overall misses -system.cpu.dcache.overall_misses::total 1775111 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33009196500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33009196500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22459728804 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22459728804 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 231661750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 231661750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 55468925304 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 55468925304 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 55468925304 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 55468925304 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9018735 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9018735 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6151618 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6151618 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200016 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200016 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 198996 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 198996 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15170353 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15170353 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15170353 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15170353 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133265 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133265 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093183 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093183 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086348 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086348 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117012 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117012 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117012 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117012 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.567267 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.567267 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39181.143985 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39181.143985 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.337386 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.337386 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31248.144653 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31248.144653 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31248.144653 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31248.144653 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63660654 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63660654 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7815445 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815445 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5575784 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5575784 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182800 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182800 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 198989 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 198989 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13391229 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13391229 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13391229 # number of overall hits +system.cpu.dcache.overall_hits::total 13391229 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201797 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201797 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 574153 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 574153 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17210 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17210 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1775950 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1775950 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1775950 # number of overall misses +system.cpu.dcache.overall_misses::total 1775950 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32866409500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32866409500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22318082000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22318082000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230873000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 230873000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 55184491500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 55184491500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 55184491500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 55184491500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9017242 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9017242 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6149937 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6149937 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200010 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200010 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 198989 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 198989 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15167179 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15167179 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15167179 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15167179 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133278 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133278 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093359 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093359 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086046 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086046 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117092 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117092 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117092 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117092 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27347.721371 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27347.721371 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38871.314789 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38871.314789 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13415.049390 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13415.049390 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31073.223627 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31073.223627 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31073.223627 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31073.223627 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,129 +527,129 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838424 # number of writebacks -system.cpu.dcache.writebacks::total 838424 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127263 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127263 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268960 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 268960 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838228 # number of writebacks +system.cpu.dcache.writebacks::total 838228 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127318 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 127318 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269861 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1115769250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23843526141 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24959295391 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336297500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336297500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892281000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1892281000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3228578500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3228578500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011272 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249288 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113145 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818182 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818182 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011272 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278519 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141946 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011272 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278519 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141946 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67840.290022 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60055.935603 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60499.503698 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 23389.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23389.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64262.751719 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64262.751719 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67840.290022 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61318.056168 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61582.729186 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67840.290022 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61318.056168 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61582.729186 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192827.922078 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192827.922078 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196723.256056 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196723.256056 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195092.059943 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195092.059943 # average overall mshr uncacheable latency +system.cpu.l2cache.writebacks::writebacks 76513 # number of writebacks +system.cpu.l2cache.writebacks::total 76513 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 317 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 317 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116534 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116534 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16403 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16403 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272179 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272179 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16403 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388713 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405116 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16403 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388713 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405116 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6934 # 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number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1160467500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17006826000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17006826000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1160467500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24777358000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25937825500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1160467500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24777358000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25937825500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364748500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364748500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1931469000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1931469000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3296217500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3296217500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800000 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382955 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382955 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011238 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249327 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249327 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278456 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141868 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011238 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278456 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141868 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 26937.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26937.500000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66680.385124 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66680.385124 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70747.271841 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70747.271841 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62483.975619 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62483.975619 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70747.271841 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63742.035898 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64025.675362 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70747.271841 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63742.035898 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64025.675362 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196819.800981 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196819.800981 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200755.534768 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200755.534768 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199107.067351 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199107.067351 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2558177 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2558144 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 838424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41594 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304274 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304274 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 6934 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2558426 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 956270 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2277118 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 20 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 20 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304302 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304302 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1459696 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091829 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2918365 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663990 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6582355 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93385664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143064988 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236450652 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41986 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3752110 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.011132 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.104918 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4377747 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219297 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8597044 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93416704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143041221 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236457925 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422839 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6149292 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.068727 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.252990 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3710343 98.89% 98.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41767 1.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5726669 93.13% 93.13% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 422623 6.87% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3752110 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2698405000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 6149292 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3706373000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2192449154 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2189771045 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2195119407 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2105677995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -930,44 +934,43 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7103 # Transaction distribution -system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51171 # Transaction distribution -system.iobus.trans_dist::WriteResp 9619 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5094 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7107 # Transaction distribution +system.iobus.trans_dist::ReadResp 7107 # Transaction distribution +system.iobus.trans_dist::WriteReq 51173 # Transaction distribution +system.iobus.trans_dist::WriteResp 51173 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5104 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33098 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33110 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116560 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20416 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44316 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44357 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705924 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4705000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2705965 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4712000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -981,7 +984,7 @@ system.iobus.reqLayer23.occupancy 13484000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) @@ -989,23 +992,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 242104189 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216063756 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23489000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42024001 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.302269 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.294607 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1729988196000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.302269 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081392 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081392 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1729988854000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.294607 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.080913 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.080913 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1013,49 +1016,49 @@ system.iocache.tags.tag_accesses 375525 # Nu system.iocache.tags.data_accesses 375525 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8768796805 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8768796805 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907200873 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4907200873 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21637883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211031.883062 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 211031.883062 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 73108 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118097.826170 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118097.826170 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9982 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.323983 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1063,83 +1066,85 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6608090807 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6608090807 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829600873 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2829600873 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12987883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159031.834978 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159031.834978 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68097.826170 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68097.826170 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 295738 # Transaction distribution -system.membus.trans_dist::ReadResp 295722 # Transaction distribution -system.membus.trans_dist::WriteReq 9619 # Transaction distribution -system.membus.trans_dist::WriteResp 9619 # Transaction distribution -system.membus.trans_dist::Writeback 118066 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 159 # Transaction distribution -system.membus.trans_dist::UpgradeResp 159 # Transaction distribution -system.membus.trans_dist::ReadExReq 116521 # Transaction distribution -system.membus.trans_dist::ReadExResp 116521 # Transaction distribution +system.membus.trans_dist::ReadReq 6934 # Transaction distribution +system.membus.trans_dist::ReadResp 295673 # Transaction distribution +system.membus.trans_dist::WriteReq 9621 # Transaction distribution +system.membus.trans_dist::WriteResp 9621 # Transaction distribution +system.membus.trans_dist::Writeback 118025 # Transaction distribution +system.membus.trans_dist::CleanEvict 262175 # Transaction distribution +system.membus.trans_dist::UpgradeReq 156 # Transaction distribution +system.membus.trans_dist::UpgradeResp 156 # Transaction distribution +system.membus.trans_dist::ReadExReq 116394 # Transaction distribution +system.membus.trans_dist::ReadExResp 116394 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288755 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886877 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33110 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920007 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1044811 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30810944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30855260 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36172316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181774 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1306591 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44357 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30796800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30841157 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33498885 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 581705 # Request fanout histogram +system.membus.snoop_fanout::samples 843789 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 581705 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 843789 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 581705 # Request fanout histogram -system.membus.reqLayer0.occupancy 29342000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 843789 # Request fanout histogram +system.membus.reqLayer0.occupancy 29576000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1229889311 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1318697936 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160670093 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160007596 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 42495999 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 72031934 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index dad37454b..e5b1b4540 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.904438 # Number of seconds simulated -sim_ticks 1904437574000 # Number of ticks simulated -final_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.907980 # Number of seconds simulated +sim_ticks 1907980084000 # Number of ticks simulated +final_tick 1907980084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 149880 # Simulator instruction rate (inst/s) -host_op_rate 149880 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5044505517 # Simulator tick rate (ticks/s) -host_mem_usage 380636 # Number of bytes of host memory used -host_seconds 377.53 # Real time elapsed on the host -sim_insts 56583768 # Number of instructions simulated -sim_ops 56583768 # Number of ops (including micro ops) simulated +host_inst_rate 144634 # Simulator instruction rate (inst/s) +host_op_rate 144633 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4918211693 # Simulator tick rate (ticks/s) +host_mem_usage 381420 # Number of bytes of host memory used +host_seconds 387.94 # Real time elapsed on the host +sim_insts 56109384 # Number of instructions simulated +sim_ops 56109384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 878144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24662016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 107328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 745792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 744000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24138496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 236608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1227584 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26394240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 878144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 107328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 985472 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7983616 # Number of bytes written to this memory -system.physmem.bytes_written::total 7983616 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13721 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385344 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1677 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11653 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26347648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 744000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 236608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 980608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7952896 # Number of bytes written to this memory +system.physmem.bytes_written::total 7952896 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 377164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3697 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 19181 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 412410 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124744 # Number of write requests responded to by this memory -system.physmem.num_writes::total 124744 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 461104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12949763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 391607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13859336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 461104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56357 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517461 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4192112 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4192112 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4192112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 461104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12949763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 391607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18051448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 412410 # Number of read requests accepted -system.physmem.writeReqs 166296 # Number of write requests accepted -system.physmem.readBursts 412410 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 166296 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26387648 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue -system.physmem.bytesWritten 9015296 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26394240 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10642944 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 25417 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4739 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25681 # Per bank write bursts -system.physmem.perBankRdBursts::1 26031 # Per bank write bursts -system.physmem.perBankRdBursts::2 26262 # Per bank write bursts -system.physmem.perBankRdBursts::3 25929 # Per bank write bursts -system.physmem.perBankRdBursts::4 25778 # Per bank write bursts -system.physmem.perBankRdBursts::5 25597 # Per bank write bursts -system.physmem.perBankRdBursts::6 26273 # Per bank write bursts -system.physmem.perBankRdBursts::7 25295 # Per bank write bursts -system.physmem.perBankRdBursts::8 25970 # Per bank write bursts -system.physmem.perBankRdBursts::9 26150 # Per bank write bursts -system.physmem.perBankRdBursts::10 25721 # Per bank write bursts -system.physmem.perBankRdBursts::11 25208 # Per bank write bursts -system.physmem.perBankRdBursts::12 25640 # Per bank write bursts -system.physmem.perBankRdBursts::13 25768 # Per bank write bursts +system.physmem.num_reads::total 411682 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124264 # Number of write requests responded to by this memory +system.physmem.num_writes::total 124264 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 389941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12651335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 124010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 643395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13809184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 389941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 124010 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4168228 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4168228 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4168228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 389941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12651335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 124010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 643395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17977412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 411682 # Number of read requests accepted +system.physmem.writeReqs 124264 # Number of write requests accepted +system.physmem.readBursts 411682 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 124264 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26340672 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue +system.physmem.bytesWritten 7951552 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26347648 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7952896 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 45002 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25908 # Per bank write bursts +system.physmem.perBankRdBursts::1 25789 # Per bank write bursts +system.physmem.perBankRdBursts::2 26010 # Per bank write bursts +system.physmem.perBankRdBursts::3 25614 # Per bank write bursts +system.physmem.perBankRdBursts::4 25643 # Per bank write bursts +system.physmem.perBankRdBursts::5 25797 # Per bank write bursts +system.physmem.perBankRdBursts::6 25922 # Per bank write bursts +system.physmem.perBankRdBursts::7 25550 # Per bank write bursts +system.physmem.perBankRdBursts::8 25897 # Per bank write bursts +system.physmem.perBankRdBursts::9 25701 # Per bank write bursts +system.physmem.perBankRdBursts::10 25484 # Per bank write bursts +system.physmem.perBankRdBursts::11 25508 # Per bank write bursts +system.physmem.perBankRdBursts::12 25696 # Per bank write bursts +system.physmem.perBankRdBursts::13 25817 # Per bank write bursts system.physmem.perBankRdBursts::14 25547 # Per bank write bursts -system.physmem.perBankRdBursts::15 25457 # Per bank write bursts -system.physmem.perBankWrBursts::0 9358 # Per bank write bursts -system.physmem.perBankWrBursts::1 9077 # Per bank write bursts -system.physmem.perBankWrBursts::2 9200 # Per bank write bursts -system.physmem.perBankWrBursts::3 8756 # Per bank write bursts -system.physmem.perBankWrBursts::4 8419 # Per bank write bursts -system.physmem.perBankWrBursts::5 8251 # Per bank write bursts -system.physmem.perBankWrBursts::6 9072 # Per bank write bursts -system.physmem.perBankWrBursts::7 8046 # Per bank write bursts -system.physmem.perBankWrBursts::8 8692 # Per bank write bursts -system.physmem.perBankWrBursts::9 8978 # Per bank write bursts -system.physmem.perBankWrBursts::10 8574 # Per bank write bursts -system.physmem.perBankWrBursts::11 8968 # Per bank write bursts -system.physmem.perBankWrBursts::12 8555 # Per bank write bursts -system.physmem.perBankWrBursts::13 9260 # Per bank write bursts -system.physmem.perBankWrBursts::14 8896 # Per bank write bursts -system.physmem.perBankWrBursts::15 8762 # Per bank write bursts +system.physmem.perBankRdBursts::15 25690 # Per bank write bursts +system.physmem.perBankWrBursts::0 7970 # Per bank write bursts +system.physmem.perBankWrBursts::1 7556 # Per bank write bursts +system.physmem.perBankWrBursts::2 7711 # Per bank write bursts +system.physmem.perBankWrBursts::3 7606 # Per bank write bursts +system.physmem.perBankWrBursts::4 7633 # Per bank write bursts +system.physmem.perBankWrBursts::5 7951 # Per bank write bursts +system.physmem.perBankWrBursts::6 7934 # Per bank write bursts +system.physmem.perBankWrBursts::7 7815 # Per bank write bursts +system.physmem.perBankWrBursts::8 8060 # Per bank write bursts +system.physmem.perBankWrBursts::9 8044 # Per bank write bursts +system.physmem.perBankWrBursts::10 7565 # Per bank write bursts +system.physmem.perBankWrBursts::11 7446 # Per bank write bursts +system.physmem.perBankWrBursts::12 7634 # Per bank write bursts +system.physmem.perBankWrBursts::13 8000 # Per bank write bursts +system.physmem.perBankWrBursts::14 7754 # Per bank write bursts +system.physmem.perBankWrBursts::15 7564 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 50 # Number of times write queue was full causing retry -system.physmem.totGap 1904433039500 # Total gap between requests +system.physmem.numWrRetry 18 # Number of times write queue was full causing retry +system.physmem.totGap 1907975777500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 412410 # Read request sizes (log2) +system.physmem.readPktSize::6 411682 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 166296 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 39027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124264 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38583 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,200 +158,204 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 92 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66375 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 533.371902 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 326.032515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.702689 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14841 22.36% 22.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11366 17.12% 39.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5910 8.90% 48.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2909 4.38% 52.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2416 3.64% 56.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1747 2.63% 59.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1634 2.46% 61.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1312 1.98% 63.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24240 36.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66375 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5272 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.206942 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2891.855588 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5269 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 46 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65129 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.524774 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 320.940318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.518091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14691 22.56% 22.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11476 17.62% 40.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5283 8.11% 48.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3332 5.12% 53.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2563 3.94% 57.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1696 2.60% 59.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1442 2.21% 62.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1386 2.13% 64.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23260 35.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65129 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5620 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 73.233096 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2814.761745 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5617 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5272 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5272 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 26.719272 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.348145 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 60.306865 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 5026 95.33% 95.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 55 1.04% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 6 0.11% 96.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 3 0.06% 96.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 6 0.11% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 3 0.06% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 3 0.06% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 6 0.11% 96.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 24 0.46% 97.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 10 0.19% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 9 0.17% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 16 0.30% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 2 0.04% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 3 0.06% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 3 0.06% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 4 0.08% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 1 0.02% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 4 0.08% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 6 0.11% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 11 0.21% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 13 0.25% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 7 0.13% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 10 0.19% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 3 0.06% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.02% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.02% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 2 0.04% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 11 0.21% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 3 0.06% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.04% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 5 0.09% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 3 0.06% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.02% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 2 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 3 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::896-911 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5272 # Writes before turning the bus around for reads -system.physmem.totQLat 4111304500 # Total ticks spent queuing -system.physmem.totMemAccLat 11842060750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2061535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9971.46 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5620 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5620 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.107295 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.769658 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.265728 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4863 86.53% 86.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 151 2.69% 89.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 190 3.38% 92.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 20 0.36% 92.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 26 0.46% 93.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 52 0.93% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 14 0.25% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.12% 94.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 2 0.04% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.04% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.11% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.12% 95.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 8 0.14% 95.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.09% 95.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.05% 95.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.05% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 8 0.14% 95.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 8 0.14% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 26 0.46% 96.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 16 0.28% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 144 2.56% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 12 0.21% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.02% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.07% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.04% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.04% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.05% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 6 0.11% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 7 0.12% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 2 0.04% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 5 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-243 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5620 # Writes before turning the bus around for reads +system.physmem.totQLat 4128600500 # Total ticks spent queuing +system.physmem.totMemAccLat 11845594250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2057865000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10031.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28721.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.59 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28781.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.81 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage +system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.27 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing -system.physmem.readRowHits 371693 # Number of row buffer hits during reads -system.physmem.writeRowHits 115102 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.15 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.70 # Row buffer hit rate for writes -system.physmem.avgGap 3290847.23 # Average gap between requests -system.physmem.pageHitRate 88.00 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 251551440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 137255250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1613398800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 454759920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 57693505320 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1092050470500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1276589123070 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.325620 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1816548038492 # Time in different power states -system.physmem_0.memoryStateTime::REF 63593140000 # Time in different power states +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 2.21 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.72 # Average write queue length when enqueuing +system.physmem.readRowHits 370844 # Number of row buffer hits during reads +system.physmem.writeRowHits 99842 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.10 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.35 # Row buffer hit rate for writes +system.physmem.avgGap 3560014.96 # Average gap between requests +system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 245019600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 133691250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1608188400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 402589440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124619576640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 57486510675 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1094357699250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1278853275255 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.267627 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1820391723000 # Time in different power states +system.physmem_0.memoryStateTime::REF 63711440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 24290182758 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23872193000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250137720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136483875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1602190200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 457604640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 57661176915 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1092078837000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1276574612190 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.317995 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1816597555496 # Time in different power states -system.physmem_1.memoryStateTime::REF 63593140000 # Time in different power states +system.physmem_1.actEnergy 247287600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134928750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1601652000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 402194160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124619576640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 57648050955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1094215997250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1278869687355 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.276229 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1820158780750 # Time in different power states +system.physmem_1.memoryStateTime::REF 63711440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 24242350004 # Time in different power states +system.physmem_1.memoryStateTime::ACT 24103898000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 16050181 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14012515 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 321303 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 9883832 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5384164 # Number of BTB hits +system.cpu0.branchPred.lookups 11788808 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10301623 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 235567 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 7623393 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4144660 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 54.474459 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 809394 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 17633 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 54.367655 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 590548 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 12472 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9185685 # DTB read hits -system.cpu0.dtb.read_misses 31794 # DTB read misses -system.cpu0.dtb.read_acv 464 # DTB read access violations -system.cpu0.dtb.read_accesses 674724 # DTB read accesses -system.cpu0.dtb.write_hits 5856177 # DTB write hits -system.cpu0.dtb.write_misses 6642 # DTB write misses -system.cpu0.dtb.write_acv 308 # DTB write access violations -system.cpu0.dtb.write_accesses 220970 # DTB write accesses -system.cpu0.dtb.data_hits 15041862 # DTB hits -system.cpu0.dtb.data_misses 38436 # DTB misses -system.cpu0.dtb.data_acv 772 # DTB access violations -system.cpu0.dtb.data_accesses 895694 # DTB accesses -system.cpu0.itb.fetch_hits 1413849 # ITB hits -system.cpu0.itb.fetch_misses 27924 # ITB misses -system.cpu0.itb.fetch_acv 522 # ITB acv -system.cpu0.itb.fetch_accesses 1441773 # ITB accesses +system.cpu0.dtb.read_hits 7021210 # DTB read hits +system.cpu0.dtb.read_misses 28922 # DTB read misses +system.cpu0.dtb.read_acv 549 # DTB read access violations +system.cpu0.dtb.read_accesses 680178 # DTB read accesses +system.cpu0.dtb.write_hits 4516223 # DTB write hits +system.cpu0.dtb.write_misses 6969 # DTB write misses +system.cpu0.dtb.write_acv 383 # DTB write access violations +system.cpu0.dtb.write_accesses 234540 # DTB write accesses +system.cpu0.dtb.data_hits 11537433 # DTB hits +system.cpu0.dtb.data_misses 35891 # DTB misses +system.cpu0.dtb.data_acv 932 # DTB access violations +system.cpu0.dtb.data_accesses 914718 # DTB accesses +system.cpu0.itb.fetch_hits 1192769 # ITB hits +system.cpu0.itb.fetch_misses 29243 # ITB misses +system.cpu0.itb.fetch_acv 632 # ITB acv +system.cpu0.itb.fetch_accesses 1222012 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -364,595 +368,598 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 115311619 # number of cpu cycles simulated +system.cpu0.numCycles 94258709 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26308115 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 70327057 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16050181 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6193558 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 81501759 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1071492 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 564 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 28477 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1405877 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 453989 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 199 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8110639 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 231031 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 110234726 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.637976 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.938280 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 18560589 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 53027757 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 11788808 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4735208 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 69979824 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 806070 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 422 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 25803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1456351 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 296845 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 178 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6342869 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 170274 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 90723047 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.584501 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.854201 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 97059343 88.05% 88.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 844439 0.77% 88.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1832569 1.66% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 778966 0.71% 91.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2587591 2.35% 93.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 590382 0.54% 94.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 655112 0.59% 94.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 842956 0.76% 95.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5043368 4.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 80634947 88.88% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 672953 0.74% 89.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1448081 1.60% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 584574 0.64% 91.86% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2111688 2.33% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 463915 0.51% 94.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 450869 0.50% 95.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 614781 0.68% 95.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3741239 4.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 110234726 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.139190 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.609887 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 21404943 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 78060690 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8511786 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1756604 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 500702 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 518589 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35397 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 61724420 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 110442 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 500702 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 22241314 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 51035680 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18875449 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9340106 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 8241473 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59592973 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 194522 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2018079 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 142482 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4327383 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 39868450 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72416227 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72269697 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 136600 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34997307 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4871143 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1466604 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 213801 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12439963 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9310742 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6112181 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1342468 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 951279 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53110388 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1887245 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52243998 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 50112 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6621677 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2924940 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1298251 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 110234726 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.473934 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.210494 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 90723047 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.125069 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.562577 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 14977569 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 67686915 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6257157 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1423439 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 377966 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 370983 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 25389 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 46677806 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 79994 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 377966 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 15660908 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 46083028 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14369152 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6948168 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7283823 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 45068314 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 191995 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1547824 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 115834 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4229403 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 30289226 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 55138176 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 55047778 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 82793 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 26689501 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 3599717 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1126936 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 168790 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10038208 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7066684 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 4739993 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1073845 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 760534 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 40346624 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1418133 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 39715880 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 51531 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 4979263 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2318512 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 978590 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 90723047 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.437771 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.168840 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 88757561 80.52% 80.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9303542 8.44% 88.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3888317 3.53% 92.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2690563 2.44% 94.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2829805 2.57% 97.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1399486 1.27% 98.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 891988 0.81% 99.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 364157 0.33% 99.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 109307 0.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 74240349 81.83% 81.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7278177 8.02% 89.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3014429 3.32% 93.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2002130 2.21% 95.38% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2057446 2.27% 97.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1059416 1.17% 98.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 709655 0.78% 99.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 273899 0.30% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 87546 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 110234726 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 90723047 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 184539 19.02% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 463483 47.76% 66.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 322428 33.22% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 128942 17.20% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 17.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 362987 48.42% 65.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 257779 34.38% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 4481 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35873428 68.67% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57323 0.11% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 30345 0.06% 68.84% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.84% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.84% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.84% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 2234 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.85% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9533353 18.25% 87.09% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5924969 11.34% 98.43% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 817865 1.57% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3788 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 27155018 68.37% 68.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 40485 0.10% 68.48% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.48% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 25259 0.06% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.55% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 7282480 18.34% 86.89% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 4576355 11.52% 98.41% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 630612 1.59% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52243998 # Type of FU issued -system.cpu0.iq.rate 0.453068 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 970450 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018575 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 215148578 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61357419 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50866456 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 594706 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 279378 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 273817 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 52889876 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 320091 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 579148 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 39715880 # Type of FU issued +system.cpu0.iq.rate 0.421350 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 749708 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018877 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 170597233 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 46586090 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 38643243 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 358812 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 172505 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 165745 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 40269961 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 191839 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 469267 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1102308 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4274 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 17841 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 488268 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 864378 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3380 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 14864 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 401917 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18769 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 362429 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 11804 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 365714 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 500702 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 47770294 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 975694 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58389413 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 117266 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9310742 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6112181 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1666926 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 38737 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 734939 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 17841 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 161758 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 354564 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 516322 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51738600 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9239994 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 505398 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 377966 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 43619498 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 675796 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 44202753 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 88904 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7066684 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 4739993 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1257449 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 23012 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 538948 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 14864 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 117466 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 265776 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 383242 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 39342618 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 7067139 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 373261 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3391780 # number of nop insts executed -system.cpu0.iew.exec_refs 15116199 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8225133 # Number of branches executed -system.cpu0.iew.exec_stores 5876205 # Number of stores executed -system.cpu0.iew.exec_rate 0.448685 # Inst execution rate -system.cpu0.iew.wb_sent 51252595 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51140273 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26435135 # num instructions producing a value -system.cpu0.iew.wb_consumers 36676301 # num instructions consuming a value +system.cpu0.iew.exec_nop 2437996 # number of nop insts executed +system.cpu0.iew.exec_refs 11599884 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6171265 # Number of branches executed +system.cpu0.iew.exec_stores 4532745 # Number of stores executed +system.cpu0.iew.exec_rate 0.417390 # Inst execution rate +system.cpu0.iew.wb_sent 38908729 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 38808988 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 20149850 # num instructions producing a value +system.cpu0.iew.wb_consumers 27578035 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.443496 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.720769 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.411728 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.730649 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6957791 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 588994 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 471378 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 109009912 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.470894 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.405994 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 5183738 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 439543 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 349838 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 89803768 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.433386 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.354442 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 90895183 83.38% 83.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7166067 6.57% 89.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3956975 3.63% 93.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2029230 1.86% 95.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1623676 1.49% 96.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 582620 0.53% 97.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 429957 0.39% 97.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 432812 0.40% 98.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1893392 1.74% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 76032999 84.67% 84.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5542678 6.17% 90.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2869062 3.19% 94.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1578965 1.76% 95.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1284314 1.43% 97.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 412798 0.46% 97.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 324191 0.36% 98.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 314453 0.35% 98.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1444308 1.61% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 109009912 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51332073 # Number of instructions committed -system.cpu0.commit.committedOps 51332073 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 89803768 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 38919724 # Number of instructions committed +system.cpu0.commit.committedOps 38919724 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13832347 # Number of memory references committed -system.cpu0.commit.loads 8208434 # Number of loads committed -system.cpu0.commit.membars 200823 # Number of memory barriers committed -system.cpu0.commit.branches 7767218 # Number of branches committed -system.cpu0.commit.fp_insts 270478 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47526784 # Number of committed integer instructions. -system.cpu0.commit.function_calls 660195 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2960587 5.77% 5.77% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 33426068 65.12% 70.88% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 56116 0.11% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 30044 0.06% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 2234 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.06% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8409257 16.38% 87.44% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5629902 10.97% 98.41% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 817865 1.59% 100.00% # Class of committed instruction +system.cpu0.commit.refs 10540382 # Number of memory references committed +system.cpu0.commit.loads 6202306 # Number of loads committed +system.cpu0.commit.membars 144405 # Number of memory barriers committed +system.cpu0.commit.branches 5839773 # Number of branches committed +system.cpu0.commit.fp_insts 162063 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 36166381 # Number of committed integer instructions. +system.cpu0.commit.function_calls 471449 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2138002 5.49% 5.49% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 25394964 65.25% 70.74% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 39484 0.10% 70.84% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.84% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 24801 0.06% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.91% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 6346711 16.31% 87.22% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 4343267 11.16% 98.38% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 630612 1.62% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51332073 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1893392 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 165216916 # The number of ROB reads -system.cpu0.rob.rob_writes 117798939 # The number of ROB writes -system.cpu0.timesIdled 506110 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5076893 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3693292578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48375955 # Number of Instructions Simulated -system.cpu0.committedOps 48375955 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.383656 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.383656 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.419524 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.419524 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67964697 # number of integer regfile reads -system.cpu0.int_regfile_writes 37032803 # number of integer regfile writes -system.cpu0.fp_regfile_reads 135608 # number of floating regfile reads -system.cpu0.fp_regfile_writes 136877 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1822860 # number of misc regfile reads -system.cpu0.misc_regfile_writes 821150 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1283357 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.867544 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10588066 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1283792 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.247493 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 26416000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.867544 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988023 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988023 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 435 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.849609 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56965784 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56965784 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6531926 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6531926 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3699481 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3699481 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164387 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 164387 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189172 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 189172 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10231407 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10231407 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10231407 # number of overall hits -system.cpu0.dcache.overall_hits::total 10231407 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1592146 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1592146 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1718300 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1718300 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20836 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20836 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2478 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2478 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3310446 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3310446 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3310446 # number of overall misses -system.cpu0.dcache.overall_misses::total 3310446 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39294199360 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 39294199360 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76231824796 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 76231824796 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326020750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 326020750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20798848 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 20798848 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 115526024156 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 115526024156 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 115526024156 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 115526024156 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8124072 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8124072 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5417781 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5417781 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 185223 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 185223 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191650 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 191650 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13541853 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13541853 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13541853 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13541853 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195979 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.195979 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.317159 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.317159 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112491 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112491 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.012930 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.012930 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244460 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.244460 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244460 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.244460 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24680.022661 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 24680.022661 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44364.677179 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44364.677179 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15646.993185 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15646.993185 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8393.401130 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8393.401130 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34897.419911 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34897.419911 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4226969 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4392 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 103766 # number of cycles access was blocked +system.cpu0.commit.op_class_0::total 38919724 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1444308 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 132264444 # The number of ROB reads +system.cpu0.rob.rob_writes 89122078 # The number of ROB writes +system.cpu0.timesIdled 337516 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3535662 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3721701460 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 36785489 # Number of Instructions Simulated +system.cpu0.committedOps 36785489 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.562388 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.562388 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.390261 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.390261 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 51878765 # number of integer regfile reads +system.cpu0.int_regfile_writes 28204778 # number of integer regfile writes +system.cpu0.fp_regfile_reads 81728 # number of floating regfile reads +system.cpu0.fp_regfile_writes 81429 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1387632 # number of misc regfile reads +system.cpu0.misc_regfile_writes 636485 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 898491 # number of replacements +system.cpu0.dcache.tags.tagsinuse 481.994698 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 8012262 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 899003 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.912386 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 26393500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.994698 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.941396 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.941396 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 236 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 43230678 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 43230678 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5046736 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5046736 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 2679789 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 2679789 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129628 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 129628 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149296 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149296 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7726525 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 7726525 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7726525 # number of overall hits +system.cpu0.dcache.overall_hits::total 7726525 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1067598 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1067598 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1496200 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1496200 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12202 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 12202 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 769 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 769 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2563798 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2563798 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2563798 # number of overall misses +system.cpu0.dcache.overall_misses::total 2563798 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 32014122500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 32014122500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 69455032918 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 69455032918 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 190587000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 190587000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5445000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 5445000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 101469155418 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 101469155418 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 101469155418 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 101469155418 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6114334 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6114334 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4175989 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4175989 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 141830 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 141830 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 150065 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 150065 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10290323 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10290323 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10290323 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10290323 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.174606 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.174606 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.358286 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.358286 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086033 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086033 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.005124 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.005124 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249147 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.249147 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249147 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.249147 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29987.057394 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 29987.057394 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46420.955031 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 46420.955031 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15619.324701 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15619.324701 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7080.624187 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7080.624187 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39577.671649 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39577.671649 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39577.671649 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39577.671649 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4094264 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5021 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 103728 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.735588 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 46.723404 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 39.471155 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 53.414894 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 752753 # number of writebacks -system.cpu0.dcache.writebacks::total 752753 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 572031 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 572031 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1457971 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1457971 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4881 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4881 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2030002 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2030002 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2030002 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2030002 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1020115 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1020115 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 260329 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 260329 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15955 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15955 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2477 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2477 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1280444 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1280444 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1280444 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1280444 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7039 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7039 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10032 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10032 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17071 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17071 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28982142208 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28982142208 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11887451669 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11887451669 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 177873500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 177873500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 17082652 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 17082652 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 40869593877 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 40869593877 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 40869593877 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 40869593877 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1464167000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1464167000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2129748498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2129748498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3593915498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3593915498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125567 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125567 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048051 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048051 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086139 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086139 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.012925 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.012925 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094555 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094555 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094555 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094555 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28410.661747 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28410.661747 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45663.186464 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45663.186464 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11148.448762 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11148.448762 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6896.508680 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6896.508680 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208007.813610 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208007.813610 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 212295.504187 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212295.504187 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 210527.531955 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210527.531955 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 426068 # number of writebacks +system.cpu0.dcache.writebacks::total 426068 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 384761 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 384761 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1282051 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1282051 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 3514 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 3514 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1666812 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1666812 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1666812 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1666812 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 682837 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 682837 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 214149 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 214149 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8688 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8688 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 769 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 769 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 896986 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 896986 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 896986 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 896986 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 4777 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 4777 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 8020 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 8020 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 12797 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 12797 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25205904500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25205904500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10851652245 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10851652245 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 107603000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 107603000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4676000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4676000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36057556745 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 36057556745 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36057556745 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 36057556745 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1013290500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1013290500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1707574498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1707574498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2720864998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2720864998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.111678 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.111678 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051281 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051281 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061256 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061256 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.005124 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.005124 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.087168 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.087168 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.087168 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.087168 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36913.501319 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36913.501319 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 50673.373422 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 50673.373422 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12385.244015 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12385.244015 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6080.624187 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6080.624187 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40198.572492 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 40198.572492 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 40198.572492 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 40198.572492 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 212118.589073 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212118.589073 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 212914.525935 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212914.525935 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212617.410174 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212617.410174 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 911417 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.418391 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7153262 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 911929 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.844100 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 28352545250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.418391 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994958 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994958 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 615978 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.684225 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5692804 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 616490 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.234220 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 28149663500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.684225 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993524 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.993524 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 430 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9022750 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9022750 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7153262 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7153262 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7153262 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7153262 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7153262 # number of overall hits -system.cpu0.icache.overall_hits::total 7153262 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 957376 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 957376 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 957376 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 957376 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 957376 # number of overall misses -system.cpu0.icache.overall_misses::total 957376 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13452406105 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13452406105 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13452406105 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13452406105 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13452406105 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13452406105 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8110638 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8110638 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8110638 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8110638 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8110638 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8110638 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118040 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.118040 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118040 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.118040 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118040 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.118040 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14051.329995 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14051.329995 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14051.329995 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14051.329995 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5687 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 6959538 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 6959538 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 5692804 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5692804 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5692804 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5692804 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5692804 # number of overall hits +system.cpu0.icache.overall_hits::total 5692804 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 650065 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 650065 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 650065 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 650065 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 650065 # number of overall misses +system.cpu0.icache.overall_misses::total 650065 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9309214992 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9309214992 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9309214992 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9309214992 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9309214992 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9309214992 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6342869 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6342869 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6342869 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6342869 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6342869 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6342869 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.102488 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.102488 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.102488 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.102488 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.102488 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.102488 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14320.437175 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14320.437175 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14320.437175 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14320.437175 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14320.437175 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14320.437175 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3481 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 195 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 166 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.164103 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.969880 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45264 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 45264 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 45264 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 45264 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 45264 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 45264 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 912112 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 912112 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 912112 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 912112 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 912112 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 912112 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11511971092 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11511971092 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11511971092 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11511971092 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11511971092 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11511971092 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112459 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.112459 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.112459 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12621.225345 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33396 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 33396 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 33396 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 33396 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 33396 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 33396 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 616669 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 616669 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 616669 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 616669 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 616669 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 616669 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8251915495 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8251915495 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8251915495 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8251915495 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8251915495 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8251915495 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.097222 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.097222 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.097222 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.097222 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13381.433954 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13381.433954 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13381.433954 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13381.433954 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 3445639 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3003437 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 69264 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1910439 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 836162 # Number of BTB hits +system.cpu1.branchPred.lookups 7710185 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6710334 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 163097 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4502045 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 2070765 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 43.768055 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 167186 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 4809 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 45.996097 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 394984 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 11166 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1858276 # DTB read hits -system.cpu1.dtb.read_misses 10905 # DTB read misses -system.cpu1.dtb.read_acv 64 # DTB read access violations -system.cpu1.dtb.read_accesses 300263 # DTB read accesses -system.cpu1.dtb.write_hits 1193771 # DTB write hits -system.cpu1.dtb.write_misses 2902 # DTB write misses -system.cpu1.dtb.write_acv 104 # DTB write access violations -system.cpu1.dtb.write_accesses 125157 # DTB write accesses -system.cpu1.dtb.data_hits 3052047 # DTB hits -system.cpu1.dtb.data_misses 13807 # DTB misses -system.cpu1.dtb.data_acv 168 # DTB access violations -system.cpu1.dtb.data_accesses 425420 # DTB accesses -system.cpu1.itb.fetch_hits 529068 # ITB hits -system.cpu1.itb.fetch_misses 7485 # ITB misses -system.cpu1.itb.fetch_acv 158 # ITB acv -system.cpu1.itb.fetch_accesses 536553 # ITB accesses +system.cpu1.dtb.read_hits 4026297 # DTB read hits +system.cpu1.dtb.read_misses 14233 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 293572 # DTB read accesses +system.cpu1.dtb.write_hits 2497972 # DTB write hits +system.cpu1.dtb.write_misses 2408 # DTB write misses +system.cpu1.dtb.write_acv 37 # DTB write access violations +system.cpu1.dtb.write_accesses 109195 # DTB write accesses +system.cpu1.dtb.data_hits 6524269 # DTB hits +system.cpu1.dtb.data_misses 16641 # DTB misses +system.cpu1.dtb.data_acv 43 # DTB access violations +system.cpu1.dtb.data_accesses 402767 # DTB accesses +system.cpu1.itb.fetch_hits 750930 # ITB hits +system.cpu1.itb.fetch_misses 5383 # ITB misses +system.cpu1.itb.fetch_acv 53 # ITB acv +system.cpu1.itb.fetch_accesses 756313 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -965,570 +972,564 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 14296923 # number of cpu cycles simulated +system.cpu1.numCycles 34369930 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5827989 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 13624759 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3445639 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1003348 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 7312463 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 270756 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 304 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 25051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 299772 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 60327 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1551048 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 55046 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 13661307 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.997325 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.404073 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 13361598 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 30714280 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7710185 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 2465749 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 18120966 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 547594 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 46 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 23797 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 211021 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 198154 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 54 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 3304195 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 117193 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 32189433 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.954173 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.349586 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 11273523 82.52% 82.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 149434 1.09% 83.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 236962 1.73% 85.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 182278 1.33% 86.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 319422 2.34% 89.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 124907 0.91% 89.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 138046 1.01% 90.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 169812 1.24% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1066923 7.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 26750456 83.10% 83.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 307184 0.95% 84.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 618506 1.92% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 382121 1.19% 87.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 801179 2.49% 89.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 249293 0.77% 90.43% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 334783 1.04% 91.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 403446 1.25% 92.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 2342465 7.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 13661307 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.241006 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.952985 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 4848979 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6756897 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1724085 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 202692 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 128653 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 104901 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 6833 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 11127112 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21450 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 128653 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 4991483 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 690115 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5206241 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1784475 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 860338 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10551561 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3558 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 63390 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 12017 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 381484 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 6914568 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12620115 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 12571129 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 43721 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5829921 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1084639 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 430965 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 39644 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1821487 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1910201 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1273290 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 221141 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 146764 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9284732 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 487174 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9053277 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 20996 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1564088 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 731721 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 360528 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 13661307 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.662695 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.384311 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 32189433 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.224329 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.893638 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 11124412 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16339992 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 3934359 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 534571 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 256098 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 250042 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 17822 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 25897409 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 55799 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 256098 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 11423416 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 4918911 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 9329125 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 4131002 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2130879 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 24789451 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 5724 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 540758 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 43054 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 820253 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 16289258 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 29487961 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 29391972 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 88964 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 13777657 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2511601 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 753305 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 82405 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 4252225 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 4127805 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 2629581 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 507300 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 331297 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 21789875 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 948507 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 21283611 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 28389 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 3414486 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1484281 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 680406 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 32189433 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.661199 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.387208 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 9895925 72.44% 72.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1648518 12.07% 84.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 704790 5.16% 89.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 494622 3.62% 93.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 437905 3.21% 96.49% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 233549 1.71% 98.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 155573 1.14% 99.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 64890 0.47% 99.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 25535 0.19% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 23533399 73.11% 73.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 3630192 11.28% 84.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 1573878 4.89% 89.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 1186258 3.69% 92.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 1178148 3.66% 96.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 546160 1.70% 98.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 337865 1.05% 99.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 151957 0.47% 99.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 51576 0.16% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 13661307 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 32189433 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 22279 8.85% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 136629 54.29% 63.14% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 92774 36.86% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 80499 16.46% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 16.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 246874 50.47% 66.92% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 161807 33.08% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 2817 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5609130 61.96% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 14890 0.16% 62.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 8778 0.10% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1408 0.02% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1940639 21.44% 83.70% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1217689 13.45% 97.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 257926 2.85% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 14071465 66.11% 66.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 30174 0.14% 66.27% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 13456 0.06% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.34% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 4194422 19.71% 86.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 2532925 11.90% 97.95% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 435892 2.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9053277 # Type of FU issued -system.cpu1.iq.rate 0.633233 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 251682 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.027800 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 31870123 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11259293 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8718718 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 170415 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 80938 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 78899 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9210850 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 91292 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 92092 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 21283611 # Type of FU issued +system.cpu1.iq.rate 0.619251 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 489180 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.022984 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 74907239 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 25989017 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 20583813 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 366985 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 171482 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 168729 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 21571772 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 197501 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 207443 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 283440 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 879 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4333 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 136775 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 572592 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1888 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 7837 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 247159 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 421 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 73078 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 7441 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 131088 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 128653 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 295868 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 364148 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10275512 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 29401 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1910201 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1273290 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 443383 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 3815 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 359581 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4333 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 31404 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 95843 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 127247 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 8933578 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1876162 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 119698 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 256098 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 4050515 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 319306 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 24169619 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 59065 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 4127805 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 2629581 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 846465 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 33159 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 202940 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 7837 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 80858 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 187737 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 268595 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 21021510 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 4051663 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 262101 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 503606 # number of nop insts executed -system.cpu1.iew.exec_refs 3078439 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1318456 # Number of branches executed -system.cpu1.iew.exec_stores 1202277 # Number of stores executed -system.cpu1.iew.exec_rate 0.624860 # Inst execution rate -system.cpu1.iew.wb_sent 8830913 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8797617 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4148200 # num instructions producing a value -system.cpu1.iew.wb_consumers 5856949 # num instructions consuming a value +system.cpu1.iew.exec_nop 1431237 # number of nop insts executed +system.cpu1.iew.exec_refs 6560061 # number of memory reference insts executed +system.cpu1.iew.exec_branches 3322997 # Number of branches executed +system.cpu1.iew.exec_stores 2508398 # Number of stores executed +system.cpu1.iew.exec_rate 0.611625 # Inst execution rate +system.cpu1.iew.wb_sent 20805592 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 20752542 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 10210202 # num instructions producing a value +system.cpu1.iew.wb_consumers 14612629 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.615350 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.708253 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.603799 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.698725 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1592161 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 126646 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 116539 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 13369044 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.644454 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.620421 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 3582987 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 268101 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 243613 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 31565232 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.650241 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.623237 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10245809 76.64% 76.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1446725 10.82% 87.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 518907 3.88% 91.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 315988 2.36% 93.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 242120 1.81% 95.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 97246 0.73% 96.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 91600 0.69% 96.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 106270 0.79% 97.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 304379 2.28% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 24282945 76.93% 76.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 2976975 9.43% 86.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1587723 5.03% 91.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 771361 2.44% 93.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 532421 1.69% 95.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 258990 0.82% 96.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 207817 0.66% 97.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 189047 0.60% 97.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 757953 2.40% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 13369044 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8615735 # Number of instructions committed -system.cpu1.commit.committedOps 8615735 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 31565232 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 20524993 # Number of instructions committed +system.cpu1.commit.committedOps 20524993 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2763276 # Number of memory references committed -system.cpu1.commit.loads 1626761 # Number of loads committed -system.cpu1.commit.membars 39485 # Number of memory barriers committed -system.cpu1.commit.branches 1225974 # Number of branches committed -system.cpu1.commit.fp_insts 77544 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 7995429 # Number of committed integer instructions. -system.cpu1.commit.function_calls 135018 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 410738 4.77% 4.77% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 5119196 59.42% 64.18% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 14466 0.17% 64.35% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.35% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 8774 0.10% 64.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1408 0.02% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.47% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1666246 19.34% 83.81% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1136981 13.20% 97.01% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 257926 2.99% 100.00% # Class of committed instruction +system.cpu1.commit.refs 5937635 # Number of memory references committed +system.cpu1.commit.loads 3555213 # Number of loads committed +system.cpu1.commit.membars 92415 # Number of memory barriers committed +system.cpu1.commit.branches 3082130 # Number of branches committed +system.cpu1.commit.fp_insts 166998 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 18893824 # Number of committed integer instructions. +system.cpu1.commit.function_calls 318960 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 1204616 5.87% 5.87% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 12808497 62.40% 68.27% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 29745 0.14% 68.42% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 68.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 13451 0.07% 68.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 68.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 68.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 68.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.01% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.49% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 3647628 17.77% 86.26% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 2383405 11.61% 97.88% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 435892 2.12% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 8615735 # Class of committed instruction -system.cpu1.commit.bw_lim_events 304379 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 23176968 # The number of ROB reads -system.cpu1.rob.rob_writes 20704388 # The number of ROB writes -system.cpu1.timesIdled 112605 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 635616 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3794578226 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8207813 # Number of Instructions Simulated -system.cpu1.committedOps 8207813 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.741868 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.741868 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.574096 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.574096 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11535994 # number of integer regfile reads -system.cpu1.int_regfile_writes 6250844 # number of integer regfile writes -system.cpu1.fp_regfile_reads 43175 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42684 # number of floating regfile writes -system.cpu1.misc_regfile_reads 891820 # number of misc regfile reads -system.cpu1.misc_regfile_writes 203240 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 102439 # number of replacements -system.cpu1.dcache.tags.tagsinuse 489.756832 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2417231 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 102951 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.479432 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1034185261500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 489.756832 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.956556 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.956556 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 11476458 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 11476458 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1494681 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1494681 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 855193 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 855193 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29899 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 29899 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 28520 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 28520 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2349874 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2349874 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2349874 # number of overall hits -system.cpu1.dcache.overall_hits::total 2349874 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 181396 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 181396 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 244262 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 244262 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4731 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4731 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2607 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2607 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 425658 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 425658 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 425658 # number of overall misses -system.cpu1.dcache.overall_misses::total 425658 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2290258065 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2290258065 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9952106154 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 9952106154 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46237999 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 46237999 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22188385 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 22188385 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12242364219 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12242364219 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12242364219 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12242364219 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1676077 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1676077 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1099455 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1099455 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 34630 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 34630 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 31127 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 31127 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2775532 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2775532 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2775532 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2775532 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.108227 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.108227 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.222166 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.222166 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.136616 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.136616 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083754 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083754 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.153361 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.153361 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.153361 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.153361 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12625.736317 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12625.736317 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40743.571059 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 40743.571059 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9773.409216 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9773.409216 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8511.079785 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8511.079785 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 28761.034020 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 28761.034020 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 574336 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 346 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 18255 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 31.461846 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 43.250000 # average number of cycles each access was blocked +system.cpu1.commit.op_class_0::total 20524993 # Class of committed instruction +system.cpu1.commit.bw_lim_events 757953 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 54833276 # The number of ROB reads +system.cpu1.rob.rob_writes 48835744 # The number of ROB writes +system.cpu1.timesIdled 276866 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2180497 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3780899978 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 19323895 # Number of Instructions Simulated +system.cpu1.committedOps 19323895 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.778623 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.778623 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.562233 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.562233 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 27142723 # number of integer regfile reads +system.cpu1.int_regfile_writes 14810250 # number of integer regfile writes +system.cpu1.fp_regfile_reads 88193 # number of floating regfile reads +system.cpu1.fp_regfile_writes 88824 # number of floating regfile writes +system.cpu1.misc_regfile_reads 1272248 # number of misc regfile reads +system.cpu1.misc_regfile_writes 377130 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 561653 # number of replacements +system.cpu1.dcache.tags.tagsinuse 496.197725 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4717582 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 561970 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 8.394722 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 37149185000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 496.197725 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.969136 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.969136 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 317 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.619141 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 24916279 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 24916279 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2844065 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2844065 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1751257 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1751257 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 62172 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 62172 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 69860 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 69860 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 4595322 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4595322 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 4595322 # number of overall hits +system.cpu1.dcache.overall_hits::total 4595322 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 792097 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 792097 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 552973 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 552973 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14160 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14160 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 786 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 786 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1345070 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1345070 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1345070 # number of overall misses +system.cpu1.dcache.overall_misses::total 1345070 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 10154789500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 10154789500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 16820667860 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 16820667860 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 217520000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 217520000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6395000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 6395000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 26975457360 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 26975457360 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 26975457360 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 26975457360 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3636162 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3636162 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2304230 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2304230 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 76332 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 76332 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 70646 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 70646 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 5940392 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 5940392 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 5940392 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 5940392 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.217839 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.217839 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.239982 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.239982 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.185505 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.185505 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.011126 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.011126 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.226428 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.226428 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.226428 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.226428 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12820.133771 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12820.133771 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30418.606080 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30418.606080 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15361.581921 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15361.581921 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8136.132316 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8136.132316 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20055.058369 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20055.058369 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20055.058369 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20055.058369 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 765854 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 810 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 36939 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 18 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.732938 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 45 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 70134 # number of writebacks -system.cpu1.dcache.writebacks::total 70134 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 110614 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 110614 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 203686 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 203686 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 700 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 700 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 314300 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 314300 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 314300 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 314300 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 70782 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 70782 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 40576 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 40576 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4031 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4031 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2607 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2607 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 111358 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 111358 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 111358 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 111358 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 158 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2893 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2893 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3051 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3051 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 815361518 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 815361518 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1580599049 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1580599049 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 32399501 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 32399501 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 18277115 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 18277115 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2395960567 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2395960567 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2395960567 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2395960567 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29330000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29330000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 630993000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 630993000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 660323000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 660323000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042231 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042231 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036906 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036906 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.116402 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.116402 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083754 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083754 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.040121 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.040121 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11519.334266 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11519.334266 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38954.038077 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 38954.038077 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8037.583974 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8037.583974 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7010.784427 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7010.784427 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185632.911392 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185632.911392 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218110.266160 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 218110.266160 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 216428.384136 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 216428.384136 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 435263 # number of writebacks +system.cpu1.dcache.writebacks::total 435263 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 332265 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 332265 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 455576 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 455576 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 2707 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 2707 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 787841 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 787841 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 787841 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 787841 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 459832 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 459832 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 97397 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 97397 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11453 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11453 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 786 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 786 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 557229 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 557229 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 557229 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 557229 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2425 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2425 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4340 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4340 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6765 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6765 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5761115500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5761115500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2818212839 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2818212839 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 135759000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 135759000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5609000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5609000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8579328339 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8579328339 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8579328339 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8579328339 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 499447000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 499447000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 957710500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 957710500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1457157500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1457157500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.126461 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.126461 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.042269 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.042269 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.150042 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.150042 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.011126 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.011126 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.093803 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.093803 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.093803 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.093803 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12528.739844 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12528.739844 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28935.314630 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28935.314630 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11853.575482 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11853.575482 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7136.132316 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7136.132316 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15396.413932 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15396.413932 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15396.413932 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15396.413932 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 205957.525773 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205957.525773 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220670.622120 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 220670.622120 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 215396.526238 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 215396.526238 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 211356 # number of replacements -system.cpu1.icache.tags.tagsinuse 472.195820 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1331062 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 211865 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.282595 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1880244277250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 472.195820 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.922257 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.922257 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 392 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1762968 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1762968 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1331062 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1331062 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1331062 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1331062 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1331062 # number of overall hits -system.cpu1.icache.overall_hits::total 1331062 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 219986 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 219986 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 219986 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 219986 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 219986 # number of overall misses -system.cpu1.icache.overall_misses::total 219986 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2974295730 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2974295730 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2974295730 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2974295730 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2974295730 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2974295730 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1551048 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1551048 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1551048 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1551048 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1551048 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1551048 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.141831 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.141831 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.141831 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.141831 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.141831 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.141831 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13520.386434 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13520.386434 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13520.386434 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13520.386434 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 613 # number of cycles access was blocked +system.cpu1.icache.tags.replacements 499853 # number of replacements +system.cpu1.icache.tags.tagsinuse 504.618896 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 2783346 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 500364 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.562642 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 48744804500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.618896 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.985584 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.985584 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 3804626 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 3804626 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 2783351 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 2783351 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 2783351 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 2783351 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 2783351 # number of overall hits +system.cpu1.icache.overall_hits::total 2783351 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 520843 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 520843 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 520843 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 520843 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 520843 # number of overall misses +system.cpu1.icache.overall_misses::total 520843 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7005360499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7005360499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7005360499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7005360499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7005360499 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7005360499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 3304194 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 3304194 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 3304194 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 3304194 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 3304194 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 3304194 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.157631 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.157631 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.157631 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.157631 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.157631 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.157631 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13450.042525 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13450.042525 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13450.042525 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13450.042525 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13450.042525 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13450.042525 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1720 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 40 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 65 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.325000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 26.461538 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8066 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 8066 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 8066 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 8066 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 8066 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 8066 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 211920 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 211920 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 211920 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 211920 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 211920 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 211920 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2567742004 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2567742004 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2567742004 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2567742004 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2567742004 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2567742004 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.136630 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.136630 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.136630 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12116.562873 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 20411 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 20411 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 20411 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 20411 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 20411 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 20411 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 500432 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 500432 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 500432 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 500432 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 500432 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 500432 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6297993499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6297993499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6297993499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6297993499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6297993499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6297993499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.151454 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.151454 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.151454 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.151454 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12585.113460 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12585.113460 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.113460 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12585.113460 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1542,54 +1543,53 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7375 # Transaction distribution -system.iobus.trans_dist::ReadResp 7375 # Transaction distribution -system.iobus.trans_dist::WriteReq 54477 # Transaction distribution -system.iobus.trans_dist::WriteResp 12925 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11660 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7377 # Transaction distribution +system.iobus.trans_dist::ReadResp 7377 # Transaction distribution +system.iobus.trans_dist::WriteReq 53912 # Transaction distribution +system.iobus.trans_dist::WriteResp 53912 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10518 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 172 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18142 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 46640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122578 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 149 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9071 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 72837 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2734485 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 11011000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 68315 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2729939 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 9868000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 148000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13500000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -1601,285 +1601,291 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 242105442 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216085248 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27319000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26764000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42037503 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.483577 # Cycle average of tags in use +system.iocache.tags.replacements 41701 # number of replacements +system.iocache.tags.tagsinuse 0.804902 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41717 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711318407000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.483577 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.030224 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.030224 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1711319254000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.804902 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.050306 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.050306 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375570 # Number of tag accesses -system.iocache.tags.data_accesses 375570 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 178 # number of demand (read+write) misses -system.iocache.demand_misses::total 178 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 178 # number of overall misses -system.iocache.overall_misses::total 178 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22300881 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22300881 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8783600058 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8783600058 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22300881 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22300881 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22300881 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22300881 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 178 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 178 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 178 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 178 # number of overall (read+write) accesses +system.iocache.tags.tag_accesses 375543 # Number of tag accesses +system.iocache.tags.data_accesses 375543 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses +system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses +system.iocache.demand_misses::total 175 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 175 # number of overall misses +system.iocache.overall_misses::total 175 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 25392883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 25392883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907312365 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4907312365 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 25392883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 25392883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 25392883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 25392883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125285.848315 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125285.848315 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211388.141558 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 211388.141558 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125285.848315 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125285.848315 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 73351 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 145102.188571 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 145102.188571 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118100.509362 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118100.509362 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 145102.188571 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 145102.188571 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 145102.188571 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 145102.188571 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10036 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.308788 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 178 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 178 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 178 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 178 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12879885 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12879885 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6622894060 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6622894060 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12879885 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12879885 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12879885 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12879885 # number of overall MSHR miss cycles +system.iocache.writebacks::writebacks 41526 # number of writebacks +system.iocache.writebacks::total 41526 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 16642883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16642883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829712365 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2829712365 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 16642883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16642883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 16642883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16642883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72358.904494 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159388.093473 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159388.093473 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 95102.188571 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 95102.188571 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68100.509362 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68100.509362 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 95102.188571 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 95102.188571 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 95102.188571 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 95102.188571 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 346915 # number of replacements -system.l2c.tags.tagsinuse 65246.496404 # Cycle average of tags in use -system.l2c.tags.total_refs 2614060 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 412065 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.343805 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7589002750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53536.501359 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5301.488199 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6124.882413 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 215.988746 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 67.635688 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.816902 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080894 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.093458 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003296 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001032 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995583 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65150 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2446 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5392 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7744 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 49345 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994110 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27379617 # Number of tag accesses -system.l2c.tags.data_accesses 27379617 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 898215 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 742471 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 210198 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 63927 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1914811 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 822887 # number of Writeback hits -system.l2c.Writeback_hits::total 822887 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 246 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 422 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 53 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 83 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 152332 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 25116 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 177448 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 898215 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 894803 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 210198 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 89043 # number of demand (read+write) hits -system.l2c.demand_hits::total 2092259 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 898215 # number of overall hits -system.l2c.overall_hits::cpu0.data 894803 # number of overall hits -system.l2c.overall_hits::cpu1.inst 210198 # number of overall hits -system.l2c.overall_hits::cpu1.data 89043 # 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number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 7202 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 8020 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4340 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 12360 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 12797 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 6765 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 19562 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 53861495 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 11082500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 64943995 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1433500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2068000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 3501500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8263056000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1632969000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 9896025000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 847954500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 277279000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1125233500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17126346500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 197172000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 17323518500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 847954500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 25389402500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 277279000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1830141000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 28344777000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 847954500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 25389402500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 277279000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1830141000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 28344777000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 953578000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 469134500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1422712500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1615175500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 905955000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2521130500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2568753500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1375089500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3943843000 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.948238 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.870550 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.933872 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.644860 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.735294 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.695473 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.478216 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.182684 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.388754 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018857 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007388 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013719 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.402714 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.004884 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.244531 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018857 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.421292 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007388 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.036304 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.161474 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018857 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.421292 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007388 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.036304 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.161474 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20852.301587 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20599.442379 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20808.713553 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20775.362319 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20680 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20718.934911 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 78361.429330 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 93376.543916 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80497.372617 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72936.048512 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75001.081958 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73434.281799 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 62941.831619 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 90528.925620 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63160.898146 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72936.048512 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67248.500845 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75001.081958 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93061.171565 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68708.781073 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72936.048512 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67248.500845 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75001.081958 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93061.171565 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68708.781073 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 199618.589073 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193457.525773 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197544.084976 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 201393.453865 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 208745.391705 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 203974.959547 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200730.913495 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 203265.262380 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 201607.350987 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296650 # Transaction distribution -system.membus.trans_dist::ReadResp 296572 # Transaction distribution -system.membus.trans_dist::WriteReq 12925 # Transaction distribution -system.membus.trans_dist::WriteResp 12925 # Transaction distribution -system.membus.trans_dist::Writeback 124744 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9402 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5001 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4742 # Transaction distribution -system.membus.trans_dist::ReadExReq 123808 # Transaction distribution -system.membus.trans_dist::ReadExResp 123481 # Transaction distribution -system.membus.trans_dist::BadAddressError 78 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927766 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 968166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1092983 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 72837 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31719616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31792453 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 37110021 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 10437 # Total snoops (count) -system.membus.snoop_fanout::samples 614132 # Request fanout histogram +system.membus.trans_dist::ReadReq 7202 # Transaction distribution +system.membus.trans_dist::ReadResp 296546 # Transaction distribution +system.membus.trans_dist::WriteReq 12360 # Transaction distribution +system.membus.trans_dist::WriteResp 12360 # Transaction distribution +system.membus.trans_dist::Writeback 124264 # Transaction distribution +system.membus.trans_dist::CleanEvict 262871 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5279 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1481 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3452 # Transaction distribution +system.membus.trans_dist::ReadExReq 122900 # Transaction distribution +system.membus.trans_dist::ReadExResp 122774 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289774 # Transaction distribution +system.membus.trans_dist::BadAddressError 430 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39124 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179542 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1219526 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1344359 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68315 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31641920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31710235 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2658624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 34368859 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3872 # Total snoops (count) +system.membus.snoop_fanout::samples 867863 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 614132 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 867863 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 614132 # Request fanout histogram -system.membus.reqLayer0.occupancy 36342500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 867863 # Request fanout histogram +system.membus.reqLayer0.occupancy 35224999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1279237311 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1361324691 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 100000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 531000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2197321028 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2190703579 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 42525497 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 72073655 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2231372 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2231278 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12925 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12925 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 822887 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41587 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 9543 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5084 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 14627 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302295 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302295 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1824058 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369862 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 423804 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 296769 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5914493 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58364544 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130195442 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13560576 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10962579 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213083141 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 72565 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3425693 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012192 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.109741 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7202 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2275897 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12360 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12360 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 985613 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1602095 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 5338 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1555 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 6893 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 317171 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 317171 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1117101 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1152039 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 430 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1728214 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2704934 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1334787 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1622621 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7390556 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39458944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 84672718 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32025024 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 62527373 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 218684059 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 464381 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5618153 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.076464 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.265739 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3383928 98.78% 98.78% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41765 1.22% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 5188566 92.35% 92.35% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 429587 7.65% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3425693 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2521355915 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 5618153 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3461836914 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 240000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1371805405 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2024294017 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 925515973 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1363977262 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 318303496 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 751744303 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 173244936 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 856189885 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2154,171 +2174,161 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6519 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 185119 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65685 40.48% 40.48% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 132 0.08% 40.56% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.19% 41.75% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 154 0.09% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 94359 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 162254 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64617 49.22% 49.22% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 132 0.10% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.47% 50.78% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 154 0.12% 50.90% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 64464 49.10% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 131291 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1861341200000 97.74% 97.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 60253000 0.00% 97.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 540538500 0.03% 97.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 69963500 0.00% 97.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 42290129000 2.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1904302084000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983741 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4815 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 139340 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 45519 38.89% 38.89% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 133 0.11% 39.01% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1927 1.65% 40.65% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 40.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 69446 59.33% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 117041 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 44932 48.88% 48.88% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 133 0.14% 49.02% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1927 2.10% 51.12% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.02% 51.14% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 44917 48.86% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 91925 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1870471244000 98.03% 98.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 61392000 0.00% 98.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 548913500 0.03% 98.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8511500 0.00% 98.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 36889187000 1.93% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1907979248000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.987104 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.683178 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.809170 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 6 2.79% 2.79% # number of syscalls executed -system.cpu0.kern.syscall::3 18 8.37% 11.16% # number of syscalls executed -system.cpu0.kern.syscall::4 3 1.40% 12.56% # number of syscalls executed -system.cpu0.kern.syscall::6 29 13.49% 26.05% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 26.51% # number of syscalls executed -system.cpu0.kern.syscall::15 1 0.47% 26.98% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.19% 31.16% # number of syscalls executed -system.cpu0.kern.syscall::19 6 2.79% 33.95% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.86% 35.81% # number of syscalls executed -system.cpu0.kern.syscall::23 2 0.93% 36.74% # number of syscalls executed -system.cpu0.kern.syscall::24 4 1.86% 38.60% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.26% 41.86% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.93% 42.79% # number of syscalls executed -system.cpu0.kern.syscall::45 35 16.28% 59.07% # number of syscalls executed -system.cpu0.kern.syscall::47 4 1.86% 60.93% # number of syscalls executed -system.cpu0.kern.syscall::48 7 3.26% 64.19% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.19% 68.37% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 68.84% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.33% 71.16% # number of syscalls executed -system.cpu0.kern.syscall::71 32 14.88% 86.05% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.40% 87.44% # number of syscalls executed -system.cpu0.kern.syscall::74 9 4.19% 91.63% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 92.09% # number of syscalls executed -system.cpu0.kern.syscall::90 1 0.47% 92.56% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.26% 95.81% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.93% 96.74% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.93% 97.67% # number of syscalls executed -system.cpu0.kern.syscall::132 2 0.93% 98.60% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.07% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 215 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.646790 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.785409 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed +system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 225 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 255 0.15% 0.15% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.15% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3502 2.05% 2.20% # number of callpals executed -system.cpu0.kern.callpal::tbi 43 0.03% 2.23% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.23% # number of callpals executed -system.cpu0.kern.callpal::swpipl 155594 91.14% 93.38% # number of callpals executed -system.cpu0.kern.callpal::rdps 6351 3.72% 97.10% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::rti 4450 2.61% 99.71% # number of callpals executed -system.cpu0.kern.callpal::callsys 347 0.20% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 148 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 170714 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6908 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1181 # number of protection mode switches +system.cpu0.kern.callpal::wripir 104 0.08% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.09% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.09% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.09% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2293 1.85% 1.93% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.04% 1.97% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.01% 1.98% # number of callpals executed +system.cpu0.kern.callpal::swpipl 110963 89.30% 91.28% # number of callpals executed +system.cpu0.kern.callpal::rdps 6296 5.07% 96.35% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.35% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.35% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.36% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.36% # number of callpals executed +system.cpu0.kern.callpal::rti 4002 3.22% 99.58% # number of callpals executed +system.cpu0.kern.callpal::callsys 382 0.31% 99.89% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.11% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 124254 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5723 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1342 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1181 -system.cpu0.kern.mode_good::user 1181 +system.cpu0.kern.mode_good::kernel 1341 +system.cpu0.kern.mode_good::user 1342 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.170961 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.234318 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.292001 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1901823094000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1927479500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.379759 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1905987592000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1991648000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3503 # number of times the context was actually changed +system.cpu0.kern.swap_context 2294 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2448 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 54000 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 16487 36.42% 36.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1922 4.25% 40.66% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 255 0.56% 41.23% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 26607 58.77% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 45271 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16178 47.20% 47.20% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1922 5.61% 52.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 255 0.74% 53.55% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 15923 46.45% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 34278 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1872287559000 98.31% 98.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533777500 0.03% 98.34% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 116465000 0.01% 98.35% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 31498958000 1.65% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1904436759500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981258 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3855 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 98215 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 36112 40.36% 40.36% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 2.15% 42.52% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 104 0.12% 42.63% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 51325 57.37% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 89466 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 35322 48.67% 48.67% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 2.65% 51.33% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 104 0.14% 51.47% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 35218 48.53% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 72569 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870768654000 98.07% 98.07% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 540231000 0.03% 98.10% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 48911000 0.00% 98.10% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 36277143500 1.90% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1907634939500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.978124 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.598452 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.757173 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 2 1.80% 1.80% # number of syscalls executed -system.cpu1.kern.syscall::3 12 10.81% 12.61% # number of syscalls executed -system.cpu1.kern.syscall::4 1 0.90% 13.51% # number of syscalls executed -system.cpu1.kern.syscall::6 13 11.71% 25.23% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.41% 30.63% # number of syscalls executed -system.cpu1.kern.syscall::19 4 3.60% 34.23% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.80% 36.04% # number of syscalls executed -system.cpu1.kern.syscall::23 2 1.80% 37.84% # number of syscalls executed -system.cpu1.kern.syscall::24 2 1.80% 39.64% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.60% 43.24% # number of syscalls executed -system.cpu1.kern.syscall::45 19 17.12% 60.36% # number of syscalls executed -system.cpu1.kern.syscall::47 2 1.80% 62.16% # number of syscalls executed -system.cpu1.kern.syscall::48 3 2.70% 64.86% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.90% 65.77% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.80% 67.57% # number of syscalls executed -system.cpu1.kern.syscall::71 22 19.82% 87.39% # number of syscalls executed -system.cpu1.kern.syscall::74 7 6.31% 93.69% # number of syscalls executed -system.cpu1.kern.syscall::90 2 1.80% 95.50% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.80% 97.30% # number of syscalls executed -system.cpu1.kern.syscall::132 2 1.80% 99.10% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.90% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 111 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.686176 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.811135 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed +system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed +system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 101 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 154 0.33% 0.33% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.33% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1023 2.18% 2.52% # number of callpals executed -system.cpu1.kern.callpal::tbi 10 0.02% 2.54% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.55% # number of callpals executed -system.cpu1.kern.callpal::swpipl 40053 85.39% 87.95% # number of callpals executed -system.cpu1.kern.callpal::rdps 2403 5.12% 93.07% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.07% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.08% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.00% 93.08% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.09% # number of callpals executed -system.cpu1.kern.callpal::rti 3040 6.48% 99.57% # number of callpals executed -system.cpu1.kern.callpal::callsys 168 0.36% 99.93% # number of callpals executed -system.cpu1.kern.callpal::imb 32 0.07% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1949 2.12% 2.14% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 2.14% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.15% # number of callpals executed +system.cpu1.kern.callpal::swpipl 84230 91.49% 93.64% # number of callpals executed +system.cpu1.kern.callpal::rdps 2466 2.68% 96.32% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 96.32% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.00% 96.32% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 96.33% # number of callpals executed +system.cpu1.kern.callpal::rti 3206 3.48% 99.81% # number of callpals executed +system.cpu1.kern.callpal::callsys 133 0.14% 99.95% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.05% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 46904 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1413 # number of protection mode switches -system.cpu1.kern.mode_switch::user 554 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2352 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 733 -system.cpu1.kern.mode_good::user 554 -system.cpu1.kern.mode_good::idle 179 -system.cpu1.kern.mode_switch_good::kernel 0.518754 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 92064 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2331 # number of protection mode switches +system.cpu1.kern.mode_switch::user 395 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 461 +system.cpu1.kern.mode_good::user 395 +system.cpu1.kern.mode_good::idle 66 +system.cpu1.kern.mode_switch_good::kernel 0.197769 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.076105 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.339430 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4023798000 0.21% 0.21% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 775821000 0.04% 0.25% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1899637132500 99.75% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1024 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.032132 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.192887 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 42837305000 2.25% 2.25% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 697376000 0.04% 2.28% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1863790118000 97.72% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1950 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 038a204b1..156f5647f 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.861006 # Number of seconds simulated -sim_ticks 1861005569500 # Number of ticks simulated -final_tick 1861005569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.861005 # Number of seconds simulated +sim_ticks 1861005347500 # Number of ticks simulated +final_tick 1861005347500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152837 # Simulator instruction rate (inst/s) -host_op_rate 152837 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5373256396 # Simulator tick rate (ticks/s) -host_mem_usage 376300 # Number of bytes of host memory used -host_seconds 346.35 # Real time elapsed on the host -sim_insts 52934565 # Number of instructions simulated -sim_ops 52934565 # Number of ops (including micro ops) simulated +host_inst_rate 149955 # Simulator instruction rate (inst/s) +host_op_rate 149955 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5267476367 # Simulator tick rate (ticks/s) +host_mem_usage 376564 # Number of bytes of host memory used +host_seconds 353.30 # Real time elapsed on the host +sim_insts 52979113 # Number of instructions simulated +sim_ops 52979113 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 968000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24876864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 965824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879488 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25845824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 968000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 968000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7517248 # Number of bytes written to this memory -system.physmem.bytes_written::total 7517248 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15125 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388701 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25846272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 965824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 965824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7524416 # Number of bytes written to this memory +system.physmem.bytes_written::total 7524416 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15091 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388742 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403841 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117457 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117457 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520149 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13367431 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403848 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117569 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117569 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518980 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13368843 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13888096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520149 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520149 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4039347 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4039347 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4039347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13367431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13888338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518980 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518980 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4043200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4043200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4043200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518980 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13368843 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17927443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403841 # Number of read requests accepted -system.physmem.writeReqs 159009 # Number of write requests accepted -system.physmem.readBursts 403841 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159009 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bw_total::total 17931538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403848 # Number of read requests accepted +system.physmem.writeReqs 117569 # Number of write requests accepted +system.physmem.readBursts 403848 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117569 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 25839488 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue -system.physmem.bytesWritten 8519424 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25845824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10176576 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 25870 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 189 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25748 # Per bank write bursts -system.physmem.perBankRdBursts::1 25559 # Per bank write bursts -system.physmem.perBankRdBursts::2 25508 # Per bank write bursts -system.physmem.perBankRdBursts::3 25346 # Per bank write bursts -system.physmem.perBankRdBursts::4 25393 # Per bank write bursts -system.physmem.perBankRdBursts::5 24806 # Per bank write bursts -system.physmem.perBankRdBursts::6 25027 # Per bank write bursts -system.physmem.perBankRdBursts::7 25127 # Per bank write bursts -system.physmem.perBankRdBursts::8 24925 # Per bank write bursts -system.physmem.perBankRdBursts::9 25034 # Per bank write bursts -system.physmem.perBankRdBursts::10 25436 # Per bank write bursts -system.physmem.perBankRdBursts::11 24774 # Per bank write bursts -system.physmem.perBankRdBursts::12 24551 # Per bank write bursts -system.physmem.perBankRdBursts::13 25233 # Per bank write bursts -system.physmem.perBankRdBursts::14 25663 # Per bank write bursts -system.physmem.perBankRdBursts::15 25612 # Per bank write bursts -system.physmem.perBankWrBursts::0 9148 # Per bank write bursts -system.physmem.perBankWrBursts::1 8514 # Per bank write bursts -system.physmem.perBankWrBursts::2 8998 # Per bank write bursts -system.physmem.perBankWrBursts::3 8298 # Per bank write bursts -system.physmem.perBankWrBursts::4 8214 # Per bank write bursts -system.physmem.perBankWrBursts::5 7705 # Per bank write bursts -system.physmem.perBankWrBursts::6 7696 # Per bank write bursts -system.physmem.perBankWrBursts::7 7707 # Per bank write bursts -system.physmem.perBankWrBursts::8 8055 # Per bank write bursts -system.physmem.perBankWrBursts::9 7602 # Per bank write bursts -system.physmem.perBankWrBursts::10 8149 # Per bank write bursts -system.physmem.perBankWrBursts::11 7799 # Per bank write bursts -system.physmem.perBankWrBursts::12 8377 # Per bank write bursts -system.physmem.perBankWrBursts::13 9062 # Per bank write bursts -system.physmem.perBankWrBursts::14 8903 # Per bank write bursts -system.physmem.perBankWrBursts::15 8889 # Per bank write bursts +system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue +system.physmem.bytesWritten 7523328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25846272 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7524416 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 41759 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25651 # Per bank write bursts +system.physmem.perBankRdBursts::1 25422 # Per bank write bursts +system.physmem.perBankRdBursts::2 25567 # Per bank write bursts +system.physmem.perBankRdBursts::3 25497 # Per bank write bursts +system.physmem.perBankRdBursts::4 25384 # Per bank write bursts +system.physmem.perBankRdBursts::5 24734 # Per bank write bursts +system.physmem.perBankRdBursts::6 24943 # Per bank write bursts +system.physmem.perBankRdBursts::7 25079 # Per bank write bursts +system.physmem.perBankRdBursts::8 24928 # Per bank write bursts +system.physmem.perBankRdBursts::9 25027 # Per bank write bursts +system.physmem.perBankRdBursts::10 25572 # Per bank write bursts +system.physmem.perBankRdBursts::11 24872 # Per bank write bursts +system.physmem.perBankRdBursts::12 24489 # Per bank write bursts +system.physmem.perBankRdBursts::13 25240 # Per bank write bursts +system.physmem.perBankRdBursts::14 25741 # Per bank write bursts +system.physmem.perBankRdBursts::15 25596 # Per bank write bursts +system.physmem.perBankWrBursts::0 7944 # Per bank write bursts +system.physmem.perBankWrBursts::1 7514 # Per bank write bursts +system.physmem.perBankWrBursts::2 7965 # Per bank write bursts +system.physmem.perBankWrBursts::3 7518 # Per bank write bursts +system.physmem.perBankWrBursts::4 7330 # Per bank write bursts +system.physmem.perBankWrBursts::5 6666 # Per bank write bursts +system.physmem.perBankWrBursts::6 6776 # Per bank write bursts +system.physmem.perBankWrBursts::7 6716 # Per bank write bursts +system.physmem.perBankWrBursts::8 7141 # Per bank write bursts +system.physmem.perBankWrBursts::9 6711 # Per bank write bursts +system.physmem.perBankWrBursts::10 7422 # Per bank write bursts +system.physmem.perBankWrBursts::11 6968 # Per bank write bursts +system.physmem.perBankWrBursts::12 7145 # Per bank write bursts +system.physmem.perBankWrBursts::13 7857 # Per bank write bursts +system.physmem.perBankWrBursts::14 8054 # Per bank write bursts +system.physmem.perBankWrBursts::15 7825 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 85 # Number of times write queue was full causing retry -system.physmem.totGap 1861000236500 # Total gap between requests +system.physmem.numWrRetry 23 # Number of times write queue was full causing retry +system.physmem.totGap 1860999975500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403841 # Read request sizes (log2) +system.physmem.readPktSize::6 403848 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 159009 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 36627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117569 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -148,199 +148,190 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 323 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62685 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 548.114030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 339.010384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.134053 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13424 21.42% 21.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10425 16.63% 38.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5386 8.59% 46.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2710 4.32% 50.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2462 3.93% 54.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1644 2.62% 57.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1512 2.41% 59.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1300 2.07% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23822 38.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62685 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4847 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 83.295234 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3032.862596 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 4844 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 41 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61779 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 540.028683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 331.823835 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.833229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13638 22.08% 22.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10412 16.85% 38.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4989 8.08% 47.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3229 5.23% 52.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2263 3.66% 55.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1516 2.45% 58.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1526 2.47% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1289 2.09% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22917 37.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61779 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5213 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.447919 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2924.392219 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5210 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4847 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4847 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.463586 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.516932 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 62.014286 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 4601 94.92% 94.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 56 1.16% 96.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 4 0.08% 96.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 1 0.02% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 13 0.27% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 3 0.06% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 3 0.06% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 6 0.12% 96.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 21 0.43% 97.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 18 0.37% 97.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 8 0.17% 97.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 12 0.25% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 2 0.04% 97.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 4 0.08% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 1 0.02% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 2 0.04% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 5 0.10% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 17 0.35% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 13 0.27% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 3 0.06% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 11 0.23% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 4 0.08% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 2 0.04% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 2 0.04% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 4 0.08% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 4 0.08% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 4 0.08% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.04% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.04% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 8 0.17% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 2 0.04% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::624-639 2 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 2 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::656-671 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4847 # Writes before turning the bus around for reads -system.physmem.totQLat 3741904500 # Total ticks spent queuing -system.physmem.totMemAccLat 11312067000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.rdPerTurnAround::total 5213 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5213 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.549779 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.928650 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.456391 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4618 88.59% 88.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 208 3.99% 92.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 74 1.42% 94.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 17 0.33% 94.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 8 0.15% 94.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 5 0.10% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 10 0.19% 94.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 10 0.19% 94.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 7 0.13% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 32 0.61% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 168 3.22% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 10 0.19% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.04% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.10% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 2 0.04% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.06% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 2 0.04% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.10% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 3 0.06% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 4 0.08% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 12 0.23% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5213 # Writes before turning the bus around for reads +system.physmem.totQLat 3805918000 # Total ticks spent queuing +system.physmem.totMemAccLat 11376080500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2018710000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9268.06 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9426.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28018.06 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28176.61 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.58 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.47 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.77 # Average write queue length when enqueuing -system.physmem.readRowHits 364326 # Number of row buffer hits during reads -system.physmem.writeRowHits 109846 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.50 # Row buffer hit rate for writes -system.physmem.avgGap 3306387.56 # Average gap between requests -system.physmem.pageHitRate 88.32 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 235516680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 128506125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1579609200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 429494400 # Energy for write commands per rank (pJ) +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.30 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing +system.physmem.readRowHits 364169 # Number of row buffer hits during reads +system.physmem.writeRowHits 95345 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.10 # Row buffer hit rate for writes +system.physmem.avgGap 3569120.25 # Average gap between requests +system.physmem.pageHitRate 88.15 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 232515360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 126868500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577760600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 378619920 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 56182721175 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1067316698250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1247423979990 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.297807 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1775410357162 # Time in different power states +system.physmem_0.actBackEnergy 56250477360 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1067257263000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1247374938900 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.271455 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1775312455750 # Time in different power states system.physmem_0.memoryStateTime::REF 62142860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23446441588 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23544343000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 238381920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 130069500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1569531600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 433097280 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 234533880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 127969875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1571380200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 383117040 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 56034129015 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1067447050500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1247403693975 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.286901 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1775626000168 # Time in different power states +system.physmem_1.actBackEnergy 55982569095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1067492278500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1247343282750 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.254439 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1775708219250 # Time in different power states system.physmem_1.memoryStateTime::REF 62142860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23231077332 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23148593250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17721924 # Number of BP lookups -system.cpu.branchPred.condPredicted 15403228 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 380344 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11703979 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5913014 # Number of BTB hits +system.cpu.branchPred.lookups 17721018 # Number of BP lookups +system.cpu.branchPred.condPredicted 15408782 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 378784 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12470436 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5897235 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.521400 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 923784 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21447 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 47.289726 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 918220 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21032 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10269214 # DTB read hits -system.cpu.dtb.read_misses 41261 # DTB read misses -system.cpu.dtb.read_acv 507 # DTB read access violations -system.cpu.dtb.read_accesses 967301 # DTB read accesses -system.cpu.dtb.write_hits 6648637 # DTB write hits -system.cpu.dtb.write_misses 9303 # DTB write misses -system.cpu.dtb.write_acv 402 # DTB write access violations -system.cpu.dtb.write_accesses 342644 # DTB write accesses -system.cpu.dtb.data_hits 16917851 # DTB hits -system.cpu.dtb.data_misses 50564 # DTB misses -system.cpu.dtb.data_acv 909 # DTB access violations -system.cpu.dtb.data_accesses 1309945 # DTB accesses -system.cpu.itb.fetch_hits 1769158 # ITB hits -system.cpu.itb.fetch_misses 36068 # ITB misses -system.cpu.itb.fetch_acv 660 # ITB acv -system.cpu.itb.fetch_accesses 1805226 # ITB accesses +system.cpu.dtb.read_hits 10294388 # DTB read hits +system.cpu.dtb.read_misses 42024 # DTB read misses +system.cpu.dtb.read_acv 506 # DTB read access violations +system.cpu.dtb.read_accesses 968687 # DTB read accesses +system.cpu.dtb.write_hits 6648521 # DTB write hits +system.cpu.dtb.write_misses 9456 # DTB write misses +system.cpu.dtb.write_acv 408 # DTB write access violations +system.cpu.dtb.write_accesses 343243 # DTB write accesses +system.cpu.dtb.data_hits 16942909 # DTB hits +system.cpu.dtb.data_misses 51480 # DTB misses +system.cpu.dtb.data_acv 914 # DTB access violations +system.cpu.dtb.data_accesses 1311930 # DTB accesses +system.cpu.itb.fetch_hits 1769476 # ITB hits +system.cpu.itb.fetch_misses 36155 # ITB misses +system.cpu.itb.fetch_acv 662 # ITB acv +system.cpu.itb.fetch_accesses 1805631 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -353,258 +344,258 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 122572361 # number of cpu cycles simulated +system.cpu.numCycles 122272854 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29541441 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78093998 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17721924 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6836798 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 84630340 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1254210 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1349 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 26888 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1745325 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 441267 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9051182 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 273719 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 117014009 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.667390 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.979034 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29542399 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 77951342 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17721018 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6815455 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 84318662 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1251172 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1032 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27002 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1751503 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 450615 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 220 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9037094 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 274713 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116717019 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.667866 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.979948 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 102427448 87.53% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 934169 0.80% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1984138 1.70% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 910061 0.78% 90.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2793690 2.39% 93.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 647956 0.55% 93.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 739168 0.63% 94.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1007210 0.86% 95.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5570169 4.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 102159840 87.53% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 935001 0.80% 88.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1975635 1.69% 90.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 907890 0.78% 90.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2798283 2.40% 93.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 634657 0.54% 93.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 731012 0.63% 94.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1008696 0.86% 95.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5566005 4.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 117014009 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.144583 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.637126 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24038562 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 80987042 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9497307 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1906242 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 584855 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 586733 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42672 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68295720 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 134238 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 584855 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24961940 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 51456440 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20841952 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10391328 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8777492 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65857652 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 204161 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2078785 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 153522 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4578470 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43917673 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79850033 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79669145 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168436 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38142428 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5775237 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1690640 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 240974 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13460579 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10430513 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6961741 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1496363 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1107333 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58622970 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2136022 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57539781 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 62715 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7824422 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3554737 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1474907 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 117014009 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.491734 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.229968 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 116717019 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.144930 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.637520 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24051579 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 80690981 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9487535 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1903773 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 583150 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 586842 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42848 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68182155 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 134674 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 583150 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24974215 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50913599 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20868972 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10381558 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8995523 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65764072 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 201455 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2078667 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 157006 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4811107 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43858088 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79749030 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79568293 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168286 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38179356 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5678724 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1691117 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 241700 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13523739 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10414999 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6951257 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1489090 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1076371 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58557437 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2137330 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57550552 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 58383 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7715649 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3482179 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1476201 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116717019 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.493078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.231262 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 93391037 79.81% 79.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10179390 8.70% 88.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4310458 3.68% 92.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3008329 2.57% 94.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3082993 2.63% 97.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1515380 1.30% 98.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1001151 0.86% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 403458 0.34% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 121813 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 93076852 79.75% 79.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10193735 8.73% 88.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4312708 3.70% 92.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3021195 2.59% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3081764 2.64% 97.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1495449 1.28% 98.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1007889 0.86% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 403235 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124192 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 117014009 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116717019 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 210088 18.84% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 537781 48.22% 67.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 367354 32.94% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 208462 18.43% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547266 48.38% 66.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 375475 33.19% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39070075 67.90% 67.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61902 0.11% 68.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38396 0.07% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10678994 18.56% 86.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6730550 11.70% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 948942 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39056911 67.87% 67.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61891 0.11% 67.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38552 0.07% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10704988 18.60% 86.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6728388 11.69% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948900 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57539781 # Type of FU issued -system.cpu.iq.rate 0.469435 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1115223 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019382 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 232558248 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68266797 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55883323 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 713260 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336497 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 329169 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58264569 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 383149 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 636979 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57550552 # Type of FU issued +system.cpu.iq.rate 0.470673 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1131203 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019656 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 232294841 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68093775 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55871823 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 712867 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336544 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 329026 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58291729 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 382740 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 634925 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1345105 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3404 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20302 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 587155 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1322411 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3516 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20331 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 573217 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18243 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 442853 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18302 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 483316 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 584855 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 48003305 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1105875 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64465821 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 144286 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10430513 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6961741 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1886655 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 45598 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 856452 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20302 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 189944 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 410798 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 600742 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56947023 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10338131 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 592757 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 583150 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 47678109 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 871068 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64398227 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 142430 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10414999 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6951257 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1888726 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 44438 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 623782 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20331 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 186400 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411798 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 598198 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56961347 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10364061 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 589204 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3706829 # number of nop insts executed -system.cpu.iew.exec_refs 17011176 # number of memory reference insts executed -system.cpu.iew.exec_branches 8976912 # Number of branches executed -system.cpu.iew.exec_stores 6673045 # Number of stores executed -system.cpu.iew.exec_rate 0.464599 # Inst execution rate -system.cpu.iew.wb_sent 56353404 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56212492 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28792537 # num instructions producing a value -system.cpu.iew.wb_consumers 40027235 # num instructions consuming a value +system.cpu.iew.exec_nop 3703460 # number of nop insts executed +system.cpu.iew.exec_refs 17037134 # number of memory reference insts executed +system.cpu.iew.exec_branches 8968929 # Number of branches executed +system.cpu.iew.exec_stores 6673073 # Number of stores executed +system.cpu.iew.exec_rate 0.465854 # Inst execution rate +system.cpu.iew.wb_sent 56337909 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56200849 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28756133 # num instructions producing a value +system.cpu.iew.wb_consumers 39912635 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.458607 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.719324 # average fanout of values written-back +system.cpu.iew.wb_rate 0.459635 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.720477 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8228560 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661115 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 549076 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 115576332 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.485596 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.428292 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8112704 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661129 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 547326 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 115294268 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.487187 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.430320 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 95814381 82.90% 82.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7848857 6.79% 89.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4272055 3.70% 93.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2211253 1.91% 95.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1764306 1.53% 96.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 615369 0.53% 97.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 473669 0.41% 97.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 490996 0.42% 98.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2085446 1.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 95501177 82.83% 82.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7867272 6.82% 89.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4280982 3.71% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2233083 1.94% 95.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1745854 1.51% 96.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 611445 0.53% 97.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 482985 0.42% 97.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 468960 0.41% 98.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2102510 1.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 115576332 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56123349 # Number of instructions committed -system.cpu.commit.committedOps 56123349 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 115294268 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56169836 # Number of instructions committed +system.cpu.commit.committedOps 56169836 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15459994 # Number of memory references committed -system.cpu.commit.loads 9085408 # Number of loads committed -system.cpu.commit.membars 226308 # Number of memory barriers committed -system.cpu.commit.branches 8435685 # Number of branches committed -system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. -system.cpu.commit.int_insts 51974864 # Number of committed integer instructions. -system.cpu.commit.function_calls 740049 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3196057 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36183700 64.47% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60673 0.11% 70.27% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.34% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.34% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.34% # Class of committed instruction +system.cpu.commit.refs 15470628 # Number of memory references committed +system.cpu.commit.loads 9092588 # Number of loads committed +system.cpu.commit.membars 226333 # Number of memory barriers committed +system.cpu.commit.branches 8440353 # Number of branches committed +system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. +system.cpu.commit.int_insts 52019375 # Number of committed integer instructions. +system.cpu.commit.function_calls 740552 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3197996 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36217639 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60667 0.11% 70.28% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction @@ -627,411 +618,417 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9311716 16.59% 86.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6380538 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 948942 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9318921 16.59% 86.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6383992 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 948900 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction -system.cpu.commit.bw_lim_events 2085446 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 177593268 # The number of ROB reads -system.cpu.rob.rob_writes 130137832 # The number of ROB writes -system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5558352 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599438779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52934565 # Number of Instructions Simulated -system.cpu.committedOps 52934565 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.315545 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.315545 # CPI: Total CPI of All Threads -system.cpu.ipc 0.431864 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.431864 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74599299 # number of integer regfile reads -system.cpu.int_regfile_writes 40560409 # number of integer regfile writes -system.cpu.fp_regfile_reads 167171 # number of floating regfile reads -system.cpu.fp_regfile_writes 167579 # number of floating regfile writes -system.cpu.misc_regfile_reads 2029670 # number of misc regfile reads -system.cpu.misc_regfile_writes 939349 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1403663 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994456 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11858482 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1404175 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.445160 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 26416000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994456 # Average occupied blocks per requestor +system.cpu.commit.op_class_0::total 56169836 # Class of committed instruction +system.cpu.commit.bw_lim_events 2102510 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 177224791 # The number of ROB reads +system.cpu.rob.rob_writes 129983616 # The number of ROB writes +system.cpu.timesIdled 573073 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5555835 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599737842 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52979113 # Number of Instructions Simulated +system.cpu.committedOps 52979113 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.307945 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.307945 # CPI: Total CPI of All Threads +system.cpu.ipc 0.433286 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.433286 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74622251 # number of integer regfile reads +system.cpu.int_regfile_writes 40551917 # number of integer regfile writes +system.cpu.fp_regfile_reads 167069 # number of floating regfile reads +system.cpu.fp_regfile_writes 167545 # number of floating regfile writes +system.cpu.misc_regfile_reads 2028916 # number of misc regfile reads +system.cpu.misc_regfile_writes 939321 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1404299 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994455 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11844191 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1404811 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.431163 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 26393500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994455 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 413 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 412 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63936372 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63936372 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7267066 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7267066 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4189300 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4189300 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186111 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186111 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215710 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215710 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11456366 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11456366 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11456366 # number of overall hits -system.cpu.dcache.overall_hits::total 11456366 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1796718 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1796718 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1954848 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1954848 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23269 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23269 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 27 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 27 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3751566 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3751566 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3751566 # number of overall misses -system.cpu.dcache.overall_misses::total 3751566 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 41841354315 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 41841354315 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890725520 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 80890725520 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376182249 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 376182249 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 455005 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 455005 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 122732079835 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 122732079835 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 122732079835 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 122732079835 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9063784 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9063784 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6144148 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6144148 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209380 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209380 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215737 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215737 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15207932 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15207932 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15207932 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15207932 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198230 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.198230 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318164 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.318164 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111133 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111133 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000125 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000125 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.246685 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.246685 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.246685 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.246685 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23287.658005 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23287.658005 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.547423 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.547423 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16166.670205 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16166.670205 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16852.037037 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16852.037037 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.892883 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32714.892883 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.892883 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32714.892883 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4477894 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2036 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 123579 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.235072 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 88.521739 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 63926076 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63926076 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7252822 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7252822 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4188714 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4188714 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186644 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186644 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215706 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215706 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11441536 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11441536 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11441536 # number of overall hits +system.cpu.dcache.overall_hits::total 11441536 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1804157 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1804157 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1958890 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1958890 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23354 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23354 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 29 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3763047 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3763047 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3763047 # number of overall misses +system.cpu.dcache.overall_misses::total 3763047 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 41750233000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 41750233000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 80527676066 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 80527676066 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 377889000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 377889000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 498500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 498500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 122277909066 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 122277909066 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 122277909066 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 122277909066 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9056979 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9056979 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147604 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147604 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209998 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209998 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215735 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215735 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15204583 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15204583 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15204583 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15204583 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199201 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.199201 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318643 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318643 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111211 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111211 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000134 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000134 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247494 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247494 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247494 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247494 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23141.130733 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23141.130733 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41108.830034 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41108.830034 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16180.911193 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16180.911193 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 17189.655172 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 17189.655172 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32494.387943 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32494.387943 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32494.387943 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32494.387943 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4529793 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2677 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 135335 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 25 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.470965 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 107.080000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 842087 # number of writebacks -system.cpu.dcache.writebacks::total 842087 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 701160 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 701160 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664055 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1664055 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5272 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5272 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2365215 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2365215 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2365215 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2365215 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1095558 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1095558 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290793 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 290793 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17997 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17997 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 27 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 27 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1386351 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1386351 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1386351 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1386351 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 842762 # number of writebacks +system.cpu.dcache.writebacks::total 842762 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 708195 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 708195 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1668077 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1668077 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5151 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5151 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2376272 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2376272 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2376272 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2376272 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1095962 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1095962 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290813 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 290813 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18203 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 18203 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 29 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 29 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1386775 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1386775 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1386775 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1386775 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9597 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9597 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16527 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16527 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29996933023 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29996933023 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12482529124 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12482529124 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214354001 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214354001 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 414495 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 414495 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42479462147 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 42479462147 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42479462147 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 42479462147 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433706500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433706500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011966000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011966000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3445672500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3445672500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120872 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120872 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047328 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047328 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085954 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085954 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000125 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000125 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091160 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091160 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091160 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091160 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27380.506576 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27380.506576 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42925.823950 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42925.823950 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11910.540701 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.540701 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 15351.666667 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 15351.666667 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30641.202803 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30641.202803 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30641.202803 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30641.202803 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206884.054834 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206884.054834 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209645.305825 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209645.305825 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208487.475041 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208487.475041 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30575992000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30575992000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12635842717 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12635842717 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 226273500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 226273500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 469500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 469500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43211834717 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 43211834717 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43211834717 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 43211834717 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1451037500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1451037500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2035928998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2035928998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3486966498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3486966498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121007 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121007 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047305 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047305 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086682 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086682 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000134 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000134 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091208 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091208 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091208 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091208 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27898.770213 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27898.770213 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43450.061438 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43450.061438 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12430.560897 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12430.560897 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16189.655172 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16189.655172 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31159.946435 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31159.946435 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31159.946435 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31159.946435 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209384.920635 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209384.920635 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212142.231739 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212142.231739 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 210986.053004 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 210986.053004 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1032757 # number of replacements -system.cpu.icache.tags.tagsinuse 509.197301 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7965141 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1033265 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.708711 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 28360334250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.197301 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994526 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994526 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1035158 # number of replacements +system.cpu.icache.tags.tagsinuse 509.238634 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7947846 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1035666 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.674140 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 28148361500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.238634 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994607 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994607 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 304 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10084699 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10084699 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7965142 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7965142 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7965142 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7965142 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7965142 # number of overall hits -system.cpu.icache.overall_hits::total 7965142 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1086038 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1086038 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1086038 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1086038 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1086038 # number of overall misses -system.cpu.icache.overall_misses::total 1086038 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15222356868 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15222356868 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15222356868 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15222356868 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15222356868 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15222356868 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9051180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9051180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9051180 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9051180 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9051180 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9051180 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119989 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.119989 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.119989 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.119989 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.119989 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.119989 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14016.412748 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14016.412748 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14016.412748 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14016.412748 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14016.412748 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14016.412748 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5848 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10073023 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10073023 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7947847 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7947847 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7947847 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7947847 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7947847 # number of overall hits +system.cpu.icache.overall_hits::total 7947847 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1089244 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1089244 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1089244 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9037091 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9037091 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9037091 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9037091 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120530 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.120530 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.120530 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.120530 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.120530 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.120530 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13976.503881 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26417263500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27523341500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1364412500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1364412500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1925547500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1925547500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3289960000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3289960000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.646341 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.646341 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.206897 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.206897 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382611 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382611 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014571 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014571 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248213 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248213 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014571 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277067 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.165671 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014571 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277067 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.165671 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 23594.339623 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 23594.339623 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 20750 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20750 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79278.696764 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79278.696764 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73289.027299 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73289.027299 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63057.724049 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63057.724049 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73289.027299 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67866.912352 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68069.291418 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73289.027299 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67866.912352 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68069.291418 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196884.920635 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196884.920635 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200640.564760 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200640.564760 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199065.771162 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199065.771162 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2143279 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2143168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2146205 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 842087 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41601 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 106 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 301613 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301613 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 94 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2066871 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3684049 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5750920 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66134528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143814956 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 209949484 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 42097 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3338284 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012514 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.111162 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::Writeback 960354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1857372 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 82 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1035932 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1103445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 85 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3106451 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4246137 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7352588 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66287680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143898860 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 210186540 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422109 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5318690 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.079299 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.270205 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3296510 98.75% 98.75% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41774 1.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4896924 92.07% 92.07% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 421766 7.93% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3338284 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2495140999 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 5318690 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3296022500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1554402947 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1555343104 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2190379636 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2119169250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1180,8 +1188,7 @@ system.disk2.dma_write_txs 1 # Nu system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51149 # Transaction distribution -system.iobus.trans_dist::WriteResp 9597 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.trans_dist::WriteResp 51149 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) @@ -1236,21 +1243,21 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 242053963 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216065006 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42024003 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.259192 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.259177 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1711311066000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.259192 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 1711311931000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.259177 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.078699 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.078699 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1260,49 +1267,49 @@ system.iocache.tags.tag_accesses 375525 # Nu system.iocache.tags.data_accesses 375525 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21719383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21719383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8765491577 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8765491577 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21719383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21719383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21719383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21719383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21637883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21637883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4909206123 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4909206123 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21637883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21637883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21637883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21637883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125545.566474 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125545.566474 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210952.338684 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 210952.338684 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125545.566474 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125545.566474 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125545.566474 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125545.566474 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 73146 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125074.468208 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125074.468208 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118146.084978 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118146.084978 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125074.468208 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125074.468208 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125074.468208 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10015 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.303645 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1310,84 +1317,86 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12567383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12567383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6604781583 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6604781583 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12567383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12567383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12567383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12567383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12987883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12987883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2831606123 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2831606123 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12987883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12987883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12987883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12987883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72643.832370 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158952.194431 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158952.194431 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72643.832370 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72643.832370 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75074.468208 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68146.084978 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68146.084978 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75074.468208 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75074.468208 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296160 # Transaction distribution -system.membus.trans_dist::ReadResp 296066 # Transaction distribution +system.membus.trans_dist::ReadReq 6930 # Transaction distribution +system.membus.trans_dist::ReadResp 295956 # Transaction distribution system.membus.trans_dist::WriteReq 9597 # Transaction distribution system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117457 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 187 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.membus.trans_dist::UpgradeResp 192 # Transaction distribution -system.membus.trans_dist::ReadExReq 115137 # Transaction distribution -system.membus.trans_dist::ReadExResp 115137 # Transaction distribution -system.membus.trans_dist::BadAddressError 94 # Transaction distribution +system.membus.trans_dist::Writeback 117569 # Transaction distribution +system.membus.trans_dist::CleanEvict 261797 # Transaction distribution +system.membus.trans_dist::UpgradeReq 204 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.membus.trans_dist::UpgradeResp 210 # Transaction distribution +system.membus.trans_dist::ReadExReq 115254 # Transaction distribution +system.membus.trans_dist::ReadExResp 115254 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289111 # Transaction distribution +system.membus.trans_dist::BadAddressError 85 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884252 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 188 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917494 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042298 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179422 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1304239 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30705344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30749484 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36066540 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30712960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30757100 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33414828 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 580180 # Request fanout histogram +system.membus.snoop_fanout::samples 842203 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 580180 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 842203 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 580180 # Request fanout histogram -system.membus.reqLayer0.occupancy 29181000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 842203 # Request fanout histogram +system.membus.reqLayer0.occupancy 29160500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1226050062 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1313577675 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 118000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 109500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2139458813 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2139558790 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 42497997 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 72030935 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1421,28 +1430,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6445 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 210982 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74654 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210978 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74652 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105549 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182213 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73287 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105547 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182209 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73285 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73287 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148584 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817355802000 97.65% 97.65% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 62075500 0.00% 97.66% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 532990500 0.03% 97.69% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 43053863500 2.31% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1861004731500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981689 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73285 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148580 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817522630000 97.66% 97.66% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 62579500 0.00% 97.67% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 533633500 0.03% 97.70% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 42885651500 2.30% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1861004494500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981688 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815441 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694335 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815437 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1478,11 +1487,11 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175098 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175094 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed @@ -1490,20 +1499,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191942 # number of callpals executed +system.cpu.kern.callpal::total 191938 # number of callpals executed system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1741 +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1907 +system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326667 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.325983 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394509 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29153631500 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2692582500 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1829158509500 98.29% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.393886 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29174464500 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2684090500 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1829145931500 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index e143de192..8b67c053c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841539 # Number of seconds simulated -sim_ticks 1841538755500 # Number of ticks simulated -final_tick 1841538755500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841548 # Number of seconds simulated +sim_ticks 1841548033500 # Number of ticks simulated +final_tick 1841548033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 221997 # Simulator instruction rate (inst/s) -host_op_rate 221997 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5796715531 # Simulator tick rate (ticks/s) -host_mem_usage 374488 # Number of bytes of host memory used -host_seconds 317.69 # Real time elapsed on the host -sim_insts 70525499 # Number of instructions simulated -sim_ops 70525499 # Number of ops (including micro ops) simulated +host_inst_rate 218310 # Simulator instruction rate (inst/s) +host_op_rate 218310 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5702515722 # Simulator tick rate (ticks/s) +host_mem_usage 375536 # Number of bytes of host memory used +host_seconds 322.94 # Real time elapsed on the host +sim_insts 70500110 # Number of instructions simulated +sim_ops 70500110 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 467648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20091072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2148032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 308096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2634304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 465600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20057408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2156416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 307456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2656704 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25797120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 467648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 308096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 922752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7481856 # Number of bytes written to this memory -system.physmem.bytes_written::total 7481856 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7307 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 313923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 33563 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4814 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41161 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25791680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 465600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 307456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 920192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7484672 # Number of bytes written to this memory +system.physmem.bytes_written::total 7484672 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7275 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 313397 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2299 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 33694 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4804 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41511 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403080 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116904 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116904 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 253944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10909937 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79829 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1166433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 167304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1430491 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 402995 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116948 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116948 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 252831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10891602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1170980 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 166955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1442647 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14008459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 253944 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 167304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 501077 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4062828 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4062828 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4062828 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 253944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10909937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1166433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 167304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1430491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 14005434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 252831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79898 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 166955 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 499684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4064337 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4064337 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4064337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 252831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10891602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1170980 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 166955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1442647 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18071287 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 81850 # Number of read requests accepted -system.physmem.writeReqs 64472 # Number of write requests accepted -system.physmem.readBursts 81850 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 64472 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5236928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1472 # Total number of bytes read from write queue -system.physmem.bytesWritten 3416192 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5238400 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4126208 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 23 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 11076 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 49 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 4878 # Per bank write bursts -system.physmem.perBankRdBursts::1 4919 # Per bank write bursts -system.physmem.perBankRdBursts::2 4947 # Per bank write bursts -system.physmem.perBankRdBursts::3 4947 # Per bank write bursts -system.physmem.perBankRdBursts::4 5010 # Per bank write bursts -system.physmem.perBankRdBursts::5 5136 # Per bank write bursts -system.physmem.perBankRdBursts::6 5318 # Per bank write bursts -system.physmem.perBankRdBursts::7 5111 # Per bank write bursts -system.physmem.perBankRdBursts::8 5349 # Per bank write bursts -system.physmem.perBankRdBursts::9 4830 # Per bank write bursts -system.physmem.perBankRdBursts::10 5530 # Per bank write bursts -system.physmem.perBankRdBursts::11 5119 # Per bank write bursts -system.physmem.perBankRdBursts::12 4880 # Per bank write bursts +system.physmem.bw_total::total 18069771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 82323 # Number of read requests accepted +system.physmem.writeReqs 47461 # Number of write requests accepted +system.physmem.readBursts 82323 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 47461 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5267264 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1408 # Total number of bytes read from write queue +system.physmem.bytesWritten 3035584 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5268672 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 3037504 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 22 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 17348 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 4998 # Per bank write bursts +system.physmem.perBankRdBursts::1 5047 # Per bank write bursts +system.physmem.perBankRdBursts::2 4951 # Per bank write bursts +system.physmem.perBankRdBursts::3 4902 # Per bank write bursts +system.physmem.perBankRdBursts::4 5135 # Per bank write bursts +system.physmem.perBankRdBursts::5 5137 # Per bank write bursts +system.physmem.perBankRdBursts::6 5321 # Per bank write bursts +system.physmem.perBankRdBursts::7 5238 # Per bank write bursts +system.physmem.perBankRdBursts::8 5355 # Per bank write bursts +system.physmem.perBankRdBursts::9 4827 # Per bank write bursts +system.physmem.perBankRdBursts::10 5539 # Per bank write bursts +system.physmem.perBankRdBursts::11 5124 # Per bank write bursts +system.physmem.perBankRdBursts::12 4881 # Per bank write bursts system.physmem.perBankRdBursts::13 5044 # Per bank write bursts -system.physmem.perBankRdBursts::14 5637 # Per bank write bursts -system.physmem.perBankRdBursts::15 5172 # Per bank write bursts -system.physmem.perBankWrBursts::0 3097 # Per bank write bursts -system.physmem.perBankWrBursts::1 3264 # Per bank write bursts -system.physmem.perBankWrBursts::2 3389 # Per bank write bursts -system.physmem.perBankWrBursts::3 3378 # Per bank write bursts -system.physmem.perBankWrBursts::4 3165 # Per bank write bursts -system.physmem.perBankWrBursts::5 3060 # Per bank write bursts -system.physmem.perBankWrBursts::6 3647 # Per bank write bursts -system.physmem.perBankWrBursts::7 3165 # Per bank write bursts -system.physmem.perBankWrBursts::8 3847 # Per bank write bursts -system.physmem.perBankWrBursts::9 3079 # Per bank write bursts -system.physmem.perBankWrBursts::10 3680 # Per bank write bursts -system.physmem.perBankWrBursts::11 3339 # Per bank write bursts -system.physmem.perBankWrBursts::12 2997 # Per bank write bursts -system.physmem.perBankWrBursts::13 3248 # Per bank write bursts -system.physmem.perBankWrBursts::14 3739 # Per bank write bursts -system.physmem.perBankWrBursts::15 3284 # Per bank write bursts +system.physmem.perBankRdBursts::14 5631 # Per bank write bursts +system.physmem.perBankRdBursts::15 5171 # Per bank write bursts +system.physmem.perBankWrBursts::0 2712 # Per bank write bursts +system.physmem.perBankWrBursts::1 2869 # Per bank write bursts +system.physmem.perBankWrBursts::2 2967 # Per bank write bursts +system.physmem.perBankWrBursts::3 2927 # Per bank write bursts +system.physmem.perBankWrBursts::4 2992 # Per bank write bursts +system.physmem.perBankWrBursts::5 2769 # Per bank write bursts +system.physmem.perBankWrBursts::6 3293 # Per bank write bursts +system.physmem.perBankWrBursts::7 2918 # Per bank write bursts +system.physmem.perBankWrBursts::8 3398 # Per bank write bursts +system.physmem.perBankWrBursts::9 2634 # Per bank write bursts +system.physmem.perBankWrBursts::10 3325 # Per bank write bursts +system.physmem.perBankWrBursts::11 2913 # Per bank write bursts +system.physmem.perBankWrBursts::12 2642 # Per bank write bursts +system.physmem.perBankWrBursts::13 2800 # Per bank write bursts +system.physmem.perBankWrBursts::14 3388 # Per bank write bursts +system.physmem.perBankWrBursts::15 2884 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 18 # Number of times write queue was full causing retry -system.physmem.totGap 1840526879500 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 1840536161000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 81850 # Read request sizes (log2) +system.physmem.readPktSize::6 82323 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 64472 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 63937 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7813 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.writePktSize::6 47461 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 64278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -153,9 +153,9 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see @@ -164,185 +164,194 @@ system.physmem.wrQLenPdf::7 39 # Wh system.physmem.wrQLenPdf::8 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 37 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 22135 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 390.924780 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 222.627349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 384.024543 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7145 32.28% 32.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4994 22.56% 54.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1972 8.91% 63.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1000 4.52% 68.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 834 3.77% 72.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 471 2.13% 74.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 534 2.41% 76.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 337 1.52% 78.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4848 21.90% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 22135 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 1909 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 42.863279 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1017.016663 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 1907 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 26 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21805 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 380.777253 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 217.097266 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 378.211296 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7203 33.03% 33.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4880 22.38% 55.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2010 9.22% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1038 4.76% 69.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 857 3.93% 73.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 538 2.47% 75.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 425 1.95% 77.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 372 1.71% 79.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4482 20.55% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21805 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2075 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 39.654458 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 980.113813 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2073 99.90% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 1909 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 1909 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.961236 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.965205 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 62.780578 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-15 45 2.36% 2.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 1768 92.61% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 14 0.73% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 2 0.10% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 2 0.10% 95.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 1 0.05% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 1 0.05% 96.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 2 0.10% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 11 0.58% 96.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 12 0.63% 97.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 5 0.26% 97.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 8 0.42% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 1 0.05% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 1 0.05% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 2 0.10% 98.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 2 0.10% 98.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 6 0.31% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 5 0.26% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 2 0.10% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 2 0.10% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.05% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 1 0.05% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.10% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 2 0.10% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.16% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 4 0.21% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::656-671 2 0.10% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 1909 # Writes before turning the bus around for reads -system.physmem.totQLat 884680000 # Total ticks spent queuing -system.physmem.totMemAccLat 2418936250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 409135000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10811.59 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2075 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2075 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.858313 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.353134 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.870235 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 34 1.64% 1.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.34% 1.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 2 0.10% 2.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 5 0.24% 2.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1736 83.66% 85.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 36 1.73% 87.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 80 3.86% 91.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 17 0.82% 92.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 12 0.58% 92.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 17 0.82% 93.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 5 0.24% 94.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 1 0.05% 94.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.05% 94.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.10% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 3 0.14% 94.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.05% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.19% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.05% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.10% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.05% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.14% 94.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 9 0.43% 95.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.19% 95.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 65 3.13% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.14% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.14% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.05% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 2 0.10% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.05% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.05% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.05% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.10% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.10% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.10% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.05% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 3 0.14% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.05% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 4 0.19% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2075 # Writes before turning the bus around for reads +system.physmem.totQLat 914891250 # Total ticks spent queuing +system.physmem.totMemAccLat 2458035000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 411505000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11116.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29561.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.24 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29866.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.86 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.65 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.86 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.65 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.99 # Average write queue length when enqueuing -system.physmem.readRowHits 70087 # Number of row buffer hits during reads -system.physmem.writeRowHits 42983 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.65 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.50 # Row buffer hit rate for writes -system.physmem.avgGap 12578606.63 # Average gap between requests -system.physmem.pageHitRate 83.62 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 81814320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 44558250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 314074800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 169549200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 35647575705 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 798651060750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 923964608865 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.989912 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1309028017250 # Time in different power states -system.physmem_0.memoryStateTime::REF 45529640000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 2.86 # Average write queue length when enqueuing +system.physmem.readRowHits 70476 # Number of row buffer hits during reads +system.physmem.writeRowHits 37451 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.91 # Row buffer hit rate for writes +system.physmem.avgGap 14181533.63 # Average gap between requests +system.physmem.pageHitRate 83.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 81194400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 44195250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 317686200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 151936560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89056992960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 35637705585 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 799850646000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 925140356955 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.881529 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1309035077000 # Time in different power states +system.physmem_0.memoryStateTime::REF 45530160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9101184500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9110965500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 85526280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 46513500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 324175800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 176340240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35475772860 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 801505403250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 926669707770 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.770193 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1309231204000 # Time in different power states -system.physmem_1.memoryStateTime::REF 45529640000 # Time in different power states +system.physmem_1.actEnergy 83651400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 45474000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 324261600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 155416320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89056992960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35441943930 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 803933138250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 929040878460 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.556246 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1309294919000 # Time in different power states +system.physmem_1.memoryStateTime::REF 45530160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8903896000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8868165750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4781172 # DTB read hits -system.cpu0.dtb.read_misses 6058 # DTB read misses -system.cpu0.dtb.read_acv 118 # DTB read access violations -system.cpu0.dtb.read_accesses 428328 # DTB read accesses -system.cpu0.dtb.write_hits 3391530 # DTB write hits -system.cpu0.dtb.write_misses 675 # DTB write misses -system.cpu0.dtb.write_acv 82 # DTB write access violations -system.cpu0.dtb.write_accesses 163639 # DTB write accesses -system.cpu0.dtb.data_hits 8172702 # DTB hits -system.cpu0.dtb.data_misses 6733 # DTB misses -system.cpu0.dtb.data_acv 200 # DTB access violations -system.cpu0.dtb.data_accesses 591967 # DTB accesses -system.cpu0.itb.fetch_hits 2720050 # ITB hits -system.cpu0.itb.fetch_misses 3046 # ITB misses -system.cpu0.itb.fetch_acv 99 # ITB acv -system.cpu0.itb.fetch_accesses 2723096 # ITB accesses +system.cpu0.dtb.read_hits 4775602 # DTB read hits +system.cpu0.dtb.read_misses 5966 # DTB read misses +system.cpu0.dtb.read_acv 109 # DTB read access violations +system.cpu0.dtb.read_accesses 428378 # DTB read accesses +system.cpu0.dtb.write_hits 3387346 # DTB write hits +system.cpu0.dtb.write_misses 667 # DTB write misses +system.cpu0.dtb.write_acv 80 # DTB write access violations +system.cpu0.dtb.write_accesses 163776 # DTB write accesses +system.cpu0.dtb.data_hits 8162948 # DTB hits +system.cpu0.dtb.data_misses 6633 # DTB misses +system.cpu0.dtb.data_acv 189 # DTB access violations +system.cpu0.dtb.data_accesses 592154 # DTB accesses +system.cpu0.itb.fetch_hits 2717036 # ITB hits +system.cpu0.itb.fetch_misses 3019 # ITB misses +system.cpu0.itb.fetch_acv 97 # ITB acv +system.cpu0.itb.fetch_accesses 2720055 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -355,87 +364,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 930048733 # number of cpu cycles simulated +system.cpu0.numCycles 930055234 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31504183 # Number of instructions committed -system.cpu0.committedOps 31504183 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 29439494 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 162688 # Number of float alu accesses -system.cpu0.num_func_calls 792913 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4107229 # number of instructions that are conditional controls -system.cpu0.num_int_insts 29439494 # number of integer instructions -system.cpu0.num_fp_insts 162688 # number of float instructions -system.cpu0.num_int_register_reads 41004383 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21582488 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 84172 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 85625 # number of times the floating registers were written -system.cpu0.num_mem_refs 8202083 # number of memory refs -system.cpu0.num_load_insts 4802046 # Number of load instructions -system.cpu0.num_store_insts 3400037 # Number of store instructions -system.cpu0.num_idle_cycles 907048310.649553 # Number of idle cycles -system.cpu0.num_busy_cycles 23000422.350447 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024730 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975270 # Percentage of idle cycles -system.cpu0.Branches 5154717 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1560474 4.95% 4.95% # Class of executed instruction -system.cpu0.op_class::IntAlu 21056937 66.82% 71.78% # Class of executed instruction -system.cpu0.op_class::IntMult 31354 0.10% 71.88% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.88% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12843 0.04% 71.92% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1601 0.01% 71.92% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.92% # Class of executed instruction -system.cpu0.op_class::MemRead 4932088 15.65% 87.57% # Class of executed instruction -system.cpu0.op_class::MemWrite 3403118 10.80% 98.37% # Class of executed instruction -system.cpu0.op_class::IprAccess 512701 1.63% 100.00% # Class of executed instruction +system.cpu0.committedInsts 31475732 # Number of instructions committed +system.cpu0.committedOps 31475732 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 29412106 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 162586 # Number of float alu accesses +system.cpu0.num_func_calls 792411 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4104277 # number of instructions that are conditional controls +system.cpu0.num_int_insts 29412106 # number of integer instructions +system.cpu0.num_fp_insts 162586 # number of float instructions +system.cpu0.num_int_register_reads 40967178 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21562005 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 84110 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 85570 # number of times the floating registers were written +system.cpu0.num_mem_refs 8192042 # number of memory refs +system.cpu0.num_load_insts 4796241 # Number of load instructions +system.cpu0.num_store_insts 3395801 # Number of store instructions +system.cpu0.num_idle_cycles 907058327.289346 # Number of idle cycles +system.cpu0.num_busy_cycles 22996906.710654 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024726 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975274 # Percentage of idle cycles +system.cpu0.Branches 5151040 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1559860 4.95% 4.95% # Class of executed instruction +system.cpu0.op_class::IntAlu 21040910 66.83% 71.79% # Class of executed instruction +system.cpu0.op_class::IntMult 31347 0.10% 71.89% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.89% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12827 0.04% 71.93% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1598 0.01% 71.93% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.93% # Class of executed instruction +system.cpu0.op_class::MemRead 4926196 15.65% 87.58% # Class of executed instruction +system.cpu0.op_class::MemWrite 3398883 10.80% 98.38% # Class of executed instruction +system.cpu0.op_class::IprAccess 510933 1.62% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 31511116 # Class of executed instruction +system.cpu0.op_class::total 31482554 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211361 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74795 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6422 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211358 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105682 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182558 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73428 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 105680 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182555 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73428 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148937 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818811073000 98.77% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38572000 0.00% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 355311500 0.02% 98.79% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22333065000 1.21% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841538021500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818800243000 98.76% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38808500 0.00% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 357216000 0.02% 98.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22351032000 1.21% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841547299500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694801 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815834 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694805 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815836 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -474,7 +483,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175301 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175298 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -483,7 +492,7 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192212 # number of callpals executed +system.cpu0.kern.callpal::total 192209 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches @@ -494,429 +503,429 @@ system.cpu0.kern.mode_switch_good::kernel 0.321851 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.390894 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29730845000 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2571229000 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809235945500 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 29750547000 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2575384000 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809221366500 98.24% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1393219 # number of replacements +system.cpu0.dcache.tags.replacements 1393348 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13266024 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393731 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.518353 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 13255372 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393860 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.509830 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 178.252416 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 164.663502 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 169.081899 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.348149 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.321608 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.330238 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 177.816582 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 164.221248 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 169.959986 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.347298 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.320745 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.331953 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63377040 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63377040 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 3961674 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1077685 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2542197 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7581556 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3105087 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 828848 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1366589 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5300524 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113741 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19662 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51148 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184551 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122328 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21764 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55225 # number of StoreCondReq hits +system.cpu0.dcache.tags.tag_accesses 63362265 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63362265 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 3956098 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1080024 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2536463 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7572585 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3101293 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 830391 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1367001 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5298685 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113681 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19703 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51298 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184682 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122268 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21809 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55240 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 199317 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7066761 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1906533 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3908786 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12882080 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7066761 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1906533 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3908786 # number of overall hits -system.cpu0.dcache.overall_hits::total 12882080 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 706841 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 96965 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 557653 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1361459 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 162721 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 43998 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 642629 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 849348 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9135 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2231 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7695 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19061 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 11 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 869562 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 140963 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1200282 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2210807 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 869562 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 140963 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1200282 # number of overall misses -system.cpu0.dcache.overall_misses::total 2210807 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2267399500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8210771504 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 10478171004 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1754611010 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19498280034 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 21252891044 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 29510000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 125540000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 155050000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 185002 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 185002 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4022010510 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 27709051538 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 31731062048 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4022010510 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 27709051538 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 31731062048 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4668515 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1174650 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 293979000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 446199000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740178000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 516452500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 777525000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1293977500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082548 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087131 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041044 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050408 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047670 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022729 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101905 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.102034 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040445 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000199 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000055 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.068847 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071612 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.033581 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.068847 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071612 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033581 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21811.633063 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15810.589349 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17395.873429 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38194.190418 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31534.830267 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33631.000823 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11726.355894 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11998.625916 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11924.863388 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 15318 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15318 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26925.029901 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19926.957037 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21873.285524 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26925.029901 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19926.957037 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21873.285524 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201881.578947 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 211980.806142 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 207804.690432 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 212719.971056 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 209384.795870 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 210696.840307 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 207911.634461 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 210483.216026 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 209449.255422 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 835740 # number of writebacks +system.cpu0.dcache.writebacks::total 835740 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 292598 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 292598 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 548626 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 548626 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1690 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1690 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 841224 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 841224 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 841224 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 841224 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 97332 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 269929 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 367261 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 44132 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 96028 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 140160 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2235 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5978 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8213 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 10 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 141464 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 365957 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 507421 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 141464 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 365957 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 507421 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1108 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1559 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2667 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1387 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2128 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3515 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2495 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3687 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6182 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170918000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4426676000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6597594000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1708808000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3106661815 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4815469815 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 27324000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 74701500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102025500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 160500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 160500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3879726000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7533337815 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11413063815 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3879726000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7533337815 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11413063815 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 226454500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 334463500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 560918000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298425500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 450956500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 749382000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 524880000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 785420000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1310300000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082670 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087102 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041084 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050464 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047736 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022791 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101878 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.101380 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040315 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000181 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000050 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.068944 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071607 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033628 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.068944 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071607 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033628 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 22304.257593 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16399.408733 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17964.319653 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38720.384302 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32351.624682 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34356.947881 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12225.503356 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12496.068919 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12422.440034 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 16050 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16050 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27425.535825 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20585.308697 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22492.296959 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27425.535825 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20585.308697 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22492.296959 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 204381.317690 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 214537.203335 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210317.960255 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 215158.976208 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211915.648496 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 213195.448080 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 210372.745491 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 213024.138866 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 211954.060175 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 964809 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.919385 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 41279952 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 965320 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 42.762972 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10189587250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 147.730782 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 136.243694 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 226.944909 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.288537 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.266101 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.443252 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997889 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 965393 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.914113 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 41264625 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 965904 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 42.721249 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10188445500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 146.904249 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 135.394605 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 228.615259 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.286922 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.264443 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.446514 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997879 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43227698 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43227698 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 31004099 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7794052 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2481801 # 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mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016265 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116593 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010873 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13261.329727 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13064.367813 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13119.689453 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13261.329727 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13064.367813 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13119.689453 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13261.329727 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13064.367813 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13119.689453 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1194215 # DTB read hits -system.cpu1.dtb.read_misses 1316 # DTB read misses +system.cpu1.dtb.read_hits 1196955 # DTB read hits +system.cpu1.dtb.read_misses 1325 # DTB read misses system.cpu1.dtb.read_acv 35 # DTB read access violations -system.cpu1.dtb.read_accesses 141030 # DTB read accesses -system.cpu1.dtb.write_hits 894755 # DTB write hits +system.cpu1.dtb.read_accesses 141268 # DTB read accesses +system.cpu1.dtb.write_hits 896481 # DTB write hits system.cpu1.dtb.write_misses 169 # DTB write misses system.cpu1.dtb.write_acv 22 # DTB write access violations -system.cpu1.dtb.write_accesses 57515 # DTB write accesses -system.cpu1.dtb.data_hits 2088970 # DTB hits -system.cpu1.dtb.data_misses 1485 # DTB misses +system.cpu1.dtb.write_accesses 57742 # DTB write accesses +system.cpu1.dtb.data_hits 2093436 # DTB hits +system.cpu1.dtb.data_misses 1494 # DTB misses system.cpu1.dtb.data_acv 57 # DTB access violations -system.cpu1.dtb.data_accesses 198545 # DTB accesses -system.cpu1.itb.fetch_hits 856400 # ITB hits -system.cpu1.itb.fetch_misses 653 # ITB misses -system.cpu1.itb.fetch_acv 34 # ITB acv -system.cpu1.itb.fetch_accesses 857053 # ITB accesses +system.cpu1.dtb.data_accesses 199010 # DTB accesses +system.cpu1.itb.fetch_hits 858438 # ITB hits +system.cpu1.itb.fetch_misses 659 # ITB misses +system.cpu1.itb.fetch_acv 35 # ITB acv +system.cpu1.itb.fetch_accesses 859097 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -929,64 +938,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953255662 # number of cpu cycles simulated +system.cpu1.numCycles 953273349 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7921357 # Number of instructions committed -system.cpu1.committedOps 7921357 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7380748 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45896 # Number of float alu accesses -system.cpu1.num_func_calls 207012 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1022630 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7380748 # number of integer instructions -system.cpu1.num_fp_insts 45896 # number of float instructions -system.cpu1.num_int_register_reads 10351742 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5363285 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24726 # number of times the floating registers were read +system.cpu1.committedInsts 7930565 # Number of instructions committed +system.cpu1.committedOps 7930565 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7389333 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45920 # Number of float alu accesses +system.cpu1.num_func_calls 207460 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1022605 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7389333 # number of integer instructions +system.cpu1.num_fp_insts 45920 # number of float instructions +system.cpu1.num_int_register_reads 10362144 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5369975 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24736 # number of times the floating registers were read system.cpu1.num_fp_register_writes 25085 # number of times the floating registers were written -system.cpu1.num_mem_refs 2096070 # number of memory refs -system.cpu1.num_load_insts 1198996 # Number of load instructions -system.cpu1.num_store_insts 897074 # Number of store instructions -system.cpu1.num_idle_cycles 923177922.874727 # Number of idle cycles -system.cpu1.num_busy_cycles 30077739.125273 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031553 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968447 # Percentage of idle cycles -system.cpu1.Branches 1296149 # Number of branches fetched -system.cpu1.op_class::No_OpClass 410448 5.18% 5.18% # Class of executed instruction -system.cpu1.op_class::IntAlu 5236817 66.10% 71.28% # Class of executed instruction -system.cpu1.op_class::IntMult 8727 0.11% 71.39% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 71.39% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5162 0.07% 71.45% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 71.46% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.46% # Class of executed instruction -system.cpu1.op_class::MemRead 1228055 15.50% 86.96% # Class of executed instruction -system.cpu1.op_class::MemWrite 898300 11.34% 98.30% # Class of executed instruction -system.cpu1.op_class::IprAccess 134580 1.70% 100.00% # Class of executed instruction +system.cpu1.num_mem_refs 2100568 # number of memory refs +system.cpu1.num_load_insts 1201762 # Number of load instructions +system.cpu1.num_store_insts 898806 # Number of store instructions +system.cpu1.num_idle_cycles 922154358.750069 # Number of idle cycles +system.cpu1.num_busy_cycles 31118990.249931 # Number of busy cycles +system.cpu1.not_idle_fraction 0.032644 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.967356 # Percentage of idle cycles +system.cpu1.Branches 1296677 # Number of branches fetched +system.cpu1.op_class::No_OpClass 410840 5.18% 5.18% # Class of executed instruction +system.cpu1.op_class::IntAlu 5240708 66.07% 71.25% # Class of executed instruction +system.cpu1.op_class::IntMult 8731 0.11% 71.36% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 71.36% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5176 0.07% 71.42% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 71.42% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 71.42% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 71.42% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 71.43% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.43% # Class of executed instruction +system.cpu1.op_class::MemRead 1230901 15.52% 86.95% # Class of executed instruction +system.cpu1.op_class::MemWrite 900034 11.35% 98.30% # Class of executed instruction +system.cpu1.op_class::IprAccess 134916 1.70% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7922899 # Class of executed instruction +system.cpu1.op_class::total 7932116 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1004,35 +1013,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 10412478 # Number of BP lookups -system.cpu2.branchPred.condPredicted 9668294 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 126557 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 8251745 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6275895 # Number of BTB hits +system.cpu2.branchPred.lookups 10402334 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9657881 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 126933 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 8330137 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6272162 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 76.055368 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 302998 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7851 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 75.294824 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 302639 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7723 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3529660 # DTB read hits -system.cpu2.dtb.read_misses 12347 # DTB read misses -system.cpu2.dtb.read_acv 141 # DTB read access violations -system.cpu2.dtb.read_accesses 225697 # DTB read accesses -system.cpu2.dtb.write_hits 2155841 # DTB write hits -system.cpu2.dtb.write_misses 2820 # DTB write misses -system.cpu2.dtb.write_acv 143 # DTB write access violations -system.cpu2.dtb.write_accesses 84900 # DTB write accesses -system.cpu2.dtb.data_hits 5685501 # DTB hits -system.cpu2.dtb.data_misses 15167 # DTB misses -system.cpu2.dtb.data_acv 284 # DTB access violations -system.cpu2.dtb.data_accesses 310597 # DTB accesses -system.cpu2.itb.fetch_hits 538073 # ITB hits -system.cpu2.itb.fetch_misses 5955 # ITB misses -system.cpu2.itb.fetch_acv 169 # ITB acv -system.cpu2.itb.fetch_accesses 544028 # ITB accesses +system.cpu2.dtb.read_hits 3549115 # DTB read hits +system.cpu2.dtb.read_misses 12776 # DTB read misses +system.cpu2.dtb.read_acv 157 # DTB read access violations +system.cpu2.dtb.read_accesses 225358 # DTB read accesses +system.cpu2.dtb.write_hits 2157791 # DTB write hits +system.cpu2.dtb.write_misses 2831 # DTB write misses +system.cpu2.dtb.write_acv 142 # DTB write access violations +system.cpu2.dtb.write_accesses 84650 # DTB write accesses +system.cpu2.dtb.data_hits 5706906 # DTB hits +system.cpu2.dtb.data_misses 15607 # DTB misses +system.cpu2.dtb.data_acv 299 # DTB access violations +system.cpu2.dtb.data_accesses 310008 # DTB accesses +system.cpu2.itb.fetch_hits 538598 # ITB hits +system.cpu2.itb.fetch_misses 5991 # ITB misses +system.cpu2.itb.fetch_acv 159 # ITB acv +system.cpu2.itb.fetch_accesses 544589 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1045,304 +1054,304 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30702821 # number of cpu cycles simulated +system.cpu2.numCycles 30759536 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9319148 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 39738878 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 10412478 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6578893 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 19243837 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 412304 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 656 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 9648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1927 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 233877 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 108804 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2828172 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 93139 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 29124256 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.364460 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.368556 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9338114 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 39735788 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 10402334 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6574801 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 19282744 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 413720 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 277 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9678 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1944 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 234903 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 108900 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 473 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2833173 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 93993 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 29183655 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.361577 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.367035 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20002999 68.68% 68.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 306830 1.05% 69.74% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 477568 1.64% 71.37% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4658363 15.99% 87.37% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 855343 2.94% 90.31% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 200502 0.69% 90.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 234860 0.81% 91.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 433547 1.49% 93.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1954244 6.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 20063773 68.75% 68.75% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 307542 1.05% 69.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 477296 1.64% 71.44% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4654234 15.95% 87.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 859104 2.94% 90.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 198525 0.68% 91.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 235442 0.81% 91.82% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 432653 1.48% 93.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1955086 6.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 29124256 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.339138 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.294307 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7666487 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 12991565 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7744961 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 527663 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 193001 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 177358 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13514 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36364188 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 42851 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 193001 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7942048 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4601261 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6305683 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7969678 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2112012 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35538074 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 62867 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 396006 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 59218 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1045972 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 23773076 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 44310063 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 44249815 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56335 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 21846032 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1927044 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 532665 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63556 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3796199 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3529311 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2248768 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 470664 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 333419 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32987424 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 681806 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32666998 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 16031 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2569271 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1151235 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 487594 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 29124256 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.121642 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.623821 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 29183655 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.338182 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.291820 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7672062 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 13049396 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7739525 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 528158 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 193789 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 177139 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13443 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36353966 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 42512 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 193789 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7950274 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4574250 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6325048 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7961138 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2178432 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35523870 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 60190 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 394243 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 57916 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1115509 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 23763436 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 44289897 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 44229633 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56339 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21842362 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1921074 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 535035 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63809 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3839801 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3528507 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2250963 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 468940 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 330687 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32977065 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 683079 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32678030 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 15337 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2566331 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1147551 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 488786 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 29183655 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.119737 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.624192 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17381860 59.68% 59.68% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2746661 9.43% 69.11% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1371662 4.71% 73.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5386342 18.49% 92.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1029310 3.53% 95.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 605779 2.08% 97.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 390861 1.34% 99.27% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 167562 0.58% 99.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 44219 0.15% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17436459 59.75% 59.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2753806 9.44% 69.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1377159 4.72% 73.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5375832 18.42% 92.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1030141 3.53% 95.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 601956 2.06% 97.92% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 392573 1.35% 99.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 169204 0.58% 99.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 46525 0.16% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 29124256 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 29183655 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 85214 22.02% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 22.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 179569 46.41% 68.43% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 122132 31.57% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 85386 21.51% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 184726 46.54% 68.05% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 126802 31.95% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2450 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 26477502 81.05% 81.06% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21078 0.06% 81.12% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.12% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20355 0.06% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1225 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.19% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3659635 11.20% 92.39% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2180799 6.68% 99.07% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 303954 0.93% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26465043 80.99% 80.99% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21101 0.06% 81.06% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20515 0.06% 81.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.13% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3679518 11.26% 92.39% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2182790 6.68% 99.07% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 305379 0.93% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32666998 # Type of FU issued -system.cpu2.iq.rate 1.063974 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 386915 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.011844 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 94607462 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 36124516 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 32054290 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 253736 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 119890 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 117198 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32915380 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 136083 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 205891 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32678030 # Type of FU issued +system.cpu2.iq.rate 1.062371 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 396914 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.012146 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 94697637 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 36112111 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 32047154 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 254329 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 120282 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 117366 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32936079 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 136409 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206083 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 443704 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1465 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6049 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 180746 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 440040 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1257 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6058 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 180485 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5094 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 200289 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5073 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 225988 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 193001 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3976817 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 219021 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 35063617 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 53776 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3529311 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2248768 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 606766 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 12977 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 164349 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6049 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 63932 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 135830 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 199762 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 32464526 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3550760 # Number of load instructions executed +system.cpu2.iew.iewSquashCycles 193789 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3993186 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 173385 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 35054322 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 55127 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3528507 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2250963 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 608084 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 13021 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 119091 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6058 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 64339 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 136180 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 200519 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 32475558 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3570784 # Number of load instructions executed system.cpu2.iew.iewExecSquashedInsts 202472 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1394387 # number of nop insts executed -system.cpu2.iew.exec_refs 5714159 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7350868 # Number of branches executed -system.cpu2.iew.exec_stores 2163399 # Number of stores executed -system.cpu2.iew.exec_rate 1.057379 # Inst execution rate -system.cpu2.iew.wb_sent 32215343 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 32171488 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18756374 # num instructions producing a value -system.cpu2.iew.wb_consumers 22505351 # num instructions consuming a value +system.cpu2.iew.exec_nop 1394178 # number of nop insts executed +system.cpu2.iew.exec_refs 5736169 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7344406 # Number of branches executed +system.cpu2.iew.exec_stores 2165385 # Number of stores executed +system.cpu2.iew.exec_rate 1.055788 # Inst execution rate +system.cpu2.iew.wb_sent 32207740 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 32164520 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18733989 # num instructions producing a value +system.cpu2.iew.wb_consumers 22461298 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.047835 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.833418 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.045676 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.834056 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2693673 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 194212 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 181849 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 28653786 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.128143 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.870801 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2690484 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 194293 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 182480 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 28713100 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.125605 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.869287 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18143596 63.32% 63.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2243135 7.83% 71.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1187950 4.15% 75.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5112990 17.84% 93.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 566123 1.98% 95.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 201198 0.70% 95.82% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 164794 0.58% 96.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 163684 0.57% 96.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 870316 3.04% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18196306 63.37% 63.37% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2254505 7.85% 71.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1188955 4.14% 75.37% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5110402 17.80% 93.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 563606 1.96% 95.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 199238 0.69% 95.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 165515 0.58% 96.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 164290 0.57% 96.97% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 870283 3.03% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 28653786 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32325567 # Number of instructions committed -system.cpu2.commit.committedOps 32325567 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 28713100 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32319619 # Number of instructions committed +system.cpu2.commit.committedOps 32319619 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5153629 # Number of memory references committed -system.cpu2.commit.loads 3085607 # Number of loads committed -system.cpu2.commit.membars 68228 # Number of memory barriers committed -system.cpu2.commit.branches 7176692 # Number of branches committed -system.cpu2.commit.fp_insts 115672 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 30802580 # Number of committed integer instructions. -system.cpu2.commit.function_calls 241655 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1228058 3.80% 3.80% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 25528107 78.97% 82.77% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20647 0.06% 82.83% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 82.83% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20076 0.06% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1225 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 82.90% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3153835 9.76% 92.66% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2069665 6.40% 99.06% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 303954 0.94% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5158945 # Number of memory references committed +system.cpu2.commit.loads 3088467 # Number of loads committed +system.cpu2.commit.membars 68233 # Number of memory barriers committed +system.cpu2.commit.branches 7171529 # Number of branches committed +system.cpu2.commit.fp_insts 115750 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 30796114 # Number of committed integer instructions. +system.cpu2.commit.function_calls 241665 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1228262 3.80% 3.80% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 25515212 78.95% 82.75% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20642 0.06% 82.81% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 82.81% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20078 0.06% 82.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 82.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 82.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 82.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1228 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 82.88% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3156700 9.77% 92.64% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2072118 6.41% 99.06% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 305379 0.94% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 32325567 # Class of committed instruction -system.cpu2.commit.bw_lim_events 870316 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 62726939 # The number of ROB reads -system.cpu2.rob.rob_writes 70507401 # The number of ROB writes -system.cpu2.timesIdled 178497 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1578565 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745106872 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 31099959 # Number of Instructions Simulated -system.cpu2.committedOps 31099959 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.987230 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.987230 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.012935 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.012935 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42640475 # number of integer regfile reads -system.cpu2.int_regfile_writes 22658201 # number of integer regfile writes -system.cpu2.fp_regfile_reads 70901 # number of floating regfile reads -system.cpu2.fp_regfile_writes 71243 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5010785 # number of misc regfile reads -system.cpu2.misc_regfile_writes 273099 # number of misc regfile writes +system.cpu2.commit.op_class_0::total 32319619 # Class of committed instruction +system.cpu2.commit.bw_lim_events 870283 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 62775514 # The number of ROB reads +system.cpu2.rob.rob_writes 70489103 # The number of ROB writes +system.cpu2.timesIdled 177769 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1575881 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745050657 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31093813 # Number of Instructions Simulated +system.cpu2.committedOps 31093813 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.989249 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.989249 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.010867 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.010867 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42649325 # number of integer regfile reads +system.cpu2.int_regfile_writes 22654905 # number of integer regfile writes +system.cpu2.fp_regfile_reads 71051 # number of floating regfile reads +system.cpu2.fp_regfile_writes 71293 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5005090 # number of misc regfile reads +system.cpu2.misc_regfile_writes 273836 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1358,8 +1367,7 @@ system.disk2.dma_write_txs 1 # Nu system.iobus.trans_dist::ReadReq 7317 # Transaction distribution system.iobus.trans_dist::ReadResp 7317 # Transaction distribution system.iobus.trans_dist::WriteReq 51362 # Transaction distribution -system.iobus.trans_dist::WriteResp 9810 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.trans_dist::WriteResp 51362 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) @@ -1398,7 +1406,7 @@ system.iobus.reqLayer1.occupancy 105000 # La system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5364000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5370000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 1863000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) @@ -1408,21 +1416,21 @@ system.iobus.reqLayer27.occupancy 7000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 100878274 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 89820170 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 8843000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 8849000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17495500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17468000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254165 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254241 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693892917000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254165 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078385 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078385 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1693892852000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254241 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078390 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078390 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1430,49 +1438,49 @@ system.iocache.tags.tag_accesses 375525 # Nu system.iocache.tags.data_accesses 375525 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9444962 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9444962 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 3667270812 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 3667270812 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9444962 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9444962 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9444962 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9444962 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9418962 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9418962 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 2040792208 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2040792208 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9418962 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9418962 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9418962 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9418962 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54595.156069 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 54595.156069 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 88257.383808 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 88257.383808 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 54595.156069 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 54595.156069 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 54595.156069 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 54595.156069 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31008 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54444.867052 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54444.867052 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 49114.175202 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 49114.175202 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 54444.867052 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 54444.867052 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 54444.867052 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 54444.867052 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4243 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.308037 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1480,237 +1488,243 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17280 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 17280 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 17280 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 17280 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5749962 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5749962 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2768710812 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2768710812 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5749962 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5749962 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5749962 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5749962 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5918962 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5918962 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1176792208 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1176792208 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5918962 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5918962 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5918962 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5918962 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82142.314286 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82142.314286 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 160226.320139 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 160226.320139 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82142.314286 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82142.314286 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82142.314286 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82142.314286 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 84556.600000 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68101.400926 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68101.400926 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 84556.600000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 84556.600000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 84556.600000 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 337569 # number of replacements -system.l2c.tags.tagsinuse 65419.566617 # Cycle average of tags in use -system.l2c.tags.total_refs 2487366 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402731 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.176247 # Average number of references to valid blocks. +system.l2c.tags.replacements 337481 # number of replacements +system.l2c.tags.tagsinuse 65419.198683 # Cycle average of tags in use +system.l2c.tags.total_refs 4010491 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402643 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.960414 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54619.974232 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2262.532885 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2731.767010 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 536.522208 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 599.592732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2415.786794 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2253.390757 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.833435 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.034524 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041683 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008187 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009149 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.036862 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.034384 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998223 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54563.896309 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2274.571035 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2764.017947 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 537.574504 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 599.716909 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2426.240023 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2253.181956 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.832579 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.034707 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042176 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008203 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009151 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.037021 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.034381 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998218 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 974 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2636 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55307 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1020 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5977 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2679 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55308 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26265257 # Number of tag accesses -system.l2c.tags.data_accesses 26265257 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 499689 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 475179 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 126551 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 83555 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 324793 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 258988 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1768755 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835707 # number of Writeback hits -system.l2c.Writeback_hits::total 835707 # number of Writeback hits +system.l2c.tags.tag_accesses 38452030 # Number of tag accesses +system.l2c.tags.data_accesses 38452030 # Number of data accesses +system.l2c.Writeback_hits::writebacks 835740 # number of Writeback hits +system.l2c.Writeback_hits::total 835740 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 8 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 12 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 9 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 89325 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 26026 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 71615 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186966 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 499689 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 564504 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 126551 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 109581 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 324793 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 330603 # number of demand (read+write) hits -system.l2c.demand_hits::total 1955721 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2199533500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 346786500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 3042757500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5752546000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 212604500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 314976000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 527580500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 282475000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 426484500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 708959500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 495079500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 741460500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1236540000 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.709677 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.511628 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.407287 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.255964 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.140765 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017819 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.014546 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.007353 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.158376 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.061563 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.030004 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017819 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.234819 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014546 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.111891 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034942 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017819 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.234819 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014546 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.111891 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034942 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 27590.909091 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 27590.909091 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 20750 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20750 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66107.210415 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 78998.458105 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 73561.744762 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71104.175729 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72187.031640 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71836.547937 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 64133.584882 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 64582.773456 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 64366.404985 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71104.175729 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65184.882791 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72187.031640 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73120.359022 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 69762.500152 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71104.175729 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65184.882791 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72187.031640 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73120.359022 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69762.500152 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191881.317690 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 202037.203335 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197817.960255 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203658.976208 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 200415.648496 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201695.448080 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 198428.657315 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 201101.301871 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 200022.646393 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 295002 # Transaction distribution -system.membus.trans_dist::ReadResp 294996 # Transaction distribution +system.membus.trans_dist::ReadReq 7144 # Transaction distribution +system.membus.trans_dist::ReadResp 294958 # Transaction distribution system.membus.trans_dist::WriteReq 9810 # Transaction distribution system.membus.trans_dist::WriteResp 9810 # Transaction distribution -system.membus.trans_dist::Writeback 116904 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 145 # Transaction distribution +system.membus.trans_dist::Writeback 116948 # Transaction distribution +system.membus.trans_dist::CleanEvict 262295 # Transaction distribution +system.membus.trans_dist::UpgradeReq 165 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 147 # Transaction distribution -system.membus.trans_dist::ReadExReq 115657 # Transaction distribution -system.membus.trans_dist::ReadExResp 115657 # Transaction distribution -system.membus.trans_dist::BadAddressError 6 # Transaction distribution +system.membus.trans_dist::UpgradeResp 167 # Transaction distribution +system.membus.trans_dist::ReadExReq 115610 # Transaction distribution +system.membus.trans_dist::ReadExResp 115610 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 287819 # Transaction distribution +system.membus.trans_dist::BadAddressError 5 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882256 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 916176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124907 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124907 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1041083 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1144349 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1178267 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125023 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 125023 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1303290 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30632256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30677824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5323648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5323648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36001472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30629632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30675200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33339520 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 157 # Total snoops (count) -system.membus.snoop_fanout::samples 579090 # Request fanout histogram +system.membus.snoop_fanout::samples 841413 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 579090 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 841413 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 579090 # Request fanout histogram -system.membus.reqLayer0.occupancy 11072500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 841413 # Request fanout histogram +system.membus.reqLayer0.occupancy 11052000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 412860298 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 394258327 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 438835201 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 441332932 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 17657500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 29902743 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2063715 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2063694 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2064402 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 835707 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 17293 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 31 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 42 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302749 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302749 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1930984 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3657230 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5588214 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61790208 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142733184 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 204523392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 41934 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3253691 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012828 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112532 # Request fanout histogram +system.toL2Bus.trans_dist::Writeback 883212 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1574760 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 43 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 53 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302767 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302767 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 966109 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1091169 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 5 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 17280 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2897413 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4214892 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7112305 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61827200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142743552 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 204570752 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 141567 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4877075 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.028983 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.167759 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3211953 98.72% 98.72% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 41738 1.28% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 4735723 97.10% 97.10% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 141352 2.90% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3253691 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1080719000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4877075 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1372572500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 82500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 689338845 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 689392754 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 790311532 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 777864461 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |