diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2013-04-22 13:20:33 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2013-04-22 13:20:33 -0400 |
| commit | d69f904a18593f75efcb0555b2bd092574181160 (patch) | |
| tree | 0afd4c3ec943f0166c70bf7b62215f404465da2f /tests/long/fs/10.linux-boot/ref/alpha | |
| parent | 33ab8f735d0979ef68d7202d3adbf28f1ae2aceb (diff) | |
| download | gem5-d69f904a18593f75efcb0555b2bd092574181160.tar.xz | |
stats: Update stats for O3 switching fix.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
6 files changed, 3523 insertions, 3519 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index edbc5da0f..4ffad8c19 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -12,15 +12,15 @@ children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 clock=1000 -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -107,6 +107,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -533,6 +534,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -913,7 +915,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -933,7 +935,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -1062,7 +1064,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index e142ab1e4..56627054e 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.900728 # Number of seconds simulated -sim_ticks 1900727697500 # Number of ticks simulated -final_tick 1900727697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.896442 # Number of seconds simulated +sim_ticks 1896441913500 # Number of ticks simulated +final_tick 1896441913500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95395 # Simulator instruction rate (inst/s) -host_op_rate 95395 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3185234659 # Simulator tick rate (ticks/s) -host_mem_usage 355712 # Number of bytes of host memory used -host_seconds 596.73 # Real time elapsed on the host -sim_insts 56925219 # Number of instructions simulated -sim_ops 56925219 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 854208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24595840 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2651904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 123328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 541952 # Number of bytes read from this memory -system.physmem.bytes_read::total 28767232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 854208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 123328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7730048 # Number of bytes written to this memory -system.physmem.bytes_written::total 7730048 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13347 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 384310 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41436 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1927 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8468 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449488 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120782 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120782 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 449411 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12940223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1395205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 64885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 285129 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15134852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 449411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 64885 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 514296 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4066889 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4066889 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4066889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 449411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12940223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1395205 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 64885 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 285129 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19201740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449488 # Total number of read requests seen -system.physmem.writeReqs 120782 # Total number of write requests seen -system.physmem.cpureqs 575881 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28767232 # Total number of bytes read from memory -system.physmem.bytesWritten 7730048 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28767232 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7730048 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 76 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 5601 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28386 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 28241 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28220 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 28022 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28087 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28039 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28071 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27938 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27835 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27859 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27848 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7706 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7703 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7519 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7864 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7579 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7606 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7518 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7651 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7586 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7578 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7350 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7241 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7443 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7270 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7347 # Track writes on a per bank basis +host_inst_rate 132187 # Simulator instruction rate (inst/s) +host_op_rate 132187 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4418345683 # Simulator tick rate (ticks/s) +host_mem_usage 311512 # Number of bytes of host memory used +host_seconds 429.22 # Real time elapsed on the host +sim_insts 56737124 # Number of instructions simulated +sim_ops 56737124 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 937984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24915648 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 39872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 337088 # Number of bytes read from this memory +system.physmem.bytes_read::total 28881280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 937984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 39872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977856 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7850944 # Number of bytes written to this memory +system.physmem.bytes_written::total 7850944 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 389307 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 623 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 5267 # Number of read requests responded to by this memory +system.physmem.num_reads::total 451270 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122671 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122671 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 494602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13138102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1397716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 21025 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 177748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15229193 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 494602 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 21025 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 515627 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4139828 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4139828 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4139828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 494602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13138102 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1397716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 21025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 177748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19369021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 451270 # Total number of read requests seen +system.physmem.writeReqs 122671 # Total number of write requests seen +system.physmem.cpureqs 578881 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28881280 # Total number of bytes read from memory +system.physmem.bytesWritten 7850944 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28881280 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7850944 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 67 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4936 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28286 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28331 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 28037 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28769 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28511 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 28476 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 28312 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28256 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28154 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27864 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27902 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28010 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27813 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 28043 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7715 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7756 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7743 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7541 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 8184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7906 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7897 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7828 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7761 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7702 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7706 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7342 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7423 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7442 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7221 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7504 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry -system.physmem.totGap 1900723138000 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry +system.physmem.totGap 1896440622000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 449488 # Categorize read packet sizes +system.physmem.readPktSize::6 451270 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 120782 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 319759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 32659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2688 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2595 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1415 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 914 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122671 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 320077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59739 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7716 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2984 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2709 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2673 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1536 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1501 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 776 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -138,224 +138,224 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see -system.physmem.totQLat 7717714750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15508692250 # Sum of mem lat for all requests -system.physmem.totBusLat 2247060000 # Total cycles spent in databus access -system.physmem.totBankLat 5543917500 # Total cycles spent in bank access -system.physmem.avgQLat 17172.92 # Average queueing delay per request -system.physmem.avgBankLat 12335.94 # Average bank access latency per request +system.physmem.wrQLenPdf::0 3224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5330 # 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Total cycles spent in queuing delays +system.physmem.totMemAccLat 15642141000 # Sum of mem lat for all requests +system.physmem.totBusLat 2256015000 # Total cycles spent in databus access +system.physmem.totBankLat 5549183750 # Total cycles spent in bank access +system.physmem.avgQLat 17368.99 # Average queueing delay per request +system.physmem.avgBankLat 12298.64 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34508.85 # Average memory access latency -system.physmem.avgRdBW 15.13 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 4.07 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 15.13 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 4.07 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 34667.64 # Average memory access latency +system.physmem.avgRdBW 15.23 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 15.23 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 4.14 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 9.47 # Average write queue length over time -system.physmem.readRowHits 421565 # Number of row buffer hits during reads -system.physmem.writeRowHits 92877 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.80 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.90 # Row buffer hit rate for writes -system.physmem.avgGap 3333023.20 # Average gap between requests -system.l2c.replacements 342612 # number of replacements -system.l2c.tagsinuse 65284.978501 # Cycle average of tags in use -system.l2c.total_refs 2568846 # Total number of references to valid blocks. -system.l2c.sampled_refs 407591 # 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miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120759.765363 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120759.765363 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256238.716885 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 256238.716885 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255657.596559 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255657.596559 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255657.596559 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255657.596559 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 286486 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120931.022989 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120931.022989 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255906.464936 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 255906.464936 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255343.608997 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255343.608997 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255343.608997 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255343.608997 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 285994 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27218 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27316 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.525608 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.469835 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12307249 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12307249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8485239667 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8485239667 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8497546916 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8497546916 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8497546916 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8497546916 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11993249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11993249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8471449424 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8471449424 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8483442673 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8483442673 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8483442673 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8483442673 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -576,14 +576,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68755.581006 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68755.581006 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204207.731686 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204207.731686 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203626.726319 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203626.726319 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203626.726319 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203626.726319 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68926.718391 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68926.718391 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203875.852522 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 203875.852522 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203313.106289 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203313.106289 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203313.106289 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203313.106289 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -597,35 +597,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12035820 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10146181 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 320311 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 7799891 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5138186 # Number of BTB hits +system.cpu0.branchPred.lookups 12584062 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10588139 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 341886 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 8301483 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5323497 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.875100 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 760204 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 30176 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 64.127060 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 804999 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 33376 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8551483 # DTB read hits -system.cpu0.dtb.read_misses 30199 # DTB read misses -system.cpu0.dtb.read_acv 541 # DTB read access violations -system.cpu0.dtb.read_accesses 624803 # DTB read accesses -system.cpu0.dtb.write_hits 5601236 # DTB write hits -system.cpu0.dtb.write_misses 7972 # DTB write misses -system.cpu0.dtb.write_acv 345 # DTB write access violations -system.cpu0.dtb.write_accesses 208308 # DTB write accesses -system.cpu0.dtb.data_hits 14152719 # DTB hits -system.cpu0.dtb.data_misses 38171 # DTB misses -system.cpu0.dtb.data_acv 886 # DTB access violations -system.cpu0.dtb.data_accesses 833111 # DTB accesses -system.cpu0.itb.fetch_hits 970030 # ITB hits -system.cpu0.itb.fetch_misses 28776 # ITB misses -system.cpu0.itb.fetch_acv 920 # ITB acv -system.cpu0.itb.fetch_accesses 998806 # ITB accesses +system.cpu0.dtb.read_hits 8950032 # DTB read hits +system.cpu0.dtb.read_misses 34820 # DTB read misses +system.cpu0.dtb.read_acv 539 # DTB read access violations +system.cpu0.dtb.read_accesses 674081 # DTB read accesses +system.cpu0.dtb.write_hits 5877992 # DTB write hits +system.cpu0.dtb.write_misses 8366 # DTB write misses +system.cpu0.dtb.write_acv 348 # DTB write access violations +system.cpu0.dtb.write_accesses 235610 # DTB write accesses +system.cpu0.dtb.data_hits 14828024 # DTB hits +system.cpu0.dtb.data_misses 43186 # DTB misses +system.cpu0.dtb.data_acv 887 # DTB access violations +system.cpu0.dtb.data_accesses 909691 # DTB accesses +system.cpu0.itb.fetch_hits 1040487 # ITB hits +system.cpu0.itb.fetch_misses 31672 # ITB misses +system.cpu0.itb.fetch_acv 1020 # ITB acv +system.cpu0.itb.fetch_accesses 1072159 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -638,269 +638,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 100119117 # number of cpu cycles simulated +system.cpu0.numCycles 103751291 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 24086973 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 61837518 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12035820 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5898390 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11653378 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1636628 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 36048574 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 32004 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 195358 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 286105 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 287 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7499654 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 215735 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 73358875 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.842945 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.179502 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 25592047 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 64430414 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12584062 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6128496 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12114182 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1732019 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 37108557 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31932 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 208707 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 355709 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 408 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7808396 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 232068 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 76528583 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.841913 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.179850 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 61705497 84.11% 84.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 747609 1.02% 85.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1536097 2.09% 87.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 679694 0.93% 88.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2532720 3.45% 91.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 506441 0.69% 92.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 557934 0.76% 93.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 775120 1.06% 94.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4317763 5.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 64414401 84.17% 84.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 777905 1.02% 85.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1574114 2.06% 87.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 716339 0.94% 88.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2604704 3.40% 91.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 529326 0.69% 92.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 586322 0.77% 93.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 831890 1.09% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4493582 5.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 73358875 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.120215 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.617639 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 25314409 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 35520182 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10594612 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 907065 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1022606 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 498090 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 33900 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 60717129 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 100549 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1022606 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 26293542 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 14517617 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17593984 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9931348 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3999776 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 57516764 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6773 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 634732 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1395914 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 38573698 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 70135572 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 69772127 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 363445 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33935332 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4638358 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1391962 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 201915 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 10849961 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8944130 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5848227 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1106835 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 734658 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 51076458 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1725873 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 49974476 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 73247 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5675710 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2876244 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1167818 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 73358875 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.681233 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.330312 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 76528583 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.121291 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.621008 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26850978 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 36641611 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 11018000 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 937421 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1080572 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 523116 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 36832 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 63252649 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 110299 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1080572 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27872767 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 14726920 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18377517 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10342666 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4128139 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 59880890 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6989 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 638699 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1446922 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 40104744 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72926681 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72541237 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 385444 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 35232895 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4871841 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1468873 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 214348 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 11259122 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9368607 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6150188 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1144221 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 763596 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 53152910 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1825418 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 51980474 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 87912 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5962808 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3052808 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1237037 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 76528583 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.679230 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.328773 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 51151747 69.73% 69.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10102031 13.77% 83.50% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4555933 6.21% 89.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2996125 4.08% 93.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2381484 3.25% 97.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1187378 1.62% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 631915 0.86% 99.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 300208 0.41% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52054 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 53422858 69.81% 69.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10519380 13.75% 83.55% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4737419 6.19% 89.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3110993 4.07% 93.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2482363 3.24% 97.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1230781 1.61% 98.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 656198 0.86% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 315996 0.41% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 52595 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 73358875 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 76528583 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 82701 12.59% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 300975 45.82% 58.41% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 273171 41.59% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 81649 11.89% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 319979 46.59% 58.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 285231 41.53% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 34554089 69.14% 69.15% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 54830 0.11% 69.26% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.26% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15268 0.03% 69.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.29% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.30% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8894109 17.80% 87.09% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5667707 11.34% 98.43% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 782820 1.57% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3782 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35814992 68.90% 68.91% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57898 0.11% 69.02% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.02% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 15714 0.03% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9315059 17.92% 86.97% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5946213 11.44% 98.41% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 824933 1.59% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 49974476 # Type of FU issued -system.cpu0.iq.rate 0.499150 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 656847 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013144 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 173517181 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 58238103 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 48994356 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 520739 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 252277 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 246003 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 50355146 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 272403 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 532794 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 51980474 # Type of FU issued +system.cpu0.iq.rate 0.501010 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 686859 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013214 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 180712322 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 60686814 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50945996 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 551979 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 267326 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 260492 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 52374713 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 288838 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 545458 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1055829 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3465 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12581 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 434891 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1121947 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2762 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13266 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 454260 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18411 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 121190 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18544 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 124618 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1022606 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10355478 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 778603 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 55935625 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 586886 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8944130 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5848227 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1520110 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 566642 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4768 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12581 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 160372 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 334885 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 495257 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 49597141 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8604090 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 377334 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1080572 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10513662 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 794213 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 58228726 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 618999 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9368607 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6150188 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1608738 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 580049 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5099 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13266 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 168319 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 356582 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 524901 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51585627 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9008604 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 394846 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3133294 # number of nop insts executed -system.cpu0.iew.exec_refs 14226525 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7904799 # Number of branches executed -system.cpu0.iew.exec_stores 5622435 # Number of stores executed -system.cpu0.iew.exec_rate 0.495381 # Inst execution rate -system.cpu0.iew.wb_sent 49326582 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 49240359 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24624844 # num instructions producing a value -system.cpu0.iew.wb_consumers 33143444 # num instructions consuming a value +system.cpu0.iew.exec_nop 3250398 # number of nop insts executed +system.cpu0.iew.exec_refs 14908735 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8218209 # Number of branches executed +system.cpu0.iew.exec_stores 5900131 # Number of stores executed +system.cpu0.iew.exec_rate 0.497205 # Inst execution rate +system.cpu0.iew.wb_sent 51301062 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51206488 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25493361 # num instructions producing a value +system.cpu0.iew.wb_consumers 34352042 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.491818 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742978 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.493550 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.742121 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6108836 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 558055 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 462633 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 72336269 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.687326 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.603373 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6443785 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 588381 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 491234 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75448011 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.685042 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.601476 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 53637775 74.15% 74.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7794815 10.78% 84.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4279099 5.92% 90.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2307939 3.19% 94.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1284633 1.78% 95.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 537599 0.74% 96.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 458507 0.63% 97.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 423032 0.58% 97.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1612870 2.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 56013876 74.24% 74.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8117892 10.76% 85.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4422865 5.86% 90.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2392310 3.17% 94.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1343441 1.78% 95.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 564278 0.75% 96.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 477580 0.63% 97.20% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 442296 0.59% 97.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1673473 2.22% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 72336269 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 49718583 # Number of instructions committed -system.cpu0.commit.committedOps 49718583 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75448011 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51685042 # Number of instructions committed +system.cpu0.commit.committedOps 51685042 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13301637 # Number of memory references committed -system.cpu0.commit.loads 7888301 # Number of loads committed -system.cpu0.commit.membars 189589 # Number of memory barriers committed -system.cpu0.commit.branches 7515884 # Number of branches committed -system.cpu0.commit.fp_insts 243820 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 46055357 # Number of committed integer instructions. -system.cpu0.commit.function_calls 629203 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1612870 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13942588 # Number of memory references committed +system.cpu0.commit.loads 8246660 # Number of loads committed +system.cpu0.commit.membars 199926 # Number of memory barriers committed +system.cpu0.commit.branches 7810095 # Number of branches committed +system.cpu0.commit.fp_insts 258326 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47876421 # Number of committed integer instructions. +system.cpu0.commit.function_calls 664533 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1673473 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 126355419 # The number of ROB reads -system.cpu0.rob.rob_writes 112677687 # The number of ROB writes -system.cpu0.timesIdled 1033455 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26760242 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3701329669 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 46863203 # Number of Instructions Simulated -system.cpu0.committedOps 46863203 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 46863203 # Number of Instructions Simulated -system.cpu0.cpi 2.136412 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.136412 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.468074 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.468074 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 65361385 # number of integer regfile reads -system.cpu0.int_regfile_writes 35679513 # number of integer regfile writes -system.cpu0.fp_regfile_reads 120846 # number of floating regfile reads -system.cpu0.fp_regfile_writes 122066 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1631915 # number of misc regfile reads -system.cpu0.misc_regfile_writes 781460 # number of misc regfile writes +system.cpu0.rob.rob_reads 131700376 # The number of ROB reads +system.cpu0.rob.rob_writes 117338865 # The number of ROB writes +system.cpu0.timesIdled 1069961 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27222708 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3689125904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48725185 # Number of Instructions Simulated +system.cpu0.committedOps 48725185 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 48725185 # Number of Instructions Simulated +system.cpu0.cpi 2.129315 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.129315 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.469634 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.469634 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 67898060 # number of integer regfile reads +system.cpu0.int_regfile_writes 37063784 # number of integer regfile writes +system.cpu0.fp_regfile_reads 127956 # number of floating regfile reads +system.cpu0.fp_regfile_writes 129360 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1719000 # number of misc regfile reads +system.cpu0.misc_regfile_writes 824833 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -932,245 +932,245 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 828283 # number of replacements -system.cpu0.icache.tagsinuse 510.309737 # Cycle average of tags in use -system.cpu0.icache.total_refs 6629306 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 828795 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.998728 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 20510250000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.309737 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.996699 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.996699 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 6629306 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6629306 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6629306 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6629306 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6629306 # number of overall hits -system.cpu0.icache.overall_hits::total 6629306 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 870348 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 870348 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 870348 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 870348 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 870348 # number of overall misses -system.cpu0.icache.overall_misses::total 870348 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12313538494 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12313538494 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12313538494 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12313538494 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12313538494 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12313538494 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7499654 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7499654 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7499654 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7499654 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7499654 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7499654 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116052 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.116052 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116052 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.116052 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116052 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.116052 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14147.833388 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14147.833388 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14147.833388 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14147.833388 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14147.833388 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14147.833388 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3221 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1246 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 147 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 21.911565 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 623 # average number of cycles each access was blocked +system.cpu0.icache.replacements 889638 # number of replacements +system.cpu0.icache.tagsinuse 510.303457 # Cycle average of tags in use +system.cpu0.icache.total_refs 6872883 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 890147 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 7.721065 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 20517812000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.303457 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.996686 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996686 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 6872883 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6872883 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6872883 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6872883 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6872883 # number of overall hits +system.cpu0.icache.overall_hits::total 6872883 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 935512 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 935512 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 935512 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 935512 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 935512 # number of overall misses +system.cpu0.icache.overall_misses::total 935512 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13284271991 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13284271991 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13284271991 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13284271991 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13284271991 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13284271991 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7808395 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7808395 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7808395 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7808395 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7808395 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7808395 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119808 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.119808 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119808 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.119808 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119808 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.119808 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14200.001701 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14200.001701 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14200.001701 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14200.001701 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14200.001701 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14200.001701 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5547 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 2537 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 34.240741 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 845.666667 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41379 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 41379 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 41379 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 41379 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 41379 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 41379 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 828969 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 828969 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 828969 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 828969 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 828969 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 828969 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10141631994 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10141631994 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10141631994 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10141631994 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10141631994 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10141631994 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.110534 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.110534 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.110534 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.110534 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.110534 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.110534 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12234.030457 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12234.030457 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12234.030457 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12234.030457 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12234.030457 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12234.030457 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45203 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 45203 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 45203 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 45203 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 45203 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 45203 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 890309 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 890309 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 890309 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 890309 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 890309 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 890309 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10926647992 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10926647992 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10926647992 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10926647992 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10926647992 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10926647992 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.114019 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.114019 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.114019 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12272.871545 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12272.871545 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12272.871545 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1248455 # number of replacements -system.cpu0.dcache.tagsinuse 505.645673 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10073371 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1248967 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 8.065362 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1284134 # number of replacements +system.cpu0.dcache.tagsinuse 505.722211 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10611019 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1284646 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 8.259878 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 22124000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.645673 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.987589 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.987589 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6208704 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6208704 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3519183 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3519183 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 154511 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 154511 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 177820 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 177820 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9727887 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9727887 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9727887 # number of overall hits -system.cpu0.dcache.overall_hits::total 9727887 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1543041 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1543041 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1697976 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1697976 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19729 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19729 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3730 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3730 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3241017 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3241017 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3241017 # number of overall misses -system.cpu0.dcache.overall_misses::total 3241017 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 33524463000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 33524463000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 64948533233 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 64948533233 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 277752500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 277752500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 27309500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 27309500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 98472996233 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 98472996233 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 98472996233 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 98472996233 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7751745 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7751745 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5217159 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5217159 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 174240 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 174240 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 181550 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 181550 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12968904 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12968904 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12968904 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12968904 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199057 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.199057 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.325460 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.325460 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113229 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113229 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.020545 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.020545 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.249907 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.249907 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.249907 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.249907 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21726.229569 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 21726.229569 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38250.560216 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38250.560216 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14078.387146 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14078.387146 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7321.581769 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7321.581769 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30383.363072 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 30383.363072 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30383.363072 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 30383.363072 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2097721 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1192 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 47310 # number of cycles access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 505.722211 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.987739 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.987739 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6528989 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6528989 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3717707 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3717707 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164546 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 164546 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 188999 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 188999 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10246696 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10246696 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10246696 # number of overall hits +system.cpu0.dcache.overall_hits::total 10246696 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1596925 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1596925 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1771522 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1771522 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20418 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20418 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2763 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2763 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3368447 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3368447 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3368447 # number of overall misses +system.cpu0.dcache.overall_misses::total 3368447 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 34533208000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 34533208000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 68837486976 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 68837486976 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 293802000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 293802000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20678500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 20678500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 103370694976 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 103370694976 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 103370694976 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 103370694976 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8125914 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8125914 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5489229 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5489229 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 184964 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 184964 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191762 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 191762 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13615143 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13615143 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13615143 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13615143 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.196523 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.196523 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.322727 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.322727 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.110389 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.110389 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014408 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014408 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247404 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.247404 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247404 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.247404 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21624.815192 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21624.815192 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38857.822243 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38857.822243 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14389.362327 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14389.362327 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7484.075280 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7484.075280 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30687.938678 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 30687.938678 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30687.938678 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 30687.938678 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2260715 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 49054 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 44.339907 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 170.285714 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 46.086252 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 80 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 729852 # number of writebacks -system.cpu0.dcache.writebacks::total 729852 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 558383 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 558383 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432185 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1432185 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4312 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4312 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1990568 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1990568 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1990568 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1990568 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 984658 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 984658 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265791 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 265791 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15417 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15417 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3730 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3730 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1250449 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1250449 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1250449 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1250449 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21282308500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21282308500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9459587261 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9459587261 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170557000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170557000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 19849500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 19849500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30741895761 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 30741895761 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30741895761 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 30741895761 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1451668000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1451668000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2155602499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2155602499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3607270499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3607270499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127024 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127024 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050946 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050946 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088481 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088481 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.020545 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.020545 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096419 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.096419 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096419 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.096419 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21613.909093 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21613.909093 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35590.321948 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35590.321948 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11062.917559 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11062.917559 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5321.581769 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5321.581769 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24584.685790 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24584.685790 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24584.685790 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24584.685790 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 757117 # number of writebacks +system.cpu0.dcache.writebacks::total 757117 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 591865 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 591865 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1494302 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1494302 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4660 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4660 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2086167 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2086167 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2086167 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2086167 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1005060 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1005060 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 277220 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 277220 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15758 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15758 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2763 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2763 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1282280 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1282280 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1282280 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1282280 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21590310000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21590310000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10033221203 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10033221203 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 180646500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 180646500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 15152500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 15152500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31623531203 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 31623531203 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31623531203 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 31623531203 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465155500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465155500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2167706499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2167706499 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3632861999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3632861999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.123686 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.123686 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050503 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050503 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085195 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085195 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014408 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014408 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094180 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.094180 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094180 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.094180 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21481.613038 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21481.613038 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36192.270410 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36192.270410 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11463.796167 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11463.796167 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5484.075280 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5484.075280 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24661.954646 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24661.954646 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24661.954646 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24661.954646 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1178,35 +1178,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2951275 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2437405 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 83356 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1836683 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 994148 # Number of BTB hits +system.cpu1.branchPred.lookups 2374472 # Number of BP lookups +system.cpu1.branchPred.condPredicted 1973565 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 63683 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1357670 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 789569 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 54.127359 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 203977 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 9132 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 58.156179 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 159848 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 6979 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2175721 # DTB read hits -system.cpu1.dtb.read_misses 10990 # DTB read misses -system.cpu1.dtb.read_acv 22 # DTB read access violations -system.cpu1.dtb.read_accesses 324709 # DTB read accesses -system.cpu1.dtb.write_hits 1432957 # DTB write hits -system.cpu1.dtb.write_misses 2208 # DTB write misses -system.cpu1.dtb.write_acv 64 # DTB write access violations -system.cpu1.dtb.write_accesses 133156 # DTB write accesses -system.cpu1.dtb.data_hits 3608678 # DTB hits -system.cpu1.dtb.data_misses 13198 # DTB misses -system.cpu1.dtb.data_acv 86 # DTB access violations -system.cpu1.dtb.data_accesses 457865 # DTB accesses -system.cpu1.itb.fetch_hits 458401 # ITB hits -system.cpu1.itb.fetch_misses 7664 # ITB misses -system.cpu1.itb.fetch_acv 238 # ITB acv -system.cpu1.itb.fetch_accesses 466065 # ITB accesses +system.cpu1.dtb.read_hits 1755569 # DTB read hits +system.cpu1.dtb.read_misses 9259 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 277737 # DTB read accesses +system.cpu1.dtb.write_hits 1124169 # DTB write hits +system.cpu1.dtb.write_misses 1775 # DTB write misses +system.cpu1.dtb.write_acv 38 # DTB write access violations +system.cpu1.dtb.write_accesses 104346 # DTB write accesses +system.cpu1.dtb.data_hits 2879738 # DTB hits +system.cpu1.dtb.data_misses 11034 # DTB misses +system.cpu1.dtb.data_acv 44 # DTB access violations +system.cpu1.dtb.data_accesses 382083 # DTB accesses +system.cpu1.itb.fetch_hits 378886 # ITB hits +system.cpu1.itb.fetch_misses 5643 # ITB misses +system.cpu1.itb.fetch_acv 144 # ITB acv +system.cpu1.itb.fetch_accesses 384529 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1219,508 +1219,512 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 18142763 # number of cpu cycles simulated +system.cpu1.numCycles 14403389 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 7059665 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 13904860 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2951275 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1198125 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2489767 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 435348 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 7028149 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 27735 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 66683 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 53717 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1666090 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 56854 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 17001992 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.817837 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.192062 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 5507969 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 11118541 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2374472 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 949417 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1985955 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 349018 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 5777579 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 25749 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 54503 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 55745 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 7 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1323443 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 42238 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 13629786 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.815753 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.191288 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 14512225 85.36% 85.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 164132 0.97% 86.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 264549 1.56% 87.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 196224 1.15% 89.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 340931 2.01% 91.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 130664 0.77% 91.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 146583 0.86% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 247056 1.45% 94.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 999628 5.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 11643831 85.43% 85.43% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 125140 0.92% 86.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 217081 1.59% 87.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 155934 1.14% 89.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 266080 1.95% 91.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 106134 0.78% 91.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 117650 0.86% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 192941 1.42% 94.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 804995 5.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 17001992 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.162670 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.766414 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 6935204 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 7342187 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2328189 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 128213 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 268198 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 130237 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 8176 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 13648246 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 24564 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 268198 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 7169583 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 530321 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6090332 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2220482 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 723074 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 12659443 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 62425 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 176745 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 8295078 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 15050859 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 14876046 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 174813 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 7154813 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1140265 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 506846 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 51390 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2247067 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2298271 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1513317 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 213048 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 119189 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 11099753 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 565057 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 10829119 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 31632 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1536258 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 758334 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 401417 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 17001992 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.636932 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.310611 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 13629786 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.164855 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.771939 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5440584 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6013692 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1859543 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 99467 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 216499 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 99353 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 5852 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 10916304 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 17556 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 216499 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5632614 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 346968 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5076489 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1765081 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 592133 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 10097386 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 38 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 55596 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 134498 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 6632848 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 12019300 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 11877082 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 142218 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5717715 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 915133 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 422143 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 38586 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1845577 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1850340 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1191384 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 164933 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 85198 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 8855097 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 461396 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 8635428 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 27588 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1251794 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 621930 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 331901 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 13629786 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.633570 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.306468 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 12225446 71.91% 71.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2205450 12.97% 84.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 929224 5.47% 90.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 621702 3.66% 94.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 537509 3.16% 97.16% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 242497 1.43% 98.59% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 153407 0.90% 99.49% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 76904 0.45% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 9853 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 9807862 71.96% 71.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1774840 13.02% 84.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 743934 5.46% 90.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 492954 3.62% 94.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 425816 3.12% 97.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 193635 1.42% 98.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 119802 0.88% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 63937 0.47% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 7006 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 17001992 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 13629786 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3913 1.80% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 115549 53.23% 55.03% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 97618 44.97% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2819 1.60% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 95112 53.88% 55.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 78586 44.52% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 6756968 62.40% 62.43% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 17928 0.17% 62.59% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11481 0.11% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.70% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2278200 21.04% 83.75% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1457808 13.46% 97.22% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 301445 2.78% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5368636 62.17% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 14579 0.17% 62.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.38% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10813 0.13% 62.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1836056 21.26% 83.79% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1146030 13.27% 97.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 254037 2.94% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 10829119 # Type of FU issued -system.cpu1.iq.rate 0.596884 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 217080 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020046 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 38657394 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 13080099 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 10523969 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 251548 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 122819 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 119141 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 10911695 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 130978 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 103489 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 8635428 # Type of FU issued +system.cpu1.iq.rate 0.599541 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 176517 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020441 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 30899211 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 10469267 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8392820 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 205536 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 100351 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 97198 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 8701253 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 107174 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 85247 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 301882 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 508 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1924 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 130297 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 244767 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 715 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1400 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 111607 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 383 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 9692 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 264 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 8613 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 268198 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 347966 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 52179 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 12265641 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 165598 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2298271 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1513317 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 508976 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 44383 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2331 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1924 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 37819 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 111790 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 149609 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 10726333 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2195343 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 102786 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 216499 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 208020 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 39541 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 9780313 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 131211 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1850340 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1191384 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 418145 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 33976 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1692 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1400 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 28557 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 89287 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 117844 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 8559872 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1771461 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 75556 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 600831 # number of nop insts executed -system.cpu1.iew.exec_refs 3637407 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1609945 # Number of branches executed -system.cpu1.iew.exec_stores 1442064 # Number of stores executed -system.cpu1.iew.exec_rate 0.591218 # Inst execution rate -system.cpu1.iew.wb_sent 10671459 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 10643110 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4954176 # num instructions producing a value -system.cpu1.iew.wb_consumers 6965889 # num instructions consuming a value +system.cpu1.iew.exec_nop 463820 # number of nop insts executed +system.cpu1.iew.exec_refs 2903123 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1270722 # Number of branches executed +system.cpu1.iew.exec_stores 1131662 # Number of stores executed +system.cpu1.iew.exec_rate 0.594296 # Inst execution rate +system.cpu1.iew.wb_sent 8515413 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8490018 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 3998147 # num instructions producing a value +system.cpu1.iew.wb_consumers 5641896 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.586631 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.711205 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.589446 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.708653 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1581528 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 163640 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 139954 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 16733794 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.633013 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.579692 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1285480 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 129495 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 111745 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 13413287 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.628190 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.573982 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 12789139 76.43% 76.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1829893 10.94% 87.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 688745 4.12% 91.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 420012 2.51% 93.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 300647 1.80% 95.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 117990 0.71% 96.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 119790 0.72% 97.21% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 126616 0.76% 97.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 340962 2.04% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10261662 76.50% 76.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1478959 11.03% 87.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 542849 4.05% 91.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 333012 2.48% 94.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 234215 1.75% 95.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 91771 0.68% 96.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 99946 0.75% 97.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 99972 0.75% 97.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 270901 2.02% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 16733794 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 10592705 # Number of instructions committed -system.cpu1.commit.committedOps 10592705 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 13413287 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8426096 # Number of instructions committed +system.cpu1.commit.committedOps 8426096 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3379409 # Number of memory references committed -system.cpu1.commit.loads 1996389 # Number of loads committed -system.cpu1.commit.membars 53397 # Number of memory barriers committed -system.cpu1.commit.branches 1516939 # Number of branches committed -system.cpu1.commit.fp_insts 117937 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 9798676 # Number of committed integer instructions. -system.cpu1.commit.function_calls 169964 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 340962 # number cycles where commit BW limit reached +system.cpu1.commit.refs 2685350 # Number of memory references committed +system.cpu1.commit.loads 1605573 # Number of loads committed +system.cpu1.commit.membars 41432 # Number of memory barriers committed +system.cpu1.commit.branches 1197085 # Number of branches committed +system.cpu1.commit.fp_insts 95994 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 7795496 # Number of committed integer instructions. +system.cpu1.commit.function_calls 132738 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 270901 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 28474562 # The number of ROB reads -system.cpu1.rob.rob_writes 24615096 # The number of ROB writes -system.cpu1.timesIdled 153586 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1140771 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3782727730 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 10062016 # Number of Instructions Simulated -system.cpu1.committedOps 10062016 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 10062016 # Number of Instructions Simulated -system.cpu1.cpi 1.803094 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.803094 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.554602 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.554602 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 13798564 # number of integer regfile reads -system.cpu1.int_regfile_writes 7546386 # number of integer regfile writes -system.cpu1.fp_regfile_reads 63884 # number of floating regfile reads -system.cpu1.fp_regfile_writes 63971 # number of floating regfile writes -system.cpu1.misc_regfile_reads 608483 # number of misc regfile reads -system.cpu1.misc_regfile_writes 251084 # number of misc regfile writes -system.cpu1.icache.replacements 263412 # number of replacements -system.cpu1.icache.tagsinuse 470.047023 # Cycle average of tags in use -system.cpu1.icache.total_refs 1392951 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 263924 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 5.277849 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1875177958000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 470.047023 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.918061 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.918061 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 1392951 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1392951 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1392951 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1392951 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1392951 # number of overall hits -system.cpu1.icache.overall_hits::total 1392951 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 273139 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 273139 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 273139 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 273139 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 273139 # number of overall misses -system.cpu1.icache.overall_misses::total 273139 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3753112000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3753112000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3753112000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3753112000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3753112000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3753112000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1666090 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1666090 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1666090 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1666090 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1666090 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1666090 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.163940 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.163940 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.163940 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.163940 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.163940 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.163940 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13740.666840 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13740.666840 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13740.666840 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13740.666840 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13740.666840 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13740.666840 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 264 # number of cycles access was blocked +system.cpu1.rob.rob_reads 22771832 # The number of ROB reads +system.cpu1.rob.rob_writes 19637981 # The number of ROB writes +system.cpu1.timesIdled 118769 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 773603 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3777797828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8011939 # Number of Instructions Simulated +system.cpu1.committedOps 8011939 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 8011939 # Number of Instructions Simulated +system.cpu1.cpi 1.797741 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.797741 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.556254 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.556254 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 11010177 # number of integer regfile reads +system.cpu1.int_regfile_writes 6039470 # number of integer regfile writes +system.cpu1.fp_regfile_reads 53089 # number of floating regfile reads +system.cpu1.fp_regfile_writes 52904 # number of floating regfile writes +system.cpu1.misc_regfile_reads 494875 # number of misc regfile reads +system.cpu1.misc_regfile_writes 202385 # number of misc regfile writes +system.cpu1.icache.replacements 202443 # number of replacements +system.cpu1.icache.tagsinuse 470.727745 # Cycle average of tags in use +system.cpu1.icache.total_refs 1113774 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 202955 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 5.487788 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1886714019000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 470.727745 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.919390 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.919390 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1113774 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1113774 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1113774 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1113774 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1113774 # number of overall hits +system.cpu1.icache.overall_hits::total 1113774 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 209669 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 209669 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 209669 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 209669 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 209669 # number of overall misses +system.cpu1.icache.overall_misses::total 209669 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2812457500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2812457500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2812457500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2812457500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2812457500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2812457500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1323443 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1323443 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1323443 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1323443 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1323443 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1323443 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.158427 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.158427 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.158427 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.158427 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.158427 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.158427 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13413.797462 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13413.797462 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13413.797462 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13413.797462 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13413.797462 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13413.797462 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 72 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.666667 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9144 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 9144 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 9144 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 9144 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 9144 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 9144 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 263995 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 263995 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 263995 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 263995 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 263995 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 263995 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3126547000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3126547000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3126547000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3126547000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3126547000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3126547000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.158452 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.158452 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.158452 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.158452 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.158452 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.158452 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11843.205364 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11843.205364 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11843.205364 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11843.205364 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11843.205364 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11843.205364 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6654 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 6654 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 6654 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 6654 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 6654 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 6654 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 203015 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 203015 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 203015 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 203015 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 203015 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 203015 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2347033500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2347033500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2347033500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2347033500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2347033500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2347033500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.153399 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.153399 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.153399 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.153399 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.153399 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.153399 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11560.887127 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11560.887127 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11560.887127 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 126526 # number of replacements -system.cpu1.dcache.tagsinuse 490.827782 # Cycle average of tags in use -system.cpu1.dcache.total_refs 2952051 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 126931 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 23.257132 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 37142562000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 490.827782 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.958648 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.958648 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1783702 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1783702 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1082593 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1082593 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 39936 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 39936 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 38619 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 38619 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2866295 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2866295 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2866295 # number of overall hits -system.cpu1.dcache.overall_hits::total 2866295 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 242985 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 242985 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 251423 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 251423 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 6626 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 6626 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3957 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3957 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 494408 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 494408 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 494408 # number of overall misses -system.cpu1.dcache.overall_misses::total 494408 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3665622000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3665622000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8223225631 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 8223225631 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 67675500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 67675500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 29039500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 29039500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 11888847631 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 11888847631 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 11888847631 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 11888847631 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2026687 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2026687 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1334016 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1334016 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 46562 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 46562 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 42576 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 42576 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3360703 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3360703 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3360703 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3360703 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.119893 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.119893 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188471 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.188471 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.142305 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.142305 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092940 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092940 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.147114 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.147114 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.147114 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.147114 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15085.795419 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15085.795419 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32706.735784 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32706.735784 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10213.628132 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10213.628132 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7338.766742 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7338.766742 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24046.632803 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 24046.632803 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24046.632803 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24046.632803 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 255815 # number of cycles access was blocked +system.cpu1.dcache.replacements 95898 # number of replacements +system.cpu1.dcache.tagsinuse 491.044785 # Cycle average of tags in use +system.cpu1.dcache.total_refs 2359205 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 96213 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 24.520647 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 39003208000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 491.044785 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.959072 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.959072 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1444297 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1444297 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 860369 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 860369 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29709 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 29709 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 28445 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 28445 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2304666 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2304666 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2304666 # number of overall hits +system.cpu1.dcache.overall_hits::total 2304666 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 191100 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 191100 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 182257 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 182257 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4958 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4958 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3002 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3002 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 373357 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 373357 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 373357 # number of overall misses +system.cpu1.dcache.overall_misses::total 373357 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2726429000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2726429000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5605304282 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5605304282 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 50865000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 50865000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22043000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 22043000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8331733282 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8331733282 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8331733282 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8331733282 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1635397 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1635397 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1042626 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1042626 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 34667 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 34667 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 31447 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 31447 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2678023 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2678023 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2678023 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2678023 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.116852 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.116852 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.174806 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.174806 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.143018 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.143018 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095462 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095462 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.139415 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.139415 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.139415 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.139415 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14267.027734 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14267.027734 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30754.946488 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30754.946488 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10259.177088 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10259.177088 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7342.771486 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7342.771486 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22315.728062 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 22315.728062 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22315.728062 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 22315.728062 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 178298 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3992 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3033 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 64.081914 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 58.786020 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 84886 # number of writebacks -system.cpu1.dcache.writebacks::total 84886 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 150812 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 150812 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 205594 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 205594 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 644 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 644 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 356406 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 356406 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 356406 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 356406 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 92173 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 92173 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 45829 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 45829 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5982 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5982 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3957 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3957 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 138002 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 138002 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 138002 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 138002 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1122474000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1122474000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1228877987 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1228877987 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 47579000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 47579000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 21125500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 21125500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2351351987 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2351351987 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2351351987 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2351351987 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30976000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30976000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 675219000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 675219000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 706195000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 706195000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.045480 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.045480 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034354 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034354 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128474 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128474 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092940 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092940 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041063 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.041063 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041063 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.041063 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12177.904592 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12177.904592 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26814.418534 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26814.418534 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7953.694417 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7953.694417 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5338.766742 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5338.766742 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17038.535579 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17038.535579 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17038.535579 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17038.535579 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 62482 # number of writebacks +system.cpu1.dcache.writebacks::total 62482 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 119560 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 119560 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 148811 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 148811 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 417 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 417 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 268371 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 268371 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 268371 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 268371 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 71540 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 71540 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 33446 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 33446 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4541 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4541 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3000 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3000 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 104986 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 104986 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 104986 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 104986 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 843257000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 843257000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 841845993 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 841845993 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 36401500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 36401500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16047000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16047000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1685102993 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1685102993 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1685102993 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1685102993 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18098500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18098500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 603885500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 603885500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 621984000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 621984000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043745 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043745 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032079 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032079 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.130989 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.130989 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095399 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095399 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039203 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.039203 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039203 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.039203 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11787.209952 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11787.209952 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25170.304162 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25170.304162 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8016.185862 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8016.185862 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5349 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5349 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16050.740032 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16050.740032 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16050.740032 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16050.740032 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1729,170 +1733,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6610 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 175912 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 61740 40.36% 40.36% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.45% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1928 1.26% 41.71% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 255 0.17% 41.88% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 88907 58.12% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 152961 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 60876 49.17% 49.17% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1928 1.56% 50.83% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 255 0.21% 51.04% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 60621 48.96% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 123811 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1865672058500 98.16% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 62377000 0.00% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 564179500 0.03% 98.19% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 124028500 0.01% 98.20% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 34304214500 1.80% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1900726858000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.986006 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6633 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 185817 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65566 40.59% 40.59% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1923 1.19% 41.86% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 201 0.12% 41.99% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 93709 58.01% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 161530 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64589 49.22% 49.22% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1923 1.47% 50.78% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 201 0.15% 50.94% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 64388 49.06% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 131232 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1860847795500 98.12% 98.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 64543000 0.00% 98.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 567978500 0.03% 98.16% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 98193500 0.01% 98.16% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 34862560000 1.84% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1896441070500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.985099 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.681847 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.809429 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed -system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed -system.cpu0.kern.syscall::6 29 14.36% 27.72% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.50% 28.22% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.46% 32.67% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.47% 36.14% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.98% 38.12% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.50% 38.61% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.49% 40.10% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.47% 43.56% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.99% 44.55% # number of syscalls executed -system.cpu0.kern.syscall::45 34 16.83% 61.39% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.49% 62.87% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.96% 66.83% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.46% 71.29% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.50% 71.78% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.48% 74.26% # number of syscalls executed -system.cpu0.kern.syscall::71 25 12.38% 86.63% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.49% 88.12% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.97% 91.09% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.50% 91.58% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.99% 92.57% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.47% 96.04% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.99% 97.03% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.99% 98.02% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.50% 98.51% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.50% 99.01% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.99% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 202 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.687106 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.812431 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed +system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 359 0.22% 0.22% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.22% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.22% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.23% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3342 2.08% 2.30% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.33% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.33% # number of callpals executed -system.cpu0.kern.callpal::swpipl 146221 90.79% 93.12% # number of callpals executed -system.cpu0.kern.callpal::rdps 6169 3.83% 96.95% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 96.96% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed -system.cpu0.kern.callpal::rti 4425 2.75% 99.71% # number of callpals executed -system.cpu0.kern.callpal::callsys 333 0.21% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 161059 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6926 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1257 # number of protection mode switches +system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3552 2.08% 2.25% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.28% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed +system.cpu0.kern.callpal::swpipl 154681 90.79% 93.08% # number of callpals executed +system.cpu0.kern.callpal::rdps 6653 3.90% 96.98% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.98% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.98% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.99% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::rti 4593 2.70% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.23% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 170374 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7193 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1256 -system.cpu0.kern.mode_good::user 1257 +system.cpu0.kern.mode_good::kernel 1369 +system.cpu0.kern.mode_good::user 1370 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.181346 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.190324 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.307100 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1898828643000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1898207000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.319865 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1894375479500 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2065583000 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3343 # number of times the context was actually changed +system.cpu0.kern.swap_context 3553 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2523 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 64668 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 20885 37.61% 37.61% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1927 3.47% 41.08% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 359 0.65% 41.72% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 32365 58.28% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 55536 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 20372 47.74% 47.74% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1927 4.52% 52.26% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 359 0.84% 53.10% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 20014 46.90% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 42672 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1875010715500 98.66% 98.66% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 532408500 0.03% 98.69% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 162327000 0.01% 98.70% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 24731034000 1.30% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1900436485000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.975437 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2383 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 53842 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 16791 36.23% 36.23% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1921 4.14% 40.37% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 284 0.61% 40.99% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 27352 59.01% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 46348 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16391 47.23% 47.23% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1921 5.54% 52.77% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 284 0.82% 53.59% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 16107 46.41% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 34703 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1871184919000 98.69% 98.69% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 531151500 0.03% 98.71% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 127549500 0.01% 98.72% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 24258165000 1.28% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1896101785000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.976178 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.618384 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.768366 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed -system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed -system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.81% 23.39% # number of syscalls executed -system.cpu1.kern.syscall::17 6 4.84% 28.23% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.42% 30.65% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.61% 32.26% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.42% 34.68% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.42% 37.10% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.23% 40.32% # number of syscalls executed -system.cpu1.kern.syscall::45 20 16.13% 56.45% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.42% 58.87% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.61% 60.48% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.81% 61.29% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.61% 62.90% # number of syscalls executed -system.cpu1.kern.syscall::71 29 23.39% 86.29% # number of syscalls executed -system.cpu1.kern.syscall::74 10 8.06% 94.35% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.81% 95.16% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.61% 96.77% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.42% 99.19% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 124 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.588878 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.748749 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed +system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed +system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed +system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 255 0.44% 0.44% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.45% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1393 2.41% 2.86% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.87% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.88% # number of callpals executed -system.cpu1.kern.callpal::swpipl 49964 86.52% 89.41% # number of callpals executed -system.cpu1.kern.callpal::rdps 2595 4.49% 93.90% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.90% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.91% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.91% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.91% # number of callpals executed -system.cpu1.kern.callpal::rti 3286 5.69% 99.61% # number of callpals executed -system.cpu1.kern.callpal::callsys 184 0.32% 99.92% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.07% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 201 0.42% 0.42% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.43% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.43% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1067 2.24% 2.67% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 2.67% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.69% # number of callpals executed +system.cpu1.kern.callpal::swpipl 41171 86.33% 89.01% # number of callpals executed +system.cpu1.kern.callpal::rdps 2098 4.40% 93.41% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% 93.42% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed +system.cpu1.kern.callpal::rti 2971 6.23% 99.66% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.25% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 57746 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1619 # number of protection mode switches -system.cpu1.kern.mode_switch::user 488 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2559 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 771 -system.cpu1.kern.mode_good::user 488 -system.cpu1.kern.mode_good::idle 283 -system.cpu1.kern.mode_switch_good::kernel 0.476220 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 47692 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1242 # number of protection mode switches +system.cpu1.kern.mode_switch::user 368 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2406 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 576 +system.cpu1.kern.mode_good::user 368 +system.cpu1.kern.mode_good::idle 208 +system.cpu1.kern.mode_switch_good::kernel 0.463768 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.110590 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.330476 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 5768410500 0.30% 0.30% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 833727500 0.04% 0.35% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893823776000 99.65% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1394 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.086451 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.286853 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4070064000 0.21% 0.21% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 689483000 0.04% 0.25% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1891020032000 99.75% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1068 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 46893c808..d2daed3ce 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -12,15 +12,15 @@ children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_dis boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 clock=1000 -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -107,6 +107,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -520,7 +521,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -540,7 +541,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -647,7 +648,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index f7cc8bd0e..1410f747e 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.854316 # Number of seconds simulated -sim_ticks 1854315933000 # Number of ticks simulated -final_tick 1854315933000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1854315535000 # Number of ticks simulated +final_tick 1854315535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49330 # Simulator instruction rate (inst/s) -host_op_rate 49330 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1727408560 # Simulator tick rate (ticks/s) -host_mem_usage 351576 # Number of bytes of host memory used -host_seconds 1073.47 # Real time elapsed on the host -sim_insts 52953842 # Number of instructions simulated -sim_ops 52953842 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 964736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879104 # Number of bytes read from this memory +host_inst_rate 136218 # Simulator instruction rate (inst/s) +host_op_rate 136218 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4770234092 # Simulator tick rate (ticks/s) +host_mem_usage 308432 # Number of bytes of host memory used +host_seconds 388.73 # Real time elapsed on the host +sim_insts 52951550 # Number of instructions simulated +sim_ops 52951550 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 963520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24877248 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28496192 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 964736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 964736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7502848 # Number of bytes written to this memory -system.physmem.bytes_written::total 7502848 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15074 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388736 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28493120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 963520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 963520 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7502080 # Number of bytes written to this memory +system.physmem.bytes_written::total 7502080 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15055 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388707 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445253 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117232 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117232 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13416864 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 445205 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117220 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117220 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 519610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13415866 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 1430367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15367496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520265 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520265 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4046154 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4046154 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4046154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520265 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13416864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 15365842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 519610 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 519610 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4045741 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4045741 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4045741 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 519610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13415866 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1430367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19413650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445253 # Total number of read requests seen -system.physmem.writeReqs 117232 # Total number of write requests seen -system.physmem.cpureqs 562681 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28496192 # Total number of bytes read from memory -system.physmem.bytesWritten 7502848 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28496192 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7502848 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 65 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 180 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28014 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27757 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27571 # Track reads on a per bank basis +system.physmem.bw_total::total 19411583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445205 # Total number of read requests seen +system.physmem.writeReqs 117220 # Total number of write requests seen +system.physmem.cpureqs 562608 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28493120 # Total number of bytes read from memory +system.physmem.bytesWritten 7502080 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28493120 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7502080 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28016 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27755 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27572 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 27335 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27900 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27985 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27992 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27903 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27978 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27988 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 27793 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28084 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27816 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27970 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27741 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27761 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27965 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27782 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27722 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7549 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7292 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7139 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6981 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7370 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis +system.physmem.perBankRdReqs::8 28085 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27815 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27957 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27734 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27759 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27962 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27777 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27720 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7553 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7293 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7144 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6986 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7373 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7381 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 7449 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7331 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7642 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7358 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7506 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7213 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7258 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7375 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7186 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7197 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7333 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7646 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7356 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7497 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7211 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7256 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7369 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7178 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7195 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 16 # Number of times wr buffer was full causing retry -system.physmem.totGap 1854310455000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry +system.physmem.totGap 1854310136000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445253 # Categorize read packet sizes +system.physmem.readPktSize::6 445205 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 117232 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 323581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2688 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 921 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 765 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117220 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 323472 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7533 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2976 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2727 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2719 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1449 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1411 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 792 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -128,46 +128,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5088 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 5097 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 5097 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see -system.physmem.totQLat 7494847250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15211767250 # Sum of mem lat for all requests -system.physmem.totBusLat 2225940000 # Total cycles spent in databus access -system.physmem.totBankLat 5490980000 # Total cycles spent in bank access -system.physmem.avgQLat 16835.24 # Average queueing delay per request -system.physmem.avgBankLat 12334.07 # Average bank access latency per request +system.physmem.wrQLenPdf::12 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see +system.physmem.totQLat 7478299000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15194295250 # Sum of mem lat for all requests +system.physmem.totBusLat 2225745000 # Total cycles spent in databus access +system.physmem.totBankLat 5490251250 # Total cycles spent in bank access +system.physmem.avgQLat 16799.54 # Average queueing delay per request +system.physmem.avgBankLat 12333.51 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 34169.31 # Average memory access latency +system.physmem.avgMemAccLat 34133.05 # Average memory access latency system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s @@ -175,21 +175,21 @@ system.physmem.avgConsumedWrBW 4.05 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 12.10 # Average write queue length over time -system.physmem.readRowHits 417708 # Number of row buffer hits during reads -system.physmem.writeRowHits 91270 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.85 # Row buffer hit rate for writes -system.physmem.avgGap 3296639.83 # Average gap between requests +system.physmem.avgWrQLen 7.57 # Average write queue length over time +system.physmem.readRowHits 417721 # Number of row buffer hits during reads +system.physmem.writeRowHits 91342 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.92 # Row buffer hit rate for writes +system.physmem.avgGap 3296990.95 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.265086 # Cycle average of tags in use +system.iocache.tagsinuse 1.265062 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1704475467000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.265086 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079068 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079068 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1704476481000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.265062 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -200,12 +200,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10643328423 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10643328423 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10664256421 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10664256421 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10664256421 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10664256421 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10641558911 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10641558911 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10662486909 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10662486909 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10662486909 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10662486909 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -224,17 +224,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256144.792621 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 256144.792621 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255584.336034 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255584.336034 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255584.336034 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255584.336034 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 284060 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256102.207138 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256102.207138 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255541.927118 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255541.927118 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255541.927118 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255541.927118 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 285704 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27214 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27220 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.438010 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.496106 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -250,12 +250,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8481334185 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8481334185 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8493265434 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8493265434 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8493265434 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8493265434 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8479547437 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8479547437 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8491478686 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8491478686 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8491478686 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8491478686 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -266,12 +266,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204113.741456 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204113.741456 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203553.395662 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203553.395662 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203553.395662 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203553.395662 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204070.741168 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204070.741168 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203510.573661 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203510.573661 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203510.573661 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203510.573661 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -285,35 +285,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13854129 # Number of BP lookups -system.cpu.branchPred.condPredicted 11621858 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 400402 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9160821 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5815827 # Number of BTB hits +system.cpu.branchPred.lookups 13835452 # Number of BP lookups +system.cpu.branchPred.condPredicted 11604498 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 397875 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9360236 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5805061 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 63.485871 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 906747 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 38946 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 62.018319 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 907052 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 38979 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9920210 # DTB read hits -system.cpu.dtb.read_misses 41076 # DTB read misses -system.cpu.dtb.read_acv 544 # DTB read access violations -system.cpu.dtb.read_accesses 941527 # DTB read accesses -system.cpu.dtb.write_hits 6593814 # DTB write hits -system.cpu.dtb.write_misses 10775 # DTB write misses -system.cpu.dtb.write_acv 404 # DTB write access violations -system.cpu.dtb.write_accesses 338229 # DTB write accesses -system.cpu.dtb.data_hits 16514024 # DTB hits -system.cpu.dtb.data_misses 51851 # DTB misses -system.cpu.dtb.data_acv 948 # DTB access violations -system.cpu.dtb.data_accesses 1279756 # DTB accesses -system.cpu.itb.fetch_hits 1305070 # ITB hits -system.cpu.itb.fetch_misses 36981 # ITB misses -system.cpu.itb.fetch_acv 1089 # ITB acv -system.cpu.itb.fetch_accesses 1342051 # ITB accesses +system.cpu.dtb.read_hits 9913942 # DTB read hits +system.cpu.dtb.read_misses 41971 # DTB read misses +system.cpu.dtb.read_acv 559 # DTB read access violations +system.cpu.dtb.read_accesses 941163 # DTB read accesses +system.cpu.dtb.write_hits 6591840 # DTB write hits +system.cpu.dtb.write_misses 10659 # DTB write misses +system.cpu.dtb.write_acv 411 # DTB write access violations +system.cpu.dtb.write_accesses 337869 # DTB write accesses +system.cpu.dtb.data_hits 16505782 # DTB hits +system.cpu.dtb.data_misses 52630 # DTB misses +system.cpu.dtb.data_acv 970 # DTB access violations +system.cpu.dtb.data_accesses 1279032 # DTB accesses +system.cpu.itb.fetch_hits 1304387 # ITB hits +system.cpu.itb.fetch_misses 38101 # ITB misses +system.cpu.itb.fetch_acv 1094 # ITB acv +system.cpu.itb.fetch_accesses 1342488 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -326,99 +326,99 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 108723981 # number of cpu cycles simulated +system.cpu.numCycles 108709176 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28071835 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70691782 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13854129 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6722574 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13248795 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1991444 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37396273 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32851 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 253900 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 295773 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 814 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8551942 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 266251 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80590196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.877176 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.220882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28075681 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70625770 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13835452 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6712113 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13231336 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1982002 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37359508 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 254255 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 361301 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 440 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8540739 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 263307 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80598838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.876263 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.220111 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67341401 83.56% 83.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 854251 1.06% 84.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1698632 2.11% 86.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 828031 1.03% 87.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2750245 3.41% 91.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 562298 0.70% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 643304 0.80% 92.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1012392 1.26% 93.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4899642 6.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67367502 83.58% 83.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 852306 1.06% 84.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1694888 2.10% 86.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 821828 1.02% 87.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2746821 3.41% 91.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 564765 0.70% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 643702 0.80% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1011325 1.25% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4895701 6.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80590196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.127425 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.650195 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29205934 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37061149 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12112258 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 963051 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1247803 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 585584 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42566 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69386312 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 128816 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1247803 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30327018 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13624252 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19779589 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11347768 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4263764 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65637148 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6817 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 509709 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1485643 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43822331 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79670452 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79191261 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479191 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38158982 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5663341 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1681975 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239504 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12131366 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10436836 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6902083 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1326454 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 859310 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58185317 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2050283 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56802944 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 107134 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6922426 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3549333 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1389358 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80590196 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.704837 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.365985 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80598838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.127270 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.649676 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29246161 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37051175 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12098296 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 961855 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1241350 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 583461 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42570 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69332672 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129212 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1241350 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30366961 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13601503 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19800886 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11334089 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4254047 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65583694 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7011 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 505967 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1480663 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43793573 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79610392 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79131107 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479285 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38157493 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5636072 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682036 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239674 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12118674 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10434139 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6898397 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1310169 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 877649 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58153519 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2049469 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56771792 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 109314 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6892902 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3544978 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1388546 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80598838 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.704375 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.365163 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55946315 69.42% 69.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10805415 13.41% 82.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5162410 6.41% 89.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3384715 4.20% 93.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2645600 3.28% 96.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1461420 1.81% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 757318 0.94% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 330868 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 96135 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55952160 69.42% 69.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10819456 13.42% 82.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5161521 6.40% 89.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3379007 4.19% 93.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2642777 3.28% 96.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1459621 1.81% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 760708 0.94% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 329892 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 93696 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80590196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80598838 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91816 11.60% 11.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91294 11.60% 11.60% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 11.60% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 11.60% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.60% # attempts to use FU when none available @@ -447,148 +447,148 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.60% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.60% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.60% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 373288 47.16% 58.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326368 41.24% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 373063 47.40% 59.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 322658 41.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38732288 68.19% 68.20% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61693 0.11% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38708062 68.18% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61690 0.11% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10350848 18.22% 86.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6672590 11.75% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 948996 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10346391 18.22% 86.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6670119 11.75% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949001 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56802944 # Type of FU issued -system.cpu.iq.rate 0.522451 # Inst issue rate -system.cpu.iq.fu_busy_cnt 791472 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013934 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194402098 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66835363 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55566146 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692591 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336490 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327919 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57225685 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361445 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 601434 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56771792 # Type of FU issued +system.cpu.iq.rate 0.522236 # Inst issue rate +system.cpu.iq.fu_busy_cnt 787015 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013863 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194345553 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66772978 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55538078 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 693197 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336730 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327888 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57189578 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361943 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 597316 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1348949 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4999 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14153 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 526604 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1346178 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3275 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14144 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 522891 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17963 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 174400 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17954 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 174426 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1247803 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9948703 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684680 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63760053 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 677795 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10436836 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6902083 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1805728 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512612 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18477 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14153 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 203761 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412011 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 615772 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56335729 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9989502 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 467214 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1241350 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9930800 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684897 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63726259 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 676325 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10434139 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6898397 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1805166 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512910 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18627 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14144 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 201347 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411340 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 612687 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56305820 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9984116 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 465971 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3524453 # number of nop insts executed -system.cpu.iew.exec_refs 16609334 # number of memory reference insts executed -system.cpu.iew.exec_branches 8926219 # Number of branches executed -system.cpu.iew.exec_stores 6619832 # Number of stores executed -system.cpu.iew.exec_rate 0.518154 # Inst execution rate -system.cpu.iew.wb_sent 56008573 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55894065 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27763400 # num instructions producing a value -system.cpu.iew.wb_consumers 37619407 # num instructions consuming a value +system.cpu.iew.exec_nop 3523271 # number of nop insts executed +system.cpu.iew.exec_refs 16601850 # number of memory reference insts executed +system.cpu.iew.exec_branches 8919814 # Number of branches executed +system.cpu.iew.exec_stores 6617734 # Number of stores executed +system.cpu.iew.exec_rate 0.517949 # Inst execution rate +system.cpu.iew.wb_sent 55981553 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55865966 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27748179 # num instructions producing a value +system.cpu.iew.wb_consumers 37603022 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.514091 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738007 # average fanout of values written-back +system.cpu.iew.wb_rate 0.513903 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.737924 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7499464 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660925 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 569249 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79342393 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.707610 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.636795 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7467988 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660923 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 566730 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79357488 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.707446 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.635929 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58576225 73.83% 73.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8604152 10.84% 84.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4604262 5.80% 90.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2532350 3.19% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1516866 1.91% 95.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 607587 0.77% 96.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 525202 0.66% 97.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 528895 0.67% 97.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1846854 2.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58581738 73.82% 73.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8607533 10.85% 84.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4610804 5.81% 90.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2534837 3.19% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1515398 1.91% 95.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 609514 0.77% 96.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 522093 0.66% 97.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 538800 0.68% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1836771 2.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79342393 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56143434 # Number of instructions committed -system.cpu.commit.committedOps 56143434 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79357488 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56141140 # Number of instructions committed +system.cpu.commit.committedOps 56141140 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15463366 # Number of memory references committed -system.cpu.commit.loads 9087887 # Number of loads committed -system.cpu.commit.membars 226338 # Number of memory barriers committed -system.cpu.commit.branches 8437404 # Number of branches committed +system.cpu.commit.refs 15463467 # Number of memory references committed +system.cpu.commit.loads 9087961 # Number of loads committed +system.cpu.commit.membars 226334 # Number of memory barriers committed +system.cpu.commit.branches 8436593 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 51994306 # Number of committed integer instructions. -system.cpu.commit.function_calls 740223 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1846854 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 51992006 # Number of committed integer instructions. +system.cpu.commit.function_calls 740231 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1836771 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 140888897 # The number of ROB reads -system.cpu.rob.rob_writes 128535372 # The number of ROB writes -system.cpu.timesIdled 1178030 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 28133785 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599901445 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52953842 # Number of Instructions Simulated -system.cpu.committedOps 52953842 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52953842 # Number of Instructions Simulated -system.cpu.cpi 2.053184 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.053184 # CPI: Total CPI of All Threads -system.cpu.ipc 0.487048 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.487048 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73863718 # number of integer regfile reads -system.cpu.int_regfile_writes 40309148 # number of integer regfile writes -system.cpu.fp_regfile_reads 166055 # number of floating regfile reads -system.cpu.fp_regfile_writes 167445 # number of floating regfile writes -system.cpu.misc_regfile_reads 1987577 # number of misc regfile reads -system.cpu.misc_regfile_writes 938916 # number of misc regfile writes +system.cpu.rob.rob_reads 140880188 # The number of ROB reads +system.cpu.rob.rob_writes 128461324 # The number of ROB writes +system.cpu.timesIdled 1178621 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 28110338 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599915455 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52951550 # Number of Instructions Simulated +system.cpu.committedOps 52951550 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52951550 # Number of Instructions Simulated +system.cpu.cpi 2.052993 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.052993 # CPI: Total CPI of All Threads +system.cpu.ipc 0.487094 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.487094 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73826909 # number of integer regfile reads +system.cpu.int_regfile_writes 40289801 # number of integer regfile writes +system.cpu.fp_regfile_reads 166028 # number of floating regfile reads +system.cpu.fp_regfile_writes 167439 # number of floating regfile writes +system.cpu.misc_regfile_reads 1985478 # number of misc regfile reads +system.cpu.misc_regfile_writes 938924 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -620,193 +620,193 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1008056 # number of replacements -system.cpu.icache.tagsinuse 510.288662 # Cycle average of tags in use -system.cpu.icache.total_refs 7486559 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1008564 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.422989 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20267924000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.288662 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996658 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996658 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7486560 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7486560 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7486560 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7486560 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7486560 # number of overall hits -system.cpu.icache.overall_hits::total 7486560 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1065380 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1065380 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1065380 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1065380 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1065380 # number of overall misses -system.cpu.icache.overall_misses::total 1065380 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14692786493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14692786493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14692786493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14692786493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14692786493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14692786493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8551940 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8551940 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8551940 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8551940 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8551940 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8551940 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124578 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124578 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124578 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124578 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124578 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124578 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13791.122879 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13791.122879 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13791.122879 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13791.122879 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13791.122879 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13791.122879 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4755 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1956 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 145 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 32.793103 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 489 # average number of cycles each access was blocked +system.cpu.icache.replacements 1007426 # number of replacements +system.cpu.icache.tagsinuse 510.288426 # Cycle average of tags in use +system.cpu.icache.total_refs 7476565 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1007934 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.417713 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 20275724000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.288426 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996657 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996657 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7476566 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7476566 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7476566 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7476566 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7476566 # number of overall hits +system.cpu.icache.overall_hits::total 7476566 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1064170 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1064170 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1064170 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1064170 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1064170 # number of overall misses +system.cpu.icache.overall_misses::total 1064170 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14673680991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14673680991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14673680991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14673680991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14673680991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14673680991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8540736 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8540736 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8540736 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8540736 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8540736 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8540736 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124599 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.124599 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.124599 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.124599 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.124599 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.124599 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13788.850457 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13788.850457 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13788.850457 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13788.850457 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13788.850457 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13788.850457 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6348 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 862 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 199 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 31.899497 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 862 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56595 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 56595 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 56595 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 56595 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 56595 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 56595 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1008785 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1008785 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1008785 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1008785 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1008785 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1008785 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12038039995 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12038039995 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12038039995 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12038039995 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12038039995 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12038039995 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117960 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117960 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117960 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.117960 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117960 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.117960 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11933.206773 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11933.206773 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11933.206773 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11933.206773 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11933.206773 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11933.206773 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56016 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 56016 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 56016 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 56016 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 56016 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 56016 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1008154 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1008154 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1008154 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1008154 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1008154 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1008154 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12024926992 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12024926992 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12024926992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12024926992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12024926992 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12024926992 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11927.668781 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11927.668781 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 338326 # number of replacements -system.cpu.l2cache.tagsinuse 65364.753625 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2543033 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 403496 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 6.302499 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 338281 # number of replacements +system.cpu.l2cache.tagsinuse 65363.167124 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2542180 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 403447 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 6.301150 # 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number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3742068 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3742068 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3742068 # number of overall misses +system.cpu.dcache.overall_misses::total 3742068 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33886585000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33886585000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 64964196004 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 64964196004 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 307808500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 307808500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 76500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 76500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 98850781004 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 98850781004 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 98850781004 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 98850781004 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9005926 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9005926 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6145297 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6145297 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208678 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 208678 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215508 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215508 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15151223 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15151223 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15151223 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15151223 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199963 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.199963 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315886 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.315886 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108895 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108895 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000023 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000023 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.246981 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.246981 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.246981 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.246981 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18816.932059 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18816.932059 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33465.791477 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33465.791477 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13545.524556 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13545.524556 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15300 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15300 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26416.083568 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26416.083568 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26416.083568 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26416.083568 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2179418 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1081 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 95907 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.964647 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 81 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.724285 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 154.428571 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840029 # number of writebacks -system.cpu.dcache.writebacks::total 840029 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717621 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 717621 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642056 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1642056 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5266 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5266 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2359677 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2359677 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2359677 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2359677 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083247 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083247 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300208 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300208 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17477 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17477 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1383455 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1383455 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1383455 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1383455 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21329073000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21329073000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9889442761 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9889442761 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199091500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199091500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 33500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 33500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31218515761 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31218515761 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31218515761 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31218515761 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423851000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423851000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997662998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997662998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421513998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421513998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120254 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120254 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048852 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048852 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083710 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083710 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091298 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091298 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091298 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091298 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19689.944214 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19689.944214 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32941.969438 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32941.969438 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11391.628998 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11391.628998 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16750 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16750 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22565.617068 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22565.617068 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22565.617068 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22565.617068 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 840025 # number of writebacks +system.cpu.dcache.writebacks::total 840025 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717752 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 717752 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1640976 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1640976 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5261 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5261 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2358728 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2358728 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2358728 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2358728 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083104 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083104 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300236 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300236 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17463 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17463 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1383340 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1383340 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1383340 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1383340 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21322279500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21322279500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9864847262 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9864847262 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200761000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200761000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 66500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 66500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31187126762 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31187126762 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31187126762 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31187126762 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423835500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423835500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997377498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997377498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421212998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421212998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120266 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120266 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048856 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048856 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083684 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083684 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000023 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091302 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091302 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091302 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091302 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19686.271586 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19686.271586 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32856.976718 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32856.976718 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11496.363740 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11496.363740 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13300 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13300 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22544.802263 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22544.802263 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22544.802263 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22544.802263 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1059,28 +1059,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 210999 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211001 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74662 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105559 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182230 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105560 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182232 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73295 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818345164500 98.06% 98.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 63914000 0.00% 98.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 557987500 0.03% 98.09% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 35348021500 1.91% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1854315087500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_good::31 73295 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148600 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1818327594000 98.06% 98.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 63775000 0.00% 98.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 558444000 0.03% 98.09% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 35364889500 1.91% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1854314702500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694342 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815442 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694344 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815444 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1119,7 +1119,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175115 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175117 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1128,20 +1128,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191959 # number of callpals executed +system.cpu.kern.callpal::total 191961 # number of callpals executed system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326552 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326381 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29469027500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2713167500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1822132884500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.394218 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29464996000 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2711269000 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1822138429500 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini index ad99994ae..84c3aa0ce 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini @@ -12,15 +12,15 @@ children=bridge cpu0 cpu1 cpu2 disk0 disk2 intrctrl iobus iocache l2c membus phy boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 clock=1000 -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -68,6 +68,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -162,6 +166,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=true system=system tracer=system.cpu1.tracer @@ -247,6 +252,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -581,7 +587,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -601,7 +607,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -730,7 +736,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 044f27d13..3510035fa 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.841723 # Number of seconds simulated -sim_ticks 1841722715000 # Number of ticks simulated -final_tick 1841722715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841721 # Number of seconds simulated +sim_ticks 1841721066000 # Number of ticks simulated +final_tick 1841721066000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105391 # Simulator instruction rate (inst/s) -host_op_rate 105391 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2775370642 # Simulator tick rate (ticks/s) -host_mem_usage 350548 # Number of bytes of host memory used -host_seconds 663.60 # Real time elapsed on the host -sim_insts 69936964 # Number of instructions simulated -sim_ops 69936964 # Number of ops (including micro ops) simulated +host_inst_rate 314597 # Simulator instruction rate (inst/s) +host_op_rate 314597 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8282501609 # Simulator tick rate (ticks/s) +host_mem_usage 307380 # Number of bytes of host memory used +host_seconds 222.36 # Real time elapsed on the host +sim_insts 69954713 # Number of instructions simulated +sim_ops 69954713 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 472704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19361152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19360768 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 152256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2812480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 294208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2695680 # Number of bytes read from this memory -system.physmem.bytes_read::total 28440832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2811776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 294016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2696640 # Number of bytes read from this memory +system.physmem.bytes_read::total 28440512 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 472704 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 152256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 294208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 919168 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7466432 # Number of bytes written to this memory -system.physmem.bytes_written::total 7466432 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu2.inst 294016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 918976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7466048 # Number of bytes written to this memory +system.physmem.bytes_written::total 7466048 # Number of bytes written to this memory system.physmem.num_reads::cpu0.inst 7386 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 302518 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 302512 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 2379 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 43945 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4597 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 42120 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444388 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116663 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116663 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 43934 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4594 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 42135 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444383 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116657 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116657 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.inst 256664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10512523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1440147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10512324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1440149 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 82670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1527092 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 159746 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1463673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15442516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1526711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 159642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1464196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15442356 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 256664 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 82670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 159746 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 499081 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4054048 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4054048 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4054048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 159642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498977 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4053843 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4053843 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4053843 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 256664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10512523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1440147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10512324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1440149 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 82670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1527092 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 159746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1463673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19496564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 109804 # Total number of read requests seen -system.physmem.writeReqs 45341 # Total number of write requests seen -system.physmem.cpureqs 155197 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 7027456 # Total number of bytes read from memory -system.physmem.bytesWritten 2901824 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 7027456 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2901824 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.data 1526711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 159642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1464196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19496199 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 109805 # Total number of read requests seen +system.physmem.writeReqs 45348 # Total number of write requests seen +system.physmem.cpureqs 155202 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 7027520 # Total number of bytes read from memory +system.physmem.bytesWritten 2902272 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 7027520 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2902272 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 5 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 42 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6899 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6714 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 6505 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 6917 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 6919 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 6872 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6836 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7202 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6979 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 6903 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6718 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6604 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6507 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 6918 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 6911 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 6891 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 6873 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7028 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6837 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7200 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6974 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 6884 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6963 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6842 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6841 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 6753 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2936 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2753 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 2939 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 2758 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 2643 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 2556 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 2819 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 2758 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2772 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2843 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3030 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 2749 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 2776 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 2848 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 3031 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 2909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 3191 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 3192 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 2889 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 2835 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 2906 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2802 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 2902 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 2803 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 2699 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry -system.physmem.totGap 1840710411000 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry +system.physmem.totGap 1840708761500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 109804 # Categorize read packet sizes +system.physmem.readPktSize::6 109805 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 45341 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 80889 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1970 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1085 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1083 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1070 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1047 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 589 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 553 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 554 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 669 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 45348 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 80824 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9409 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1285 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1092 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1088 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1066 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 590 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -148,46 +148,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1972 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1964 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1962 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 1960 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1953 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 1953 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 1951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 13 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see -system.physmem.totQLat 2345988500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4348949750 # Sum of mem lat for all requests -system.physmem.totBusLat 548995000 # Total cycles spent in databus access -system.physmem.totBankLat 1453966250 # Total cycles spent in bank access -system.physmem.avgQLat 21366.21 # Average queueing delay per request -system.physmem.avgBankLat 13242.07 # Average bank access latency per request +system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see +system.physmem.totQLat 2404806500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4407346500 # Sum of mem lat for all requests +system.physmem.totBusLat 549000000 # Total cycles spent in databus access +system.physmem.totBankLat 1453540000 # Total cycles spent in bank access +system.physmem.avgQLat 21901.70 # Average queueing delay per request +system.physmem.avgBankLat 13238.07 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 39608.28 # Average memory access latency +system.physmem.avgMemAccLat 40139.77 # Average memory access latency system.physmem.avgRdBW 3.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.82 # Average consumed read bandwidth in MB/s @@ -196,194 +196,194 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.17 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 44768.560388 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40404.453831 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -494,14 +494,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.255752 # Cycle average of tags in use +system.iocache.tagsinuse 1.255737 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1693877946000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.255752 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.078485 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.078485 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1693878100000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.255737 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.078484 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.078484 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -512,12 +512,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 9177998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 9177998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 4282592586 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 4282592586 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4291770584 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4291770584 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4291770584 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4291770584 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 4330975325 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 4330975325 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4340153323 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4340153323 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4340153323 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4340153323 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -536,17 +536,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53052.011561 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 53052.011561 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 103065.859309 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 103065.859309 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 102858.492127 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 102858.492127 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 102858.492127 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 102858.492127 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 114365 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 104230.249446 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 104230.249446 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 104018.054476 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 104018.054476 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 104018.054476 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 104018.054476 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 117509 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10981 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11192 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.414807 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.499375 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -562,12 +562,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 16837 system.iocache.overall_mshr_misses::total 16837 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5589249 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 5589249 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3410139151 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3410139151 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3415728400 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3415728400 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3415728400 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3415728400 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3458522887 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3458522887 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3464112136 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3464112136 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3464112136 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3464112136 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses @@ -578,12 +578,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523 system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81003.608696 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 81003.608696 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203371.848223 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 203371.848223 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202870.368831 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 202870.368831 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202870.368831 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 202870.368831 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 206257.328662 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 206257.328662 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205744.024232 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 205744.024232 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205744.024232 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 205744.024232 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -601,22 +601,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4882466 # DTB read hits -system.cpu0.dtb.read_misses 6004 # DTB read misses -system.cpu0.dtb.read_acv 119 # DTB read access violations -system.cpu0.dtb.read_accesses 427336 # DTB read accesses -system.cpu0.dtb.write_hits 3509197 # DTB write hits -system.cpu0.dtb.write_misses 661 # DTB write misses +system.cpu0.dtb.read_hits 4882934 # DTB read hits +system.cpu0.dtb.read_misses 6016 # DTB read misses +system.cpu0.dtb.read_acv 120 # DTB read access violations +system.cpu0.dtb.read_accesses 427387 # DTB read accesses +system.cpu0.dtb.write_hits 3510109 # DTB write hits +system.cpu0.dtb.write_misses 663 # DTB write misses system.cpu0.dtb.write_acv 82 # DTB write access violations -system.cpu0.dtb.write_accesses 162892 # DTB write accesses -system.cpu0.dtb.data_hits 8391663 # DTB hits -system.cpu0.dtb.data_misses 6665 # DTB misses -system.cpu0.dtb.data_acv 201 # DTB access violations -system.cpu0.dtb.data_accesses 590228 # DTB accesses -system.cpu0.itb.fetch_hits 2746663 # ITB hits -system.cpu0.itb.fetch_misses 2999 # ITB misses -system.cpu0.itb.fetch_acv 99 # ITB acv -system.cpu0.itb.fetch_accesses 2749662 # ITB accesses +system.cpu0.dtb.write_accesses 162920 # DTB write accesses +system.cpu0.dtb.data_hits 8393043 # DTB hits +system.cpu0.dtb.data_misses 6679 # DTB misses +system.cpu0.dtb.data_acv 202 # DTB access violations +system.cpu0.dtb.data_accesses 590307 # DTB accesses +system.cpu0.itb.fetch_hits 2747668 # ITB hits +system.cpu0.itb.fetch_misses 3002 # ITB misses +system.cpu0.itb.fetch_acv 100 # ITB acv +system.cpu0.itb.fetch_accesses 2750670 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -629,51 +629,51 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928532780 # number of cpu cycles simulated +system.cpu0.numCycles 928534019 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33005928 # Number of instructions committed -system.cpu0.committedOps 33005928 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 30880412 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 168592 # Number of float alu accesses -system.cpu0.num_func_calls 809679 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4456286 # number of instructions that are conditional controls -system.cpu0.num_int_insts 30880412 # number of integer instructions -system.cpu0.num_fp_insts 168592 # number of float instructions -system.cpu0.num_int_register_reads 43182890 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22546428 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87049 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 88627 # number of times the floating registers were written -system.cpu0.num_mem_refs 8421419 # number of memory refs -system.cpu0.num_load_insts 4903545 # Number of load instructions -system.cpu0.num_store_insts 3517874 # Number of store instructions -system.cpu0.num_idle_cycles 214028071508.499786 # Number of idle cycles -system.cpu0.num_busy_cycles -213099538728.499786 # Number of busy cycles -system.cpu0.not_idle_fraction -229.501363 # Percentage of non-idle cycles -system.cpu0.idle_fraction 230.501363 # Percentage of idle cycles +system.cpu0.committedInsts 33030135 # Number of instructions committed +system.cpu0.committedOps 33030135 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 30904296 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 168660 # Number of float alu accesses +system.cpu0.num_func_calls 809909 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4463035 # number of instructions that are conditional controls +system.cpu0.num_int_insts 30904296 # number of integer instructions +system.cpu0.num_fp_insts 168660 # number of float instructions +system.cpu0.num_int_register_reads 43221651 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22562663 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87082 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 88661 # number of times the floating registers were written +system.cpu0.num_mem_refs 8422848 # number of memory refs +system.cpu0.num_load_insts 4904051 # Number of load instructions +system.cpu0.num_store_insts 3518797 # Number of store instructions +system.cpu0.num_idle_cycles 214028158129.505707 # Number of idle cycles +system.cpu0.num_busy_cycles -213099624110.505707 # Number of busy cycles +system.cpu0.not_idle_fraction -229.501149 # Percentage of non-idle cycles +system.cpu0.idle_fraction 230.501149 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211353 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 211352 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105678 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182553 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105677 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182552 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818570193000 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39079500 0.00% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 365062500 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22747610500 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841721945500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1818574542500 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39495500 0.00% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 364949500 0.02% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22741309000 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841720296500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694818 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815845 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694825 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815850 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -712,7 +712,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175296 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175295 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -721,20 +721,20 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192207 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1908 -system.cpu0.kern.mode_good::user 1739 +system.cpu0.kern.callpal::total 192206 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5921 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1907 +system.cpu0.kern.mode_good::user 1738 system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.322188 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322074 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391224 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29799200000 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2569954000 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809352787000 98.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.391059 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29798472500 1.62% 1.62% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2570740000 0.14% 1.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809351079500 98.24% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -767,372 +767,372 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 952928 # number of replacements -system.cpu0.icache.tagsinuse 511.202677 # Cycle average of tags in use -system.cpu0.icache.total_refs 42504111 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 953439 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 44.579791 # Average number of references to valid blocks. +system.cpu0.icache.replacements 953317 # number of replacements +system.cpu0.icache.tagsinuse 511.202573 # Cycle average of tags in use +system.cpu0.icache.total_refs 42520473 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 953828 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 44.578764 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 10247489000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 252.529954 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 82.679092 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 175.993631 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.493223 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.161483 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.343738 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 251.172377 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 83.809654 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 176.220543 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.490571 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.163691 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.344181 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998443 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 32488547 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7734067 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2281497 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 42504111 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32488547 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7734067 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2281497 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 42504111 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32488547 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7734067 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2281497 # number of overall hits -system.cpu0.icache.overall_hits::total 42504111 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 524247 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 129266 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 316688 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 970201 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 524247 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 129266 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 316688 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 970201 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 524247 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 129266 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 316688 # number of overall misses -system.cpu0.icache.overall_misses::total 970201 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1820027500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4433734984 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6253762484 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1820027500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4433734984 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6253762484 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1820027500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4433734984 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6253762484 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 33012794 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7863333 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2598185 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 43474312 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 33012794 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7863333 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2598185 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 43474312 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 33012794 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7863333 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2598185 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 43474312 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015880 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016439 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.121888 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.022317 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015880 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016439 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.121888 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.022317 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015880 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016439 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.121888 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.022317 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14079.707734 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14000.325191 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6445.842134 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14079.707734 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14000.325191 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6445.842134 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14079.707734 # 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number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2131428631 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3428273631 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24718500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69834500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94553000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu1.data 152979 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 345859 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 498838 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 152979 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 345859 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 498838 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1973436500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4297066000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6270502500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1295329500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2136901128 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3432230628 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24853500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 70377000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95230500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3265053500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6431550131 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9696603631 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3265053500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6431550131 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9696603631 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287785000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 353197500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 640982500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 356424500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 429964000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 786388500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 644209500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 783161500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1427371000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086847 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088596 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041028 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053275 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045350 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021584 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.103106 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099737 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037983 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3268766000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6433967128 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9702733128 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3268766000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6433967128 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9702733128 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287559000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 353651000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 641210000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 356203000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 430620000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 786823000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 643762000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 784271000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1428033000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.087118 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088515 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041030 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.053190 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.045415 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021583 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.103394 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099840 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.038037 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072396 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071885 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072520 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071857 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.033094 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072396 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071885 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072520 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071857 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.033094 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18852.210686 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16432.245651 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17122.374280 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26792.657480 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25265.269090 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25822.119015 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11164.634146 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12701.800655 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12260.503112 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18847.946095 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16439.918892 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17128.636129 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26831.748695 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25295.057091 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25853.870875 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11175.134892 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12798.145117 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.765247 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21367.451981 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18585.609395 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19437.719640 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21367.451981 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18585.609395 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19437.719640 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21367.416443 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18602.861652 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19450.669612 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21367.416443 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18602.861652 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19450.669612 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1147,22 +1147,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1221293 # DTB read hits +system.cpu1.dtb.read_hits 1221065 # DTB read hits system.cpu1.dtb.read_misses 1489 # DTB read misses system.cpu1.dtb.read_acv 40 # DTB read access violations system.cpu1.dtb.read_accesses 143781 # DTB read accesses -system.cpu1.dtb.write_hits 930282 # DTB write hits +system.cpu1.dtb.write_hits 929390 # DTB write hits system.cpu1.dtb.write_misses 202 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 59266 # DTB write accesses -system.cpu1.dtb.data_hits 2151575 # DTB hits +system.cpu1.dtb.data_hits 2150455 # DTB hits system.cpu1.dtb.data_misses 1691 # DTB misses system.cpu1.dtb.data_acv 64 # DTB access violations system.cpu1.dtb.data_accesses 203047 # DTB accesses -system.cpu1.itb.fetch_hits 872259 # ITB hits +system.cpu1.itb.fetch_hits 872017 # ITB hits system.cpu1.itb.fetch_misses 756 # ITB misses system.cpu1.itb.fetch_acv 43 # ITB acv -system.cpu1.itb.fetch_accesses 873015 # ITB accesses +system.cpu1.itb.fetch_accesses 872773 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1175,28 +1175,28 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953618286 # number of cpu cycles simulated +system.cpu1.numCycles 953614996 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7861577 # Number of instructions committed -system.cpu1.committedOps 7861577 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7312995 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45507 # Number of float alu accesses -system.cpu1.num_func_calls 212083 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 960021 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7312995 # number of integer instructions -system.cpu1.num_fp_insts 45507 # number of float instructions -system.cpu1.num_int_register_reads 10166941 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5319886 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24589 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24824 # number of times the floating registers were written -system.cpu1.num_mem_refs 2159267 # number of memory refs -system.cpu1.num_load_insts 1226545 # Number of load instructions -system.cpu1.num_store_insts 932722 # Number of store instructions -system.cpu1.num_idle_cycles -1640970508.007204 # Number of idle cycles -system.cpu1.num_busy_cycles 2594588794.007204 # Number of busy cycles -system.cpu1.not_idle_fraction 2.720783 # Percentage of non-idle cycles -system.cpu1.idle_fraction -1.720783 # Percentage of idle cycles +system.cpu1.committedInsts 7860477 # Number of instructions committed +system.cpu1.committedOps 7860477 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7311992 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45303 # Number of float alu accesses +system.cpu1.num_func_calls 212165 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 960179 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7311992 # number of integer instructions +system.cpu1.num_fp_insts 45303 # number of float instructions +system.cpu1.num_int_register_reads 10165443 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5319467 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24490 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24717 # number of times the floating registers were written +system.cpu1.num_mem_refs 2158115 # number of memory refs +system.cpu1.num_load_insts 1226297 # Number of load instructions +system.cpu1.num_store_insts 931818 # Number of store instructions +system.cpu1.num_idle_cycles -703122010.262243 # Number of idle cycles +system.cpu1.num_busy_cycles 1656737006.262243 # Number of busy cycles +system.cpu1.not_idle_fraction 1.737323 # Percentage of non-idle cycles +system.cpu1.idle_fraction -0.737323 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1214,35 +1214,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8378030 # Number of BP lookups -system.cpu2.branchPred.condPredicted 7687664 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 128422 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6832370 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5743236 # Number of BTB hits +system.cpu2.branchPred.lookups 8370437 # Number of BP lookups +system.cpu2.branchPred.condPredicted 7682240 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 128031 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 6854257 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 5743720 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 84.059206 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 286145 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 15066 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 83.797850 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 284899 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 14987 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3213070 # DTB read hits -system.cpu2.dtb.read_misses 11858 # DTB read misses -system.cpu2.dtb.read_acv 125 # DTB read access violations -system.cpu2.dtb.read_accesses 216838 # DTB read accesses -system.cpu2.dtb.write_hits 1985729 # DTB write hits -system.cpu2.dtb.write_misses 2626 # DTB write misses -system.cpu2.dtb.write_acv 132 # DTB write access violations -system.cpu2.dtb.write_accesses 82100 # DTB write accesses -system.cpu2.dtb.data_hits 5198799 # DTB hits -system.cpu2.dtb.data_misses 14484 # DTB misses -system.cpu2.dtb.data_acv 257 # DTB access violations -system.cpu2.dtb.data_accesses 298938 # DTB accesses -system.cpu2.itb.fetch_hits 371799 # ITB hits -system.cpu2.itb.fetch_misses 5527 # ITB misses -system.cpu2.itb.fetch_acv 268 # ITB acv -system.cpu2.itb.fetch_accesses 377326 # ITB accesses +system.cpu2.dtb.read_hits 3211638 # DTB read hits +system.cpu2.dtb.read_misses 11756 # DTB read misses +system.cpu2.dtb.read_acv 123 # DTB read access violations +system.cpu2.dtb.read_accesses 216825 # DTB read accesses +system.cpu2.dtb.write_hits 1985602 # DTB write hits +system.cpu2.dtb.write_misses 2511 # DTB write misses +system.cpu2.dtb.write_acv 137 # DTB write access violations +system.cpu2.dtb.write_accesses 81903 # DTB write accesses +system.cpu2.dtb.data_hits 5197240 # DTB hits +system.cpu2.dtb.data_misses 14267 # DTB misses +system.cpu2.dtb.data_acv 260 # DTB access violations +system.cpu2.dtb.data_accesses 298728 # DTB accesses +system.cpu2.itb.fetch_hits 370869 # ITB hits +system.cpu2.itb.fetch_misses 5705 # ITB misses +system.cpu2.itb.fetch_acv 274 # ITB acv +system.cpu2.itb.fetch_accesses 376574 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1255,137 +1255,137 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30456501 # number of cpu cycles simulated +system.cpu2.numCycles 30454355 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8496671 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 34814108 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8378030 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6029381 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8102862 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 619747 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9664951 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 11667 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1935 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 63044 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 81651 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2598193 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 89272 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 26826827 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.297735 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.308224 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8502723 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 34791371 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8370437 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6028619 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8097928 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 618452 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9649671 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 10614 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1974 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 63437 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 88147 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 485 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2592037 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 89025 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 26817742 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.297327 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.307851 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18723965 69.80% 69.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 272177 1.01% 70.81% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 439981 1.64% 72.45% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4242616 15.81% 88.27% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 731901 2.73% 90.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 167093 0.62% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 195068 0.73% 92.34% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 431564 1.61% 93.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1622462 6.05% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18719814 69.80% 69.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 271918 1.01% 70.82% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 439106 1.64% 72.46% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4240914 15.81% 88.27% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 731900 2.73% 91.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 166811 0.62% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 194731 0.73% 92.35% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 431926 1.61% 93.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1620622 6.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 26826827 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.275082 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.143076 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8629429 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9759568 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7506924 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 293586 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 391402 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 168327 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12875 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34412678 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40383 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 391402 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8983257 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2851254 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5747978 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7364591 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1242431 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33259666 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2378 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 235537 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 408509 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 22329491 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41447748 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41283919 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 163829 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20504321 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1825170 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 503302 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 59735 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3683278 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3372566 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2079103 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 375078 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 254621 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30740575 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 627044 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30281796 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 33788 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2178999 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1098942 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 442743 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 26826827 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.128788 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.564676 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 26817742 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.274852 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.142410 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8640997 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9744638 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7501940 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 293665 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 390587 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 167981 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12867 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34389263 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 40403 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 390587 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8994385 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2850333 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5733998 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7360278 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1242256 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33240737 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2380 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 234906 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 409580 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 22320164 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 41423386 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41259446 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 163940 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20500425 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1819739 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 502711 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 59638 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3682174 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3369954 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2075842 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 372990 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 254270 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 30724821 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 626542 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 30272457 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 30970 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2165066 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1087715 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 442386 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 26817742 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.128822 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.564509 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15280016 56.96% 56.96% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3100114 11.56% 68.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1550183 5.78% 74.29% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5057659 18.85% 93.15% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 908873 3.39% 96.53% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 486444 1.81% 98.35% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 282646 1.05% 99.40% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 142385 0.53% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18507 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15272797 56.95% 56.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3099841 11.56% 68.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1551477 5.79% 74.29% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5057037 18.86% 93.15% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 907037 3.38% 96.53% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 485633 1.81% 98.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 283575 1.06% 99.40% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 141972 0.53% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18373 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 26826827 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 26817742 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 34417 13.83% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 111473 44.80% 58.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 102914 41.36% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 34129 13.74% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 111357 44.84% 58.58% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 102854 41.42% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24609882 81.27% 81.28% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20276 0.07% 81.34% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.34% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8461 0.03% 81.37% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 24602631 81.27% 81.28% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20294 0.07% 81.35% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8465 0.03% 81.37% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.37% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.37% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.37% # Type of FU issued @@ -1411,114 +1411,114 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.38% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.38% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.38% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3342059 11.04% 92.41% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2007965 6.63% 99.04% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 289481 0.96% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3340354 11.03% 92.41% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2007868 6.63% 99.04% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 289173 0.96% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30281796 # Type of FU issued -system.cpu2.iq.rate 0.994264 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 248804 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.008216 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 87438155 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33435914 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 29882334 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 234856 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114775 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 111304 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30405901 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 122251 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 189317 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 30272457 # Type of FU issued +system.cpu2.iq.rate 0.994027 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 248340 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.008203 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 87406741 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 33405587 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 29873950 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 235225 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114899 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 111509 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 30395868 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 122481 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 188565 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 413545 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 931 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4171 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 163357 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 411297 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 939 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4131 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 160227 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4715 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 24094 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4708 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 24260 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 391402 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2071748 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 210417 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32647605 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 226082 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3372566 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2079103 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 556688 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 148464 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2072 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4171 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 65897 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 129325 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 195222 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30121577 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3233216 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 160219 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 390587 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2070216 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 210596 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32630441 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 224813 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3369954 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2075842 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 556425 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 148713 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2116 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4131 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 65748 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 128933 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 194681 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 30112166 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3231643 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 160291 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1279986 # number of nop insts executed -system.cpu2.iew.exec_refs 5226048 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6791959 # Number of branches executed -system.cpu2.iew.exec_stores 1992832 # Number of stores executed -system.cpu2.iew.exec_rate 0.989003 # Inst execution rate -system.cpu2.iew.wb_sent 30026869 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 29993638 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17325737 # num instructions producing a value -system.cpu2.iew.wb_consumers 20548779 # num instructions consuming a value +system.cpu2.iew.exec_nop 1279078 # number of nop insts executed +system.cpu2.iew.exec_refs 5224243 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6789433 # Number of branches executed +system.cpu2.iew.exec_stores 1992600 # Number of stores executed +system.cpu2.iew.exec_rate 0.988764 # Inst execution rate +system.cpu2.iew.wb_sent 30017965 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 29985459 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17323993 # num instructions producing a value +system.cpu2.iew.wb_consumers 20546016 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.984802 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.843152 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.984603 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.843180 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2362249 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 184301 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 181159 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26435425 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.143965 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.849596 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2350466 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 184156 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 180720 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26427155 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.144119 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.849310 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16333385 61.79% 61.79% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2318132 8.77% 70.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1214509 4.59% 75.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4793021 18.13% 93.28% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 499893 1.89% 95.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 185577 0.70% 95.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 178746 0.68% 96.55% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 182246 0.69% 97.24% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 729916 2.76% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16325181 61.77% 61.77% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2317842 8.77% 70.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1215370 4.60% 75.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4792789 18.14% 93.28% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 500443 1.89% 95.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 186108 0.70% 95.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 178909 0.68% 96.55% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 180996 0.68% 97.24% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 729517 2.76% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26435425 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30241196 # Number of instructions committed -system.cpu2.commit.committedOps 30241196 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26427155 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30235823 # Number of instructions committed +system.cpu2.commit.committedOps 30235823 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4874767 # Number of memory references committed -system.cpu2.commit.loads 2959021 # Number of loads committed -system.cpu2.commit.membars 64729 # Number of memory barriers committed -system.cpu2.commit.branches 6642526 # Number of branches committed -system.cpu2.commit.fp_insts 110158 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28786790 # Number of committed integer instructions. -system.cpu2.commit.function_calls 230913 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 729916 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4874272 # Number of memory references committed +system.cpu2.commit.loads 2958657 # Number of loads committed +system.cpu2.commit.membars 64665 # Number of memory barriers committed +system.cpu2.commit.branches 6641301 # Number of branches committed +system.cpu2.commit.fp_insts 110294 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28781664 # Number of committed integer instructions. +system.cpu2.commit.function_calls 230734 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 729517 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 58235962 # The number of ROB reads -system.cpu2.rob.rob_writes 65598028 # The number of ROB writes -system.cpu2.timesIdled 242236 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3629674 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1745367915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 29069459 # Number of Instructions Simulated -system.cpu2.committedOps 29069459 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 29069459 # Number of Instructions Simulated -system.cpu2.cpi 1.047715 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.047715 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.954458 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.954458 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39608389 # number of integer regfile reads -system.cpu2.int_regfile_writes 21201849 # number of integer regfile writes -system.cpu2.fp_regfile_reads 67944 # number of floating regfile reads -system.cpu2.fp_regfile_writes 68330 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4592802 # number of misc regfile reads -system.cpu2.misc_regfile_writes 258987 # number of misc regfile writes +system.cpu2.rob.rob_reads 58211181 # The number of ROB reads +system.cpu2.rob.rob_writes 65562875 # The number of ROB writes +system.cpu2.timesIdled 242498 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3636613 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745370399 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 29064101 # Number of Instructions Simulated +system.cpu2.committedOps 29064101 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 29064101 # Number of Instructions Simulated +system.cpu2.cpi 1.047834 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.047834 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.954350 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.954350 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 39595533 # number of integer regfile reads +system.cpu2.int_regfile_writes 21195830 # number of integer regfile writes +system.cpu2.fp_regfile_reads 68078 # number of floating regfile reads +system.cpu2.fp_regfile_writes 68404 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4592506 # number of misc regfile reads +system.cpu2.misc_regfile_writes 258747 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed |