diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/long/fs/10.linux-boot/ref/alpha | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
4 files changed, 4857 insertions, 4820 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index d1ad31617..4fcd96b8e 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.884241 # Number of seconds simulated -sim_ticks 1884241273000 # Number of ticks simulated -final_tick 1884241273000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.884236 # Number of seconds simulated +sim_ticks 1884235597000 # Number of ticks simulated +final_tick 1884235597000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 193195 # Simulator instruction rate (inst/s) -host_op_rate 193195 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6486085343 # Simulator tick rate (ticks/s) -host_mem_usage 317148 # Number of bytes of host memory used -host_seconds 290.51 # Real time elapsed on the host -sim_insts 56124126 # Number of instructions simulated -sim_ops 56124126 # Number of ops (including micro ops) simulated +host_inst_rate 284222 # Simulator instruction rate (inst/s) +host_op_rate 284222 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9542341098 # Simulator tick rate (ticks/s) +host_mem_usage 373416 # Number of bytes of host memory used +host_seconds 197.46 # Real time elapsed on the host +sim_insts 56122640 # Number of instructions simulated +sim_ops 56122640 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 25914944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 25914816 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25915904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1052928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1052928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7561408 # Number of bytes written to this memory -system.physmem.bytes_written::total 7561408 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 404921 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25915776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1053184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1053184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7561856 # Number of bytes written to this memory +system.physmem.bytes_written::total 7561856 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 404919 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404936 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118147 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118147 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13753517 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404934 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118154 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118154 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13753490 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13754026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 558807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 558807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4012972 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4012972 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4012972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13753517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13754000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 558945 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 558945 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4013222 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4013222 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4013222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13753490 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17766999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404936 # Number of read requests accepted -system.physmem.writeReqs 159699 # Number of write requests accepted -system.physmem.readBursts 404936 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159699 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25909568 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue -system.physmem.bytesWritten 10083392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25915904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10220736 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2126 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 153 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25482 # Per bank write bursts +system.physmem.bw_total::total 17767222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404934 # Number of read requests accepted +system.physmem.writeReqs 159706 # Number of write requests accepted +system.physmem.readBursts 404934 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159706 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25910208 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5568 # Total number of bytes read from write queue +system.physmem.bytesWritten 10081344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25915776 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10221184 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 87 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2165 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25481 # Per bank write bursts system.physmem.perBankRdBursts::1 25742 # Per bank write bursts -system.physmem.perBankRdBursts::2 25842 # Per bank write bursts -system.physmem.perBankRdBursts::3 25776 # Per bank write bursts -system.physmem.perBankRdBursts::4 25226 # Per bank write bursts +system.physmem.perBankRdBursts::2 25839 # Per bank write bursts +system.physmem.perBankRdBursts::3 25784 # Per bank write bursts +system.physmem.perBankRdBursts::4 25228 # Per bank write bursts system.physmem.perBankRdBursts::5 24953 # Per bank write bursts -system.physmem.perBankRdBursts::6 24814 # Per bank write bursts -system.physmem.perBankRdBursts::7 24563 # Per bank write bursts +system.physmem.perBankRdBursts::6 24817 # Per bank write bursts +system.physmem.perBankRdBursts::7 24560 # Per bank write bursts system.physmem.perBankRdBursts::8 25102 # Per bank write bursts -system.physmem.perBankRdBursts::9 25273 # Per bank write bursts -system.physmem.perBankRdBursts::10 25528 # Per bank write bursts -system.physmem.perBankRdBursts::11 24851 # Per bank write bursts -system.physmem.perBankRdBursts::12 24526 # Per bank write bursts +system.physmem.perBankRdBursts::9 25274 # Per bank write bursts +system.physmem.perBankRdBursts::10 25530 # Per bank write bursts +system.physmem.perBankRdBursts::11 24856 # Per bank write bursts +system.physmem.perBankRdBursts::12 24523 # Per bank write bursts system.physmem.perBankRdBursts::13 25574 # Per bank write bursts -system.physmem.perBankRdBursts::14 25842 # Per bank write bursts -system.physmem.perBankRdBursts::15 25743 # Per bank write bursts -system.physmem.perBankWrBursts::0 10288 # Per bank write bursts -system.physmem.perBankWrBursts::1 10037 # Per bank write bursts -system.physmem.perBankWrBursts::2 10678 # Per bank write bursts -system.physmem.perBankWrBursts::3 10053 # Per bank write bursts -system.physmem.perBankWrBursts::4 9806 # Per bank write bursts -system.physmem.perBankWrBursts::5 9437 # Per bank write bursts -system.physmem.perBankWrBursts::6 9137 # Per bank write bursts -system.physmem.perBankWrBursts::7 8750 # Per bank write bursts -system.physmem.perBankWrBursts::8 9885 # Per bank write bursts -system.physmem.perBankWrBursts::9 8937 # Per bank write bursts -system.physmem.perBankWrBursts::10 9881 # Per bank write bursts -system.physmem.perBankWrBursts::11 9301 # Per bank write bursts -system.physmem.perBankWrBursts::12 9770 # Per bank write bursts -system.physmem.perBankWrBursts::13 10691 # Per bank write bursts -system.physmem.perBankWrBursts::14 10395 # Per bank write bursts -system.physmem.perBankWrBursts::15 10507 # Per bank write bursts +system.physmem.perBankRdBursts::14 25845 # Per bank write bursts +system.physmem.perBankRdBursts::15 25739 # Per bank write bursts +system.physmem.perBankWrBursts::0 10323 # Per bank write bursts +system.physmem.perBankWrBursts::1 10094 # Per bank write bursts +system.physmem.perBankWrBursts::2 10597 # Per bank write bursts +system.physmem.perBankWrBursts::3 9998 # Per bank write bursts +system.physmem.perBankWrBursts::4 9794 # Per bank write bursts +system.physmem.perBankWrBursts::5 9430 # Per bank write bursts +system.physmem.perBankWrBursts::6 9122 # Per bank write bursts +system.physmem.perBankWrBursts::7 8746 # Per bank write bursts +system.physmem.perBankWrBursts::8 9866 # Per bank write bursts +system.physmem.perBankWrBursts::9 8965 # Per bank write bursts +system.physmem.perBankWrBursts::10 9841 # Per bank write bursts +system.physmem.perBankWrBursts::11 9391 # Per bank write bursts +system.physmem.perBankWrBursts::12 9895 # Per bank write bursts +system.physmem.perBankWrBursts::13 10602 # Per bank write bursts +system.physmem.perBankWrBursts::14 10396 # Per bank write bursts +system.physmem.perBankWrBursts::15 10461 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1884232486500 # Total gap between requests +system.physmem.totGap 1884226862500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404936 # Read request sizes (log2) +system.physmem.readPktSize::6 404934 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 159699 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402545 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 71 # What read queue length does an incoming req see +system.physmem.writePktSize::6 159706 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -144,119 +144,119 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 10015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65749 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 547.429771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 335.789885 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 418.130322 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14719 22.39% 22.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10714 16.30% 38.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4807 7.31% 45.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3176 4.83% 50.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2550 3.88% 54.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1953 2.97% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1437 2.19% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1697 2.58% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24696 37.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65749 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5738 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.553154 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2788.767091 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5735 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65747 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 547.425008 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 336.336786 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.790126 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14590 22.19% 22.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10813 16.45% 38.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4856 7.39% 46.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3188 4.85% 50.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2531 3.85% 54.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1959 2.98% 57.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1455 2.21% 59.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1675 2.55% 62.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24680 37.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65747 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5741 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.518028 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2788.038880 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5738 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5738 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5738 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.457825 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.746842 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 34.017596 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4693 81.79% 81.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 187 3.26% 85.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 275 4.79% 89.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 67 1.17% 91.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 92 1.60% 92.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 47 0.82% 93.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 24 0.42% 93.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 11 0.19% 94.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 19 0.33% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 7 0.12% 94.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 14 0.24% 94.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 6 0.10% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 7 0.12% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 4 0.07% 95.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 17 0.30% 95.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 47 0.82% 96.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 17 0.30% 96.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 17 0.30% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 79 1.38% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 32 0.56% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 20 0.35% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 19 0.33% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 15 0.26% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 7 0.12% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 4 0.07% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 3 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5738 # Writes before turning the bus around for reads -system.physmem.totQLat 2167079250 # Total ticks spent queuing -system.physmem.totMemAccLat 9757773000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2024185000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5352.97 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5741 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5741 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.437903 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.774518 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 33.753883 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4686 81.62% 81.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 175 3.05% 84.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 305 5.31% 89.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 60 1.05% 91.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 91 1.59% 92.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 55 0.96% 93.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 13 0.23% 93.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 10 0.17% 93.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 19 0.33% 94.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.09% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 16 0.28% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 10 0.17% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 11 0.19% 95.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.05% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 17 0.30% 95.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 40 0.70% 96.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 20 0.35% 96.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 16 0.28% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 94 1.64% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 33 0.57% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 16 0.28% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 17 0.30% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 9 0.16% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 5 0.09% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 3 0.05% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 3 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5741 # Writes before turning the bus around for reads +system.physmem.totQLat 2143675250 # Total ticks spent queuing +system.physmem.totMemAccLat 9734556500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2024235000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5295.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24102.97 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24045.03 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 5.35 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.75 # Average system read bandwidth in MiByte/s @@ -266,66 +266,71 @@ system.physmem.busUtil 0.15 # Da system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing -system.physmem.readRowHits 364185 # Number of row buffer hits during reads -system.physmem.writeRowHits 132456 # Number of row buffer hits during writes +system.physmem.avgWrQLen 25.52 # Average write queue length when enqueuing +system.physmem.readRowHits 364210 # Number of row buffer hits during reads +system.physmem.writeRowHits 132411 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.06 # Row buffer hit rate for writes -system.physmem.avgGap 3337080.57 # Average gap between requests +system.physmem.writeRowHitRate 84.05 # Row buffer hit rate for writes +system.physmem.avgGap 3337041.06 # Average gap between requests system.physmem.pageHitRate 88.31 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1774592996500 # Time in different power states -system.physmem.memoryStateTime::REF 62918700000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 46722146000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 242668440 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 254394000 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 132408375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 138806250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1578704400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1579024200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 506645280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 514298160 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 123068977200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 123068977200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 59931006120 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 60719870160 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1077969239250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1077277253250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1263429649065 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1263552623220 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.526996 # Core power per rank (mW) -system.physmem.averagePower::1 670.592261 # Core power per rank (mW) -system.cpu.branchPred.lookups 15011318 # Number of BP lookups -system.cpu.branchPred.condPredicted 13019220 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 376037 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9980368 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5204970 # Number of BTB hits +system.physmem_0.actEnergy 243152280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132672375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1578751200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 506113920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 123068977200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 59789504475 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1078093355250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1263412526700 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.517914 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1793297401750 # Time in different power states +system.physmem_0.memoryStateTime::REF 62918700000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 28017727000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 253895040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 138534000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579055400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 514622160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 123068977200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 60612218820 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1077371684250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1263538986870 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.585024 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1792097761500 # Time in different power states +system.physmem_1.memoryStateTime::REF 62918700000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29217381000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 15006303 # Number of BP lookups +system.cpu.branchPred.condPredicted 13014667 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 375459 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9787101 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5202858 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.152085 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 808971 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32603 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 53.160359 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 808926 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32598 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9241438 # DTB read hits -system.cpu.dtb.read_misses 17791 # DTB read misses +system.cpu.dtb.read_hits 9241313 # DTB read hits +system.cpu.dtb.read_misses 17796 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766265 # DTB read accesses -system.cpu.dtb.write_hits 6385998 # DTB write hits -system.cpu.dtb.write_misses 2317 # DTB write misses -system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298404 # DTB write accesses -system.cpu.dtb.data_hits 15627436 # DTB hits -system.cpu.dtb.data_misses 20108 # DTB misses -system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1064669 # DTB accesses -system.cpu.itb.fetch_hits 4019003 # ITB hits -system.cpu.itb.fetch_misses 6884 # ITB misses -system.cpu.itb.fetch_acv 661 # ITB acv -system.cpu.itb.fetch_accesses 4025887 # ITB accesses +system.cpu.dtb.read_accesses 766310 # DTB read accesses +system.cpu.dtb.write_hits 6385986 # DTB write hits +system.cpu.dtb.write_misses 2327 # DTB write misses +system.cpu.dtb.write_acv 160 # DTB write access violations +system.cpu.dtb.write_accesses 298447 # DTB write accesses +system.cpu.dtb.data_hits 15627299 # DTB hits +system.cpu.dtb.data_misses 20123 # DTB misses +system.cpu.dtb.data_acv 371 # DTB access violations +system.cpu.dtb.data_accesses 1064757 # DTB accesses +system.cpu.itb.fetch_hits 4016976 # ITB hits +system.cpu.itb.fetch_misses 6883 # ITB misses +system.cpu.itb.fetch_acv 674 # ITB acv +system.cpu.itb.fetch_accesses 4023859 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -338,39 +343,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 175285694 # number of cpu cycles simulated +system.cpu.numCycles 175257245 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56124126 # Number of instructions committed -system.cpu.committedOps 56124126 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2495853 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5575 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593196852 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.123179 # CPI: cycles per instruction -system.cpu.ipc 0.320187 # IPC: instructions per cycle +system.cpu.committedInsts 56122640 # Number of instructions committed +system.cpu.committedOps 56122640 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2496382 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5595 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3593213949 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.122755 # CPI: cycles per instruction +system.cpu.ipc 0.320230 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211480 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74791 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211475 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74790 40.94% 40.94% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105868 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182691 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73424 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105864 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182686 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73423 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73424 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148880 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1833816082000 97.32% 97.32% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 80474500 0.00% 97.33% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 673053000 0.04% 97.36% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 49670669500 2.64% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1884240279000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_good::31 73423 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148878 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1833807390500 97.32% 97.32% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 80545000 0.00% 97.33% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 673176000 0.04% 97.36% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 49673506000 2.64% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1884234617500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693543 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814928 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693560 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814939 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -409,7 +414,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175532 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175527 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -418,28 +423,28 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192418 # number of callpals executed +system.cpu.kern.callpal::total 192413 # number of callpals executed system.cpu.kern.mode_switch::kernel 5870 # number of protection mode switches -system.cpu.kern.mode_switch::user 1743 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1913 -system.cpu.kern.mode_good::user 1743 +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.325894 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.325383 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393986 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36270859500 1.92% 1.92% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4083023000 0.22% 2.14% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1843886386500 97.86% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.393490 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 36258202500 1.92% 1.92% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4079939000 0.22% 2.14% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1843896466000 97.86% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.tickCycles 84485847 # Number of cycles that the object actually ticked -system.cpu.idleCycles 90799847 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395229 # number of replacements +system.cpu.tickCycles 84474734 # Number of cycles that the object actually ticked +system.cpu.idleCycles 90782511 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395383 # number of replacements system.cpu.dcache.tags.tagsinuse 511.982334 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13773041 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395741 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.867906 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 13772439 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395895 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.866386 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 86820250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.inst 511.982334 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999965 # Average percentage of cache occupancy @@ -449,72 +454,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63657366 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63657366 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 7814636 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7814636 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 5576637 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5576637 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182736 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182736 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 63656284 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63656284 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 7814297 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7814297 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 5576378 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5576378 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 182732 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182732 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 198999 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 198999 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 13391273 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13391273 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 13391273 # number of overall hits -system.cpu.dcache.overall_hits::total 13391273 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 1201532 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201532 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 573582 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573582 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17284 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17284 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.inst 1775114 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1775114 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1775114 # number of overall misses -system.cpu.dcache.overall_misses::total 1775114 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31036730750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31036730750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20700048539 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20700048539 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 231020000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 231020000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 51736779289 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51736779289 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 51736779289 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51736779289 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 9016168 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9016168 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 6150219 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6150219 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.inst 13390675 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13390675 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 13390675 # number of overall hits +system.cpu.dcache.overall_hits::total 13390675 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 1201640 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201640 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 573763 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573763 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.inst 17288 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17288 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.inst 1775403 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1775403 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 1775403 # number of overall misses +system.cpu.dcache.overall_misses::total 1775403 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 31034654250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31034654250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 20679395543 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20679395543 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 231275750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 231275750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 51714049793 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51714049793 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 51714049793 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51714049793 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 9015937 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9015937 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 6150141 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6150141 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 200020 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200020 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 198999 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 198999 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 15166387 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15166387 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 15166387 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15166387 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133264 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133264 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093262 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093262 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086411 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086411 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.117043 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117043 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.117043 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25830.964760 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25830.964760 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36089.083233 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36089.083233 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13366.118954 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13366.118954 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29145.609403 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29145.609403 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29145.609403 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29145.609403 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.inst 15166078 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15166078 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 15166078 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15166078 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.133280 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133280 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.093293 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093293 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.086431 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086431 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.117064 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117064 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.117064 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117064 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25826.915091 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25826.915091 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 36041.702834 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36041.702834 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13377.819875 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13377.819875 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29128.062639 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29128.062639 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29128.062639 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29128.062639 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -523,64 +528,64 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838115 # number of writebacks -system.cpu.dcache.writebacks::total 838115 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127210 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127210 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269406 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269406 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838265 # number of writebacks +system.cpu.dcache.writebacks::total 838265 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 127268 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 127268 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 269487 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269487 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 396616 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 396616 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 396616 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 396616 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074322 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074322 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304176 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304176 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17281 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17281 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1378498 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378498 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1378498 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378498 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26919627250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26919627250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10259801597 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10259801597 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196291500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196291500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37179428847 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37179428847 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37179428847 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37179428847 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423887000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423887000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002910000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002910000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426797000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426797000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119155 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119155 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049458 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049458 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086396 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086396 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090892 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090892 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090892 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090892 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25057.317313 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25057.317313 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33729.819568 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33729.819568 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11358.804467 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11358.804467 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26970.970467 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26970.970467 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26970.970467 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26970.970467 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.inst 396755 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 396755 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 396755 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 396755 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074372 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074372 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304276 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304276 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17285 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17285 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 1378648 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378648 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 1378648 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378648 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26917637000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26917637000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10249005096 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10249005096 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196537750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196537750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37166642096 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37166642096 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37166642096 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37166642096 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423897500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423897500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002909000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002909000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426806500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426806500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119164 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119164 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049475 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049475 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086416 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086416 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090903 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090903 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090903 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090903 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25054.298697 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25054.298697 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33683.251706 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33683.251706 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11370.422332 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11370.422332 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26958.761117 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26958.761117 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26958.761117 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26958.761117 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -588,58 +593,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1458001 # number of replacements -system.cpu.icache.tags.tagsinuse 509.626489 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 18970775 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1458512 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13.006938 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 31607473250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.626489 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 1459474 # number of replacements +system.cpu.icache.tags.tagsinuse 509.626385 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 18964719 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1459985 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12.989667 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 31607466250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.626385 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.995364 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.995364 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 21888154 # Number of tag accesses -system.cpu.icache.tags.data_accesses 21888154 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 18970778 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 18970778 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 18970778 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 18970778 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 18970778 # number of overall hits -system.cpu.icache.overall_hits::total 18970778 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1458688 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1458688 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1458688 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1458688 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1458688 # number of overall misses -system.cpu.icache.overall_misses::total 1458688 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20029373869 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20029373869 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20029373869 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20029373869 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20029373869 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20029373869 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 20429466 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 20429466 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 20429466 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 20429466 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 20429466 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 20429466 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071401 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.071401 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.071401 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.071401 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.071401 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.071401 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13731.088395 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13731.088395 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13731.088395 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13731.088395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13731.088395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13731.088395 # average overall miss latency +system.cpu.icache.tags.tag_accesses 21885040 # Number of tag accesses +system.cpu.icache.tags.data_accesses 21885040 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 18964722 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 18964722 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 18964722 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 18964722 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 18964722 # number of overall hits +system.cpu.icache.overall_hits::total 18964722 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1460159 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1460159 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1460159 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1460159 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1460159 # number of overall misses +system.cpu.icache.overall_misses::total 1460159 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20038728384 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20038728384 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20038728384 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20038728384 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20038728384 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20038728384 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 20424881 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 20424881 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 20424881 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 20424881 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 20424881 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 20424881 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071489 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.071489 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.071489 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.071489 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.071489 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.071489 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13723.661864 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13723.661864 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13723.661864 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13723.661864 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13723.661864 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13723.661864 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -648,115 +653,115 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458688 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1458688 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1458688 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1458688 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1458688 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1458688 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17104729131 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17104729131 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17104729131 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17104729131 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17104729131 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17104729131 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071401 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071401 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071401 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071401 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071401 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071401 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11726.105330 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11726.105330 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11726.105330 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11726.105330 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11726.105330 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11726.105330 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1460159 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1460159 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1460159 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1460159 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1460159 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1460159 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17111152616 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17111152616 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17111152616 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17111152616 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17111152616 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17111152616 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071489 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.071489 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.071489 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11718.691332 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11718.691332 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11718.691332 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11718.691332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11718.691332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11718.691332 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 339435 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65326.200893 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2981535 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 404597 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.369148 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 339433 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65325.334655 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2983211 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 404595 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.373326 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 5873248750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 54494.769777 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10831.431116 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.831524 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165275 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996799 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 54499.677348 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10825.657308 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.831599 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165186 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996786 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1458 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5147 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2791 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55536 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1456 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2809 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55530 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 30249203 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 30249203 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2261508 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2261508 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 838115 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 838115 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 30263477 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 30263477 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 2263052 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2263052 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 838265 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 838265 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.inst 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 187530 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187530 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2449038 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2449038 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2449038 # number of overall hits -system.cpu.l2cache.overall_hits::total 2449038 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 288693 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 288693 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.inst 187609 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187609 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2450661 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2450661 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2450661 # number of overall hits +system.cpu.l2cache.overall_hits::total 2450661 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 288671 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 288671 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.inst 17 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 116655 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116655 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 405348 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405348 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 405348 # number of overall misses -system.cpu.l2cache.overall_misses::total 405348 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18932535000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18932535000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_misses::cpu.inst 116676 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116676 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 405347 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405347 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 405347 # number of overall misses +system.cpu.l2cache.overall_misses::total 405347 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18920562000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18920562000 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 214497 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 214497 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8075894612 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8075894612 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27008429612 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27008429612 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27008429612 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27008429612 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 2550201 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2550201 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 838115 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 838115 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 8064568611 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8064568611 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 26985130611 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26985130611 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 26985130611 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26985130611 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 2551723 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2551723 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 838265 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 838265 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 21 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304185 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304185 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 2854386 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2854386 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2854386 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2854386 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113204 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.113204 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 304285 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304285 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 2856008 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2856008 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2856008 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2856008 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113128 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.113128 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.809524 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383500 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383500 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.142009 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.142009 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.142009 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.142009 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65580.166474 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 65580.166474 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.383443 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383443 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.141928 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.141928 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.141928 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.141928 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65543.688143 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 65543.688143 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 12617.470588 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12617.470588 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69228.876705 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69228.876705 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66630.227883 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66630.227883 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66630.227883 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66630.227883 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69119.344261 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69119.344261 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66572.913111 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66572.913111 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66572.913111 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66572.913111 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -765,54 +770,54 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76635 # number of writebacks -system.cpu.l2cache.writebacks::total 76635 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288693 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288693 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 76642 # number of writebacks +system.cpu.l2cache.writebacks::total 76642 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 288671 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288671 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 17 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116655 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116655 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 405348 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405348 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 405348 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405348 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15323296500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15323296500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 116676 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116676 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 405347 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405347 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 405347 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405347 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15311644500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15311644500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 271014 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271014 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6608324888 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6608324888 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21931621388 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21931621388 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21931621388 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21931621388 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333779000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333779000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1887481500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887481500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3221260500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221260500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113204 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113204 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6596786889 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6596786889 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21908431389 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21908431389 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21908431389 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21908431389 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1333789500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333789500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 1887480500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887480500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3221270000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221270000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113128 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113128 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.809524 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383500 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383500 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.142009 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.142009 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.142009 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.142009 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53078.171275 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53078.171275 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.383443 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383443 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.141928 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141928 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.141928 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141928 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53041.852143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53041.852143 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 15942 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15942 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56648.449599 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56648.449599 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54105.660785 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54105.660785 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54105.660785 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54105.660785 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56539.364471 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56539.364471 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54048.584026 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54048.584026 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54048.584026 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54048.584026 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -820,42 +825,42 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2557364 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2557331 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2558889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2558856 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 838115 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 838265 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304285 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304285 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917316 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662927 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6580243 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143021148 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236373340 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41941 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3734307 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.011173 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105112 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2920255 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663385 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6583640 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93446144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143040604 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236486748 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41944 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3736082 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.011168 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105088 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3692582 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3694357 98.88% 98.88% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 41725 1.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3734307 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2697490998 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3736082 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2698528498 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2191666369 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2193867384 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194528153 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2194759654 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -928,7 +933,7 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406196790 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406197789 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) @@ -937,14 +942,14 @@ system.iobus.respLayer0.utilization 0.0 # La system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.296059 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.296028 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1728026020000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.296059 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081004 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081004 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1728025570000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.296028 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081002 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081002 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -960,8 +965,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635314907 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13635314907 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635920906 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13635920906 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles @@ -984,17 +989,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328150.628297 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328150.628297 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328165.212409 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328165.212409 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206297 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 206267 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23564 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23556 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.754753 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.756453 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1010,8 +1015,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474610907 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474610907 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11475216906 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11475216906 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles @@ -1026,57 +1031,57 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276150.628297 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276150.628297 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276165.212409 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276165.212409 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 295796 # Transaction distribution -system.membus.trans_dist::ReadResp 295780 # Transaction distribution +system.membus.trans_dist::ReadReq 295774 # Transaction distribution +system.membus.trans_dist::ReadResp 295758 # Transaction distribution system.membus.trans_dist::WriteReq 9619 # Transaction distribution system.membus.trans_dist::WriteResp 9619 # Transaction distribution -system.membus.trans_dist::Writeback 118147 # Transaction distribution +system.membus.trans_dist::Writeback 118154 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 155 # Transaction distribution -system.membus.trans_dist::UpgradeResp 155 # Transaction distribution -system.membus.trans_dist::ReadExReq 116517 # Transaction distribution -system.membus.trans_dist::ReadExResp 116517 # Transaction distribution +system.membus.trans_dist::UpgradeReq 156 # Transaction distribution +system.membus.trans_dist::UpgradeResp 156 # Transaction distribution +system.membus.trans_dist::ReadExReq 116537 # Transaction distribution +system.membus.trans_dist::ReadExResp 116537 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887058 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887063 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920188 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920193 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1044992 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1044997 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30819584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30863900 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30819904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30864220 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36180956 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36181276 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 565237 # Request fanout histogram +system.membus.snoop_fanout::samples 565243 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 565237 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 565243 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 565237 # Request fanout histogram -system.membus.reqLayer0.occupancy 30298500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 565243 # Request fanout histogram +system.membus.reqLayer0.occupancy 30308000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1878232500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1878196000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3792450097 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3792332596 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 092a1319f..38c6e11f9 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.901187 # Number of seconds simulated -sim_ticks 1901187238000 # Number of ticks simulated -final_tick 1901187238000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.901175 # Number of seconds simulated +sim_ticks 1901175003500 # Number of ticks simulated +final_tick 1901175003500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164685 # Simulator instruction rate (inst/s) -host_op_rate 164685 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5473626023 # Simulator tick rate (ticks/s) -host_mem_usage 324480 # Number of bytes of host memory used -host_seconds 347.34 # Real time elapsed on the host -sim_insts 57201060 # Number of instructions simulated -sim_ops 57201060 # Number of ops (including micro ops) simulated +host_inst_rate 154934 # Simulator instruction rate (inst/s) +host_op_rate 154934 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5197600055 # Simulator tick rate (ticks/s) +host_mem_usage 378544 # Number of bytes of host memory used +host_seconds 365.78 # Real time elapsed on the host +sim_insts 56671579 # Number of instructions simulated +sim_ops 56671579 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 886592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24764800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 96384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 525056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 885824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24795264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 95808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 496320 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26273792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 886592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 96384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 982976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7873024 # Number of bytes written to this memory -system.physmem.bytes_written::total 7873024 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13853 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386950 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1506 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8204 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26274176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 885824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 95808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 981632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7885056 # Number of bytes written to this memory +system.physmem.bytes_written::total 7885056 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13841 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387426 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1497 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7755 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410528 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123016 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123016 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 466336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13025966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 50697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 276173 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 410534 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123204 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123204 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 465935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13042073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 50394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 261060 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13819676 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 466336 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 50697 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517033 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4141109 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4141109 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4141109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 466336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13025966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 50697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 276173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13819967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 465935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 50394 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4147465 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4147465 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4147465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 465935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13042073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 50394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 261060 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 505 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17960785 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410528 # Number of read requests accepted -system.physmem.writeReqs 164568 # Number of write requests accepted -system.physmem.readBursts 410528 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 164568 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26267072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue -system.physmem.bytesWritten 10385920 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26273792 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10532352 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2261 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 6311 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25881 # Per bank write bursts -system.physmem.perBankRdBursts::1 25672 # Per bank write bursts -system.physmem.perBankRdBursts::2 26260 # Per bank write bursts -system.physmem.perBankRdBursts::3 25757 # Per bank write bursts -system.physmem.perBankRdBursts::4 25283 # Per bank write bursts -system.physmem.perBankRdBursts::5 25202 # Per bank write bursts -system.physmem.perBankRdBursts::6 25755 # Per bank write bursts -system.physmem.perBankRdBursts::7 25257 # Per bank write bursts -system.physmem.perBankRdBursts::8 25550 # Per bank write bursts -system.physmem.perBankRdBursts::9 25721 # Per bank write bursts -system.physmem.perBankRdBursts::10 25770 # Per bank write bursts -system.physmem.perBankRdBursts::11 25804 # Per bank write bursts -system.physmem.perBankRdBursts::12 25810 # Per bank write bursts -system.physmem.perBankRdBursts::13 25881 # Per bank write bursts -system.physmem.perBankRdBursts::14 25644 # Per bank write bursts -system.physmem.perBankRdBursts::15 25176 # Per bank write bursts -system.physmem.perBankWrBursts::0 10943 # Per bank write bursts -system.physmem.perBankWrBursts::1 9789 # Per bank write bursts -system.physmem.perBankWrBursts::2 10222 # Per bank write bursts -system.physmem.perBankWrBursts::3 9625 # Per bank write bursts -system.physmem.perBankWrBursts::4 9290 # Per bank write bursts -system.physmem.perBankWrBursts::5 9560 # Per bank write bursts -system.physmem.perBankWrBursts::6 10277 # Per bank write bursts -system.physmem.perBankWrBursts::7 9346 # Per bank write bursts -system.physmem.perBankWrBursts::8 9649 # Per bank write bursts -system.physmem.perBankWrBursts::9 9784 # Per bank write bursts -system.physmem.perBankWrBursts::10 9978 # Per bank write bursts -system.physmem.perBankWrBursts::11 10113 # Per bank write bursts -system.physmem.perBankWrBursts::12 11182 # Per bank write bursts -system.physmem.perBankWrBursts::13 11629 # Per bank write bursts -system.physmem.perBankWrBursts::14 10712 # Per bank write bursts -system.physmem.perBankWrBursts::15 10181 # Per bank write bursts +system.physmem.bw_total::total 17967432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410534 # Number of read requests accepted +system.physmem.writeReqs 164756 # Number of write requests accepted +system.physmem.readBursts 410534 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 164756 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26267904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6272 # Total number of bytes read from write queue +system.physmem.bytesWritten 10393408 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26274176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10544384 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 98 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2335 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4921 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25742 # Per bank write bursts +system.physmem.perBankRdBursts::1 25822 # Per bank write bursts +system.physmem.perBankRdBursts::2 25939 # Per bank write bursts +system.physmem.perBankRdBursts::3 25643 # Per bank write bursts +system.physmem.perBankRdBursts::4 25873 # Per bank write bursts +system.physmem.perBankRdBursts::5 25657 # Per bank write bursts +system.physmem.perBankRdBursts::6 25709 # Per bank write bursts +system.physmem.perBankRdBursts::7 25201 # Per bank write bursts +system.physmem.perBankRdBursts::8 25222 # Per bank write bursts +system.physmem.perBankRdBursts::9 26115 # Per bank write bursts +system.physmem.perBankRdBursts::10 25677 # Per bank write bursts +system.physmem.perBankRdBursts::11 25575 # Per bank write bursts +system.physmem.perBankRdBursts::12 25800 # Per bank write bursts +system.physmem.perBankRdBursts::13 26085 # Per bank write bursts +system.physmem.perBankRdBursts::14 25301 # Per bank write bursts +system.physmem.perBankRdBursts::15 25075 # Per bank write bursts +system.physmem.perBankWrBursts::0 10194 # Per bank write bursts +system.physmem.perBankWrBursts::1 10103 # Per bank write bursts +system.physmem.perBankWrBursts::2 10030 # Per bank write bursts +system.physmem.perBankWrBursts::3 9736 # Per bank write bursts +system.physmem.perBankWrBursts::4 9490 # Per bank write bursts +system.physmem.perBankWrBursts::5 10167 # Per bank write bursts +system.physmem.perBankWrBursts::6 10200 # Per bank write bursts +system.physmem.perBankWrBursts::7 9338 # Per bank write bursts +system.physmem.perBankWrBursts::8 9741 # Per bank write bursts +system.physmem.perBankWrBursts::9 10459 # Per bank write bursts +system.physmem.perBankWrBursts::10 10157 # Per bank write bursts +system.physmem.perBankWrBursts::11 10688 # Per bank write bursts +system.physmem.perBankWrBursts::12 11170 # Per bank write bursts +system.physmem.perBankWrBursts::13 11200 # Per bank write bursts +system.physmem.perBankWrBursts::14 10147 # Per bank write bursts +system.physmem.perBankWrBursts::15 9577 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1901182789000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 1901170614000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410528 # Read request sizes (log2) +system.physmem.readPktSize::6 410534 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 164568 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 40637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 164756 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 40588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,187 +158,193 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 12109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 180 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67066 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 546.521218 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 334.319778 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.846112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14858 22.15% 22.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11363 16.94% 39.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5157 7.69% 46.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2935 4.38% 51.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2350 3.50% 54.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1701 2.54% 57.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1587 2.37% 59.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1704 2.54% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25411 37.89% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67066 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 68.402667 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2725.840527 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5997 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 545.527075 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 333.566914 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 419.530844 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14928 22.21% 22.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11337 16.87% 39.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5205 7.75% 46.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2937 4.37% 51.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2377 3.54% 54.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1798 2.68% 57.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1602 2.38% 59.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1684 2.51% 62.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25335 37.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67203 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6020 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 68.178073 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2721.311016 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 6017 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6000 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.046667 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.651184 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 33.190276 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4953 82.55% 82.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 193 3.22% 85.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 289 4.82% 90.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 50 0.83% 91.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 96 1.60% 93.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 44 0.73% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 19 0.32% 94.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 8 0.13% 94.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 23 0.38% 94.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 10 0.17% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 13 0.22% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 6 0.10% 95.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 7 0.12% 95.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 5 0.08% 95.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 20 0.33% 95.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 38 0.63% 96.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 17 0.28% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 12 0.20% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 91 1.52% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 43 0.72% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 17 0.28% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 19 0.32% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 8 0.13% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 9 0.15% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 3 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6000 # Writes before turning the bus around for reads -system.physmem.totQLat 3893190750 # Total ticks spent queuing -system.physmem.totMemAccLat 11588622000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2052115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9485.80 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6020 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6020 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 26.976246 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.646869 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 33.117275 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4955 82.31% 82.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 186 3.09% 85.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 316 5.25% 90.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 58 0.96% 91.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 93 1.54% 93.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 41 0.68% 93.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 21 0.35% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 11 0.18% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 26 0.43% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.07% 94.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 17 0.28% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.07% 95.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 7 0.12% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.03% 95.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 20 0.33% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 42 0.70% 96.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 17 0.28% 96.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 7 0.12% 96.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 80 1.33% 98.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 45 0.75% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 12 0.20% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 27 0.45% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 6 0.10% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 5 0.08% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 4 0.07% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.03% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.07% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 4 0.07% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6020 # Writes before turning the bus around for reads +system.physmem.totQLat 3885054500 # Total ticks spent queuing +system.physmem.totMemAccLat 11580729500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2052180000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9465.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28235.80 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28215.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 5.47 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.54 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.97 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing -system.physmem.readRowHits 370176 # Number of row buffer hits during reads -system.physmem.writeRowHits 135461 # Number of row buffer hits during writes +system.physmem.avgRdQLen 2.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.77 # Average write queue length when enqueuing +system.physmem.readRowHits 370181 # Number of row buffer hits during reads +system.physmem.writeRowHits 135448 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.46 # Row buffer hit rate for writes -system.physmem.avgGap 3305852.92 # Average gap between requests -system.physmem.pageHitRate 88.29 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1800384684500 # Time in different power states -system.physmem.memoryStateTime::REF 63484720000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37315104250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 252216720 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 254802240 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 137618250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 139029000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1599522600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1601776800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 512256960 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 539317440 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 124176112320 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 124176112320 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 57055460715 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 57001965930 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1090662047250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1090708972500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1274395234815 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1274421976230 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.316446 # Core power per rank (mW) -system.physmem.averagePower::1 670.330512 # Core power per rank (mW) -system.cpu0.branchPred.lookups 15024669 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13090822 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 302150 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 9266199 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5129053 # Number of BTB hits +system.physmem.writeRowHitRate 83.39 # Row buffer hit rate for writes +system.physmem.avgGap 3304716.95 # Average gap between requests +system.physmem.pageHitRate 88.26 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 253260000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 138187500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1603570800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 513591840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124175095200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 57090888495 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1090621618500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1274396212335 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.322456 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1814181645000 # Time in different power states +system.physmem_0.memoryStateTime::REF 63484200000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23503077500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 254688840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 138967125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1597455600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 538429680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124175095200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 57028143465 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1090676670000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1274409449910 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.329412 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1814277217000 # Time in different power states +system.physmem_1.memoryStateTime::REF 63484200000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23408681000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu0.branchPred.lookups 16131633 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14074847 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 326763 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 9526803 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5411642 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 55.352286 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 762066 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 14857 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 56.804387 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 814199 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 17678 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8699665 # DTB read hits -system.cpu0.dtb.read_misses 31652 # DTB read misses -system.cpu0.dtb.read_acv 518 # DTB read access violations -system.cpu0.dtb.read_accesses 684964 # DTB read accesses -system.cpu0.dtb.write_hits 5527628 # DTB write hits -system.cpu0.dtb.write_misses 7312 # DTB write misses -system.cpu0.dtb.write_acv 384 # DTB write access violations -system.cpu0.dtb.write_accesses 236678 # DTB write accesses -system.cpu0.dtb.data_hits 14227293 # DTB hits -system.cpu0.dtb.data_misses 38964 # DTB misses -system.cpu0.dtb.data_acv 902 # DTB access violations -system.cpu0.dtb.data_accesses 921642 # DTB accesses -system.cpu0.itb.fetch_hits 1360805 # ITB hits -system.cpu0.itb.fetch_misses 29325 # ITB misses -system.cpu0.itb.fetch_acv 623 # ITB acv -system.cpu0.itb.fetch_accesses 1390130 # ITB accesses +system.cpu0.dtb.read_hits 9231009 # DTB read hits +system.cpu0.dtb.read_misses 34580 # DTB read misses +system.cpu0.dtb.read_acv 535 # DTB read access violations +system.cpu0.dtb.read_accesses 687791 # DTB read accesses +system.cpu0.dtb.write_hits 5940395 # DTB write hits +system.cpu0.dtb.write_misses 7538 # DTB write misses +system.cpu0.dtb.write_acv 382 # DTB write access violations +system.cpu0.dtb.write_accesses 237219 # DTB write accesses +system.cpu0.dtb.data_hits 15171404 # DTB hits +system.cpu0.dtb.data_misses 42118 # DTB misses +system.cpu0.dtb.data_acv 917 # DTB access violations +system.cpu0.dtb.data_accesses 925010 # DTB accesses +system.cpu0.itb.fetch_hits 1435355 # ITB hits +system.cpu0.itb.fetch_misses 29386 # ITB misses +system.cpu0.itb.fetch_acv 625 # ITB acv +system.cpu0.itb.fetch_accesses 1464741 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -351,467 +357,466 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 108792579 # number of cpu cycles simulated +system.cpu0.numCycles 112944275 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 24480610 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 66921510 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 15024669 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5891119 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 76960209 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1006918 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 587 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 30320 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1459024 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 459440 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 228 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7808182 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 214478 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 103893877 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.644133 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.944480 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 26734623 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 70871158 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16131633 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6225841 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 78572167 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1087344 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 938 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 28136 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1452901 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 461019 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 278 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8195583 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 233790 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 107793734 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.657470 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.965319 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 91308838 87.89% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 814381 0.78% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1763801 1.70% 90.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 741690 0.71% 91.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2523255 2.43% 93.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 561128 0.54% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 635570 0.61% 94.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 719335 0.69% 95.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4825879 4.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 94531257 87.70% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 858509 0.80% 88.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1823492 1.69% 90.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 785861 0.73% 90.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2602190 2.41% 93.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 590625 0.55% 93.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 664328 0.62% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 839547 0.78% 95.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5097925 4.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 103893877 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.138104 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.615129 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 19900832 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 73745257 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8046257 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1730950 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 470580 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 495026 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 33344 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 58913691 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 103815 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 470580 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 20722206 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 48316669 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17970373 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8856068 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7557979 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 56901533 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 202703 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2015999 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 141191 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 3736855 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 38160864 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 69501237 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 69376844 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 115358 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33567232 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4593624 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1365129 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 198221 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12480015 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8824182 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5791367 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1299957 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 953544 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50831435 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1735186 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 49951846 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 52661 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5989483 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2856975 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1193961 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 103893877 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.480797 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.214404 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 107793734 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.142828 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.627488 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 21731474 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 75223274 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8544304 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1787077 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 507604 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 524648 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 36495 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 62167212 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 115754 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 507604 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 22589385 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 48401768 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 19164228 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9376952 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7753795 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 60013920 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 204923 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2024034 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 144343 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 3822558 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 40119139 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72975711 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72834321 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 131688 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 35221894 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4897237 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1480119 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 216056 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12920416 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9368350 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6206352 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1340557 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 962340 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 53512619 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1895957 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52599778 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 52230 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6392747 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 3006442 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1305426 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 107793734 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.487967 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.221871 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 83240383 80.12% 80.12% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 8994841 8.66% 88.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3729897 3.59% 92.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2662216 2.56% 94.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2692674 2.59% 97.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1272103 1.22% 98.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 842802 0.81% 99.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 349148 0.34% 99.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 109813 0.11% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 86044446 79.82% 79.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9475309 8.79% 88.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3928815 3.64% 92.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2790586 2.59% 94.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2836372 2.63% 97.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1349941 1.25% 98.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 893970 0.83% 99.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 358292 0.33% 99.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 116003 0.11% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 103893877 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 107793734 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 174329 19.02% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 437335 47.71% 66.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 305033 33.28% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 177733 18.25% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.25% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 467063 47.95% 66.19% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 329340 33.81% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 34481483 69.03% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 54630 0.11% 69.15% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.15% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 27712 0.06% 69.20% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.20% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.20% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.20% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.21% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9019851 18.06% 87.26% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5598402 11.21% 98.47% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 764115 1.53% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 36087462 68.61% 68.61% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57222 0.11% 68.72% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.72% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 28709 0.05% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9582527 18.22% 87.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6011046 11.43% 98.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 827159 1.57% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 49951846 # Type of FU issued -system.cpu0.iq.rate 0.459148 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 916697 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018352 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 204260867 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 58336070 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 48679612 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 506059 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 237571 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 232415 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 50592327 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 272446 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 560089 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52599778 # Type of FU issued +system.cpu0.iq.rate 0.465714 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 974136 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018520 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 213441030 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61548330 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 51220095 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 578625 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 270952 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 265721 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 53258517 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 311627 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 583786 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1038811 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4304 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 17864 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 487331 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1112279 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 5019 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18330 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 503254 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18869 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 349661 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18853 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 369989 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 470580 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 44276704 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1577501 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 55768983 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 120052 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8824182 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5791367 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1533608 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 47079 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1307470 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 17864 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 152204 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 328517 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 480721 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 49479281 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8753036 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 472564 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 507604 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 44339596 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1604348 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 58817574 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 124782 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9368350 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6206352 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1675353 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 48473 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1332642 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18330 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 164161 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 356822 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 520983 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 52091421 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9288991 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 508356 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3202362 # number of nop insts executed -system.cpu0.iew.exec_refs 14301032 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7879408 # Number of branches executed -system.cpu0.iew.exec_stores 5547996 # Number of stores executed -system.cpu0.iew.exec_rate 0.454804 # Inst execution rate -system.cpu0.iew.wb_sent 49022541 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 48912027 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25297454 # num instructions producing a value -system.cpu0.iew.wb_consumers 34938196 # num instructions consuming a value +system.cpu0.iew.exec_nop 3408998 # number of nop insts executed +system.cpu0.iew.exec_refs 15250639 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8273174 # Number of branches executed +system.cpu0.iew.exec_stores 5961648 # Number of stores executed +system.cpu0.iew.exec_rate 0.461213 # Inst execution rate +system.cpu0.iew.wb_sent 51600991 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51485816 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26436063 # num instructions producing a value +system.cpu0.iew.wb_consumers 36546981 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.449590 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.724063 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.455851 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.723345 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6548409 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 541225 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 440159 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 102738863 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.478033 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.411836 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 7016261 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 590531 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 476969 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 106554717 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.485172 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.424408 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 85310078 83.04% 83.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6928869 6.74% 89.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3804927 3.70% 93.48% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2004533 1.95% 95.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1514323 1.47% 96.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 555844 0.54% 97.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 414883 0.40% 97.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 408778 0.40% 98.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1796628 1.75% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 88252662 82.82% 82.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7298996 6.85% 89.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3974083 3.73% 93.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2090799 1.96% 95.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1561874 1.47% 96.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 585444 0.55% 97.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 439090 0.41% 97.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 445608 0.42% 98.21% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1906161 1.79% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 102738863 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 49112602 # Number of instructions committed -system.cpu0.commit.committedOps 49112602 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 106554717 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51697359 # Number of instructions committed +system.cpu0.commit.committedOps 51697359 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13089407 # Number of memory references committed -system.cpu0.commit.loads 7785371 # Number of loads committed -system.cpu0.commit.membars 183023 # Number of memory barriers committed -system.cpu0.commit.branches 7443994 # Number of branches committed -system.cpu0.commit.fp_insts 229281 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 45524861 # Number of committed integer instructions. -system.cpu0.commit.function_calls 617737 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2801788 5.70% 5.70% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 32185758 65.53% 71.24% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 53394 0.11% 71.35% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.35% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 27239 0.06% 71.40% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.40% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.40% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.40% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.41% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7968394 16.22% 87.63% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5310031 10.81% 98.44% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 764115 1.56% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13959169 # Number of memory references committed +system.cpu0.commit.loads 8256071 # Number of loads committed +system.cpu0.commit.membars 200989 # Number of memory barriers committed +system.cpu0.commit.branches 7816314 # Number of branches committed +system.cpu0.commit.fp_insts 262681 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47879291 # Number of committed integer instructions. +system.cpu0.commit.function_calls 663768 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2971590 5.75% 5.75% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 33646334 65.08% 70.83% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55999 0.11% 70.94% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.94% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 28236 0.05% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8457060 16.36% 87.36% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5709098 11.04% 98.40% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 827159 1.60% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 49112602 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1796628 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 51697359 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1906161 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 156399894 # The number of ROB reads -system.cpu0.rob.rob_writes 112470885 # The number of ROB writes -system.cpu0.timesIdled 448982 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 4898702 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3693581898 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 46314581 # Number of Instructions Simulated -system.cpu0.committedOps 46314581 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.348992 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.348992 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.425715 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.425715 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 65241971 # number of integer regfile reads -system.cpu0.int_regfile_writes 35484902 # number of integer regfile writes -system.cpu0.fp_regfile_reads 114300 # number of floating regfile reads -system.cpu0.fp_regfile_writes 114851 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1680980 # number of misc regfile reads -system.cpu0.misc_regfile_writes 762179 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1226061 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.967877 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9972327 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1226573 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.130235 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 163161097 # The number of ROB reads +system.cpu0.rob.rob_writes 118660594 # The number of ROB writes +system.cpu0.timesIdled 501791 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5150541 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3689405733 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48729536 # Number of Instructions Simulated +system.cpu0.committedOps 48729536 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.317779 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.317779 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.431448 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.431448 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 68466406 # number of integer regfile reads +system.cpu0.int_regfile_writes 37249066 # number of integer regfile writes +system.cpu0.fp_regfile_reads 130692 # number of floating regfile reads +system.cpu0.fp_regfile_writes 131766 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1811017 # number of misc regfile reads +system.cpu0.misc_regfile_writes 827352 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1291740 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.889209 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10636670 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1292252 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.231111 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 25151000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.967877 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988219 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988219 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.889209 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988065 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988065 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 236 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 53849509 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 53849509 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6192446 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6192446 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3442531 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3442531 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 150135 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 150135 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 172107 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 172107 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9634977 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9634977 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9634977 # number of overall hits -system.cpu0.dcache.overall_hits::total 9634977 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1501821 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1501821 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1669841 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1669841 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19141 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19141 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4636 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 4636 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3171662 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3171662 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3171662 # number of overall misses -system.cpu0.dcache.overall_misses::total 3171662 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39101656628 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 39101656628 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78115764371 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 78115764371 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 290102987 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 290102987 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 35172730 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 35172730 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 117217420999 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 117217420999 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 117217420999 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 117217420999 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7694267 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7694267 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5112372 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5112372 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 169276 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 169276 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176743 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 176743 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12806639 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12806639 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12806639 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12806639 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195187 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.195187 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.326627 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.326627 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113076 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113076 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026230 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.026230 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.247658 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.247658 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.247658 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.247658 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26036.163183 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26036.163183 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 46780.360748 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 46780.360748 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15156.104018 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15156.104018 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7586.870147 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7586.870147 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36957.727841 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36957.727841 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36957.727841 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36957.727841 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3837622 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3343 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 160954 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 89 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.842974 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 37.561798 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 57483025 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 57483025 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6556019 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6556019 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3715997 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3715997 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164872 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 164872 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189733 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 189733 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10272016 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10272016 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10272016 # number of overall hits +system.cpu0.dcache.overall_hits::total 10272016 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1615331 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1615331 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1779982 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1779982 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21282 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21282 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2627 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2627 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3395313 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3395313 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3395313 # number of overall misses +system.cpu0.dcache.overall_misses::total 3395313 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40801843239 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 40801843239 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 80191363617 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 80191363617 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336613990 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 336613990 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 19436381 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 19436381 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 120993206856 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 120993206856 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 120993206856 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 120993206856 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8171350 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8171350 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495979 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5495979 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 186154 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 186154 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192360 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 192360 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13667329 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13667329 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13667329 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13667329 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197682 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197682 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323870 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.323870 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.114325 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.114325 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.013657 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.013657 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248425 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248425 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248425 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248425 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25259.122272 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25259.122272 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45051.783455 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45051.783455 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15816.840053 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15816.840053 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7398.698515 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7398.698515 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35635.361705 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35635.361705 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35635.361705 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35635.361705 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 3895440 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3799 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 167914 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.199019 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 40.414894 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 711843 # number of writebacks -system.cpu0.dcache.writebacks::total 711843 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 520027 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 520027 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1419840 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1419840 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4544 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4544 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1939867 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1939867 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1939867 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1939867 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 981794 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 981794 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 250001 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250001 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14597 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14597 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4636 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 4636 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1231795 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1231795 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1231795 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1231795 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27071690424 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27071690424 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11368022018 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11368022018 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 148174261 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 148174261 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25899270 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25899270 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38439712442 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38439712442 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38439712442 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38439712442 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1458085000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1458085000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2211101998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2211101998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3669186998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3669186998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127601 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127601 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048901 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048901 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086232 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086232 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026230 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026230 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096184 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.096184 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096184 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.096184 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27573.697154 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27573.697154 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45471.906184 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45471.906184 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10151.007810 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10151.007810 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5586.555220 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5586.555220 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31206.257894 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31206.257894 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31206.257894 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31206.257894 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 762456 # number of writebacks +system.cpu0.dcache.writebacks::total 762456 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 593909 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 593909 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1512221 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1512221 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5168 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5168 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2106130 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2106130 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2106130 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2106130 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1021422 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1021422 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 267761 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 267761 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16114 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16114 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2626 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2626 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1289183 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1289183 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1289183 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1289183 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27591103326 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27591103326 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11693886534 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11693886534 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 178834256 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 178834256 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14183619 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14183619 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 39284989860 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 39284989860 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 39284989860 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 39284989860 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1458359000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1458359000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2137811998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2137811998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3596170998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3596170998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125000 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125000 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048719 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048719 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086563 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086563 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.013651 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.013651 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094326 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.094326 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094326 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.094326 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27012.442777 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27012.442777 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43672.852036 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43672.852036 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11098.067271 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11098.067271 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5401.225819 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5401.225819 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30472.779939 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30472.779939 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30472.779939 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30472.779939 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -819,126 +824,126 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 821620 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.585426 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6946118 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 822130 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.448929 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26485869250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.585426 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995284 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995284 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 914535 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.589702 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7236389 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 915045 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.908233 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26485919250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.589702 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995292 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995292 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 431 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 427 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 8630516 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 8630516 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6946118 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6946118 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6946118 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6946118 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6946118 # number of overall hits -system.cpu0.icache.overall_hits::total 6946118 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 862061 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 862061 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 862061 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 862061 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 862061 # number of overall misses -system.cpu0.icache.overall_misses::total 862061 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12338398473 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12338398473 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12338398473 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12338398473 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12338398473 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12338398473 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7808179 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7808179 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7808179 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7808179 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7808179 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7808179 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110405 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.110405 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110405 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.110405 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110405 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.110405 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14312.674478 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14312.674478 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14312.674478 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14312.674478 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14312.674478 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14312.674478 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4878 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 9110810 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9110810 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7236389 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7236389 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7236389 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7236389 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7236389 # number of overall hits +system.cpu0.icache.overall_hits::total 7236389 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 959193 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 959193 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 959193 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 959193 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 959193 # number of overall misses +system.cpu0.icache.overall_misses::total 959193 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13598697683 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13598697683 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13598697683 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13598697683 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13598697683 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13598697683 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8195582 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8195582 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8195582 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8195582 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8195582 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8195582 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117038 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.117038 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117038 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.117038 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117038 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.117038 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14177.227819 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14177.227819 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14177.227819 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14177.227819 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14177.227819 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14177.227819 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4960 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 185 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 197 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.367568 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.177665 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 39724 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 39724 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 39724 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 39724 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 39724 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 39724 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 822337 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 822337 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 822337 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 822337 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 822337 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 822337 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10177943027 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10177943027 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10177943027 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10177943027 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10177943027 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10177943027 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105317 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105317 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105317 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.105317 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105317 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.105317 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12376.851616 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12376.851616 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12376.851616 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12376.851616 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12376.851616 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12376.851616 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43965 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43965 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43965 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43965 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43965 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43965 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915228 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 915228 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 915228 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 915228 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 915228 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 915228 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11221708315 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11221708315 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11221708315 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11221708315 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11221708315 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11221708315 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111673 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.111673 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.111673 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12261.106866 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12261.106866 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12261.106866 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 4575539 # Number of BP lookups -system.cpu1.branchPred.condPredicted 4011453 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 80159 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2846769 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1118608 # Number of BTB hits +system.cpu1.branchPred.lookups 3410499 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2981782 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 63006 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1861186 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 813170 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 39.293950 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 219011 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 6943 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 43.690958 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 161954 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 4822 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2376918 # DTB read hits -system.cpu1.dtb.read_misses 9978 # DTB read misses -system.cpu1.dtb.read_acv 5 # DTB read access violations -system.cpu1.dtb.read_accesses 290947 # DTB read accesses -system.cpu1.dtb.write_hits 1576285 # DTB write hits -system.cpu1.dtb.write_misses 2026 # DTB write misses -system.cpu1.dtb.write_acv 38 # DTB write access violations -system.cpu1.dtb.write_accesses 109535 # DTB write accesses -system.cpu1.dtb.data_hits 3953203 # DTB hits -system.cpu1.dtb.data_misses 12004 # DTB misses -system.cpu1.dtb.data_acv 43 # DTB access violations -system.cpu1.dtb.data_accesses 400482 # DTB accesses -system.cpu1.itb.fetch_hits 602928 # ITB hits -system.cpu1.itb.fetch_misses 5576 # ITB misses -system.cpu1.itb.fetch_acv 51 # ITB acv -system.cpu1.itb.fetch_accesses 608504 # ITB accesses +system.cpu1.dtb.read_hits 1800297 # DTB read hits +system.cpu1.dtb.read_misses 9623 # DTB read misses +system.cpu1.dtb.read_acv 4 # DTB read access violations +system.cpu1.dtb.read_accesses 290908 # DTB read accesses +system.cpu1.dtb.write_hits 1120103 # DTB write hits +system.cpu1.dtb.write_misses 2035 # DTB write misses +system.cpu1.dtb.write_acv 37 # DTB write access violations +system.cpu1.dtb.write_accesses 109629 # DTB write accesses +system.cpu1.dtb.data_hits 2920400 # DTB hits +system.cpu1.dtb.data_misses 11658 # DTB misses +system.cpu1.dtb.data_acv 41 # DTB access violations +system.cpu1.dtb.data_accesses 400537 # DTB accesses +system.cpu1.itb.fetch_hits 513208 # ITB hits +system.cpu1.itb.fetch_misses 5417 # ITB misses +system.cpu1.itb.fetch_acv 59 # ITB acv +system.cpu1.itb.fetch_accesses 518625 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -951,463 +956,463 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 18735029 # number of cpu cycles simulated +system.cpu1.numCycles 13834996 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8327481 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 17619609 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4575539 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1337619 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9079051 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 321428 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 26636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 222369 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 65129 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1934705 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 65647 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 17881393 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.985360 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.396691 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 5742756 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13201278 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3410499 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 975124 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 7052078 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 251690 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 24829 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 212437 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 51117 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1482208 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 50416 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 13209086 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.999409 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.408470 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 14806869 82.81% 82.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 203122 1.14% 83.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 303524 1.70% 85.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 223355 1.25% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 384843 2.15% 89.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 149669 0.84% 89.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 166893 0.93% 90.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 294645 1.65% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1348473 7.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 10898169 82.51% 82.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 144102 1.09% 83.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 239022 1.81% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 173764 1.32% 86.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 293834 2.22% 88.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 119928 0.91% 89.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 132080 1.00% 90.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 175112 1.33% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1033075 7.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 17881393 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.244224 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.940463 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 6834927 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 8400269 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2240291 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 252863 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 153042 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 134285 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7749 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 14408505 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 25621 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 153042 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 7012697 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 586426 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6840794 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2316099 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 972333 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 13683407 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 9781 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 69005 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 16467 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 367791 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 8910587 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 16181694 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 16097130 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 77675 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 7724005 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1186582 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 556647 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 57942 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2323703 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2456737 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1657029 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 275399 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 155321 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 12021391 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 653222 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 11806375 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 22216 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1705669 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 770229 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 468205 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 17881393 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.660260 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.377042 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 13209086 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.246512 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.954195 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 4781490 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6446001 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1665086 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 196515 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 119993 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 102189 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 5928 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 10739248 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 19374 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 119993 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 4918512 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 544557 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5139003 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1724887 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 762132 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 10178184 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 4877 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 68265 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 13199 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 289695 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 6692544 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 12133960 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 12078154 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 50250 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5671659 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1020885 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 419664 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 38232 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1772644 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1865226 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1191683 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 210655 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 119712 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 8963290 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 478811 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 8726606 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 20522 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1437541 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 698510 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 352654 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 13209086 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.660652 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.378469 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 12935770 72.34% 72.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2198264 12.29% 84.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 914656 5.12% 89.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 630896 3.53% 93.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 572849 3.20% 96.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 314457 1.76% 98.24% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 208202 1.16% 99.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 77174 0.43% 99.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 29125 0.16% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 9547804 72.28% 72.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1625741 12.31% 84.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 686242 5.20% 89.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 474957 3.60% 93.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 417301 3.16% 96.54% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 221804 1.68% 98.22% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 145793 1.10% 99.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 65024 0.49% 99.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 24420 0.18% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 17881393 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 13209086 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 23808 8.12% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 159009 54.21% 62.33% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 110483 37.67% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 22353 9.61% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 126163 54.23% 63.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 84116 36.16% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 7355530 62.30% 62.33% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 19854 0.17% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.50% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 12327 0.10% 62.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2486397 21.06% 83.68% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1602376 13.57% 97.25% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 324614 2.75% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5425627 62.17% 62.21% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 15090 0.17% 62.39% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 10661 0.12% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1878240 21.52% 84.05% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1141614 13.08% 97.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 250097 2.87% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 11806375 # Type of FU issued -system.cpu1.iq.rate 0.630176 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 293300 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.024843 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 41494201 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 14236824 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 11389686 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 315458 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 147457 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 145351 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 11926347 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 169810 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 115792 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 8726606 # Type of FU issued +system.cpu1.iq.rate 0.630763 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 232632 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.026658 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 30722514 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 10791679 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8409842 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 192938 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 91772 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 89511 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 8852667 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 103053 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 90033 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 308768 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1081 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4102 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 143102 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 271460 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 498 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 3940 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 125337 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 395 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 55406 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 380 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 50736 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 153042 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 303896 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 248843 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 13398271 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 36703 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2456737 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1657029 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 586577 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4501 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 243181 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4102 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 36741 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 118067 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 154808 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 11654930 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2396476 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 151445 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 119993 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 268498 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 245239 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 9936241 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 29107 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1865226 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1191683 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 435120 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4465 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 239666 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 3940 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 28286 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 93108 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 121394 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 8606074 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1816179 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 120532 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 723658 # number of nop insts executed -system.cpu1.iew.exec_refs 3982565 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1739472 # Number of branches executed -system.cpu1.iew.exec_stores 1586089 # Number of stores executed -system.cpu1.iew.exec_rate 0.622093 # Inst execution rate -system.cpu1.iew.wb_sent 11565622 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 11535037 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5422471 # num instructions producing a value -system.cpu1.iew.wb_consumers 7736628 # num instructions consuming a value +system.cpu1.iew.exec_nop 494140 # number of nop insts executed +system.cpu1.iew.exec_refs 2943760 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1279494 # Number of branches executed +system.cpu1.iew.exec_stores 1127581 # Number of stores executed +system.cpu1.iew.exec_rate 0.622051 # Inst execution rate +system.cpu1.iew.wb_sent 8526125 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8499353 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4051784 # num instructions producing a value +system.cpu1.iew.wb_consumers 5752933 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.615694 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.700883 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.614337 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.704299 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1839025 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 185017 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 142916 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 17538839 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.655077 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.643008 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1506985 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 126157 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 110245 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 12932417 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.645119 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.622232 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 13431880 76.58% 76.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1875136 10.69% 87.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 688221 3.92% 91.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 418119 2.38% 93.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 312509 1.78% 95.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 131127 0.75% 96.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 110360 0.63% 96.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 156367 0.89% 97.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 415120 2.37% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 9905025 76.59% 76.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1407731 10.89% 87.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 501740 3.88% 91.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 308618 2.39% 93.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 224670 1.74% 95.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 96970 0.75% 96.23% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 89070 0.69% 96.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 100805 0.78% 97.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 297788 2.30% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 17538839 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 11489295 # Number of instructions committed -system.cpu1.commit.committedOps 11489295 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 12932417 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8342954 # Number of instructions committed +system.cpu1.commit.committedOps 8342954 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3661896 # Number of memory references committed -system.cpu1.commit.loads 2147969 # Number of loads committed -system.cpu1.commit.membars 61867 # Number of memory barriers committed -system.cpu1.commit.branches 1640602 # Number of branches committed -system.cpu1.commit.fp_insts 143665 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 10598150 # Number of committed integer instructions. -system.cpu1.commit.function_calls 183822 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 606334 5.28% 5.28% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 6800030 59.19% 64.46% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 19654 0.17% 64.63% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.63% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 12323 0.11% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 2209836 19.23% 83.99% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1514745 13.18% 97.17% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 324614 2.83% 100.00% # Class of committed instruction +system.cpu1.commit.refs 2660112 # Number of memory references committed +system.cpu1.commit.loads 1593766 # Number of loads committed +system.cpu1.commit.membars 39768 # Number of memory barriers committed +system.cpu1.commit.branches 1189273 # Number of branches committed +system.cpu1.commit.fp_insts 87820 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 7729091 # Number of committed integer instructions. +system.cpu1.commit.function_calls 132492 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 404429 4.85% 4.85% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 4960733 59.46% 64.31% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 14917 0.18% 64.49% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.49% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 10656 0.13% 64.61% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.61% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.61% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.61% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1633534 19.58% 84.22% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1066829 12.79% 97.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 250097 3.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 11489295 # Class of committed instruction -system.cpu1.commit.bw_lim_events 415120 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 8342954 # Class of committed instruction +system.cpu1.commit.bw_lim_events 297788 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 30366198 # The number of ROB reads -system.cpu1.rob.rob_writes 26995045 # The number of ROB writes -system.cpu1.timesIdled 163095 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 853636 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3782985916 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 10886479 # Number of Instructions Simulated -system.cpu1.committedOps 10886479 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.720945 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.720945 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.581076 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.581076 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 14951888 # number of integer regfile reads -system.cpu1.int_regfile_writes 8155185 # number of integer regfile writes -system.cpu1.fp_regfile_reads 77020 # number of floating regfile reads -system.cpu1.fp_regfile_writes 77068 # number of floating regfile writes -system.cpu1.misc_regfile_reads 1117526 # number of misc regfile reads -system.cpu1.misc_regfile_writes 276759 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 138501 # number of replacements -system.cpu1.dcache.tags.tagsinuse 492.617684 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3193598 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 138812 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.006642 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 39570817000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.617684 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.962144 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.962144 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 15087685 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 15087685 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1906947 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1906947 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1195571 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1195571 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 44901 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 44901 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 43886 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 43886 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3102518 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3102518 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3102518 # number of overall hits -system.cpu1.dcache.overall_hits::total 3102518 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 266692 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 266692 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 262982 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 262982 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8052 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8052 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 4916 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 4916 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 529674 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 529674 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 529674 # number of overall misses -system.cpu1.dcache.overall_misses::total 529674 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4020623652 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4020623652 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8531401983 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 8531401983 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 76759992 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 76759992 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 36344731 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 36344731 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12552025635 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12552025635 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12552025635 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12552025635 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2173639 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2173639 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1458553 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1458553 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 52953 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 52953 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 48802 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 48802 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3632192 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3632192 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3632192 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3632192 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.122694 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.122694 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.180303 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.180303 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152059 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152059 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100734 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100734 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.145828 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.145828 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.145828 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.145828 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15075.906484 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15075.906484 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32441.011107 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32441.011107 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9533.034277 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9533.034277 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7393.151139 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7393.151139 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23697.643522 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23697.643522 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23697.643522 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23697.643522 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 379144 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 215 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 18342 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.670810 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 23.888889 # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 22401053 # The number of ROB reads +system.cpu1.rob.rob_writes 19972727 # The number of ROB writes +system.cpu1.timesIdled 110858 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 625910 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3787862669 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 7942043 # Number of Instructions Simulated +system.cpu1.committedOps 7942043 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.741995 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.741995 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.574055 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.574055 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 11080172 # number of integer regfile reads +system.cpu1.int_regfile_writes 6056867 # number of integer regfile writes +system.cpu1.fp_regfile_reads 49492 # number of floating regfile reads +system.cpu1.fp_regfile_writes 48750 # number of floating regfile writes +system.cpu1.misc_regfile_reads 911686 # number of misc regfile reads +system.cpu1.misc_regfile_writes 198554 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 93396 # number of replacements +system.cpu1.dcache.tags.tagsinuse 491.127271 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2362095 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 93708 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 25.206973 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1032235519500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.127271 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.959233 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.959233 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.609375 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 11044469 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 11044469 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1462423 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1462423 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 846221 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 846221 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29364 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 29364 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 27945 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 27945 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2308644 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2308644 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2308644 # number of overall hits +system.cpu1.dcache.overall_hits::total 2308644 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 178507 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 178507 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 183677 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 183677 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4603 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4603 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2762 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2762 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 362184 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 362184 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 362184 # number of overall misses +system.cpu1.dcache.overall_misses::total 362184 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2741731463 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2741731463 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7132330313 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 7132330313 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 45481992 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 45481992 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 20461911 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 20461911 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 9874061776 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 9874061776 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 9874061776 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 9874061776 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1640930 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1640930 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1029898 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1029898 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 33967 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 33967 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 30707 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 30707 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2670828 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2670828 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2670828 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2670828 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.108784 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.108784 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.178345 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.178345 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135514 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135514 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.089947 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.089947 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135607 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135607 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135607 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135607 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15359.237806 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15359.237806 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38830.829734 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 38830.829734 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9880.945470 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9880.945470 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7408.367487 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7408.367487 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27262.556535 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 27262.556535 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27262.556535 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 27262.556535 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 351094 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 268 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 15302 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 15 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 22.944321 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 17.866667 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 93139 # number of writebacks -system.cpu1.dcache.writebacks::total 93139 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 164682 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 164682 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 213530 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 213530 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 655 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 655 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 378212 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 378212 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 378212 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 378212 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 102010 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 102010 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 49452 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 49452 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7397 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7397 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 4916 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 4916 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 151462 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 151462 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 151462 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 151462 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1194457513 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1194457513 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1312928589 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1312928589 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 54001007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 54001007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 26510269 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 26510269 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2507386102 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2507386102 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2507386102 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2507386102 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 24847500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 24847500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 692513000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 692513000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 717360500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 717360500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.046931 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.046931 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033905 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033905 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.139690 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.139690 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100734 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100734 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041700 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.041700 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041700 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.041700 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11709.219812 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11709.219812 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26549.554902 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26549.554902 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7300.392997 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7300.392997 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5392.650325 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5392.650325 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16554.555611 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16554.555611 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16554.555611 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16554.555611 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 60059 # number of writebacks +system.cpu1.dcache.writebacks::total 60059 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 108966 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 108966 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 150714 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 150714 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 427 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 259680 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 259680 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 259680 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 259680 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 69541 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 69541 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 32963 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 32963 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4176 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4176 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2762 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2762 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 102504 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 102504 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 102504 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 102504 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 829052502 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 829052502 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1081287205 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1081287205 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 31817008 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 31817008 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14937089 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14937089 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1910339707 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1910339707 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1910339707 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1910339707 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 24846500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 24846500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 618764500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 618764500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 643611000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 643611000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042379 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042379 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032006 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032006 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.122943 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.122943 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.089947 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.089947 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038379 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.038379 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038379 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.038379 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11921.779986 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11921.779986 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32803.058126 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32803.058126 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7619.015326 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7619.015326 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5408.069877 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5408.069877 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18636.733269 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18636.733269 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18636.733269 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18636.733269 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1415,95 +1420,95 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 306147 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.962529 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1618659 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 306656 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.278419 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1878409820250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.962529 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919849 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.919849 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id +system.cpu1.icache.tags.replacements 205003 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.613699 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1269898 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 205514 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.179131 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1878408675250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.613699 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919167 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.919167 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2241410 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2241410 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1618659 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1618659 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1618659 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1618659 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1618659 # number of overall hits -system.cpu1.icache.overall_hits::total 1618659 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 316046 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 316046 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 316046 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 316046 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 316046 # number of overall misses -system.cpu1.icache.overall_misses::total 316046 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4251188208 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4251188208 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4251188208 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4251188208 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4251188208 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4251188208 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1934705 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1934705 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1934705 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1934705 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1934705 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1934705 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.163356 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.163356 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.163356 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.163356 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.163356 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.163356 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13451.169159 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13451.169159 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13451.169159 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13451.169159 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13451.169159 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13451.169159 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 528 # number of cycles access was blocked +system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 1687783 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1687783 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1269898 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1269898 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1269898 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1269898 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1269898 # number of overall hits +system.cpu1.icache.overall_hits::total 1269898 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 212310 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 212310 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 212310 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 212310 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 212310 # number of overall misses +system.cpu1.icache.overall_misses::total 212310 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2888653039 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2888653039 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2888653039 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2888653039 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2888653039 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2888653039 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1482208 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1482208 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1482208 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1482208 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1482208 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1482208 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.143239 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.143239 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.143239 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.143239 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.143239 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.143239 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13605.826570 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13605.826570 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13605.826570 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13605.826570 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13605.826570 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13605.826570 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 412 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.307692 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.846154 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9341 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 9341 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 9341 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 9341 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 9341 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 9341 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 306705 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 306705 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 306705 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 306705 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 306705 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 306705 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3543296218 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3543296218 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3543296218 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3543296218 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3543296218 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3543296218 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.158528 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.158528 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.158528 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.158528 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.158528 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.158528 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11552.782700 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11552.782700 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11552.782700 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11552.782700 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11552.782700 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11552.782700 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6735 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 6735 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 6735 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 6735 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 6735 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 6735 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 205575 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 205575 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 205575 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 205575 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 205575 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 205575 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2403236890 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2403236890 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2403236890 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2403236890 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2403236890 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2403236890 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.138695 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.138695 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.138695 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11690.316867 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11690.316867 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11690.316867 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1517,13 +1522,13 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7368 # Transaction distribution -system.iobus.trans_dist::ReadResp 7368 # Transaction distribution -system.iobus.trans_dist::WriteReq 55198 # Transaction distribution -system.iobus.trans_dist::WriteResp 13646 # Transaction distribution +system.iobus.trans_dist::ReadReq 7377 # Transaction distribution +system.iobus.trans_dist::ReadResp 7377 # Transaction distribution +system.iobus.trans_dist::WriteReq 54536 # Transaction distribution +system.iobus.trans_dist::WriteResp 12984 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13082 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1534,12 +1539,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 41682 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125132 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 52328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40360 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83466 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83466 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 123826 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47024 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1550,13 +1555,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 78554 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2740162 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12437000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 73266 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661672 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661672 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2734938 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 11111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1576,52 +1581,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406224779 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406222784 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28036000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27376000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42010550 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42026793 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41693 # number of replacements -system.iocache.tags.tagsinuse 0.465320 # Cycle average of tags in use +system.iocache.tags.replacements 41701 # number of replacements +system.iocache.tags.tagsinuse 0.465228 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41709 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41717 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710336865000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.465320 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.029083 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.029083 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710337218000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.465228 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.029077 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.029077 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses +system.iocache.tags.tag_accesses 375597 # Number of tag accesses +system.iocache.tags.data_accesses 375597 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 181 # number of ReadReq misses +system.iocache.ReadReq_misses::total 181 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses -system.iocache.demand_misses::total 173 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 173 # number of overall misses -system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13658910846 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13658910846 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21134383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21134383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21134383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21134383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 181 # number of demand (read+write) misses +system.iocache.demand_misses::total 181 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 181 # number of overall misses +system.iocache.overall_misses::total 181 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22038383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22038383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13652440608 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13652440608 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22038383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22038383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22038383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22038383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 181 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 181 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 181 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 181 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 181 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 181 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1630,40 +1635,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328718.493598 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328718.493598 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122164.063584 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122164.063584 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122164.063584 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122164.063584 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 207096 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121759.022099 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 121759.022099 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328562.779361 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328562.779361 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 121759.022099 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 121759.022099 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 121759.022099 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 121759.022099 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 206720 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23572 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23552 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.785678 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.777174 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 181 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11498106946 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11498106946 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12137383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12137383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12137383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12137383 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 181 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 181 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 181 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 181 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12625383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12625383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11491649194 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11491649194 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12625383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12625383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12625383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12625383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1672,189 +1677,189 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276716.089382 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276716.089382 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70158.283237 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70158.283237 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 69753.497238 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276560.675635 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276560.675635 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69753.497238 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69753.497238 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 345011 # number of replacements -system.l2c.tags.tagsinuse 65255.839207 # Cycle average of tags in use -system.l2c.tags.total_refs 2587062 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 410177 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.307184 # Average number of references to valid blocks. +system.l2c.tags.replacements 345072 # number of replacements +system.l2c.tags.tagsinuse 65237.196274 # Cycle average of tags in use +system.l2c.tags.total_refs 2611817 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 410198 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.367210 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 7093665750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53401.606938 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5320.695867 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6228.167915 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 214.693065 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 90.675422 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.814844 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081187 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.095034 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003276 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001384 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995725 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65166 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2663 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5629 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5286 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51350 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994354 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27100727 # Number of tag accesses -system.l2c.tags.data_accesses 27100727 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 808308 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 697381 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 305176 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 93224 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1904089 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 804982 # number of Writeback hits -system.l2c.Writeback_hits::total 804982 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 430 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 602 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 51 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 137834 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 34568 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172402 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 808308 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 835215 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 305176 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 127792 # number of demand (read+write) hits -system.l2c.demand_hits::total 2076491 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 808308 # number of overall hits -system.l2c.overall_hits::cpu0.data 835215 # number of overall hits -system.l2c.overall_hits::cpu1.inst 305176 # number of overall hits -system.l2c.overall_hits::cpu1.data 127792 # number of overall hits -system.l2c.overall_hits::total 2076491 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13868 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273214 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1510 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 835 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289427 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2863 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1520 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4383 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 730 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 742 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1472 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114473 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7452 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121925 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13868 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387687 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1510 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8287 # number of demand (read+write) misses -system.l2c.demand_misses::total 411352 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13868 # number of overall misses -system.l2c.overall_misses::cpu0.data 387687 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1510 # number of overall misses -system.l2c.overall_misses::cpu1.data 8287 # number of overall misses -system.l2c.overall_misses::total 411352 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1064381750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17940986000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 121354750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 74847500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 19201570000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1318455 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 8321116 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 9639571 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1217948 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 209991 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1427939 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9484677078 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 797025966 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10281703044 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1064381750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 27425663078 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 121354750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 871873466 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 29483273044 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1064381750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 27425663078 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 121354750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 871873466 # number of overall miss cycles -system.l2c.overall_miss_latency::total 29483273044 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 822176 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 970595 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 306686 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 94059 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2193516 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 804982 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 804982 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3035 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1950 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4985 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 781 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 763 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1544 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 252307 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 42020 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 294327 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 822176 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1222902 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 306686 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 136079 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2487843 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 822176 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1222902 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 306686 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 136079 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2487843 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.016867 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.281491 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.004924 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.008877 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.131947 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.943328 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.779487 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.879238 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.934699 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.972477 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.953368 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.453705 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.177344 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.414250 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.016867 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.317022 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004924 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.060898 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.165345 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.016867 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.317022 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004924 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.060898 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.165345 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76750.919383 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 65666.422658 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80367.384106 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 89637.724551 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 66343.395744 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 460.515194 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5474.418421 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2199.308921 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1668.421918 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 283.006739 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 970.067255 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82855.145563 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 106954.638486 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 84328.095501 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 76750.919383 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 70741.766110 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 80367.384106 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 105209.782310 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 71674.072434 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 76750.919383 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 70741.766110 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 80367.384106 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 105209.782310 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 71674.072434 # average overall miss latency +system.l2c.tags.occ_blocks::writebacks 53609.898857 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5305.766317 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6049.152476 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 209.737010 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 62.641613 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.818022 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.080960 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.092303 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003200 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000956 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995441 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65126 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 2602 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5798 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5210 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 51300 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.993744 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 27343076 # Number of tag accesses +system.l2c.tags.data_accesses 27343076 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 901250 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 743094 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 204045 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 62863 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1911252 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 822515 # number of Writeback hits +system.l2c.Writeback_hits::total 822515 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 236 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 410 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 50 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 78 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 157590 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 21227 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 178817 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 901250 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 900684 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 204045 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 84090 # number of demand (read+write) hits +system.l2c.demand_hits::total 2090069 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 901250 # number of overall hits +system.l2c.overall_hits::cpu0.data 900684 # number of overall hits +system.l2c.overall_hits::cpu1.inst 204045 # number of overall hits +system.l2c.overall_hits::cpu1.data 84090 # number of overall hits +system.l2c.overall_hits::total 2090069 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13855 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 273150 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1501 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 784 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289290 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2701 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1143 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3844 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 381 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 416 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 797 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 114840 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 7053 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 121893 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13855 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 387990 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1501 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 7837 # number of demand (read+write) misses +system.l2c.demand_misses::total 411183 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13855 # number of overall misses +system.l2c.overall_misses::cpu0.data 387990 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1501 # number of overall misses +system.l2c.overall_misses::cpu1.data 7837 # number of overall misses +system.l2c.overall_misses::total 411183 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 1053790500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 17926629500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 116949250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 69771500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 19167140750 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1289954 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 4510297 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 5800251 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 801966 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 70497 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 872463 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 9554653251 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 752768967 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10307422218 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1053790500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 27481282751 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 116949250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 822540467 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 29474562968 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1053790500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 27481282751 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 116949250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 822540467 # number of overall miss cycles +system.l2c.overall_miss_latency::total 29474562968 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 915105 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1016244 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 205546 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 63647 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2200542 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 822515 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 822515 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2875 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1379 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4254 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 431 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 444 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 875 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 272430 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 28280 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300710 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 915105 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1288674 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 205546 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 91927 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2501252 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 915105 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1288674 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 205546 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 91927 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2501252 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015140 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.268784 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.007303 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.012318 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.131463 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.939478 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.828861 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.903620 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.883991 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.936937 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.910857 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.421539 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.249399 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.405351 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015140 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.301077 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007303 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.085252 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.164391 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015140 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.301077 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007303 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.085252 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.164391 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76058.498737 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 65629.249497 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77914.223851 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 88994.260204 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 66255.801272 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 477.583858 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3946.016623 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1508.910250 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2104.897638 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 169.463942 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1094.683814 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83199.697414 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 106730.322841 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 84561.231720 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 76058.498737 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 70829.873840 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 77914.223851 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 104956.037642 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71682.348171 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 76058.498737 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 70829.873840 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 77914.223851 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 104956.037642 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71682.348171 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1863,8 +1868,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 81496 # number of writebacks -system.l2c.writebacks::total 81496 # number of writebacks +system.l2c.writebacks::writebacks 81684 # number of writebacks +system.l2c.writebacks::total 81684 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 13 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits @@ -1877,111 +1882,111 @@ system.l2c.overall_mshr_hits::cpu0.inst 13 # nu system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 13855 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 273213 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1506 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 835 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 289409 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2863 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1520 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 4383 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 730 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 742 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1472 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 114473 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7452 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 121925 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13855 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 387686 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1506 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8287 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 411334 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13855 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 387686 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1506 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8287 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 411334 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 888852750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14535939000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 102112500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 64568500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15591472750 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 28831355 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15242993 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 44074348 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7325227 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 7431733 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 14756960 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8087686422 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 705343034 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8793029456 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 888852750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 22623625422 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 102112500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 769911534 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 24384502206 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 888852750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 22623625422 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 102112500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 769911534 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 24384502206 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1366200000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23157500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1389357500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2085104000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 652738500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2737842500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3451304000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 675896000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4127200000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016852 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.281490 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.004911 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.008877 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.131938 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.943328 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.779487 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.879238 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.934699 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.972477 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.953368 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.453705 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.177344 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.414250 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016852 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.317021 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004911 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.060898 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.165338 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016852 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.317021 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004911 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.060898 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.165338 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64153.933598 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53203.687233 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67803.784861 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77327.544910 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 53873.489594 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10070.330073 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.284868 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10055.749030 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10034.557534 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.812668 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.108696 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70651.476086 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 94651.507515 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 72118.346984 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64153.933598 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58355.538817 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67803.784861 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 92905.941113 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59281.513821 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64153.933598 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58355.538817 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67803.784861 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 92905.941113 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59281.513821 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 13842 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 273149 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1497 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 784 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289272 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2701 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1143 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3844 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 381 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 416 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 797 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 114840 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 7053 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 121893 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13842 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 387989 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1497 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 7837 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 411165 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13842 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 387989 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1497 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 7837 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 411165 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 878413500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14522738500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 97828500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 60106500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15559087000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27191193 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 11450632 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 38641825 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3833377 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4164911 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 7998288 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8153414747 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 665986031 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8819400778 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 878413500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 22676153247 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 97828500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 726092531 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 24378487778 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 878413500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 22676153247 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 97828500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 726092531 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 24378487778 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1366462500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23156500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1389619000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2015759500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 582978000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2598737500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3382222000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 606134500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3988356500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015126 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.268783 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007283 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012318 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.131455 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.939478 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.828861 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.903620 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.883991 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.936937 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.910857 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.421539 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.249399 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.405351 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015126 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.301076 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007283 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.085252 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.164384 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015126 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.301076 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007283 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.085252 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.164384 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53167.825985 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76666.454082 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 53787.048176 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10067.083673 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.050744 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.503902 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10061.356955 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.805288 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.493099 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70998.038549 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 94425.922444 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72353.628002 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58445.350891 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 92649.295776 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59291.252363 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58445.350891 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 92649.295776 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59291.252363 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1992,101 +1997,101 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296777 # Transaction distribution -system.membus.trans_dist::ReadResp 296698 # Transaction distribution -system.membus.trans_dist::WriteReq 13646 # Transaction distribution -system.membus.trans_dist::WriteResp 13646 # Transaction distribution -system.membus.trans_dist::Writeback 123016 # Transaction distribution +system.membus.trans_dist::ReadReq 296649 # Transaction distribution +system.membus.trans_dist::ReadResp 296568 # Transaction distribution +system.membus.trans_dist::WriteReq 12984 # Transaction distribution +system.membus.trans_dist::WriteResp 12984 # Transaction distribution +system.membus.trans_dist::Writeback 123204 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 14268 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 9480 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6314 # Transaction distribution -system.membus.trans_dist::ReadExReq 122151 # Transaction distribution -system.membus.trans_dist::ReadExResp 121466 # Transaction distribution -system.membus.trans_dist::BadAddressError 79 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 41682 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 933549 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 975389 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124812 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124812 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1100201 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 78554 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31488576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31567130 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 9668 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5310 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4924 # Transaction distribution +system.membus.trans_dist::ReadExReq 121989 # Transaction distribution +system.membus.trans_dist::ReadExResp 121610 # Transaction distribution +system.membus.trans_dist::BadAddressError 81 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40360 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 923282 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 162 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 963804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1088624 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73266 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31500992 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31574258 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36884698 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 18563 # Total snoops (count) -system.membus.snoop_fanout::samples 600049 # Request fanout histogram +system.membus.pkt_size::total 36891826 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 10884 # Total snoops (count) +system.membus.snoop_fanout::samples 591178 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 600049 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 591178 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 600049 # Request fanout histogram -system.membus.reqLayer0.occupancy 40411498 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 591178 # Request fanout histogram +system.membus.reqLayer0.occupancy 38973998 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1927899500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1927807998 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 99500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 100000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3832783452 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3829664091 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43159450 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43225207 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2231232 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2231137 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13646 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13646 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 804982 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 14411 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 9552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 23963 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296031 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296031 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 79 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1644513 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3224840 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 613391 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 402307 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5885051 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 52619264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 123882452 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19627904 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 14694726 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 210824346 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 91368 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3390565 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012306 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.110249 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2228449 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2228352 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12984 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12984 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 822515 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41553 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 9795 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5388 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 15183 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 301926 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301926 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1830333 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3396960 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 411121 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 269188 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5907602 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58566720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 131328844 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13154944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 9749222 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 212799730 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 73699 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3402430 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012266 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.110070 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3348840 98.77% 98.77% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41725 1.23% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3360696 98.77% 98.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41734 1.23% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3390565 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4912159072 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3402430 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4987291538 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 706500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3705712969 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4124247177 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5664612723 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5936070669 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1381251781 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 692182943 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 925874109 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 467054772 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2120,32 +2125,32 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6735 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 170888 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 59399 40.36% 40.36% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.45% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1921 1.31% 41.76% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 339 0.23% 41.99% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 85372 58.01% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 147162 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 58699 49.14% 49.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.25% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1921 1.61% 50.86% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 339 0.28% 51.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 58360 48.86% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 119450 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1860822176500 97.88% 97.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 61176000 0.00% 97.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 541931500 0.03% 97.91% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 152116500 0.01% 97.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 39608995500 2.08% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1901186396000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.988215 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6564 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 186274 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65832 40.54% 40.54% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1922 1.18% 41.81% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 173 0.11% 41.91% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 94323 58.09% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 162381 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64799 49.22% 49.22% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1922 1.46% 50.78% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 173 0.13% 50.91% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 64626 49.09% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 131651 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1859979639500 97.83% 97.83% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 61305500 0.00% 97.84% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 538798500 0.03% 97.86% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 78674500 0.00% 97.87% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 40515747500 2.13% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1901174165500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984309 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.683596 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811691 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.685156 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810754 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed @@ -2177,60 +2182,60 @@ system.cpu0.kern.syscall::144 2 0.86% 99.14% # nu system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 232 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 432 0.28% 0.28% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.28% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.28% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.28% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3241 2.09% 2.37% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.40% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.40% # number of callpals executed -system.cpu0.kern.callpal::swpipl 140334 90.29% 92.69% # number of callpals executed -system.cpu0.kern.callpal::rdps 6381 4.11% 96.80% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.80% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.80% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.80% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.81% # number of callpals executed -system.cpu0.kern.callpal::rti 4436 2.85% 99.66% # number of callpals executed -system.cpu0.kern.callpal::callsys 391 0.25% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 155429 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7000 # number of protection mode switches +system.cpu0.kern.callpal::wripir 266 0.16% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3573 2.09% 2.25% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.28% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed +system.cpu0.kern.callpal::swpipl 155550 90.98% 93.26% # number of callpals executed +system.cpu0.kern.callpal::rdps 6382 3.73% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.99% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 97.00% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed +system.cpu0.kern.callpal::rti 4604 2.69% 99.69% # number of callpals executed +system.cpu0.kern.callpal::callsys 391 0.23% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 170980 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7167 # number of protection mode switches system.cpu0.kern.mode_switch::user 1355 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1354 system.cpu0.kern.mode_good::user 1355 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.193429 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.188921 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.324237 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1899184407000 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2001981000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.317883 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1899194834000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1979323500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3242 # number of times the context was actually changed +system.cpu0.kern.swap_context 3574 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2589 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 70429 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 23508 38.03% 38.03% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1920 3.11% 41.14% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 432 0.70% 41.84% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 35949 58.16% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 61809 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 22831 47.98% 47.98% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1920 4.04% 52.02% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 432 0.91% 52.93% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 22399 47.07% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 47582 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1869145937500 98.33% 98.33% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 530408500 0.03% 98.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 194479500 0.01% 98.37% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 30989632500 1.63% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1900860458000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.971201 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2428 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 53091 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 16423 36.25% 36.25% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1920 4.24% 40.49% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 266 0.59% 41.08% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 26695 58.92% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 45304 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16079 47.18% 47.18% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1920 5.63% 52.82% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 266 0.78% 53.60% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 15813 46.40% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 34078 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870417466500 98.40% 98.40% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 530332500 0.03% 98.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 120265000 0.01% 98.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29780754000 1.57% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1900848818000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.979054 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.623077 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.769823 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.592358 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.752207 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed @@ -2246,35 +2251,35 @@ system.cpu1.kern.syscall::74 9 9.57% 96.81% # nu system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 94 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 339 0.53% 0.53% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.53% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.53% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1656 2.59% 3.12% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.13% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.14% # number of callpals executed -system.cpu1.kern.callpal::swpipl 56045 87.56% 90.70% # number of callpals executed -system.cpu1.kern.callpal::rdps 2366 3.70% 94.40% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.40% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.41% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.41% # number of callpals executed -system.cpu1.kern.callpal::rti 3411 5.33% 99.74% # number of callpals executed -system.cpu1.kern.callpal::callsys 124 0.19% 99.93% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.07% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 173 0.37% 0.37% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed +system.cpu1.kern.callpal::swpctx 989 2.11% 2.49% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 2.49% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed +system.cpu1.kern.callpal::swpipl 40205 85.85% 88.36% # number of callpals executed +system.cpu1.kern.callpal::rdps 2366 5.05% 93.41% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.42% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed +system.cpu1.kern.callpal::rti 2912 6.22% 99.64% # number of callpals executed +system.cpu1.kern.callpal::callsys 124 0.26% 99.91% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 64005 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1702 # number of protection mode switches +system.cpu1.kern.callpal::total 46833 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1197 # number of protection mode switches system.cpu1.kern.mode_switch::user 384 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2700 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 740 +system.cpu1.kern.mode_switch::idle 2372 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 574 system.cpu1.kern.mode_good::user 384 -system.cpu1.kern.mode_good::idle 356 -system.cpu1.kern.mode_switch_good::kernel 0.434783 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 190 +system.cpu1.kern.mode_switch_good::kernel 0.479532 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.131852 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.309235 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 6130779500 0.32% 0.32% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 692688500 0.04% 0.36% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893719133000 99.64% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1657 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.080101 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.290412 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 3852720500 0.20% 0.20% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 690217500 0.04% 0.24% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1895996394000 99.76% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 990 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 44e9b2e2b..aba3b9944 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,113 +1,113 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.859049 # Number of seconds simulated -sim_ticks 1859049148500 # Number of ticks simulated -final_tick 1859049148500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.859045 # Number of seconds simulated +sim_ticks 1859045389000 # Number of ticks simulated +final_tick 1859045389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168870 # Simulator instruction rate (inst/s) -host_op_rate 168870 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5931192571 # Simulator tick rate (ticks/s) -host_mem_usage 320216 # Number of bytes of host memory used -host_seconds 313.44 # Real time elapsed on the host -sim_insts 52930035 # Number of instructions simulated -sim_ops 52930035 # Number of ops (including micro ops) simulated +host_inst_rate 155751 # Simulator instruction rate (inst/s) +host_op_rate 155751 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5470499619 # Simulator tick rate (ticks/s) +host_mem_usage 374716 # Number of bytes of host memory used +host_seconds 339.83 # Real time elapsed on the host +sim_insts 52929026 # Number of instructions simulated +sim_ops 52929026 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 967168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24875776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 968128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24876416 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25843904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 967168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 967168 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7516224 # Number of bytes written to this memory -system.physmem.bytes_written::total 7516224 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15112 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388684 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25845504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 968128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 968128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7516800 # Number of bytes written to this memory +system.physmem.bytes_written::total 7516800 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15127 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388694 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403811 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117441 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117441 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13380914 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403836 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117450 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117450 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 520766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13381285 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13901679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4043047 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4043047 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4043047 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13380914 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13902567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 520766 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520766 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4043366 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4043366 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4043366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 520766 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13381285 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17944726 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403811 # Number of read requests accepted -system.physmem.writeReqs 158993 # Number of write requests accepted -system.physmem.readBursts 403811 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 158993 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25836928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue -system.physmem.bytesWritten 10037376 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25843904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10175552 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2130 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 189 # Number of requests that are neither read nor write +system.physmem.bw_total::total 17945933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403836 # Number of read requests accepted +system.physmem.writeReqs 159002 # Number of write requests accepted +system.physmem.readBursts 403836 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159002 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25838848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue +system.physmem.bytesWritten 10042304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25845504 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10176128 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2068 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 208 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25744 # Per bank write bursts -system.physmem.perBankRdBursts::1 25560 # Per bank write bursts -system.physmem.perBankRdBursts::2 25512 # Per bank write bursts -system.physmem.perBankRdBursts::3 25342 # Per bank write bursts -system.physmem.perBankRdBursts::4 25388 # Per bank write bursts -system.physmem.perBankRdBursts::5 24802 # Per bank write bursts -system.physmem.perBankRdBursts::6 25022 # Per bank write bursts -system.physmem.perBankRdBursts::7 25128 # Per bank write bursts -system.physmem.perBankRdBursts::8 24929 # Per bank write bursts -system.physmem.perBankRdBursts::9 25033 # Per bank write bursts -system.physmem.perBankRdBursts::10 25435 # Per bank write bursts -system.physmem.perBankRdBursts::11 24778 # Per bank write bursts -system.physmem.perBankRdBursts::12 24542 # Per bank write bursts -system.physmem.perBankRdBursts::13 25239 # Per bank write bursts -system.physmem.perBankRdBursts::14 25649 # Per bank write bursts -system.physmem.perBankRdBursts::15 25599 # Per bank write bursts -system.physmem.perBankWrBursts::0 10531 # Per bank write bursts -system.physmem.perBankWrBursts::1 10049 # Per bank write bursts -system.physmem.perBankWrBursts::2 10576 # Per bank write bursts -system.physmem.perBankWrBursts::3 9740 # Per bank write bursts -system.physmem.perBankWrBursts::4 9614 # Per bank write bursts -system.physmem.perBankWrBursts::5 9115 # Per bank write bursts -system.physmem.perBankWrBursts::6 9087 # Per bank write bursts -system.physmem.perBankWrBursts::7 8933 # Per bank write bursts -system.physmem.perBankWrBursts::8 9694 # Per bank write bursts -system.physmem.perBankWrBursts::9 8895 # Per bank write bursts -system.physmem.perBankWrBursts::10 9699 # Per bank write bursts -system.physmem.perBankWrBursts::11 9449 # Per bank write bursts -system.physmem.perBankWrBursts::12 10004 # Per bank write bursts +system.physmem.perBankRdBursts::1 25557 # Per bank write bursts +system.physmem.perBankRdBursts::2 25510 # Per bank write bursts +system.physmem.perBankRdBursts::3 25348 # Per bank write bursts +system.physmem.perBankRdBursts::4 25387 # Per bank write bursts +system.physmem.perBankRdBursts::5 24799 # Per bank write bursts +system.physmem.perBankRdBursts::6 25027 # Per bank write bursts +system.physmem.perBankRdBursts::7 25129 # Per bank write bursts +system.physmem.perBankRdBursts::8 24928 # Per bank write bursts +system.physmem.perBankRdBursts::9 25032 # Per bank write bursts +system.physmem.perBankRdBursts::10 25436 # Per bank write bursts +system.physmem.perBankRdBursts::11 24784 # Per bank write bursts +system.physmem.perBankRdBursts::12 24551 # Per bank write bursts +system.physmem.perBankRdBursts::13 25235 # Per bank write bursts +system.physmem.perBankRdBursts::14 25659 # Per bank write bursts +system.physmem.perBankRdBursts::15 25606 # Per bank write bursts +system.physmem.perBankWrBursts::0 10485 # Per bank write bursts +system.physmem.perBankWrBursts::1 10108 # Per bank write bursts +system.physmem.perBankWrBursts::2 10574 # Per bank write bursts +system.physmem.perBankWrBursts::3 9632 # Per bank write bursts +system.physmem.perBankWrBursts::4 9668 # Per bank write bursts +system.physmem.perBankWrBursts::5 9137 # Per bank write bursts +system.physmem.perBankWrBursts::6 9064 # Per bank write bursts +system.physmem.perBankWrBursts::7 8900 # Per bank write bursts +system.physmem.perBankWrBursts::8 9821 # Per bank write bursts +system.physmem.perBankWrBursts::9 8750 # Per bank write bursts +system.physmem.perBankWrBursts::10 9677 # Per bank write bursts +system.physmem.perBankWrBursts::11 9460 # Per bank write bursts +system.physmem.perBankWrBursts::12 10019 # Per bank write bursts system.physmem.perBankWrBursts::13 10709 # Per bank write bursts -system.physmem.perBankWrBursts::14 10413 # Per bank write bursts -system.physmem.perBankWrBursts::15 10326 # Per bank write bursts +system.physmem.perBankWrBursts::14 10502 # Per bank write bursts +system.physmem.perBankWrBursts::15 10405 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 1859043836000 # Total gap between requests +system.physmem.totGap 1859040142000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403811 # Read request sizes (log2) +system.physmem.readPktSize::6 403836 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 158993 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314947 # What read queue length does an incoming req see +system.physmem.writePktSize::6 159002 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314988 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 37560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -148,120 +148,119 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 562.390130 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 348.747922 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.715872 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13502 21.17% 21.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10319 16.18% 37.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4795 7.52% 44.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2857 4.48% 49.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2332 3.66% 53.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1655 2.59% 55.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1501 2.35% 57.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1587 2.49% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25241 39.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63789 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5661 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.309309 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2806.420357 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5658 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63696 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 563.318764 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 349.809758 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 419.596932 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13378 21.00% 21.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10306 16.18% 37.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4860 7.63% 44.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2855 4.48% 49.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2272 3.57% 52.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1671 2.62% 55.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1518 2.38% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1616 2.54% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25220 39.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63696 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5671 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.190619 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2803.945627 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5668 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5661 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5661 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.704293 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.909682 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 34.456612 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4621 81.63% 81.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 191 3.37% 85.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 281 4.96% 89.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 54 0.95% 90.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 96 1.70% 92.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 48 0.85% 93.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 17 0.30% 93.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 14 0.25% 94.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 19 0.34% 94.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.09% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 15 0.26% 94.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.07% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 5 0.09% 94.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 19 0.34% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 42 0.74% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 21 0.37% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 11 0.19% 96.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 96 1.70% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 35 0.62% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 14 0.25% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 13 0.23% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 10 0.18% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.09% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 5 0.09% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.04% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 5 0.09% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 6 0.11% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 2 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5661 # Writes before turning the bus around for reads -system.physmem.totQLat 3666880250 # Total ticks spent queuing -system.physmem.totMemAccLat 11236292750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018510000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9083.14 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5671 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5671 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.669018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.928355 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 34.069194 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4623 81.52% 81.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 171 3.02% 84.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 302 5.33% 89.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 63 1.11% 90.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 97 1.71% 92.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 43 0.76% 93.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 19 0.34% 93.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 6 0.11% 93.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 22 0.39% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.07% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 17 0.30% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.07% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 14 0.25% 94.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 6 0.11% 95.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 18 0.32% 95.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 43 0.76% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 8 0.14% 96.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 17 0.30% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 89 1.57% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 36 0.63% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 17 0.30% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 22 0.39% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 13 0.23% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 4 0.07% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 3 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 5 0.09% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5671 # Writes before turning the bus around for reads +system.physmem.totQLat 3621320000 # Total ticks spent queuing +system.physmem.totMemAccLat 11191295000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018660000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8969.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27833.14 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27719.61 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 5.40 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.90 # Average system read bandwidth in MiByte/s @@ -270,67 +269,72 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing -system.physmem.readRowHits 364667 # Number of row buffer hits during reads -system.physmem.writeRowHits 132080 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.20 # Row buffer hit rate for writes -system.physmem.avgGap 3303181.63 # Average gap between requests -system.physmem.pageHitRate 88.62 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1760890123500 # Time in different power states -system.physmem.memoryStateTime::REF 62077600000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 36077600250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 239795640 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 242449200 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 130840875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 132288750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1579484400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1569391200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 503139600 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 513144720 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 121423785600 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 121423785600 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 55719498420 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 55486362150 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1066550433000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1066754938500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1246146977535 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1246122360120 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.315549 # Core power per rank (mW) -system.physmem.averagePower::1 670.302307 # Core power per rank (mW) -system.cpu.branchPred.lookups 17761302 # Number of BP lookups -system.cpu.branchPred.condPredicted 15456576 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 379954 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12009119 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5937139 # Number of BTB hits +system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.54 # Average write queue length when enqueuing +system.physmem.readRowHits 364717 # Number of row buffer hits during reads +system.physmem.writeRowHits 132230 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.26 # Row buffer hit rate for writes +system.physmem.avgGap 3302975.53 # Average gap between requests +system.physmem.pageHitRate 88.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 239009400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130411875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1579507800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 502640640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 121423785600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 55671864660 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1066592208750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1246139428725 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.311493 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1774205493250 # Time in different power states +system.physmem_0.memoryStateTime::REF 62077600000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22762216750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 242532360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 132334125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1569601800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 514142640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 121423785600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 55569327930 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1066682161500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1246133885955 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.308507 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1774360012750 # Time in different power states +system.physmem_1.memoryStateTime::REF 62077600000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22607711000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 17755011 # Number of BP lookups +system.cpu.branchPred.condPredicted 15447257 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 380557 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11928628 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5915753 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 49.438589 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 914399 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21305 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 49.592904 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 917507 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21428 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10308188 # DTB read hits -system.cpu.dtb.read_misses 41379 # DTB read misses -system.cpu.dtb.read_acv 521 # DTB read access violations -system.cpu.dtb.read_accesses 967155 # DTB read accesses -system.cpu.dtb.write_hits 6646702 # DTB write hits -system.cpu.dtb.write_misses 9325 # DTB write misses -system.cpu.dtb.write_acv 410 # DTB write access violations -system.cpu.dtb.write_accesses 342603 # DTB write accesses -system.cpu.dtb.data_hits 16954890 # DTB hits -system.cpu.dtb.data_misses 50704 # DTB misses -system.cpu.dtb.data_acv 931 # DTB access violations -system.cpu.dtb.data_accesses 1309758 # DTB accesses -system.cpu.itb.fetch_hits 1770443 # ITB hits -system.cpu.itb.fetch_misses 36092 # ITB misses -system.cpu.itb.fetch_acv 664 # ITB acv -system.cpu.itb.fetch_accesses 1806535 # ITB accesses +system.cpu.dtb.read_hits 10297861 # DTB read hits +system.cpu.dtb.read_misses 41459 # DTB read misses +system.cpu.dtb.read_acv 502 # DTB read access violations +system.cpu.dtb.read_accesses 968382 # DTB read accesses +system.cpu.dtb.write_hits 6648165 # DTB write hits +system.cpu.dtb.write_misses 9537 # DTB write misses +system.cpu.dtb.write_acv 407 # DTB write access violations +system.cpu.dtb.write_accesses 342637 # DTB write accesses +system.cpu.dtb.data_hits 16946026 # DTB hits +system.cpu.dtb.data_misses 50996 # DTB misses +system.cpu.dtb.data_acv 909 # DTB access violations +system.cpu.dtb.data_accesses 1311019 # DTB accesses +system.cpu.itb.fetch_hits 1769037 # ITB hits +system.cpu.itb.fetch_misses 35976 # ITB misses +system.cpu.itb.fetch_acv 675 # ITB acv +system.cpu.itb.fetch_accesses 1805013 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -343,256 +347,256 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 118298016 # number of cpu cycles simulated +system.cpu.numCycles 118253854 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29541198 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78055768 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17761302 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6851538 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80476428 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1253224 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1384 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 28562 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1737629 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 451562 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 217 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9019799 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 273133 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 29528041 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78024704 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17755011 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6833260 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80443267 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1255548 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1917 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1737879 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 457742 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 201 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9020958 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 272859 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 112863592 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.691594 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.010851 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 112824612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.691557 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.011053 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 98289284 87.09% 87.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 935566 0.83% 87.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1976201 1.75% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 911928 0.81% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2795335 2.48% 92.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 642698 0.57% 93.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 727750 0.64% 94.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1007954 0.89% 95.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5576876 4.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 98261708 87.09% 87.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 933543 0.83% 87.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1973411 1.75% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 908515 0.81% 90.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2794922 2.48% 92.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 638903 0.57% 93.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 728605 0.65% 94.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1007079 0.89% 95.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5577926 4.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 112863592 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.150140 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.659823 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24058379 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 76821722 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9496623 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1902660 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 584207 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 588094 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42817 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68303161 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 133250 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 584207 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24982800 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 47259981 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20734687 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10387203 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8914712 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65869472 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 202922 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2041149 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 141248 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4766165 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43946104 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79818079 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79637315 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168311 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38139253 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5806843 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1691151 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 241440 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13536828 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10424364 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6928356 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1483959 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1059889 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58630025 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2138995 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57603342 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 50950 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7503583 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3485287 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1477804 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 112863592 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.510380 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.252962 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 112824612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.150143 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.659807 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24062318 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 76790103 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9490656 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1896068 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 585466 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 586954 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42767 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68209057 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 130935 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 585466 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24987088 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 47248716 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20734654 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10372019 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8896667 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65782894 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 200446 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2040001 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 143212 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4746299 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43863584 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79748694 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79567373 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168869 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38138490 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5725086 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1691130 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 241601 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13583154 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10423192 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6953251 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1496634 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1073096 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58558441 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2136854 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57535876 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 59225 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7428094 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3503981 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1475675 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 112824612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.509959 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.252016 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 89383207 79.20% 79.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10013548 8.87% 88.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4301377 3.81% 91.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 2962557 2.62% 94.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3086274 2.73% 97.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1586017 1.41% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1012124 0.90% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 396460 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 122028 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 89346173 79.19% 79.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10029271 8.89% 88.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4305402 3.82% 91.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 2956038 2.62% 94.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3073019 2.72% 97.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1592834 1.41% 98.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1003723 0.89% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 396113 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 122039 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 112863592 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 112824612 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 213045 18.77% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547519 48.24% 67.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 374446 32.99% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 206156 18.23% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547934 48.46% 66.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 376604 33.31% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39102059 67.88% 67.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61815 0.11% 68.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38377 0.07% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10718615 18.61% 86.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6722522 11.67% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949032 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39037949 67.85% 67.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61847 0.11% 67.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38375 0.07% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10709010 18.61% 86.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6728743 11.69% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949030 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57603342 # Type of FU issued -system.cpu.iq.rate 0.486934 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1135010 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019704 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 228544022 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67957775 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55921178 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 712213 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 334464 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328973 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58348779 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 382287 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 639736 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57535876 # Type of FU issued +system.cpu.iq.rate 0.486545 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1130694 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019652 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 228371695 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67806986 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55854530 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 714587 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336328 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 329574 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58275622 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 383662 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 641458 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1339690 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4038 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20047 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 554552 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1338736 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3932 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20392 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 579549 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18285 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 544771 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18260 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 537508 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 584207 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 44318330 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 613096 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64473181 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 145267 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10424364 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6928356 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1890724 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 42751 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 366947 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20047 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 190952 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 410451 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 601403 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 57018878 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10377294 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 584463 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 585466 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 44292826 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 620223 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64391845 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 145304 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10423192 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6953251 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1888969 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 42563 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 374293 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20392 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 192990 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 410068 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 603058 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56949005 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10367007 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 586870 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3704161 # number of nop insts executed -system.cpu.iew.exec_refs 17048455 # number of memory reference insts executed -system.cpu.iew.exec_branches 8982580 # Number of branches executed -system.cpu.iew.exec_stores 6671161 # Number of stores executed -system.cpu.iew.exec_rate 0.481994 # Inst execution rate -system.cpu.iew.wb_sent 56384919 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56250151 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28947314 # num instructions producing a value -system.cpu.iew.wb_consumers 40326252 # num instructions consuming a value +system.cpu.iew.exec_nop 3696550 # number of nop insts executed +system.cpu.iew.exec_refs 17039818 # number of memory reference insts executed +system.cpu.iew.exec_branches 8972525 # Number of branches executed +system.cpu.iew.exec_stores 6672811 # Number of stores executed +system.cpu.iew.exec_rate 0.481583 # Inst execution rate +system.cpu.iew.wb_sent 56323297 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56184104 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28889312 # num instructions producing a value +system.cpu.iew.wb_consumers 40263081 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.475495 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717828 # average fanout of values written-back +system.cpu.iew.wb_rate 0.475114 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717514 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8239076 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661191 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 548552 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 111427799 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.503633 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.455266 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8158001 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661179 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 549251 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 111396128 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.503767 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.456242 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91796177 82.38% 82.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7808087 7.01% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4129534 3.71% 93.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2155296 1.93% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1855711 1.67% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 615462 0.55% 97.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 470761 0.42% 97.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 513166 0.46% 98.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2083605 1.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91779533 82.39% 82.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7802293 7.00% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4122327 3.70% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2151634 1.93% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1854051 1.66% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 612708 0.55% 97.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 470628 0.42% 97.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 511278 0.46% 98.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2091676 1.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 111427799 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56118765 # Number of instructions committed -system.cpu.commit.committedOps 56118765 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 111396128 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56117715 # Number of instructions committed +system.cpu.commit.committedOps 56117715 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15458478 # Number of memory references committed -system.cpu.commit.loads 9084674 # Number of loads committed -system.cpu.commit.membars 226351 # Number of memory barriers committed -system.cpu.commit.branches 8434924 # Number of branches committed -system.cpu.commit.fp_insts 324518 # Number of committed floating point instructions. -system.cpu.commit.int_insts 51970227 # Number of committed integer instructions. -system.cpu.commit.function_calls 739937 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3196003 5.70% 5.70% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36180557 64.47% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60666 0.11% 70.27% # Class of committed instruction +system.cpu.commit.refs 15458158 # Number of memory references committed +system.cpu.commit.loads 9084456 # Number of loads committed +system.cpu.commit.membars 226347 # Number of memory barriers committed +system.cpu.commit.branches 8434758 # Number of branches committed +system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. +system.cpu.commit.int_insts 51969244 # Number of committed integer instructions. +system.cpu.commit.function_calls 739915 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3195962 5.70% 5.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36179881 64.47% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60661 0.11% 70.27% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 38089 0.07% 70.34% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.34% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.34% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.34% # Class of committed instruction @@ -618,192 +622,192 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9311025 16.59% 86.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6379757 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949032 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9310803 16.59% 86.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6379655 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949030 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56118765 # Class of committed instruction -system.cpu.commit.bw_lim_events 2083605 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 56117715 # Class of committed instruction +system.cpu.commit.bw_lim_events 2091676 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 173452486 # The number of ROB reads -system.cpu.rob.rob_writes 130147702 # The number of ROB writes -system.cpu.timesIdled 575947 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5434424 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599800282 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52930035 # Number of Instructions Simulated -system.cpu.committedOps 52930035 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.234988 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.234988 # CPI: Total CPI of All Threads -system.cpu.ipc 0.447430 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.447430 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74659793 # number of integer regfile reads -system.cpu.int_regfile_writes 40587610 # number of integer regfile writes -system.cpu.fp_regfile_reads 166949 # number of floating regfile reads -system.cpu.fp_regfile_writes 167607 # number of floating regfile writes -system.cpu.misc_regfile_reads 2029497 # number of misc regfile reads -system.cpu.misc_regfile_writes 939434 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1404580 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994645 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11874772 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1405092 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.451242 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 173330307 # The number of ROB reads +system.cpu.rob.rob_writes 129976168 # The number of ROB writes +system.cpu.timesIdled 574999 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5429242 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599836925 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52929026 # Number of Instructions Simulated +system.cpu.committedOps 52929026 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.234197 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.234197 # CPI: Total CPI of All Threads +system.cpu.ipc 0.447588 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.447588 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74582639 # number of integer regfile reads +system.cpu.int_regfile_writes 40531859 # number of integer regfile writes +system.cpu.fp_regfile_reads 167323 # number of floating regfile reads +system.cpu.fp_regfile_writes 167888 # number of floating regfile writes +system.cpu.misc_regfile_reads 2030592 # number of misc regfile reads +system.cpu.misc_regfile_writes 939419 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1404198 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994647 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11876238 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1404710 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.454584 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994645 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994647 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 413 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63937777 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63937777 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7284414 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7284414 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4188003 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4188003 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186359 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186359 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215726 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215726 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11472417 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11472417 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11472417 # number of overall hits -system.cpu.dcache.overall_hits::total 11472417 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1780024 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1780024 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1955346 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1955346 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23271 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23271 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 63918355 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63918355 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7286393 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7286393 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4187319 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4187319 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186500 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186500 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215720 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215720 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11473712 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11473712 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11473712 # number of overall hits +system.cpu.dcache.overall_hits::total 11473712 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1773211 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1773211 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1955934 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1955934 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23306 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23306 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3735370 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3735370 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3735370 # number of overall misses -system.cpu.dcache.overall_misses::total 3735370 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 39520730746 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39520730746 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 78084026192 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 78084026192 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 364876749 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 364876749 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 441006 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 441006 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117604756938 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117604756938 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117604756938 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117604756938 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9064438 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9064438 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6143349 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6143349 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209630 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209630 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215754 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215754 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15207787 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15207787 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15207787 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15207787 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196374 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.196374 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318287 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.318287 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111010 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111010 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 3729145 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3729145 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3729145 # number of overall misses +system.cpu.dcache.overall_misses::total 3729145 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 39410540501 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 39410540501 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 77932908678 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77932908678 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 363692999 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 363692999 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 466008 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 466008 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117343449179 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117343449179 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117343449179 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117343449179 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9059604 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9059604 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6143253 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6143253 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209806 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209806 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215748 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215748 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15202857 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15202857 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15202857 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15202857 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.195727 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.195727 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318387 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318387 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111084 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111084 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.245622 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.245622 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.245622 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.245622 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22202.358365 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22202.358365 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39933.610825 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39933.610825 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15679.461519 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15679.461519 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15750.214286 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15750.214286 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31484.098480 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31484.098480 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31484.098480 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31484.098480 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3992388 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1705 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 180260 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 24 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.147942 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 71.041667 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.245292 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.245292 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.245292 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.245292 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.522231 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.522231 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39844.344788 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39844.344788 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15605.123101 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15605.123101 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16643.142857 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16643.142857 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31466.582602 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31466.582602 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31466.582602 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31466.582602 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3975824 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1887 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 179816 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.110513 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 82.043478 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 842675 # number of writebacks -system.cpu.dcache.writebacks::total 842675 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 683874 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 683874 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664228 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1664228 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5276 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5276 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2348102 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2348102 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2348102 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2348102 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1096150 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1096150 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291118 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 291118 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17995 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17995 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 842396 # number of writebacks +system.cpu.dcache.writebacks::total 842396 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 677447 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 677447 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664842 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1664842 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5278 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5278 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2342289 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2342289 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2342289 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2342289 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1095764 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1095764 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291092 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 291092 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18028 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 18028 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1387268 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1387268 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1387268 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1387268 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27519652282 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27519652282 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11779193020 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11779193020 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204738251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204738251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 384994 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 384994 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39298845302 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 39298845302 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39298845302 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 39298845302 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423580000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423580000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999637498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999637498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423217498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423217498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120929 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120929 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047388 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047388 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085842 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085842 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1386856 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1386856 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1386856 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1386856 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27504145773 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27504145773 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11747551273 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11747551273 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205106501 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205106501 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 409992 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 409992 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39251697046 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 39251697046 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39251697046 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 39251697046 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423712500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423712500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999632498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999632498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423344998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423344998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047384 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047384 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085927 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085927 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091221 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091221 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25105.735786 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25105.735786 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40461.919290 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40461.919290 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11377.507697 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11377.507697 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13749.785714 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13749.785714 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28328.228794 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28328.228794 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28328.228794 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28328.228794 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091223 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091223 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091223 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091223 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25100.428352 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25100.428352 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40356.833142 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40356.833142 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11377.107888 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11377.107888 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14642.571429 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14642.571429 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28302.647893 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28302.647893 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28302.647893 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28302.647893 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -811,213 +815,213 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1035530 # number of replacements -system.cpu.icache.tags.tagsinuse 509.402349 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7932375 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1036038 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.656452 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26422155250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.402349 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994926 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994926 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1034381 # number of replacements +system.cpu.icache.tags.tagsinuse 509.395054 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7933874 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1034889 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.666401 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26421984250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.395054 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994912 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994912 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 302 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10056088 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10056088 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7932376 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7932376 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7932376 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7932376 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7932376 # number of overall hits -system.cpu.icache.overall_hits::total 7932376 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1087421 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1087421 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1087421 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1087421 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1087421 # number of overall misses -system.cpu.icache.overall_misses::total 1087421 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15131971529 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15131971529 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15131971529 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15131971529 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15131971529 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15131971529 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9019797 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9019797 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9019797 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9019797 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9019797 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9019797 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120559 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.120559 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.120559 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.120559 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.120559 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.120559 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13915.467449 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13915.467449 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13915.467449 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13915.467449 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13915.467449 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13915.467449 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5307 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10056110 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10056110 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7933875 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7933875 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7933875 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7933875 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7933875 # number of overall hits +system.cpu.icache.overall_hits::total 7933875 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1087081 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1087081 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1087081 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1087081 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1087081 # number of overall misses +system.cpu.icache.overall_misses::total 1087081 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15110067823 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15110067823 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15110067823 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15110067823 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15110067823 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15110067823 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9020956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9020956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9020956 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9020956 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9020956 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9020956 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120506 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.120506 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.120506 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.120506 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.120506 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.120506 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13899.670607 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13899.670607 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13899.670607 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13899.670607 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13899.670607 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13899.670607 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3991 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26.142857 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.808743 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51130 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 51130 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 51130 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 51130 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 51130 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 51130 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1036291 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1036291 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1036291 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1036291 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1036291 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1036291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12436978135 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12436978135 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12436978135 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12436978135 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12436978135 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12436978135 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114891 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114891 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114891 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114891 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114891 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114891 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12001.434090 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12001.434090 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12001.434090 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12001.434090 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12001.434090 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12001.434090 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51927 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 51927 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 51927 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 51927 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 51927 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 51927 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035154 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1035154 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1035154 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1035154 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1035154 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1035154 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12419429847 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12419429847 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12419429847 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12419429847 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12419429847 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12419429847 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114750 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114750 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114750 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114750 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114750 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114750 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11997.663968 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11997.663968 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11997.663968 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11997.663968 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11997.663968 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11997.663968 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338304 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65336.722890 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2576408 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403470 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.385625 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 338332 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65337.269998 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2574624 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 403501 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.380713 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 5538371750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53740.358806 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5341.050861 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6255.313222 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.820013 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081498 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.095449 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996959 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65166 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 494 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3497 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3329 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2414 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55432 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994354 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26978409 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26978409 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1021005 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 829436 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1850441 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 842675 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 842675 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 32 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 32 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 186561 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 186561 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1021005 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1015997 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2037002 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1021005 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1015997 # number of overall hits -system.cpu.l2cache.overall_hits::total 2037002 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15114 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273817 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 288931 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 47 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 47 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 6 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115372 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115372 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15114 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389189 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404303 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15114 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389189 # number of overall misses -system.cpu.l2cache.overall_misses::total 404303 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1159992750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17995310250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19155303000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 355494 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 355494 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 92496 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 92496 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9679121611 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9679121611 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1159992750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 27674431861 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28834424611 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1159992750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 27674431861 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28834424611 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1036119 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1103253 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2139372 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 842675 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 842675 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 79 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.tags.occ_blocks::writebacks 53714.137748 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5350.111230 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6273.021020 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.819613 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081636 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.095719 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996968 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65169 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 498 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3501 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3328 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2420 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55422 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994400 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 26963891 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26963891 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 1019836 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 829079 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1848915 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 842396 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 842396 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 20 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 20 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 186519 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 186519 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1019836 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1015598 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2035434 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1019836 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1015598 # number of overall hits +system.cpu.l2cache.overall_hits::total 2035434 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 15129 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 273823 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 288952 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 57 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 57 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 8 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 8 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 115376 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 115376 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15129 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389199 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404328 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15129 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389199 # number of overall misses +system.cpu.l2cache.overall_misses::total 404328 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1155504000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17984856500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19140360500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 331495 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 331495 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 92996 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 92996 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9647937355 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9647937355 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1155504000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 27632793855 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28788297855 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1155504000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 27632793855 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28788297855 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1034965 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1102902 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2137867 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 842396 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 842396 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 88 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 88 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 28 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 301933 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 301933 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1036119 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1405186 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2441305 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1036119 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1405186 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2441305 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014587 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248191 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.135054 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.594937 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.594937 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382111 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.382111 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014587 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.276966 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.165609 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014587 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.276966 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.165609 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76749.553394 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65720.208205 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66297.153992 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7563.702128 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7563.702128 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 15416 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 15416 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83894.893137 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83894.893137 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76749.553394 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71107.949765 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71318.849009 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76749.553394 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71107.949765 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71318.849009 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 301895 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 301895 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1034965 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1404797 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2439762 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1034965 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1404797 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2439762 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014618 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248275 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.135159 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.647727 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.647727 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.285714 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382173 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.382173 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014618 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.277050 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.165724 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014618 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.277050 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.165724 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76376.759865 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65680.591112 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66240.623010 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 5815.701754 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 5815.701754 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 11624.500000 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 11624.500000 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83621.700830 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83621.700830 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76376.759865 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70999.138885 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71200.356777 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76376.759865 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70999.138885 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71200.356777 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1026,80 +1030,80 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75929 # number of writebacks -system.cpu.l2cache.writebacks::total 75929 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75938 # number of writebacks +system.cpu.l2cache.writebacks::total 75938 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15113 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273817 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288930 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 47 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 47 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 6 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 6 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115372 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115372 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15113 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389189 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404302 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15113 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389189 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404302 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 969372000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14584664250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15554036250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 622542 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 622542 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 60006 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 60006 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8273073889 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8273073889 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 969372000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22857738139 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23827110139 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 969372000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22857738139 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23827110139 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333490000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333490000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884459000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884459000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3217949000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3217949000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014586 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248191 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135054 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.594937 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.594937 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382111 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382111 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014586 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276966 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165609 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014586 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276966 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165609 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64141.599947 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53264.275958 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53833.233828 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13245.574468 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13245.574468 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15128 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273823 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288951 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 57 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 57 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 8 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 8 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115376 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115376 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15128 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389199 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404327 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15128 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389199 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404327 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 964671250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14573298500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15537969750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 720554 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 720554 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 80008 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 80008 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8241634145 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8241634145 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 964671250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22814932645 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23779603895 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 964671250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22814932645 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23779603895 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333622500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333622500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884454000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884454000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3218076500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3218076500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014617 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248275 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135159 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.647727 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.647727 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382173 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382173 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014617 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277050 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.165724 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014617 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277050 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.165724 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63767.269302 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53221.601180 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53773.718554 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 12641.298246 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 12641.298246 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71707.813759 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71707.813759 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64141.599947 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58731.716824 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58933.940814 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64141.599947 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58731.716824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58933.940814 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71432.829575 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71432.829575 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63767.269302 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58620.224217 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58812.802249 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63767.269302 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58620.224217 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58812.802249 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1107,43 +1111,43 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2146647 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2146537 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2145159 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2145056 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 842675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 842396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41553 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 88 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 301933 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301933 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 93 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2072410 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3686471 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5758881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66311616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143911276 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 210222892 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 42053 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3325984 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012545 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.111300 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 116 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 86 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2070119 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3685432 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5755551 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66237760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143868972 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 210106732 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 42071 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3324189 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.012552 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.111331 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3284259 98.75% 98.75% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41725 1.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3282463 98.74% 98.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41726 1.26% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3325984 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2497867498 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3324189 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2496690997 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1558461609 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1556745400 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2189866891 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2189304171 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1216,23 +1220,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406221775 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406216778 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42010536 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42011283 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.260575 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.260535 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1709355371000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.260575 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078786 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078786 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1709356303000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.260535 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078783 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078783 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1248,8 +1252,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13648838856 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13648838856 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13645647112 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13645647112 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles @@ -1272,17 +1276,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328476.098768 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328476.098768 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328399.285522 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328399.285522 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206574 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 206436 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23538 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23523 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.776192 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.775921 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1298,8 +1302,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11488062928 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11488062928 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11484876678 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11484876678 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles @@ -1314,60 +1318,60 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276474.367732 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276474.367732 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276397.686706 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276397.686706 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296033 # Transaction distribution -system.membus.trans_dist::ReadResp 295940 # Transaction distribution +system.membus.trans_dist::ReadReq 296054 # Transaction distribution +system.membus.trans_dist::ReadResp 295968 # Transaction distribution system.membus.trans_dist::WriteReq 9597 # Transaction distribution system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117441 # Transaction distribution +system.membus.trans_dist::Writeback 117450 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 186 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 192 # Transaction distribution -system.membus.trans_dist::ReadExReq 115233 # Transaction distribution -system.membus.trans_dist::ReadExResp 115233 # Transaction distribution -system.membus.trans_dist::BadAddressError 93 # Transaction distribution +system.membus.trans_dist::UpgradeReq 203 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution +system.membus.trans_dist::UpgradeResp 211 # Transaction distribution +system.membus.trans_dist::ReadExReq 115230 # Transaction distribution +system.membus.trans_dist::ReadExResp 115230 # Transaction distribution +system.membus.trans_dist::BadAddressError 86 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 186 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917416 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884273 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917499 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042303 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30746540 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30748716 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36063596 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36065772 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 563522 # Request fanout histogram +system.membus.snoop_fanout::samples 563568 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 563522 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 563568 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 563522 # Request fanout histogram -system.membus.reqLayer0.occupancy 31470000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 563568 # Request fanout histogram +system.membus.reqLayer0.occupancy 31570500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1857946999 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1858044250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 115000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 107000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3754266813 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3754720043 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43145464 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43142717 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1401,28 +1405,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211003 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74662 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211002 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105561 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105562 57.93% 100.00% # number of times we switched to this ipl system.cpu.kern.ipl_count::total 182233 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73295 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73295 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148600 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817339213500 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 61863500 0.00% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 521835500 0.03% 97.79% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41125418500 2.21% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1859048331000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817332157500 97.76% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 61952500 0.00% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 528077500 0.03% 97.79% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41122369500 2.21% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1859044557000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694338 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815440 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694322 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815429 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1458,10 +1462,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4178 2.18% 2.18% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175118 91.22% 93.44% # number of callpals executed +system.cpu.kern.callpal::swpipl 175118 91.23% 93.44% # number of callpals executed system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1470,20 +1474,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191963 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1741 +system.cpu.kern.callpal::total 191962 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches +system.cpu.kern.mode_switch::user 1743 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1913 +system.cpu.kern.mode_good::user 1743 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326499 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326953 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394468 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29096339500 1.57% 1.57% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2660038000 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827291945500 98.29% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4179 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394840 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29081819500 1.56% 1.56% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2655993500 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827306736000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 3aeb0bbf5..b0cdac391 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,131 +1,131 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.842592 # Number of seconds simulated -sim_ticks 1842592129000 # Number of ticks simulated -final_tick 1842592129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1842591955000 # Number of ticks simulated +final_tick 1842591955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 226605 # Simulator instruction rate (inst/s) -host_op_rate 226605 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6393875150 # Simulator tick rate (ticks/s) -host_mem_usage 320256 # Number of bytes of host memory used -host_seconds 288.18 # Real time elapsed on the host -sim_insts 65303087 # Number of instructions simulated -sim_ops 65303087 # Number of ops (including micro ops) simulated +host_inst_rate 212167 # Simulator instruction rate (inst/s) +host_op_rate 212167 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5858461865 # Simulator tick rate (ticks/s) +host_mem_usage 373744 # Number of bytes of host memory used +host_seconds 314.52 # Real time elapsed on the host +sim_insts 66730424 # Number of instructions simulated +sim_ops 66730424 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 480640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20073664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 146816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2246336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 292800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2554880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 480192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20072256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 146880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2246976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 294016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2555648 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25796096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 480640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 146816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 292800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 920256 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7481536 # Number of bytes written to this memory -system.physmem.bytes_written::total 7481536 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7510 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 313651 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2294 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 35099 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4575 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39920 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25796928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 480192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 146880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 294016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 921088 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7481920 # Number of bytes written to this memory +system.physmem.bytes_written::total 7481920 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7503 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 313629 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2295 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 35109 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4594 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39932 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403064 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116899 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116899 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 260850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10894253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1219117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 158907 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1386568 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403077 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116905 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116905 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 260607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10893489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1219465 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 159567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1386985 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13999895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 260850 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 158907 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 499436 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4060332 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4060332 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4060332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10894253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1219117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 158907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1386568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 14000348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 260607 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 159567 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 499887 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4060541 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4060541 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4060541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 260607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10893489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1219465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 159567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1386985 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18060227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 81903 # Number of read requests accepted -system.physmem.writeReqs 62699 # Number of write requests accepted -system.physmem.readBursts 81903 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 62699 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5240384 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1408 # Total number of bytes read from write queue -system.physmem.bytesWritten 3952512 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5241792 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4012736 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 22 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 916 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 49 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5341 # Per bank write bursts -system.physmem.perBankRdBursts::1 4966 # Per bank write bursts -system.physmem.perBankRdBursts::2 4940 # Per bank write bursts -system.physmem.perBankRdBursts::3 5071 # Per bank write bursts -system.physmem.perBankRdBursts::4 5028 # Per bank write bursts -system.physmem.perBankRdBursts::5 5062 # Per bank write bursts -system.physmem.perBankRdBursts::6 5140 # Per bank write bursts -system.physmem.perBankRdBursts::7 5148 # Per bank write bursts -system.physmem.perBankRdBursts::8 5331 # Per bank write bursts +system.physmem.bw_total::total 18060889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 81945 # Number of read requests accepted +system.physmem.writeReqs 62218 # Number of write requests accepted +system.physmem.readBursts 81945 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 62218 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5243136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1344 # Total number of bytes read from write queue +system.physmem.bytesWritten 3931008 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5244480 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 3981952 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 21 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 773 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 65 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5216 # Per bank write bursts +system.physmem.perBankRdBursts::1 4952 # Per bank write bursts +system.physmem.perBankRdBursts::2 4966 # Per bank write bursts +system.physmem.perBankRdBursts::3 5032 # Per bank write bursts +system.physmem.perBankRdBursts::4 5011 # Per bank write bursts +system.physmem.perBankRdBursts::5 5077 # Per bank write bursts +system.physmem.perBankRdBursts::6 5139 # Per bank write bursts +system.physmem.perBankRdBursts::7 5153 # Per bank write bursts +system.physmem.perBankRdBursts::8 5336 # Per bank write bursts system.physmem.perBankRdBursts::9 5012 # Per bank write bursts -system.physmem.perBankRdBursts::10 5278 # Per bank write bursts -system.physmem.perBankRdBursts::11 5132 # Per bank write bursts -system.physmem.perBankRdBursts::12 4684 # Per bank write bursts -system.physmem.perBankRdBursts::13 5065 # Per bank write bursts -system.physmem.perBankRdBursts::14 5602 # Per bank write bursts -system.physmem.perBankRdBursts::15 5081 # Per bank write bursts -system.physmem.perBankWrBursts::0 3943 # Per bank write bursts -system.physmem.perBankWrBursts::1 3578 # Per bank write bursts -system.physmem.perBankWrBursts::2 3780 # Per bank write bursts -system.physmem.perBankWrBursts::3 4114 # Per bank write bursts -system.physmem.perBankWrBursts::4 3703 # Per bank write bursts -system.physmem.perBankWrBursts::5 3530 # Per bank write bursts -system.physmem.perBankWrBursts::6 4127 # Per bank write bursts -system.physmem.perBankWrBursts::7 3704 # Per bank write bursts -system.physmem.perBankWrBursts::8 4410 # Per bank write bursts -system.physmem.perBankWrBursts::9 3736 # Per bank write bursts -system.physmem.perBankWrBursts::10 4083 # Per bank write bursts -system.physmem.perBankWrBursts::11 3942 # Per bank write bursts -system.physmem.perBankWrBursts::12 3446 # Per bank write bursts -system.physmem.perBankWrBursts::13 3846 # Per bank write bursts -system.physmem.perBankWrBursts::14 4153 # Per bank write bursts -system.physmem.perBankWrBursts::15 3663 # Per bank write bursts +system.physmem.perBankRdBursts::10 5284 # Per bank write bursts +system.physmem.perBankRdBursts::11 5137 # Per bank write bursts +system.physmem.perBankRdBursts::12 4814 # Per bank write bursts +system.physmem.perBankRdBursts::13 5083 # Per bank write bursts +system.physmem.perBankRdBursts::14 5582 # Per bank write bursts +system.physmem.perBankRdBursts::15 5130 # Per bank write bursts +system.physmem.perBankWrBursts::0 3820 # Per bank write bursts +system.physmem.perBankWrBursts::1 3672 # Per bank write bursts +system.physmem.perBankWrBursts::2 3762 # Per bank write bursts +system.physmem.perBankWrBursts::3 4075 # Per bank write bursts +system.physmem.perBankWrBursts::4 3759 # Per bank write bursts +system.physmem.perBankWrBursts::5 3520 # Per bank write bursts +system.physmem.perBankWrBursts::6 4123 # Per bank write bursts +system.physmem.perBankWrBursts::7 3706 # Per bank write bursts +system.physmem.perBankWrBursts::8 4379 # Per bank write bursts +system.physmem.perBankWrBursts::9 3471 # Per bank write bursts +system.physmem.perBankWrBursts::10 3889 # Per bank write bursts +system.physmem.perBankWrBursts::11 3981 # Per bank write bursts +system.physmem.perBankWrBursts::12 3541 # Per bank write bursts +system.physmem.perBankWrBursts::13 3879 # Per bank write bursts +system.physmem.perBankWrBursts::14 4169 # Per bank write bursts +system.physmem.perBankWrBursts::15 3676 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1841579852500 # Total gap between requests +system.physmem.totGap 1841579678500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 81903 # Read request sizes (log2) +system.physmem.readPktSize::6 81945 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 62699 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 65847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see +system.physmem.writePktSize::6 62218 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 65839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1657 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -153,193 +153,216 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 3168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 3243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 81 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 22200 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 414.094414 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 234.871610 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 395.166984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 6979 31.44% 31.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4758 21.43% 52.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1802 8.12% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1018 4.59% 65.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 909 4.09% 69.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 488 2.20% 71.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 377 1.70% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 379 1.71% 75.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5490 24.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 22200 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2135 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 38.346604 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1004.576162 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2133 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 22279 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 411.784371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 233.119875 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 394.569349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7102 31.88% 31.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4721 21.19% 53.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1798 8.07% 61.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1010 4.53% 65.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 955 4.29% 69.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 478 2.15% 72.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 370 1.66% 73.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 364 1.63% 75.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5481 24.60% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 22279 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2129 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 38.475810 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1006.180082 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2127 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2135 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2135 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 28.926464 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.717874 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 36.556650 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 42 1.97% 1.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 3 0.14% 2.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 1647 77.14% 79.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 96 4.50% 83.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 109 5.11% 88.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 21 0.98% 89.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 47 2.20% 92.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 14 0.66% 92.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 5 0.23% 92.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 4 0.19% 93.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 8 0.37% 93.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 8 0.37% 93.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 2 0.09% 93.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 2 0.09% 94.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.05% 94.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 13 0.61% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 15 0.70% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 12 0.56% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 7 0.33% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 36 1.69% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 13 0.61% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 7 0.33% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 7 0.33% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 5 0.23% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.14% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.14% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.05% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::296-303 1 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2135 # Writes before turning the bus around for reads -system.physmem.totQLat 816878250 # Total ticks spent queuing -system.physmem.totMemAccLat 2352147000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 409405000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9976.41 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2129 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2129 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 28.850164 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.675931 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 36.499081 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 34 1.60% 1.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.33% 1.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.05% 1.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 1 0.05% 2.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 1615 75.86% 77.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 35 1.64% 79.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 10 0.47% 79.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 84 3.95% 83.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 64 3.01% 86.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 45 2.11% 89.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 9 0.42% 89.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.52% 90.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 35 1.64% 91.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 5 0.23% 91.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 21 0.99% 92.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.09% 92.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 3 0.14% 93.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.09% 93.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.23% 93.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.05% 93.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.19% 93.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.05% 93.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.14% 93.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.19% 94.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.05% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.05% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.28% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.09% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.05% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 15 0.70% 95.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.14% 95.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.09% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.05% 95.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 4 0.19% 95.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 43 2.02% 97.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.05% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 11 0.52% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.14% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.14% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.09% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 6 0.28% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 4 0.19% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 5 0.23% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 3 0.14% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 3 0.14% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 3 0.14% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.09% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::244-247 1 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2129 # Writes before turning the bus around for reads +system.physmem.totQLat 814366500 # Total ticks spent queuing +system.physmem.totMemAccLat 2350441500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 409620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9940.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28726.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.15 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28690.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.85 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.85 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing system.physmem.avgWrQLen 8.28 # Average write queue length when enqueuing -system.physmem.readRowHits 70255 # Number of row buffer hits during reads -system.physmem.writeRowHits 51184 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.80 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.84 # Row buffer hit rate for writes -system.physmem.avgGap 12735507.48 # Average gap between requests -system.physmem.pageHitRate 84.53 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1767479155500 # Time in different power states -system.physmem.memoryStateTime::REF 61527960000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 13578075750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 83696760 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 84135240 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 45667875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 45907125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 317428800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 321243000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 197503920 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 202687920 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 120348689760 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 120348689760 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 46124478945 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 45810126225 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1065091037250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1065366785250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1232208503310 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1232179574520 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.738964 # Core power per rank (mW) -system.physmem.averagePower::1 668.723264 # Core power per rank (mW) +system.physmem.readRowHits 70260 # Number of row buffer hits during reads +system.physmem.writeRowHits 50807 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.76 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.69 # Row buffer hit rate for writes +system.physmem.avgGap 12774287.98 # Average gap between requests +system.physmem.pageHitRate 84.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 83779920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 45618375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 316258800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 197231760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89126157120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 35724246975 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 802806617250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 928299910200 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.726630 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1309959191250 # Time in different power states +system.physmem_0.memoryStateTime::REF 45565260000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9222216250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 84649320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 46030875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 322748400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 200782800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89126157120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35431940430 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 799831550250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 925043859195 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.972279 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1310405285500 # Time in different power states +system.physmem_1.memoryStateTime::REF 45565260000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8771812500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4840766 # DTB read hits +system.cpu0.dtb.read_hits 4841130 # DTB read hits system.cpu0.dtb.read_misses 6162 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations system.cpu0.dtb.read_accesses 429577 # DTB read accesses -system.cpu0.dtb.write_hits 3449248 # DTB write hits +system.cpu0.dtb.write_hits 3448228 # DTB write hits system.cpu0.dtb.write_misses 688 # DTB write misses system.cpu0.dtb.write_acv 85 # DTB write access violations system.cpu0.dtb.write_accesses 165228 # DTB write accesses -system.cpu0.dtb.data_hits 8290014 # DTB hits +system.cpu0.dtb.data_hits 8289358 # DTB hits system.cpu0.dtb.data_misses 6850 # DTB misses system.cpu0.dtb.data_acv 211 # DTB access violations system.cpu0.dtb.data_accesses 594805 # DTB accesses -system.cpu0.itb.fetch_hits 2745005 # ITB hits +system.cpu0.itb.fetch_hits 2744473 # ITB hits system.cpu0.itb.fetch_misses 3071 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2748076 # ITB accesses +system.cpu0.itb.fetch_accesses 2747544 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -352,87 +375,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 930170502 # number of cpu cycles simulated +system.cpu0.numCycles 929111283 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31084978 # Number of instructions committed -system.cpu0.committedOps 31084978 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 28990115 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 165280 # Number of float alu accesses -system.cpu0.num_func_calls 801354 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3884267 # number of instructions that are conditional controls -system.cpu0.num_int_insts 28990115 # number of integer instructions -system.cpu0.num_fp_insts 165280 # number of float instructions -system.cpu0.num_int_register_reads 40144651 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21293303 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 85481 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 86924 # number of times the floating registers were written -system.cpu0.num_mem_refs 8319976 # number of memory refs -system.cpu0.num_load_insts 4862063 # Number of load instructions -system.cpu0.num_store_insts 3457913 # Number of store instructions -system.cpu0.num_idle_cycles 907838728.357051 # Number of idle cycles -system.cpu0.num_busy_cycles 22331773.642949 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024008 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975992 # Percentage of idle cycles -system.cpu0.Branches 4943919 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1583961 5.09% 5.09% # Class of executed instruction -system.cpu0.op_class::IntAlu 20486094 65.89% 70.98% # Class of executed instruction -system.cpu0.op_class::IntMult 31888 0.10% 71.09% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.09% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12950 0.04% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1606 0.01% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::MemRead 4993462 16.06% 87.19% # Class of executed instruction -system.cpu0.op_class::MemWrite 3461022 11.13% 98.32% # Class of executed instruction -system.cpu0.op_class::IprAccess 521056 1.68% 100.00% # Class of executed instruction +system.cpu0.committedInsts 30392058 # Number of instructions committed +system.cpu0.committedOps 30392058 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 28296981 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 165313 # Number of float alu accesses +system.cpu0.num_func_calls 800920 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3653475 # number of instructions that are conditional controls +system.cpu0.num_int_insts 28296981 # number of integer instructions +system.cpu0.num_fp_insts 165313 # number of float instructions +system.cpu0.num_int_register_reads 38988704 # number of times the integer registers were read +system.cpu0.num_int_register_writes 20831324 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 85482 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 86956 # number of times the floating registers were written +system.cpu0.num_mem_refs 8319320 # number of memory refs +system.cpu0.num_load_insts 4862427 # Number of load instructions +system.cpu0.num_store_insts 3456893 # Number of store instructions +system.cpu0.num_idle_cycles 905971177.002448 # Number of idle cycles +system.cpu0.num_busy_cycles 23140105.997552 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024906 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975094 # Percentage of idle cycles +system.cpu0.Branches 4712544 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1584509 5.21% 5.21% # Class of executed instruction +system.cpu0.op_class::IntAlu 19793641 65.11% 70.32% # Class of executed instruction +system.cpu0.op_class::IntMult 31883 0.10% 70.43% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 70.43% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12951 0.04% 70.47% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 70.47% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 70.47% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 70.47% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1606 0.01% 70.48% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.48% # Class of executed instruction +system.cpu0.op_class::MemRead 4993701 16.43% 86.90% # Class of executed instruction +system.cpu0.op_class::MemWrite 3459999 11.38% 98.29% # Class of executed instruction +system.cpu0.op_class::IprAccess 520829 1.71% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 31092039 # Class of executed instruction +system.cpu0.op_class::total 30399119 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6422 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211371 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6424 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211373 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 74797 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105691 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182570 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105693 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182572 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 73430 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73430 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148942 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819773509500 98.76% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38545500 0.00% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 357643000 0.02% 98.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22421661500 1.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842591359500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1819763275500 98.76% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38885000 0.00% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 357575500 0.02% 98.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22431449500 1.22% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842591185500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694761 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815808 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694748 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815799 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -471,7 +494,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175311 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175313 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -480,266 +503,266 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192226 # number of callpals executed +system.cpu0.kern.callpal::total 192228 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1740 # number of protection mode switches system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1908 -system.cpu0.kern.mode_good::user 1738 +system.cpu0.kern.mode_good::kernel 1910 +system.cpu0.kern.mode_good::user 1740 system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322188 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322526 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29639680500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2561811500 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810389863000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.391474 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29641344500 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2562591500 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810387245000 98.25% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4177 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1393201 # number of replacements +system.cpu0.dcache.tags.replacements 1393017 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997818 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13277254 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393713 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.526534 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 13281490 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393529 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.530831 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 261.608452 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 74.750107 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 175.639259 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.510954 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.145996 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.343045 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 260.752731 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 75.043138 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.201949 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.509283 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.146569 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.344144 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63354718 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63354718 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4014926 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1052133 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2504051 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7571110 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3157714 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 807247 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1357321 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5322282 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114982 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 18680 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 50783 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184445 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123850 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 20650 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 54829 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199329 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7172640 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1859380 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3861372 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12893392 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7172640 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1859380 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3861372 # number of overall hits -system.cpu0.dcache.overall_hits::total 12893392 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 712217 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 95395 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 559235 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1366847 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 166399 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 43585 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 617129 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 827113 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9420 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2097 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7598 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19115 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 63366474 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63366474 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4014509 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1053432 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2506621 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7574562 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3156846 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 808200 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1357961 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5323007 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114880 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 18791 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 50813 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184484 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123743 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 20765 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 54820 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199328 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7171355 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1861632 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3864582 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12897569 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7171355 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1861632 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3864582 # number of overall hits +system.cpu0.dcache.overall_hits::total 12897569 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 713110 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 94552 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 558128 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1365790 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 166356 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 43595 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 617033 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 826984 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9412 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2104 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7556 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19072 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 8 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 878616 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 138980 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1176364 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2193960 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 878616 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 138980 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1176364 # number of overall misses -system.cpu0.dcache.overall_misses::total 2193960 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2203388500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9682985565 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11886374065 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1649926260 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19421964168 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 21071890428 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27653250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 126867246 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 154520496 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 104000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 104000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 3853314760 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 29104949733 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 32958264493 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3853314760 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 29104949733 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 32958264493 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4727143 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1147528 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3063286 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8937957 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3324113 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 850832 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1974450 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6149395 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124402 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 20777 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58381 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203560 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123852 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 20650 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 54837 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199339 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8051256 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 1998360 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5037736 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15087352 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8051256 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 1998360 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5037736 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15087352 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150665 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083131 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.182560 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.152926 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050058 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051226 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.312557 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.134503 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075722 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100929 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130145 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.093904 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 7 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 879466 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 138147 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1175161 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2192774 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 879466 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 138147 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1175161 # number of overall misses +system.cpu0.dcache.overall_misses::total 2192774 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2193347250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9664547340 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11857894590 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1652894510 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19391335975 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 21044230485 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27729500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 125483249 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 153212749 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 91000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 91000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 3846241760 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 29055883315 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 32902125075 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 3846241760 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 29055883315 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 32902125075 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4727619 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1147984 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 3064749 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8940352 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3323202 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 851795 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 1974994 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6149991 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124292 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 20895 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58369 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203556 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123745 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 20765 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 54827 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 199337 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8050821 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 1999779 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 5039743 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15090343 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8050821 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 1999779 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 5039743 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15090343 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150839 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082364 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.182112 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.152767 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050059 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051180 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.312423 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.134469 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075725 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100694 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.129452 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.093694 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000016 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000146 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000050 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109128 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069547 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233510 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.145417 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109128 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069547 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.233510 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.145417 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23097.526076 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17314.698767 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8696.199403 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37855.369049 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31471.481924 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25476.434814 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13187.052933 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16697.452751 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8083.729846 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000128 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000045 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109239 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069081 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233179 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.145310 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109239 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069081 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.233179 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.145310 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23197.259180 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17316.005182 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8682.077472 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37914.772566 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31426.740507 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 25446.962075 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13179.420152 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16607.100185 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8033.386588 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10400 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27725.678227 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24741.448848 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15022.272281 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27725.678227 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24741.448848 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15022.272281 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 825872 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 866 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 61038 # number of cycles access was blocked +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10111.111111 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27841.659681 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24725.023478 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15004.795330 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27841.659681 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24725.023478 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15004.795330 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 825255 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1343 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 61465 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.530456 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 96.222222 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.426422 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 149.222222 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835902 # number of writebacks -system.cpu0.dcache.writebacks::total 835902 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 293112 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 293112 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 524642 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 524642 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1568 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1568 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 817754 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 817754 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 817754 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 817754 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 95395 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 266123 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 361518 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43585 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 92487 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 136072 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2097 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6030 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8127 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 8 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 138980 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 358610 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 497590 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 138980 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 358610 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 497590 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2005063500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4453995148 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6459058648 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1554433740 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2785719201 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4340152941 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 23457750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 72881252 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96339002 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 88000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 88000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3559497240 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7239714349 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10799211589 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3559497240 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7239714349 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10799211589 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 248461000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342715000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 591176000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 319650500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 420043000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 739693500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 568111500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 762758000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1330869500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083131 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086875 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040447 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051226 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046842 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022128 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100929 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103287 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.039924 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000146 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069547 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071185 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032981 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069547 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071185 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032981 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21018.538707 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16736.603555 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17866.492534 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35664.419869 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 30120.116351 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31896.003153 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11186.337625 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12086.443118 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11854.189984 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 835667 # number of writebacks +system.cpu0.dcache.writebacks::total 835667 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 292188 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 292188 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 524505 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 524505 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1570 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1570 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 816693 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 816693 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 816693 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 816693 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 94552 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 265940 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 360492 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43595 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 92528 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 136123 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2104 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5986 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8090 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 7 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 138147 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 358468 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 496615 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 138147 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 358468 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 496615 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1996702750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4449426882 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6446129632 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1557368490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2781486410 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4338854900 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 23520500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 72740751 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96261251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 77000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 77000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3554071240 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7230913292 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10784984532 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3554071240 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7230913292 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10784984532 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 249355000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342279000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 591634000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320316500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 419818000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740134500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 569671500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 762097000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1331768500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082364 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086774 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040322 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051180 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046850 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022134 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100694 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.102554 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.039743 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000128 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000035 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069081 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071128 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032909 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069081 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071128 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032909 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21117.509413 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16730.942626 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17881.477625 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35723.557518 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 30061.023798 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31874.517165 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11178.944867 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12151.812730 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11898.794932 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25611.578932 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20188.266777 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21703.031791 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25611.578932 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20188.266777 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21703.031791 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25726.734855 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20171.712097 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21716.993107 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25726.734855 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20171.712097 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21716.993107 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -750,163 +773,163 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 964194 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.195402 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 40365438 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 964705 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 41.842261 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10190503250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 263.118461 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.369800 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 180.707141 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.513903 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131582 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.352944 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998429 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 964323 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.193139 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 39678129 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 964834 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 41.124306 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10191163250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 263.937948 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 65.959779 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 181.295411 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.515504 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.128828 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.354093 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998424 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 42311419 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 42311419 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 30577752 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7329263 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2458423 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 40365438 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30577752 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7329263 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2458423 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 40365438 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 30577752 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7329263 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2458423 # number of overall hits -system.cpu0.icache.overall_hits::total 40365438 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 514287 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 123865 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 342932 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 981084 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 514287 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 123865 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 342932 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 981084 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 514287 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 123865 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 342932 # number of overall misses -system.cpu0.icache.overall_misses::total 981084 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1766313750 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4813307095 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6579620845 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1766313750 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4813307095 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6579620845 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1766313750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4813307095 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6579620845 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 31092039 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7453128 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2801355 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 41346522 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 31092039 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7453128 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2801355 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 41346522 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 31092039 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7453128 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2801355 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 41346522 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016541 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016619 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122416 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.023728 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016541 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016619 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122416 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023728 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016541 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016619 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122416 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023728 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14259.990716 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14035.747889 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6706.480633 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14259.990716 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14035.747889 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6706.480633 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14259.990716 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14035.747889 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6706.480633 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3823 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 41624427 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 41624427 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29884884 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7331949 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2461296 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 39678129 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29884884 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7331949 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2461296 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 39678129 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29884884 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7331949 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2461296 # number of overall hits +system.cpu0.icache.overall_hits::total 39678129 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 514235 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 124188 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 342842 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 981265 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 514235 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 124188 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 342842 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 981265 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 514235 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 124188 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 342842 # number of overall misses +system.cpu0.icache.overall_misses::total 981265 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1771676000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4819389197 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6591065197 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1771676000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4819389197 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6591065197 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1771676000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4819389197 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6591065197 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30399119 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7456137 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2804138 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 40659394 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30399119 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7456137 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2804138 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 40659394 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30399119 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7456137 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2804138 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 40659394 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016916 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016656 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122263 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.024134 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016916 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016656 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122263 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.024134 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016916 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016656 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122263 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.024134 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14266.080459 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14057.172683 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6716.906439 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14266.080459 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14057.172683 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6716.906439 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14266.080459 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14057.172683 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6716.906439 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2709 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 167 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.892216 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.705882 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16187 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16187 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16187 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16187 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16187 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16187 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 123865 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 326745 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 450610 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 123865 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 326745 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 450610 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 123865 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 326745 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 450610 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1517675250 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3982959026 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5500634276 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1517675250 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3982959026 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5500634276 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1517675250 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3982959026 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5500634276 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016619 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116638 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010898 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016619 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116638 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010898 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016619 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116638 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010898 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12252.656118 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12189.808646 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12207.084343 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12252.656118 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12189.808646 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12207.084343 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12252.656118 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12189.808646 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12207.084343 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16232 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16232 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16232 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16232 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16232 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16232 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 124188 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 326610 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 450798 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 124188 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 326610 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 450798 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 124188 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 326610 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 450798 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1522394000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3982795175 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5505189175 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1522394000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3982795175 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5505189175 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1522394000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3982795175 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5505189175 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011087 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011087 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011087 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12212.097602 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12212.097602 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12212.097602 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1166206 # DTB read hits +system.cpu1.dtb.read_hits 1166781 # DTB read hits system.cpu1.dtb.read_misses 1314 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations system.cpu1.dtb.read_accesses 141633 # DTB read accesses -system.cpu1.dtb.write_hits 871808 # DTB write hits +system.cpu1.dtb.write_hits 872888 # DTB write hits system.cpu1.dtb.write_misses 168 # DTB write misses system.cpu1.dtb.write_acv 22 # DTB write access violations system.cpu1.dtb.write_accesses 57088 # DTB write accesses -system.cpu1.dtb.data_hits 2038014 # DTB hits +system.cpu1.dtb.data_hits 2039669 # DTB hits system.cpu1.dtb.data_misses 1482 # DTB misses system.cpu1.dtb.data_acv 56 # DTB access violations system.cpu1.dtb.data_accesses 198721 # DTB accesses -system.cpu1.itb.fetch_hits 847614 # ITB hits +system.cpu1.itb.fetch_hits 848090 # ITB hits system.cpu1.itb.fetch_misses 662 # ITB misses system.cpu1.itb.fetch_acv 32 # ITB acv -system.cpu1.itb.fetch_accesses 848276 # ITB accesses +system.cpu1.itb.fetch_accesses 848752 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -919,64 +942,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953409628 # number of cpu cycles simulated +system.cpu1.numCycles 953408444 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7451589 # Number of instructions committed -system.cpu1.committedOps 7451589 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6926409 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 43920 # Number of float alu accesses -system.cpu1.num_func_calls 202937 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 904115 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6926409 # number of integer instructions -system.cpu1.num_fp_insts 43920 # number of float instructions -system.cpu1.num_int_register_reads 9636713 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5051586 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 23745 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24097 # number of times the floating registers were written -system.cpu1.num_mem_refs 2044932 # number of memory refs -system.cpu1.num_load_insts 1170872 # Number of load instructions -system.cpu1.num_store_insts 874060 # Number of store instructions -system.cpu1.num_idle_cycles 925046236.205368 # Number of idle cycles -system.cpu1.num_busy_cycles 28363391.794632 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029749 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970251 # Percentage of idle cycles -system.cpu1.Branches 1171500 # Number of branches fetched -system.cpu1.op_class::No_OpClass 399169 5.36% 5.36% # Class of executed instruction -system.cpu1.op_class::IntAlu 4836084 64.89% 70.24% # Class of executed instruction -system.cpu1.op_class::IntMult 8208 0.11% 70.35% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.35% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5096 0.07% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 70.43% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.43% # Class of executed instruction -system.cpu1.op_class::MemRead 1198833 16.08% 86.52% # Class of executed instruction -system.cpu1.op_class::MemWrite 875271 11.74% 98.26% # Class of executed instruction -system.cpu1.op_class::IprAccess 129656 1.74% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7454598 # Number of instructions committed +system.cpu1.committedOps 7454598 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 6929268 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 43953 # Number of float alu accesses +system.cpu1.num_func_calls 203515 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 903765 # number of instructions that are conditional controls +system.cpu1.num_int_insts 6929268 # number of integer instructions +system.cpu1.num_fp_insts 43953 # number of float instructions +system.cpu1.num_int_register_reads 9641119 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5054145 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 23746 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24129 # number of times the floating registers were written +system.cpu1.num_mem_refs 2046592 # number of memory refs +system.cpu1.num_load_insts 1171450 # Number of load instructions +system.cpu1.num_store_insts 875142 # Number of store instructions +system.cpu1.num_idle_cycles 924951081.946169 # Number of idle cycles +system.cpu1.num_busy_cycles 28457362.053831 # Number of busy cycles +system.cpu1.not_idle_fraction 0.029848 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.970152 # Percentage of idle cycles +system.cpu1.Branches 1171881 # Number of branches fetched +system.cpu1.op_class::No_OpClass 398972 5.35% 5.35% # Class of executed instruction +system.cpu1.op_class::IntAlu 4837309 64.88% 70.23% # Class of executed instruction +system.cpu1.op_class::IntMult 8193 0.11% 70.34% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.34% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5097 0.07% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.41% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 70.42% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::MemRead 1199545 16.09% 86.50% # Class of executed instruction +system.cpu1.op_class::MemWrite 876356 11.75% 98.26% # Class of executed instruction +system.cpu1.op_class::IprAccess 129854 1.74% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7453127 # Class of executed instruction +system.cpu1.op_class::total 7456136 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -994,35 +1017,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8975833 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8240091 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 125146 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6986744 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 4884457 # Number of BTB hits +system.cpu2.branchPred.lookups 9673449 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8936896 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 125098 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7569787 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 5584968 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 69.910347 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 298693 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7800 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 73.779725 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 299823 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7809 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3460113 # DTB read hits -system.cpu2.dtb.read_misses 12059 # DTB read misses -system.cpu2.dtb.read_acv 120 # DTB read access violations -system.cpu2.dtb.read_accesses 225843 # DTB read accesses -system.cpu2.dtb.write_hits 2120785 # DTB write hits -system.cpu2.dtb.write_misses 2578 # DTB write misses -system.cpu2.dtb.write_acv 111 # DTB write access violations -system.cpu2.dtb.write_accesses 84303 # DTB write accesses -system.cpu2.dtb.data_hits 5580898 # DTB hits -system.cpu2.dtb.data_misses 14637 # DTB misses -system.cpu2.dtb.data_acv 231 # DTB access violations -system.cpu2.dtb.data_accesses 310146 # DTB accesses -system.cpu2.itb.fetch_hits 534656 # ITB hits -system.cpu2.itb.fetch_misses 5715 # ITB misses -system.cpu2.itb.fetch_acv 156 # ITB acv -system.cpu2.itb.fetch_accesses 540371 # ITB accesses +system.cpu2.dtb.read_hits 3461968 # DTB read hits +system.cpu2.dtb.read_misses 12174 # DTB read misses +system.cpu2.dtb.read_acv 114 # DTB read access violations +system.cpu2.dtb.read_accesses 224881 # DTB read accesses +system.cpu2.dtb.write_hits 2122047 # DTB write hits +system.cpu2.dtb.write_misses 2563 # DTB write misses +system.cpu2.dtb.write_acv 106 # DTB write access violations +system.cpu2.dtb.write_accesses 83942 # DTB write accesses +system.cpu2.dtb.data_hits 5584015 # DTB hits +system.cpu2.dtb.data_misses 14737 # DTB misses +system.cpu2.dtb.data_acv 220 # DTB access violations +system.cpu2.dtb.data_accesses 308823 # DTB accesses +system.cpu2.itb.fetch_hits 534012 # ITB hits +system.cpu2.itb.fetch_misses 5788 # ITB misses +system.cpu2.itb.fetch_acv 158 # ITB acv +system.cpu2.itb.fetch_accesses 539800 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1035,305 +1058,305 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 29309170 # number of cpu cycles simulated +system.cpu2.numCycles 30013580 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9355872 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 35312418 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8975833 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 5183150 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 17863271 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 408038 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 9363383 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 37425902 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9673449 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 5884791 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 18558568 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 408186 # Number of cycles fetch has spent squashing system.cpu2.fetch.TlbCycles 247 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 9336 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1926 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 226509 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 98836 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 360 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2801357 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 93254 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27760138 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.272055 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.388957 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.MiscStallCycles 10133 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1974 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 231517 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 99918 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 308 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2804138 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 92736 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 28469903 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.314578 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.374234 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20067804 72.29% 72.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 312324 1.13% 73.42% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 471431 1.70% 75.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3277065 11.80% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 832356 3.00% 89.92% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 194310 0.70% 90.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 239050 0.86% 91.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 435621 1.57% 93.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1930177 6.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 20072313 70.50% 70.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 312422 1.10% 71.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 471724 1.66% 73.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3982470 13.99% 87.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 833365 2.93% 90.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 193345 0.68% 90.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 238464 0.84% 91.69% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 434747 1.53% 93.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1931053 6.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27760138 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.306247 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.204825 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7663207 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 13056286 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6071971 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 531660 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 191161 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 175121 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13218 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 31964587 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 42189 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 191161 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7944282 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4747926 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6306317 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 6292094 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2032514 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 31148031 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 68690 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 405455 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 57635 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 961672 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 20857546 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 38489272 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 38429323 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56078 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 18957389 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1900157 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 527032 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63032 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3906781 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3488819 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2211142 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 463556 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 329659 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 28630875 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 676639 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 28279580 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 16369 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2426454 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1141058 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 483735 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27760138 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.018712 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.595651 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 28469903 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.322302 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.246966 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7673000 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 13050358 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6778876 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 530616 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 191226 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 175016 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13225 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34075356 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 43360 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 191226 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7953535 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4758129 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6310003 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 6998808 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2012380 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33260601 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 68695 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 404029 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 57097 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 943831 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 22264761 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 41311324 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41251440 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56013 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 20369021 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1895740 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 527174 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63098 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3903100 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3489643 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2214871 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 462169 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 329723 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 30742037 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 676819 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 30393110 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 17376 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2421658 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1144384 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 483915 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 28469903 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.067552 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.605150 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17419876 62.75% 62.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2765921 9.96% 72.72% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1372782 4.95% 77.66% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4034544 14.53% 92.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1009748 3.64% 95.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 570537 2.06% 97.89% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 383332 1.38% 99.27% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 154390 0.56% 99.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 49008 0.18% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17422923 61.20% 61.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2767864 9.72% 70.92% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1373994 4.83% 75.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4735624 16.63% 92.38% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1013556 3.56% 95.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 570411 2.00% 97.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 382804 1.34% 99.29% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 154533 0.54% 99.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 48194 0.17% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27760138 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 28469903 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 83197 21.73% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 176333 46.06% 67.80% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 123266 32.20% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 82144 21.47% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.47% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 176872 46.24% 67.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 123495 32.29% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 22202311 78.51% 78.52% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21087 0.07% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 78.59% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20489 0.07% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 78.67% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3587142 12.68% 91.35% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2144327 7.58% 98.94% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 300564 1.06% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 24311305 79.99% 80.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21079 0.07% 80.07% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 80.07% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20485 0.07% 80.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 80.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 80.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 80.13% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3589842 11.81% 91.95% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2146129 7.06% 99.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 300610 0.99% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 28279580 # Type of FU issued -system.cpu2.iq.rate 0.964871 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 382796 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.013536 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 84465202 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 31620396 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27707676 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 253261 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 119445 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 116967 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 28524107 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 135829 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206522 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 30393110 # Type of FU issued +system.cpu2.iq.rate 1.012645 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 382511 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.012585 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 89403074 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 33727235 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 29817840 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 252936 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 119279 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 116815 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 30637549 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 135632 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 205530 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 435956 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1412 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6012 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 178431 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 436638 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1484 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6154 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 181627 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5029 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 168380 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4994 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 170094 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 191161 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3997544 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 279888 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 30686163 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 51755 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3488819 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2211142 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 602233 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 15645 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 216255 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6012 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 63410 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 133827 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197237 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 28083451 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3480678 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 196129 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 191226 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3996466 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 295299 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32798710 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 54858 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3489643 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2214871 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 602209 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 15595 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 231865 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6154 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 62873 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 134195 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 197068 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 30195469 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3482644 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 197641 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1378649 # number of nop insts executed -system.cpu2.iew.exec_refs 5608668 # number of memory reference insts executed -system.cpu2.iew.exec_branches 5940571 # Number of branches executed -system.cpu2.iew.exec_stores 2127990 # Number of stores executed -system.cpu2.iew.exec_rate 0.958180 # Inst execution rate -system.cpu2.iew.wb_sent 27865492 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27824643 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15848860 # num instructions producing a value -system.cpu2.iew.wb_consumers 19489990 # num instructions consuming a value +system.cpu2.iew.exec_nop 1379854 # number of nop insts executed +system.cpu2.iew.exec_refs 5611883 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6643679 # Number of branches executed +system.cpu2.iew.exec_stores 2129239 # Number of stores executed +system.cpu2.iew.exec_rate 1.006060 # Inst execution rate +system.cpu2.iew.wb_sent 29976342 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 29934655 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17254819 # num instructions producing a value +system.cpu2.iew.wb_consumers 20895222 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.949349 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.813179 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.997370 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.825778 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2662629 # The number of squashed insts skipped by commit +system.cpu2.commit.commitSquashedInsts 2658447 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 192904 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 180156 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 27293607 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.025131 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.859726 # Number of insts commited each cycle +system.cpu2.commit.branchMispredicts 180111 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 28004103 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.074728 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.862098 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18211809 66.73% 66.73% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2232896 8.18% 74.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1177901 4.32% 79.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 3741262 13.71% 92.93% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 541174 1.98% 94.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 200137 0.73% 95.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 164418 0.60% 96.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 176928 0.65% 96.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 847082 3.10% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18216020 65.05% 65.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2235913 7.98% 73.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1176646 4.20% 77.23% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4445185 15.87% 93.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 540129 1.93% 95.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 200547 0.72% 95.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 166033 0.59% 96.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 176455 0.63% 96.97% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 847175 3.03% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 27293607 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 27979525 # Number of instructions committed -system.cpu2.commit.committedOps 27979525 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 28004103 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30096794 # Number of instructions committed +system.cpu2.commit.committedOps 30096794 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5085574 # Number of memory references committed -system.cpu2.commit.loads 3052863 # Number of loads committed -system.cpu2.commit.membars 67982 # Number of memory barriers committed -system.cpu2.commit.branches 5768887 # Number of branches committed -system.cpu2.commit.fp_insts 115191 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 26471742 # Number of committed integer instructions. -system.cpu2.commit.function_calls 239400 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1215445 4.34% 4.34% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 21266434 76.01% 80.35% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20635 0.07% 80.42% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 80.42% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20039 0.07% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 80.50% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3120845 11.15% 91.65% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2034343 7.27% 98.93% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 300564 1.07% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5086249 # Number of memory references committed +system.cpu2.commit.loads 3053005 # Number of loads committed +system.cpu2.commit.membars 67981 # Number of memory barriers committed +system.cpu2.commit.branches 6474041 # Number of branches committed +system.cpu2.commit.fp_insts 115125 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 28589001 # Number of committed integer instructions. +system.cpu2.commit.function_calls 239427 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1215466 4.04% 4.04% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 23382957 77.69% 81.73% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20643 0.07% 81.80% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 81.80% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20037 0.07% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 81.87% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3120986 10.37% 92.24% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2034876 6.76% 99.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 300609 1.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 27979525 # Class of committed instruction -system.cpu2.commit.bw_lim_events 847082 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 30096794 # Class of committed instruction +system.cpu2.commit.bw_lim_events 847175 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 57015033 # The number of ROB reads -system.cpu2.rob.rob_writes 61749251 # The number of ROB writes -system.cpu2.timesIdled 174924 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1549032 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1748451761 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 26766520 # Number of Instructions Simulated -system.cpu2.committedOps 26766520 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.094994 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.094994 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.913247 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.913247 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 36812900 # number of integer regfile reads -system.cpu2.int_regfile_writes 19756149 # number of integer regfile writes -system.cpu2.fp_regfile_reads 70792 # number of floating regfile reads -system.cpu2.fp_regfile_writes 70904 # number of floating regfile writes -system.cpu2.misc_regfile_reads 3635366 # number of misc regfile reads -system.cpu2.misc_regfile_writes 270473 # number of misc regfile writes +system.cpu2.rob.rob_reads 59838509 # The number of ROB reads +system.cpu2.rob.rob_writes 65974697 # The number of ROB writes +system.cpu2.timesIdled 175016 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1543677 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1747747743 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 28883768 # Number of Instructions Simulated +system.cpu2.committedOps 28883768 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.039116 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.039116 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.962357 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.962357 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 39632695 # number of integer regfile reads +system.cpu2.int_regfile_writes 21162382 # number of integer regfile writes +system.cpu2.fp_regfile_reads 70702 # number of floating regfile reads +system.cpu2.fp_regfile_writes 70843 # number of floating regfile writes +system.cpu2.misc_regfile_reads 4340126 # number of misc regfile reads +system.cpu2.misc_regfile_writes 270474 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1389,25 +1412,25 @@ system.iobus.reqLayer1.occupancy 102000 # La system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5523000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5529000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 2073000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 169052512 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 166547212 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9350000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9356000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17532500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17276500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.262652 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.262651 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693890023000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.262652 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 1693890143000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.262651 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.078916 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.078916 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1425,8 +1448,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 9417462 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 9417462 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 5715176550 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 5715176550 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 5628764250 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 5628764250 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 9417462 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 9417462 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 9417462 # number of overall miss cycles @@ -1449,17 +1472,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54436.196532 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 54436.196532 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 137542.754861 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 137542.754861 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 135463.136552 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 135463.136552 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency system.iocache.demand_avg_miss_latency::total 54436.196532 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency system.iocache.overall_avg_miss_latency::total 54436.196532 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 87544 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 86158 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9998 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9840 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.756151 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.755894 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1467,234 +1490,234 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17280 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 17280 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17024 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 17024 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5776462 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 5776462 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 4816616550 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4816616550 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 4743516250 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4743516250 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 5776462 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 5776462 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 5776462 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 5776462 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.409704 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.409704 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 278739.383681 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 278739.383681 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 278636.997768 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 278636.997768 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 337552 # number of replacements -system.l2c.tags.tagsinuse 65418.667862 # Cycle average of tags in use -system.l2c.tags.total_refs 2487006 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402715 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.175598 # Average number of references to valid blocks. +system.l2c.tags.replacements 337565 # number of replacements +system.l2c.tags.tagsinuse 65420.967844 # Cycle average of tags in use +system.l2c.tags.total_refs 2486640 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402728 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.174490 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54698.574366 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2340.440822 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2723.231256 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 572.328176 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 607.228358 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2274.234670 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2202.630214 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.834634 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.035712 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041553 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008733 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009266 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034702 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.033609 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998210 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54725.451973 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2331.479005 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2701.186077 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 572.371097 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 609.192683 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2285.385373 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2195.901635 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.835044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.035576 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041217 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008734 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009296 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.034872 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.033507 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998245 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1015 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5951 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2685 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55344 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1013 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5954 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2697 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55331 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26261755 # Number of tag accesses -system.l2c.tags.data_accesses 26261755 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 506757 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 483132 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 121571 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 80695 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 322132 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 253945 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1768232 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835902 # number of Writeback hits -system.l2c.Writeback_hits::total 835902 # number of Writeback hits +system.l2c.tags.tag_accesses 26259538 # Number of tag accesses +system.l2c.tags.data_accesses 26259538 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 506712 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 484023 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 121893 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 79858 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 321963 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 253653 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1768102 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835667 # number of Writeback hits +system.l2c.Writeback_hits::total 835667 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 8 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 12 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 90966 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 25233 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 70678 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186877 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 506757 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 574098 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 121571 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 105928 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 322132 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 324623 # number of demand (read+write) hits -system.l2c.demand_hits::total 1955109 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 506757 # number of overall hits -system.l2c.overall_hits::cpu0.data 574098 # number of overall hits -system.l2c.overall_hits::cpu1.inst 121571 # number of overall hits -system.l2c.overall_hits::cpu1.data 105928 # number of overall hits -system.l2c.overall_hits::cpu2.inst 322132 # number of overall hits -system.l2c.overall_hits::cpu2.data 324623 # number of overall hits -system.l2c.overall_hits::total 1955109 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 7510 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 238505 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2294 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 16797 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4575 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 17928 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287609 # number of ReadReq misses +system.l2c.UpgradeReq_hits::cpu2.data 7 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 11 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 7 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 90939 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 25234 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 70756 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 186929 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 506712 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 574962 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 121893 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 105092 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 321963 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 324409 # number of demand (read+write) hits +system.l2c.demand_hits::total 1955031 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 506712 # number of overall hits +system.l2c.overall_hits::cpu0.data 574962 # number of overall hits +system.l2c.overall_hits::cpu1.inst 121893 # number of overall hits +system.l2c.overall_hits::cpu1.data 105092 # number of overall hits +system.l2c.overall_hits::cpu2.inst 321963 # number of overall hits +system.l2c.overall_hits::cpu2.data 324409 # number of overall hits +system.l2c.overall_hits::total 1955031 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 7503 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 238499 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2295 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 16798 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 4594 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 17926 # number of ReadReq misses +system.l2c.ReadReq_misses::total 287615 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 23 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 29 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 37 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 75422 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 18351 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 22068 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115841 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 7510 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 313927 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2294 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 35148 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 4575 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 39996 # number of demand (read+write) misses -system.l2c.demand_misses::total 403450 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 7510 # number of overall misses -system.l2c.overall_misses::cpu0.data 313927 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2294 # number of overall misses -system.l2c.overall_misses::cpu1.data 35148 # number of overall misses -system.l2c.overall_misses::cpu2.inst 4575 # number of overall misses -system.l2c.overall_misses::cpu2.data 39996 # number of overall misses -system.l2c.overall_misses::total 403450 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 171175250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 1120981750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 346316750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1198339500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2836813250 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 317996 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 317996 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1257891740 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1818546723 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 3076438463 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 171175250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2378873490 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 346316750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 3016886223 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 5913251713 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 171175250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2378873490 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 346316750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 3016886223 # number of overall miss cycles -system.l2c.overall_miss_latency::total 5913251713 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 514267 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 721637 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 123865 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 97492 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 326707 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 271873 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2055841 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835902 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835902 # number of Writeback accesses(hits+misses) +system.l2c.ReadExReq_misses::cpu0.data 75406 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 18360 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 22084 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115850 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 7503 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 313905 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2295 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 35158 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 4594 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 40010 # number of demand (read+write) misses +system.l2c.demand_misses::total 403465 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 7503 # number of overall misses +system.l2c.overall_misses::cpu0.data 313905 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2295 # number of overall misses +system.l2c.overall_misses::cpu1.data 35158 # number of overall misses +system.l2c.overall_misses::cpu2.inst 4594 # number of overall misses +system.l2c.overall_misses::cpu2.data 40010 # number of overall misses +system.l2c.overall_misses::total 403465 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 172333500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 1121869750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 347709750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 1196370250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2838283250 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 294497 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 294497 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1260800990 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1814777221 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 3075578211 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 172333500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2382670740 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 347709750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 3011147471 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 5913861461 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 172333500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2382670740 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 347709750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 3011147471 # number of overall miss cycles +system.l2c.overall_miss_latency::total 5913861461 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 514215 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 722522 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 124188 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 96656 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 326557 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 271579 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2055717 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 835667 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835667 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 23 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 35 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 36 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 48 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 8 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 166388 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 43584 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 92746 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 302718 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 514267 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 888025 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 123865 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 141076 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 326707 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 364619 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2358559 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 514267 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 888025 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 123865 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 141076 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 326707 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 364619 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2358559 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014603 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.330506 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.018520 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.172291 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.014003 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.065943 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.139898 # miss rate for ReadReq accesses +system.l2c.SCUpgradeReq_accesses::cpu2.data 7 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 9 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 166345 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 43594 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 92840 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 302779 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 514215 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 888867 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 124188 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 140250 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 326557 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 364419 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2358496 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 514215 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 888867 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 124188 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 140250 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 326557 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 364419 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2358496 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014591 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.330092 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.018480 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.173792 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.014068 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.066007 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.139910 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.652174 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.657143 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.805556 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.770833 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.453290 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.421049 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.237940 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.382670 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014603 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.353511 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.018520 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.249142 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.014003 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.109693 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.171058 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014603 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.353511 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.018520 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.249142 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.014003 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.109693 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.171058 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74618.679163 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 66737.021492 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75697.650273 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 66841.783802 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 9863.436993 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 21199.733333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 13825.913043 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68546.223094 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82406.503670 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 26557.423218 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 74618.679163 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 67681.617446 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 75697.650273 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 75429.698545 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 14656.715115 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 74618.679163 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 67681.617446 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 75697.650273 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 75429.698545 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 14656.715115 # average overall miss latency +system.l2c.SCUpgradeReq_miss_rate::total 0.222222 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.453311 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.421159 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.237872 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.382622 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014591 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.353152 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.018480 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.250681 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.014068 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.109791 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.171069 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014591 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.353152 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.018480 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.250681 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.014068 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.109791 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.171069 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75090.849673 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 66785.912013 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75687.799303 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 66739.386924 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 9868.342228 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 10155.068966 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 7959.378378 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68671.077887 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82176.110351 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 26547.934493 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75090.849673 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 67770.372035 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 75687.799303 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 75259.871807 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 14657.681487 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75090.849673 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 67770.372035 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 75687.799303 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 75259.871807 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 14657.681487 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1703,97 +1726,97 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 75387 # number of writebacks -system.l2c.writebacks::total 75387 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu1.inst 2294 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 16797 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 4575 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 17928 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 41594 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 18351 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 22068 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 40419 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2294 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 35148 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 4575 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 39996 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 82013 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2294 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 35148 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 4575 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 39996 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 82013 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 141975250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 910694250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 288727250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 974576000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2315972750 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 309012 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 309012 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1027334260 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1548976277 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2576310537 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 141975250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1938028510 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 288727250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2523552277 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 4892283287 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 141975250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1938028510 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 288727250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2523552277 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 4892283287 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 232613500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 320671000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 553284500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 301613500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 395814000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 697427500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 534227000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 716485000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1250712000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018520 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.172291 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014003 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.065943 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.020232 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.652174 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.421049 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.237940 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.133520 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018520 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.249142 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014003 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.109693 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.034773 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018520 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.249142 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014003 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.109693 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034773 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61889.821273 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54217.672799 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63109.781421 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54360.553324 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 55680.452710 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20600.800000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20600.800000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55982.467440 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70191.058410 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63740.086024 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61889.821273 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55139.083589 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63109.781421 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63095.116437 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59652.534196 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61889.821273 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55139.083589 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63109.781421 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63095.116437 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59652.534196 # average overall mshr miss latency +system.l2c.writebacks::writebacks 75393 # number of writebacks +system.l2c.writebacks::total 75393 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu1.inst 2295 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 16798 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 4594 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 17926 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 41613 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 29 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 29 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 18360 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 22084 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 40444 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2295 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 35158 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 4594 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 40010 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 82057 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2295 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 35158 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 4594 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 40010 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 82057 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 143128000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 911545250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 289854250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 972645250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2317172750 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 449026 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 449026 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1030142510 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1544955279 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 2575097789 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 143128000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1941687760 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 289854250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2517600529 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 4892270539 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 143128000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1941687760 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 289854250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2517600529 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 4892270539 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 233455500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 320261000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 553716500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 302243500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 395601500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 697845000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 535699000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 715862500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1251561500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018480 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.173792 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014068 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.066007 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020243 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.805556 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.604167 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.421159 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.237872 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.133576 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018480 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.250681 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014068 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.109791 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034792 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018480 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.250681 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014068 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.109791 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034792 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62365.141612 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54265.105965 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63094.090118 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54258.911637 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 55683.866820 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 15483.655172 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 15483.655172 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56107.979847 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69958.127106 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63670.699955 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62365.141612 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55227.480517 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63094.090118 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62924.282154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59620.392398 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62365.141612 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55227.480517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63094.090118 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62924.282154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59620.392398 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1804,91 +1827,91 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 294926 # Transaction distribution -system.membus.trans_dist::ReadResp 294920 # Transaction distribution +system.membus.trans_dist::ReadReq 294932 # Transaction distribution +system.membus.trans_dist::ReadResp 294926 # Transaction distribution system.membus.trans_dist::WriteReq 9811 # Transaction distribution system.membus.trans_dist::WriteResp 9811 # Transaction distribution -system.membus.trans_dist::Writeback 116899 # Transaction distribution +system.membus.trans_dist::Writeback 116905 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 147 # Transaction distribution +system.membus.trans_dist::UpgradeReq 163 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 149 # Transaction distribution -system.membus.trans_dist::ReadExReq 115717 # Transaction distribution -system.membus.trans_dist::ReadExResp 115717 # Transaction distribution +system.membus.trans_dist::UpgradeResp 165 # Transaction distribution +system.membus.trans_dist::ReadExReq 115724 # Transaction distribution +system.membus.trans_dist::ReadExResp 115724 # Transaction distribution system.membus.trans_dist::BadAddressError 6 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882240 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882304 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 916162 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 916226 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124907 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124907 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1041069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1041133 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30632000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30677576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30633216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30678792 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5323648 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5323648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36001224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36002440 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 140 # Total snoops (count) -system.membus.snoop_fanout::samples 562099 # Request fanout histogram +system.membus.snoop_fanout::samples 562134 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 562099 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 562134 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 562099 # Request fanout histogram -system.membus.reqLayer0.occupancy 11803000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 562134 # Request fanout histogram +system.membus.reqLayer0.occupancy 11832500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 659094000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 654960000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 769927201 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 770434435 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 17910500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 17654500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2063113 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2063092 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2063004 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2062983 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 9811 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 9811 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 835902 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 17280 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 35 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 45 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302718 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302718 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 835667 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 17024 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 48 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 57 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302779 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302779 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1929756 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3657397 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5587153 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61750976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142744520 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 204495496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 41919 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3236289 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012893 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112812 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1930013 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3656818 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5586831 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61758720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142717704 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 204476424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 41934 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3236018 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012894 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112817 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3194564 98.71% 98.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3194293 98.71% 98.71% # Request fanout histogram system.toL2Bus.snoop_fanout::2 41725 1.29% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3236289 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2206148499 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3236018 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2201638999 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2029921963 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2030846564 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2294082992 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2289452792 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |