diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-24 12:29:00 -0600 |
| commit | 9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b (patch) | |
| tree | 64b85031cb791a21af6059778384d358d992b817 /tests/long/fs/10.linux-boot/ref/alpha | |
| parent | dbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (diff) | |
| download | gem5-9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b.tar.xz | |
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
9 files changed, 285 insertions, 251 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index aca491b43..0d25f966b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -12,15 +12,15 @@ children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 clock=1000 -console=/gem5/dist/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console init_param=0 -kernel=/gem5/dist/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/gem5/dist/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -46,22 +46,18 @@ slave=system.membus.master[0] [system.cpu0] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts isa itb tracer -BTBEntries=4096 -BTBTagSize=16 +children=branchPred dcache dtb fuPool icache interrupts isa itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 -RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +branchPred=system.cpu0.branchPred cachePorts=200 checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 @@ -84,23 +80,15 @@ forwardComSize=5 fuPool=system.cpu0.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -instShiftAmt=2 interrupts=system.cpu0.interrupts isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu0.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -112,7 +100,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -predType=tournament profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -141,6 +128,24 @@ workload= dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side +[system.cpu0.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + [system.cpu0.dcache] type=BaseCache addr_ranges=0:18446744073709551615 @@ -467,22 +472,18 @@ type=ExeTracer [system.cpu1] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts isa itb tracer -BTBEntries=4096 -BTBTagSize=16 +children=branchPred dcache dtb fuPool icache interrupts isa itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 -RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +branchPred=system.cpu1.branchPred cachePorts=200 checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 @@ -505,23 +506,15 @@ forwardComSize=5 fuPool=system.cpu1.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -instShiftAmt=2 interrupts=system.cpu1.interrupts isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu1.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -533,7 +526,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -predType=tournament profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -562,6 +554,24 @@ workload= dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side +[system.cpu1.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + [system.cpu1.dcache] type=BaseCache addr_ranges=0:18446744073709551615 @@ -903,7 +913,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/gem5/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -923,7 +933,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/gem5/dist/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -1048,7 +1058,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/gem5/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index f4163d49e..560862c38 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 4 2013 21:09:21 -gem5 started Jan 4 2013 21:41:13 -gem5 executing on u200540 +gem5 compiled Jan 23 2013 13:29:14 +gem5 started Jan 23 2013 13:29:25 +gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /gem5/dist/binaries/vmlinux +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 107840000 -Exiting @ tick 1897857556000 because m5_exit instruction encountered +info: Launching CPU 1 @ 107825000 +Exiting @ tick 1901719660500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 46b1b53be..30313ea26 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.901720 # Nu sim_ticks 1901719660500 # Number of ticks simulated final_tick 1901719660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128809 # Simulator instruction rate (inst/s) -host_op_rate 128809 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4317556960 # Simulator tick rate (ticks/s) -host_mem_usage 340604 # Number of bytes of host memory used -host_seconds 440.46 # Real time elapsed on the host +host_inst_rate 97307 # Simulator instruction rate (inst/s) +host_op_rate 97307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3261646555 # Simulator tick rate (ticks/s) +host_mem_usage 383552 # Number of bytes of host memory used +host_seconds 583.06 # Real time elapsed on the host sim_insts 56735321 # Number of instructions simulated sim_ops 56735321 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory @@ -612,6 +612,15 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.cpu0.branchPred.lookups 12372868 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10433314 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 330387 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 8151024 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5278103 # Number of BTB hits +system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu0.branchPred.BTBHitPct 64.753864 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 784011 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 32544 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv @@ -647,14 +656,6 @@ system.cpu0.itb.data_accesses 0 # DT system.cpu0.numCycles 101814962 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 12372868 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 10433314 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 330387 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 8151024 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5278103 # Number of BTB hits -system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 784011 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 32544 # Number of incorrect RAS predictions. system.cpu0.fetch.icacheStallCycles 24931217 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.Insts 63627814 # Number of instructions fetch has processed system.cpu0.fetch.Branches 12372868 # Number of branches that fetch encountered @@ -1192,6 +1193,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.branchPred.lookups 2617746 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2161338 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 77903 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1516620 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 873996 # Number of BTB hits +system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu1.branchPred.BTBHitPct 57.627883 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 182212 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8242 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv @@ -1227,14 +1237,6 @@ system.cpu1.itb.data_accesses 0 # DT system.cpu1.numCycles 16039611 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 2617746 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 2161338 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 77903 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 1516620 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 873996 # Number of BTB hits -system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 182212 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 8242 # Number of incorrect RAS predictions. system.cpu1.fetch.icacheStallCycles 6032367 # Number of cycles fetch is stalled on an Icache miss system.cpu1.fetch.Insts 12375417 # Number of instructions fetch has processed system.cpu1.fetch.Branches 2617746 # Number of branches that fetch encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index ebcbd1b8c..8b454d95b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -12,15 +12,15 @@ children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_dis boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 clock=1000 -console=/gem5/dist/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console init_param=0 -kernel=/gem5/dist/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/gem5/dist/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -46,22 +46,18 @@ slave=system.membus.master[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer -BTBEntries=4096 -BTBTagSize=16 +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 -RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +branchPred=system.cpu.branchPred cachePorts=200 checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 @@ -84,23 +80,15 @@ forwardComSize=5 fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -instShiftAmt=2 interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -112,7 +100,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -predType=tournament profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -141,6 +128,24 @@ workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + [system.cpu.dcache] type=BaseCache addr_ranges=0:18446744073709551615 @@ -514,7 +519,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/gem5/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -534,7 +539,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/gem5/dist/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -637,7 +642,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/gem5/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 5e5126f62..4fc9bce9f 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 4 2013 21:09:21 -gem5 started Jan 4 2013 21:39:46 -gem5 executing on u200540 +gem5 compiled Jan 23 2013 13:29:14 +gem5 started Jan 23 2013 13:39:31 +gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /gem5/dist/binaries/vmlinux +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1854349611000 because m5_exit instruction encountered +Exiting @ tick 1854344296500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 7d46ecd48..2f976aa78 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.854344 # Nu sim_ticks 1854344296500 # Number of ticks simulated final_tick 1854344296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131278 # Simulator instruction rate (inst/s) -host_op_rate 131278 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4595190559 # Simulator tick rate (ticks/s) -host_mem_usage 336376 # Number of bytes of host memory used -host_seconds 403.54 # Real time elapsed on the host +host_inst_rate 90928 # Simulator instruction rate (inst/s) +host_op_rate 90928 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3182808238 # Simulator tick rate (ticks/s) +host_mem_usage 379332 # Number of bytes of host memory used +host_seconds 582.61 # Real time elapsed on the host sim_insts 52976017 # Number of instructions simulated sim_ops 52976017 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 964864 # Number of bytes read from this memory @@ -300,6 +300,15 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.cpu.branchPred.lookups 13851594 # Number of BP lookups +system.cpu.branchPred.condPredicted 11614390 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 401305 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9533712 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5819078 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 61.036855 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 909714 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 39020 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -335,14 +344,6 @@ system.cpu.itb.data_accesses 0 # DT system.cpu.numCycles 108725026 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 13851594 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11614390 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 401305 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9533712 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 5819078 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 909714 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 39020 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 28116472 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 70876145 # Number of instructions fetch has processed system.cpu.fetch.Branches 13851594 # Number of branches that fetch encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini index 3b827b59e..0afd8d12c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini @@ -12,15 +12,15 @@ children=bridge cpu0 cpu1 cpu2 disk0 disk2 intrctrl iobus iocache l2c membus phy boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 clock=1000 -console=/arm/scratch/sysexplr/dist/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console init_param=0 -kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/arm/scratch/sysexplr/dist/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -47,6 +47,7 @@ slave=system.membus.master[0] [system.cpu0] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer +branchPred=Null checker=Null clock=500 cpu_id=0 @@ -141,6 +142,7 @@ type=ExeTracer [system.cpu1] type=TimingSimpleCPU children=dtb interrupts isa itb tracer +branchPred=Null checker=Null clock=500 cpu_id=0 @@ -184,22 +186,18 @@ type=ExeTracer [system.cpu2] type=DerivO3CPU -children=dtb fuPool interrupts isa itb tracer -BTBEntries=4096 -BTBTagSize=16 +children=branchPred dtb fuPool interrupts isa itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 -RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +branchPred=system.cpu2.branchPred cachePorts=200 checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 @@ -222,23 +220,15 @@ forwardComSize=5 fuPool=system.cpu2.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -instShiftAmt=2 interrupts=system.cpu2.interrupts isa=system.cpu2.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu2.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -250,7 +240,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -predType=tournament profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -277,6 +266,24 @@ wbDepth=1 wbWidth=8 workload= +[system.cpu2.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + [system.cpu2.dtb] type=AlphaTLB size=64 @@ -574,7 +581,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -594,7 +601,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -719,7 +726,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout index 94a2dd47e..c03321be6 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 11 2012 16:31:37 -gem5 started Dec 11 2012 16:31:53 -gem5 executing on e103721-lin +gem5 compiled Jan 23 2013 13:29:14 +gem5 started Jan 23 2013 13:29:38 +gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... Switching CPUs... @@ -54,163 +56,166 @@ Switching CPUs... Next CPU: AtomicSimpleCPU info: Entering event queue @ 10452679000. Starting simulation... switching cpus -info: Entering event queue @ 10452683500. Starting simulation... +info: Entering event queue @ 10452682000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 11452683500. Starting simulation... +info: Entering event queue @ 11452682000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 12452683500. Starting simulation... +info: Entering event queue @ 12452682000. Starting simulation... +info: Entering event queue @ 12452693500. Starting simulation... switching cpus -info: Entering event queue @ 12452684500. Starting simulation... +info: Entering event queue @ 12452696000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 13452684500. Starting simulation... +info: Entering event queue @ 13452696000. Starting simulation... switching cpus -info: Entering event queue @ 13452690000. Starting simulation... +info: Entering event queue @ 13452709500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 14452690000. Starting simulation... +info: Entering event queue @ 14452709500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 15452690000. Starting simulation... +info: Entering event queue @ 15452709500. Starting simulation... +info: Entering event queue @ 15452713500. Starting simulation... switching cpus -info: Entering event queue @ 15452691000. Starting simulation... +info: Entering event queue @ 15452714500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 16452691000. Starting simulation... +info: Entering event queue @ 16452714500. Starting simulation... switching cpus -info: Entering event queue @ 16452704500. Starting simulation... +info: Entering event queue @ 16452717000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 17452704500. Starting simulation... +info: Entering event queue @ 17452717000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 18452704500. Starting simulation... +info: Entering event queue @ 18452717000. Starting simulation... +info: Entering event queue @ 18452728500. Starting simulation... switching cpus -info: Entering event queue @ 18452705500. Starting simulation... +info: Entering event queue @ 18452732000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 19452705500. Starting simulation... -info: Entering event queue @ 19452711000. Starting simulation... +info: Entering event queue @ 19452732000. Starting simulation... +info: Entering event queue @ 19452741000. Starting simulation... switching cpus -info: Entering event queue @ 19452715500. Starting simulation... +info: Entering event queue @ 19452745500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 20452715500. Starting simulation... +info: Entering event queue @ 20452745500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 21452715500. Starting simulation... +info: Entering event queue @ 21452745500. Starting simulation... switching cpus -info: Entering event queue @ 21452716000. Starting simulation... +info: Entering event queue @ 21452746000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 22452716000. Starting simulation... -info: Entering event queue @ 22452727500. Starting simulation... +info: Entering event queue @ 22452746000. Starting simulation... switching cpus -info: Entering event queue @ 22452733000. Starting simulation... +info: Entering event queue @ 22452748000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 23452733000. Starting simulation... +info: Entering event queue @ 23452748000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 24452733000. Starting simulation... +info: Entering event queue @ 24452748000. Starting simulation... switching cpus -info: Entering event queue @ 24452734000. Starting simulation... +info: Entering event queue @ 24452750000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 25452734000. Starting simulation... +info: Entering event queue @ 25452750000. Starting simulation... +info: Entering event queue @ 25452773000. Starting simulation... switching cpus -info: Entering event queue @ 25452745500. Starting simulation... +info: Entering event queue @ 25452778500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 26452745500. Starting simulation... +info: Entering event queue @ 26452778500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 27452745500. Starting simulation... +info: Entering event queue @ 27452778500. Starting simulation... +info: Entering event queue @ 27452782500. Starting simulation... switching cpus -info: Entering event queue @ 27452746500. Starting simulation... +info: Entering event queue @ 27452786000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 28452746500. Starting simulation... -info: Entering event queue @ 28452758500. Starting simulation... -info: Entering event queue @ 28452769000. Starting simulation... +info: Entering event queue @ 28452786000. Starting simulation... +info: Entering event queue @ 28452802500. Starting simulation... switching cpus -info: Entering event queue @ 28452773500. Starting simulation... +info: Entering event queue @ 28452808000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 29452773500. Starting simulation... +info: Entering event queue @ 29452808000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 30452773500. Starting simulation... +info: Entering event queue @ 30452808000. Starting simulation... switching cpus -info: Entering event queue @ 30452992500. Starting simulation... +info: Entering event queue @ 30452820500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 31452992500. Starting simulation... +info: Entering event queue @ 31452820500. Starting simulation... switching cpus -info: Entering event queue @ 31452995500. Starting simulation... +info: Entering event queue @ 31452823500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 32452995500. Starting simulation... +info: Entering event queue @ 32452823500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 33452995500. Starting simulation... +info: Entering event queue @ 33452823500. Starting simulation... switching cpus -info: Entering event queue @ 33452996500. Starting simulation... +info: Entering event queue @ 33452824500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 34452996500. Starting simulation... +info: Entering event queue @ 34452824500. Starting simulation... switching cpus -info: Entering event queue @ 34452999500. Starting simulation... +info: Entering event queue @ 34452827500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 35452999500. Starting simulation... +info: Entering event queue @ 35452827500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 36452999500. Starting simulation... +info: Entering event queue @ 36452827500. Starting simulation... switching cpus -info: Entering event queue @ 36453000500. Starting simulation... +info: Entering event queue @ 36452828500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 37453000500. Starting simulation... +info: Entering event queue @ 37452828500. Starting simulation... switching cpus -info: Entering event queue @ 37453003500. Starting simulation... +info: Entering event queue @ 37452831500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 38453003500. Starting simulation... +info: Entering event queue @ 38452831500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 39453003500. Starting simulation... +info: Entering event queue @ 39452831500. Starting simulation... switching cpus -info: Entering event queue @ 39453004500. Starting simulation... +info: Entering event queue @ 39452832500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 40453004500. Starting simulation... +info: Entering event queue @ 40452832500. Starting simulation... switching cpus -info: Entering event queue @ 40453007500. Starting simulation... +info: Entering event queue @ 40452835500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 41453007500. Starting simulation... +info: Entering event queue @ 41452835500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 42453007500. Starting simulation... +info: Entering event queue @ 42452835500. Starting simulation... switching cpus -info: Entering event queue @ 42453008500. Starting simulation... +info: Entering event queue @ 42452836500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 43453008500. Starting simulation... +info: Entering event queue @ 43452836500. Starting simulation... switching cpus info: Entering event queue @ 43945335500. Starting simulation... Switching CPUs... @@ -1083,18 +1088,18 @@ Switching CPUs... Next CPU: AtomicSimpleCPU info: Entering event queue @ 304757835500. Starting simulation... switching cpus -info: Entering event queue @ 304758059500. Starting simulation... +info: Entering event queue @ 304758051500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 305758059500. Starting simulation... +info: Entering event queue @ 305758051500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 306758059500. Starting simulation... +info: Entering event queue @ 306758051500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 307758059500. Starting simulation... +info: Entering event queue @ 307758051500. Starting simulation... switching cpus info: Entering event queue @ 308593773000. Starting simulation... Switching CPUs... @@ -2151,18 +2156,18 @@ Switching CPUs... Next CPU: AtomicSimpleCPU info: Entering event queue @ 624093773500. Starting simulation... switching cpus -info: Entering event queue @ 624216549000. Starting simulation... +info: Entering event queue @ 624218766000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 625216549000. Starting simulation... +info: Entering event queue @ 625218766000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 626216549000. Starting simulation... +info: Entering event queue @ 626218766000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 627216549000. Starting simulation... +info: Entering event queue @ 627218766000. Starting simulation... switching cpus info: Entering event queue @ 627929709000. Starting simulation... Switching CPUs... @@ -3931,49 +3936,49 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1157273460500. Starting simulation... switching cpus -info: Entering event queue @ 1157273461500. Starting simulation... +info: Entering event queue @ 1157273461000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1158273461500. Starting simulation... +info: Entering event queue @ 1158273461000. Starting simulation... switching cpus -info: Entering event queue @ 1159361690000. Starting simulation... +info: Entering event queue @ 1159361004000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1160361690000. Starting simulation... +info: Entering event queue @ 1160361004000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1161361690000. Starting simulation... +info: Entering event queue @ 1161361004000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1162361690000. Starting simulation... +info: Entering event queue @ 1162361004000. Starting simulation... switching cpus -info: Entering event queue @ 1162361693000. Starting simulation... +info: Entering event queue @ 1162361007000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1163361693000. Starting simulation... +info: Entering event queue @ 1163361007000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1164361693000. Starting simulation... +info: Entering event queue @ 1164361007000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1165361693000. Starting simulation... +info: Entering event queue @ 1165361007000. Starting simulation... switching cpus -info: Entering event queue @ 1165361696000. Starting simulation... +info: Entering event queue @ 1165361010000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1166361696000. Starting simulation... +info: Entering event queue @ 1166361010000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1167361696000. Starting simulation... +info: Entering event queue @ 1167361010000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1168361696000. Starting simulation... +info: Entering event queue @ 1168361010000. Starting simulation... switching cpus info: Entering event queue @ 1168945335500. Starting simulation... Switching CPUs... @@ -5934,12 +5939,11 @@ switching cpus info: Entering event queue @ 1755882835500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1756882835500. Starting simulation... switching cpus -info: Entering event queue @ 1756882836500. Starting simulation... +info: Entering event queue @ 1756882835500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1757882836500. Starting simulation... +info: Entering event queue @ 1757882835500. Starting simulation... switching cpus info: Entering event queue @ 1758789085500. Starting simulation... Switching CPUs... @@ -5976,10 +5980,10 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1768601585500. Starting simulation... switching cpus -info: Entering event queue @ 1768601586500. Starting simulation... +info: Entering event queue @ 1768601735500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1769601586500. Starting simulation... +info: Entering event queue @ 1769601735500. Starting simulation... switching cpus info: Entering event queue @ 1770507835500. Starting simulation... Switching CPUs... @@ -6007,18 +6011,18 @@ Switching CPUs... Next CPU: AtomicSimpleCPU info: Entering event queue @ 1777414085500. Starting simulation... switching cpus -info: Entering event queue @ 1777414489000. Starting simulation... +info: Entering event queue @ 1777414674000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1778414489000. Starting simulation... +info: Entering event queue @ 1778414674000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1779414489000. Starting simulation... +info: Entering event queue @ 1779414674000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1780414489000. Starting simulation... +info: Entering event queue @ 1780414674000. Starting simulation... switching cpus info: Entering event queue @ 1781250023000. Starting simulation... Switching CPUs... @@ -6154,33 +6158,32 @@ Switching CPUs... Next CPU: AtomicSimpleCPU info: Entering event queue @ 1819406274000. Starting simulation... switching cpus -info: Entering event queue @ 1819406280500. Starting simulation... +info: Entering event queue @ 1819406403500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1820406280500. Starting simulation... +info: Entering event queue @ 1820406403500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1821406280500. Starting simulation... +info: Entering event queue @ 1821406403500. Starting simulation... switching cpus -info: Entering event queue @ 1821406281500. Starting simulation... +info: Entering event queue @ 1821406404500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1822406281500. Starting simulation... -info: Entering event queue @ 1822406288500. Starting simulation... +info: Entering event queue @ 1822406404500. Starting simulation... switching cpus -info: Entering event queue @ 1822406293000. Starting simulation... +info: Entering event queue @ 1822406407500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1823406293000. Starting simulation... +info: Entering event queue @ 1823406407500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1824406293000. Starting simulation... +info: Entering event queue @ 1824406407500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1825406293000. Starting simulation... +info: Entering event queue @ 1825406407500. Starting simulation... switching cpus info: Entering event queue @ 1826171898000. Starting simulation... Switching CPUs... @@ -6194,22 +6197,21 @@ info: Entering event queue @ 1828171898000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU info: Entering event queue @ 1829171898000. Starting simulation... -info: Entering event queue @ 1829171911500. Starting simulation... -info: Entering event queue @ 1829171916500. Starting simulation... +info: Entering event queue @ 1829171913500. Starting simulation... switching cpus -info: Entering event queue @ 1829171921000. Starting simulation... +info: Entering event queue @ 1829171918000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1830171921000. Starting simulation... +info: Entering event queue @ 1830171918000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1831171921000. Starting simulation... +info: Entering event queue @ 1831171918000. Starting simulation... switching cpus -info: Entering event queue @ 1831171922000. Starting simulation... +info: Entering event queue @ 1831171920000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1832171922000. Starting simulation... +info: Entering event queue @ 1832171920000. Starting simulation... switching cpus info: Entering event queue @ 1833007835500. Starting simulation... Switching CPUs... @@ -6232,14 +6234,16 @@ info: Entering event queue @ 1837914085500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 1838914085500. Starting simulation... +info: Entering event queue @ 1838914092000. Starting simulation... switching cpus -info: Entering event queue @ 1838914086500. Starting simulation... +info: Entering event queue @ 1838914095500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1839914086500. Starting simulation... +info: Entering event queue @ 1839914095500. Starting simulation... +info: Entering event queue @ 1839914105000. Starting simulation... switching cpus -info: Entering event queue @ 1839914091000. Starting simulation... +info: Entering event queue @ 1839914109500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1840914091000. Starting simulation... +info: Entering event queue @ 1840914109500. Starting simulation... diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index e61c2a067..a2c647b2a 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.841687 # Nu sim_ticks 1841687115500 # Number of ticks simulated final_tick 1841687115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 299654 # Simulator instruction rate (inst/s) -host_op_rate 299654 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8001020229 # Simulator tick rate (ticks/s) -host_mem_usage 317816 # Number of bytes of host memory used -host_seconds 230.18 # Real time elapsed on the host +host_inst_rate 216690 # Simulator instruction rate (inst/s) +host_op_rate 216690 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5785819991 # Simulator tick rate (ticks/s) +host_mem_usage 360768 # Number of bytes of host memory used +host_seconds 318.31 # Real time elapsed on the host sim_insts 68974794 # Number of instructions simulated sim_ops 68974794 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 474496 # Number of bytes read from this memory @@ -1229,6 +1229,15 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed +system.cpu2.branchPred.lookups 8367198 # Number of BP lookups +system.cpu2.branchPred.condPredicted 7675066 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 129021 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 6898028 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 5713360 # Number of BTB hits +system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu2.branchPred.BTBHitPct 82.825990 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 286292 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 15213 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv @@ -1264,14 +1273,6 @@ system.cpu2.itb.data_accesses 0 # DT system.cpu2.numCycles 30553382 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 8367198 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 7675066 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 129021 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 6898028 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 5713360 # Number of BTB hits -system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 286292 # Number of times the RAS was used to get a target. -system.cpu2.BPredUnit.RASInCorrect 15213 # Number of incorrect RAS predictions. system.cpu2.fetch.icacheStallCycles 8548806 # Number of cycles fetch is stalled on an Icache miss system.cpu2.fetch.Insts 34839646 # Number of instructions fetch has processed system.cpu2.fetch.Branches 8367198 # Number of branches that fetch encountered |