diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
| commit | f2e2410a505ef48516f121ce1b2232ba7aa389af (patch) | |
| tree | dbe4c8482b37e854302410318fc474f507310724 /tests/long/fs/10.linux-boot/ref/alpha | |
| parent | 184c6d7ebd7faa0869f294526a54a239a216b7c8 (diff) | |
| download | gem5-f2e2410a505ef48516f121ce1b2232ba7aa389af.tar.xz | |
stats: Get all stats updated to reflect current behaviour
Line everything up again.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
3 files changed, 3841 insertions, 3843 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 4852a1186..75078a9be 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,110 +1,110 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.893228 # Number of seconds simulated -sim_ticks 1893227633000 # Number of ticks simulated -final_tick 1893227633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1893227678500 # Number of ticks simulated +final_tick 1893227678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25790 # Simulator instruction rate (inst/s) -host_op_rate 25790 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 869674472 # Simulator tick rate (ticks/s) -host_mem_usage 393476 # Number of bytes of host memory used -host_seconds 2176.94 # Real time elapsed on the host -sim_insts 56143729 # Number of instructions simulated -sim_ops 56143729 # Number of ops (including micro ops) simulated +host_inst_rate 31053 # Simulator instruction rate (inst/s) +host_op_rate 31053 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1047239405 # Simulator tick rate (ticks/s) +host_mem_usage 384600 # Number of bytes of host memory used +host_seconds 1807.83 # Real time elapsed on the host +sim_insts 56138739 # Number of instructions simulated +sim_ops 56138739 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1047552 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1046400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24860352 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25908864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1047552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1047552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7567040 # Number of bytes written to this memory -system.physmem.bytes_written::total 7567040 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16368 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25907712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1046400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1046400 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7566528 # Number of bytes written to this memory +system.physmem.bytes_written::total 7566528 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16350 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 388443 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404826 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118235 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118235 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 553315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13131201 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404808 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118227 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118227 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 552707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13131200 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13685023 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 553315 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 553315 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3996899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3996899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3996899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 553315 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13131201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13684414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 552707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 552707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3996629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3996629 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3996629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 552707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13131200 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17681922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404826 # Number of read requests accepted -system.physmem.writeReqs 118235 # Number of write requests accepted -system.physmem.readBursts 404826 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118235 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25901888 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue -system.physmem.bytesWritten 7565888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25908864 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7567040 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17681043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404808 # Number of read requests accepted +system.physmem.writeReqs 118227 # Number of write requests accepted +system.physmem.readBursts 404808 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118227 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25900800 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6912 # Total number of bytes read from write queue +system.physmem.bytesWritten 7564480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25907712 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7566528 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 108 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25487 # Per bank write bursts system.physmem.perBankRdBursts::1 25708 # Per bank write bursts -system.physmem.perBankRdBursts::2 25813 # Per bank write bursts -system.physmem.perBankRdBursts::3 25780 # Per bank write bursts -system.physmem.perBankRdBursts::4 25224 # Per bank write bursts +system.physmem.perBankRdBursts::2 25811 # Per bank write bursts +system.physmem.perBankRdBursts::3 25775 # Per bank write bursts +system.physmem.perBankRdBursts::4 25223 # Per bank write bursts system.physmem.perBankRdBursts::5 24955 # Per bank write bursts system.physmem.perBankRdBursts::6 24789 # Per bank write bursts -system.physmem.perBankRdBursts::7 24580 # Per bank write bursts -system.physmem.perBankRdBursts::8 25111 # Per bank write bursts +system.physmem.perBankRdBursts::7 24582 # Per bank write bursts +system.physmem.perBankRdBursts::8 25110 # Per bank write bursts system.physmem.perBankRdBursts::9 25258 # Per bank write bursts -system.physmem.perBankRdBursts::10 25520 # Per bank write bursts +system.physmem.perBankRdBursts::10 25516 # Per bank write bursts system.physmem.perBankRdBursts::11 24876 # Per bank write bursts -system.physmem.perBankRdBursts::12 24529 # Per bank write bursts -system.physmem.perBankRdBursts::13 25563 # Per bank write bursts -system.physmem.perBankRdBursts::14 25801 # Per bank write bursts +system.physmem.perBankRdBursts::12 24528 # Per bank write bursts +system.physmem.perBankRdBursts::13 25560 # Per bank write bursts +system.physmem.perBankRdBursts::14 25799 # Per bank write bursts system.physmem.perBankRdBursts::15 25723 # Per bank write bursts -system.physmem.perBankWrBursts::0 7828 # Per bank write bursts -system.physmem.perBankWrBursts::1 7672 # Per bank write bursts -system.physmem.perBankWrBursts::2 8070 # Per bank write bursts -system.physmem.perBankWrBursts::3 7747 # Per bank write bursts -system.physmem.perBankWrBursts::4 7316 # Per bank write bursts -system.physmem.perBankWrBursts::5 6943 # Per bank write bursts -system.physmem.perBankWrBursts::6 6787 # Per bank write bursts -system.physmem.perBankWrBursts::7 6421 # Per bank write bursts -system.physmem.perBankWrBursts::8 7240 # Per bank write bursts -system.physmem.perBankWrBursts::9 6874 # Per bank write bursts -system.physmem.perBankWrBursts::10 7389 # Per bank write bursts -system.physmem.perBankWrBursts::11 6891 # Per bank write bursts -system.physmem.perBankWrBursts::12 7084 # Per bank write bursts -system.physmem.perBankWrBursts::13 8012 # Per bank write bursts -system.physmem.perBankWrBursts::14 7998 # Per bank write bursts -system.physmem.perBankWrBursts::15 7945 # Per bank write bursts +system.physmem.perBankWrBursts::0 7831 # Per bank write bursts +system.physmem.perBankWrBursts::1 7673 # Per bank write bursts +system.physmem.perBankWrBursts::2 8069 # Per bank write bursts +system.physmem.perBankWrBursts::3 7745 # Per bank write bursts +system.physmem.perBankWrBursts::4 7318 # Per bank write bursts +system.physmem.perBankWrBursts::5 6942 # Per bank write bursts +system.physmem.perBankWrBursts::6 6789 # Per bank write bursts +system.physmem.perBankWrBursts::7 6426 # Per bank write bursts +system.physmem.perBankWrBursts::8 7239 # Per bank write bursts +system.physmem.perBankWrBursts::9 6872 # Per bank write bursts +system.physmem.perBankWrBursts::10 7384 # Per bank write bursts +system.physmem.perBankWrBursts::11 6889 # Per bank write bursts +system.physmem.perBankWrBursts::12 7081 # Per bank write bursts +system.physmem.perBankWrBursts::13 8010 # Per bank write bursts +system.physmem.perBankWrBursts::14 7995 # Per bank write bursts +system.physmem.perBankWrBursts::15 7932 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 56 # Number of times write queue was full causing retry -system.physmem.totGap 1893218679000 # Total gap between requests +system.physmem.numWrRetry 72 # Number of times write queue was full causing retry +system.physmem.totGap 1893218795000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404826 # Read request sizes (log2) +system.physmem.readPktSize::6 404808 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118235 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118227 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -149,205 +149,206 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 136 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 528.007825 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 321.906071 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.488828 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14518 22.90% 22.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11005 17.36% 40.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4663 7.36% 47.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3176 5.01% 52.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2328 3.67% 56.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2299 3.63% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1937 3.06% 62.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1572 2.48% 65.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21887 34.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63385 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5244 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.176964 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2915.674794 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5241 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 189 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63391 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 527.918474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 322.301426 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.348187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14401 22.72% 22.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11109 17.52% 40.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4782 7.54% 47.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3159 4.98% 52.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2221 3.50% 56.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2316 3.65% 59.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1932 3.05% 62.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1599 2.52% 65.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21872 34.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63391 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5234 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.317348 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2918.457754 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5231 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5244 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5244 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.543288 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.756988 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.319215 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4714 89.89% 89.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 44 0.84% 90.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 176 3.36% 94.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 4 0.08% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 4 0.08% 94.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 12 0.23% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 7 0.13% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 2 0.04% 94.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 32 0.61% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.10% 95.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 158 3.01% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 14 0.27% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 6 0.11% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 4 0.08% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.11% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.04% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 11 0.21% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.08% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 14 0.27% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 9 0.17% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 4 0.08% 99.89% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5234 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5234 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.582155 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.722612 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.927693 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4724 90.26% 90.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 39 0.75% 91.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 163 3.11% 94.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 4 0.08% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 3 0.06% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 11 0.21% 94.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 8 0.15% 94.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 2 0.04% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 33 0.63% 95.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.08% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 144 2.75% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 23 0.44% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 9 0.17% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.06% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 7 0.13% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 10 0.19% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.10% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 14 0.27% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 10 0.19% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.06% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 5 0.10% 99.89% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-231 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5244 # Writes before turning the bus around for reads -system.physmem.totQLat 5894702000 # Total ticks spent queuing -system.physmem.totMemAccLat 13483145750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023585000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14565.00 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-359 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5234 # Writes before turning the bus around for reads +system.physmem.totQLat 5912751750 # Total ticks spent queuing +system.physmem.totMemAccLat 13500876750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14610.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33315.00 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 33360.21 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.69 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.89 # Average write queue length when enqueuing -system.physmem.readRowHits 363769 # Number of row buffer hits during reads -system.physmem.writeRowHits 95780 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.88 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.01 # Row buffer hit rate for writes -system.physmem.avgGap 3619498.83 # Average gap between requests -system.physmem.pageHitRate 87.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 221604180 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 117785415 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1444679040 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 306852480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4717362000.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4796151000 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 296411520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 10938570180 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 5566653120 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 443189598645 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 471596477220 # Total energy per rank (pJ) -system.physmem_0.averagePower 249.096553 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1881819292000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 462054000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2003948000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1843451492500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 14496450250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8825649500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 23988038750 # Time in different power states -system.physmem_1.actEnergy 230964720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122760660 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1445000340 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 310240260 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4792348080.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4813778250 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 297177120 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11174584380 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 5627937120 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 443035577925 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 471852130095 # Total energy per rank (pJ) -system.physmem_1.averagePower 249.231588 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1881891335250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 468372250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2035962000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1842731534750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 14656099500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8829934000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 24505730500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 15259378 # Number of BP lookups -system.cpu.branchPred.condPredicted 13119579 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 525820 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12061992 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4569562 # Number of BTB hits +system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing +system.physmem.readRowHits 363798 # Number of row buffer hits during reads +system.physmem.writeRowHits 95706 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.95 # Row buffer hit rate for writes +system.physmem.avgGap 3619678.98 # Average gap between requests +system.physmem.pageHitRate 87.87 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 222139680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 118070040 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1444636200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 306899460 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4706913120.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4768209600 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 303610560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 10937646210 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 5541404160 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 443214367815 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 471564552855 # Total energy per rank (pJ) +system.physmem_0.averagePower 249.079684 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1881862215000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 479498250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1999510000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1843562153500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 14430696500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8769616250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 23986204000 # Time in different power states +system.physmem_1.actEnergy 230472060 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122498805 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1444921800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 310078440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 4819392240.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4890695190 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 314585760 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11137759530 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 5641159680 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 443008801920 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 471922426215 # Total energy per rank (pJ) +system.physmem_1.averagePower 249.268712 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1881676600250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 514596250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2047516000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1842563195250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 14690458500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8987140500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 24424772000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 15251875 # Number of BP lookups +system.cpu.branchPred.condPredicted 13114549 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 526465 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12070936 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4577345 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.883975 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 862888 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32219 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6522078 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 538261 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5983817 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 225046 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 37.920382 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 863154 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33512 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6526029 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 541717 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5984312 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 221941 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9322510 # DTB read hits -system.cpu.dtb.read_misses 17386 # DTB read misses +system.cpu.dtb.read_hits 9319487 # DTB read hits +system.cpu.dtb.read_misses 17755 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 764595 # DTB read accesses -system.cpu.dtb.write_hits 6393584 # DTB write hits -system.cpu.dtb.write_misses 2379 # DTB write misses +system.cpu.dtb.read_accesses 764786 # DTB read accesses +system.cpu.dtb.write_hits 6392965 # DTB write hits +system.cpu.dtb.write_misses 2560 # DTB write misses system.cpu.dtb.write_acv 158 # DTB write access violations -system.cpu.dtb.write_accesses 298734 # DTB write accesses -system.cpu.dtb.data_hits 15716094 # DTB hits -system.cpu.dtb.data_misses 19765 # DTB misses +system.cpu.dtb.write_accesses 298884 # DTB write accesses +system.cpu.dtb.data_hits 15712452 # DTB hits +system.cpu.dtb.data_misses 20315 # DTB misses system.cpu.dtb.data_acv 369 # DTB access violations -system.cpu.dtb.data_accesses 1063329 # DTB accesses -system.cpu.itb.fetch_hits 4018414 # ITB hits -system.cpu.itb.fetch_misses 6313 # ITB misses -system.cpu.itb.fetch_acv 710 # ITB acv -system.cpu.itb.fetch_accesses 4024727 # ITB accesses +system.cpu.dtb.data_accesses 1063670 # DTB accesses +system.cpu.itb.fetch_hits 4023125 # ITB hits +system.cpu.itb.fetch_misses 6293 # ITB misses +system.cpu.itb.fetch_acv 687 # ITB acv +system.cpu.itb.fetch_accesses 4029418 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -360,88 +361,88 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12750 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6375 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281835914.509804 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 440008281.220830 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6375 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 224500 # Distribution of time spent in the clock gated state +system.cpu.numPwrStateTransitions 12752 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 281784609.786700 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439970621.768515 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 121000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6375 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 96523678000 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1796703955000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 193068084 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 96569006500 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1796658672000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 193159059 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56143729 # Number of instructions committed -system.cpu.committedOps 56143729 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2983109 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 6375 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593387182 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.438818 # CPI: cycles per instruction -system.cpu.ipc 0.290798 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 3199033 5.70% 5.70% # Class of committed instruction -system.cpu.op_class_0::IntAlu 36198718 64.48% 70.17% # Class of committed instruction -system.cpu.op_class_0::IntMult 60825 0.11% 70.28% # Class of committed instruction +system.cpu.committedInsts 56138739 # Number of instructions committed +system.cpu.committedOps 56138739 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2973387 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3593296298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.440745 # CPI: cycles per instruction +system.cpu.ipc 0.290635 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 3199075 5.70% 5.70% # Class of committed instruction +system.cpu.op_class_0::IntAlu 36194440 64.47% 70.17% # Class of committed instruction +system.cpu.op_class_0::IntMult 60814 0.11% 70.28% # Class of committed instruction system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::MemRead 9175039 16.34% 86.70% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6234994 11.11% 97.80% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.op_class_0::MemRead 9174678 16.34% 86.70% # Class of committed instruction +system.cpu.op_class_0::MemWrite 6234348 11.11% 97.80% # Class of committed instruction system.cpu.op_class_0::FloatMemRead 144497 0.26% 98.06% # Class of committed instruction system.cpu.op_class_0::FloatMemWrite 137980 0.25% 98.31% # Class of committed instruction -system.cpu.op_class_0::IprAccess 950928 1.69% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 951192 1.69% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 56143729 # Class of committed instruction +system.cpu.op_class_0::total 56138739 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211453 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74770 40.93% 40.93% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211522 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74796 40.93% 40.93% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105857 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182663 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73403 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105900 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182732 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73429 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73403 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148842 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1837707081000 97.07% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 86418000 0.00% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 712034000 0.04% 97.11% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 54721100500 2.89% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1893226633500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981717 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73429 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148894 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1837688968000 97.07% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 86405500 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 711997500 0.04% 97.11% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 54739315500 2.89% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1893226686500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693417 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814845 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693381 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814822 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed @@ -449,7 +450,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175496 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal::swpipl 175565 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -458,31 +459,31 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192387 # number of callpals executed +system.cpu.kern.callpal::total 192456 # number of callpals executed system.cpu.kern.mode_switch::kernel 5875 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::user 1736 # number of protection mode switches system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1907 -system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_good::kernel 1904 +system.cpu.kern.mode_good::user 1736 system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.324596 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324085 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392872 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 37288586500 1.97% 1.97% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4317914500 0.23% 2.20% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1851620122500 97.80% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.392375 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 37303090500 1.97% 1.97% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4315388500 0.23% 2.20% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1851608197500 97.80% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4174 # number of times the context was actually changed -system.cpu.tickCycles 85319079 # Number of cycles that the object actually ticked -system.cpu.idleCycles 107749005 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1394486 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.980102 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13946466 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1394998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.997481 # Average number of references to valid blocks. +system.cpu.tickCycles 85358190 # Number of cycles that the object actually ticked +system.cpu.idleCycles 107800869 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1394352 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.980074 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13943564 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1394864 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.996361 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 99338500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.980102 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.980074 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -490,369 +491,369 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 225 system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63927467 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63927467 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7985618 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7985618 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5578297 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5578297 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183538 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183538 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 198978 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 198978 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13563915 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13563915 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13563915 # number of overall hits -system.cpu.dcache.overall_hits::total 13563915 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1096590 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1096590 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 573634 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573634 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 16462 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 16462 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1670224 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1670224 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1670224 # number of overall misses -system.cpu.dcache.overall_misses::total 1670224 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33587119500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33587119500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25315634500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25315634500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222567500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 222567500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 58902754000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 58902754000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 58902754000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 58902754000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9082208 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9082208 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6151931 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6151931 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200000 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200000 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 198978 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 198978 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15234139 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15234139 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15234139 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15234139 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120740 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120740 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093245 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093245 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082310 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082310 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.109637 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.109637 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.109637 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.109637 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30628.693951 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30628.693951 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44132.032794 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44132.032794 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13520.076540 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13520.076540 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35266.379839 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35266.379839 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35266.379839 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35266.379839 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63916074 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63916074 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 7983580 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7983580 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5577346 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5577346 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183586 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183586 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199016 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199016 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13560926 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13560926 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13560926 # number of overall hits +system.cpu.dcache.overall_hits::total 13560926 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1096421 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1096421 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 573901 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573901 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 16452 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 16452 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1670322 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1670322 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1670322 # number of overall misses +system.cpu.dcache.overall_misses::total 1670322 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33580747500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33580747500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25364054000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25364054000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223095000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 223095000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 58944801500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 58944801500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 58944801500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 58944801500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9080001 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9080001 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6151247 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6151247 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200038 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200038 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199016 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199016 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15231248 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15231248 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15231248 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15231248 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120751 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120751 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093298 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093298 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082244 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082244 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.109664 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.109664 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.109664 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.109664 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30627.603357 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30627.603357 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44195.870019 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44195.870019 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13560.357403 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13560.357403 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35289.484004 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35289.484004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35289.484004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35289.484004 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 837775 # number of writebacks -system.cpu.dcache.writebacks::total 837775 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21966 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21966 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269674 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269674 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 837673 # number of writebacks +system.cpu.dcache.writebacks::total 837673 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269878 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269878 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 291640 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 291640 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 291640 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 291640 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074624 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074624 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303960 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 303960 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16459 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16459 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378584 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378584 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378584 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378584 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 291859 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 291859 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 291859 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 291859 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074440 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074440 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304023 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304023 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16449 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16449 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1378463 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378463 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1378463 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378463 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32024640000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32024640000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12912591500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12912591500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205405000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205405000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44937231500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 44937231500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44937231500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 44937231500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534181500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534181500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534181500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534181500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118322 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118322 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049409 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049409 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082295 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082295 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090493 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090493 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090493 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090493 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29800.786135 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29800.786135 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42481.219568 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42481.219568 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12479.798287 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12479.798287 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32596.658238 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32596.658238 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32596.658238 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32596.658238 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221382.611833 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221382.611833 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92682.987978 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92682.987978 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1476860 # number of replacements -system.cpu.icache.tags.tagsinuse 509.256241 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 19221452 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1477371 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13.010579 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 36168783500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.256241 # Average occupied blocks per requestor +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32016506000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32016506000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12938125500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12938125500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205942500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205942500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44954631500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44954631500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44954631500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44954631500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534159000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534159000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534159000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534159000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118330 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118330 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049425 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049425 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082229 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082229 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090502 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090502 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090502 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090502 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29798.319124 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29798.319124 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42556.403627 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42556.403627 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12520.062010 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12520.062010 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32612.142292 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32612.142292 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32612.142292 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32612.142292 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221379.365079 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221379.365079 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92681.628708 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92681.628708 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1477259 # number of replacements +system.cpu.icache.tags.tagsinuse 509.256262 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 19240724 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1477770 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.020107 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 36168160500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.256262 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.994641 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.994641 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 398 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 22176547 # Number of tag accesses -system.cpu.icache.tags.data_accesses 22176547 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 19221455 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 19221455 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 19221455 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 19221455 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 19221455 # number of overall hits -system.cpu.icache.overall_hits::total 19221455 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1477546 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1477546 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1477546 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1477546 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1477546 # number of overall misses -system.cpu.icache.overall_misses::total 1477546 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20691200000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20691200000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20691200000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20691200000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20691200000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20691200000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 20699001 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 20699001 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 20699001 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 20699001 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 20699001 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 20699001 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071382 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.071382 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.071382 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.071382 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.071382 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.071382 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14003.760289 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14003.760289 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14003.760289 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14003.760289 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14003.760289 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14003.760289 # average overall miss latency +system.cpu.icache.tags.tag_accesses 22196619 # Number of tag accesses +system.cpu.icache.tags.data_accesses 22196619 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 19240727 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 19240727 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 19240727 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 19240727 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 19240727 # number of overall hits +system.cpu.icache.overall_hits::total 19240727 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1477946 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1477946 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1477946 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1477946 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1477946 # number of overall misses +system.cpu.icache.overall_misses::total 1477946 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20694155000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20694155000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20694155000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20694155000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20694155000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20694155000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 20718673 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 20718673 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 20718673 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 20718673 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 20718673 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 20718673 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071334 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.071334 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.071334 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.071334 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.071334 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.071334 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14001.969625 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14001.969625 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14001.969625 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14001.969625 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14001.969625 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14001.969625 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1476860 # number of writebacks -system.cpu.icache.writebacks::total 1476860 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1477546 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1477546 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1477546 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1477546 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1477546 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1477546 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19213654000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19213654000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19213654000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19213654000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19213654000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19213654000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071382 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071382 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071382 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071382 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13003.760289 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13003.760289 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13003.760289 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13003.760289 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13003.760289 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13003.760289 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 339644 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65408.616626 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5336317 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 405166 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.170693 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6813000000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 268.269404 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5779.515007 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59360.832216 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.004093 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088188 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.905774 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998056 # Average percentage of cache occupancy +system.cpu.icache.writebacks::writebacks 1477259 # number of writebacks +system.cpu.icache.writebacks::total 1477259 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1477946 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1477946 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1477946 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1477946 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1477946 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1477946 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19216209000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19216209000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19216209000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19216209000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19216209000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19216209000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071334 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071334 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071334 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.071334 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071334 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.071334 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13001.969625 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13001.969625 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13001.969625 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13001.969625 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13001.969625 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13001.969625 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 339629 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65408.640121 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5336861 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 405151 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.172523 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6812650000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 268.308507 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5784.509565 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59355.822049 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.004094 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088265 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.905698 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998057 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 585 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5148 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59335 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59336 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 46341070 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 46341070 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 837775 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 837775 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1476292 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1476292 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 15 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 15 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187328 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187328 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461124 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1461124 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818824 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 818824 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1461124 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1006152 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2467276 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1461124 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1006152 # number of overall hits -system.cpu.l2cache.overall_hits::total 2467276 # number of overall hits +system.cpu.l2cache.tags.tag_accesses 46345268 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 46345268 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 837673 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 837673 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1476684 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1476684 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187384 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187384 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1461541 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1461541 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 818635 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 818635 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1461541 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1006019 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2467560 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1461541 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1006019 # number of overall hits +system.cpu.l2cache.overall_hits::total 2467560 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116642 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116642 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16369 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 16369 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272228 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 272228 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 16369 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388870 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405239 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 16369 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388870 # number of overall misses -system.cpu.l2cache.overall_misses::total 405239 # number of overall misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 116650 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116650 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16351 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 16351 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 272221 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 272221 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 16351 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388871 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405222 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 16351 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388871 # number of overall misses +system.cpu.l2cache.overall_misses::total 405222 # number of overall misses system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 331500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 331500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10483953000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10483953000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1616348000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1616348000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21973293500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 21973293500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1616348000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 32457246500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34073594500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1616348000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 32457246500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34073594500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 837775 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 837775 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1476292 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1476292 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 21 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 303970 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 303970 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1477493 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1477493 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1091052 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1091052 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1477493 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1395022 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2872515 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1477493 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1395022 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2872515 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.285714 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383729 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383729 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011079 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011079 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249510 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249510 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011079 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.278755 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.141075 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011079 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.278755 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.141075 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10508664000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10508664000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1613902000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1613902000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21967740000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 21967740000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1613902000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 32476404000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34090306000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1613902000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 32476404000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34090306000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 837673 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 837673 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1476684 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1476684 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 22 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 22 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1477892 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1477892 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1090856 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1090856 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1477892 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1394890 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2872782 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1477892 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1394890 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2872782 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.272727 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.272727 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383674 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383674 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.011064 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.011064 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.249548 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.249548 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011064 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.278783 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.141056 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011064 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.278783 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.141056 # miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 55250 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 55250 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89881.457794 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89881.457794 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 98744.455984 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 98744.455984 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80716.507854 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80716.507854 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 98744.455984 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83465.545041 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84082.712918 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 98744.455984 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83465.545041 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84082.712918 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90087.132447 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90087.132447 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 98703.565531 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 98703.565531 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80698.182727 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80698.182727 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 98703.565531 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83514.594814 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84127.480739 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 98703.565531 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83514.594814 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84127.480739 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 76723 # number of writebacks -system.cpu.l2cache.writebacks::total 76723 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 76715 # number of writebacks +system.cpu.l2cache.writebacks::total 76715 # number of writebacks system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116642 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116642 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16369 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16369 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272228 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272228 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16369 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388870 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405239 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16369 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388870 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405239 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116650 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116650 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16351 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16351 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272221 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272221 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16351 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388871 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405222 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16351 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388871 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405222 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable @@ -861,103 +862,103 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16553 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 271500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9317533000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9317533000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1452658000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1452658000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19254021000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19254021000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1452658000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28571554000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30024212000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1452658000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28571554000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30024212000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447536000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447536000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447536000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447536000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383729 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383729 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011079 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249510 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249510 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278755 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141075 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011079 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278755 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141075 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9342164000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9342164000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1450392000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1450392000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19248668000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19248668000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1450392000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28590832000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30041224000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1450392000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28590832000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30041224000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447515000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447515000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447515000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447515000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.272727 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.272727 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383674 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383674 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011064 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011064 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249548 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249548 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011064 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278783 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141056 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011064 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278783 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141056 # mshr miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 45250 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 45250 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79881.457794 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79881.457794 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 88744.455984 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 88744.455984 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70727.555578 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70727.555578 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 88744.455984 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73473.278988 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74090.134464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 88744.455984 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73473.278988 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74090.134464 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208879.653680 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208879.653680 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87448.559174 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87448.559174 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5743935 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871442 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2378 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 998 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 998 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80087.132447 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80087.132447 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 88703.565531 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 88703.565531 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70709.710125 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70709.710125 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 88703.565531 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73522.664328 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74135.224642 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 88703.565531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73522.664328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74135.224642 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208876.623377 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208876.623377 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87447.290521 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87447.290521 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5744469 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871707 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 999 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2575661 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2575864 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 914498 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1476860 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 819632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 303970 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 303970 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 23 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 240 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4431899 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217835 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8649734 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189078592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142951868 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 332030460 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 340255 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4923648 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3229187 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001046 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.032331 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 914388 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1477259 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 819593 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477946 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 237 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4433097 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217440 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8650537 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189129664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142936828 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 332066492 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 340239 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4923200 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3229438 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001049 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032373 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3225808 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3379 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3226050 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3388 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3229187 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5199690500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3229438 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5200254500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 292383 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 292883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2216461215 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2217065706 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2104266491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2104067991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -971,7 +972,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51175 # Transaction distribution @@ -1002,46 +1003,46 @@ system.iobus.pkt_size_system.bridge.master::total 44348 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5413000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5413500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 807000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 792000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 181000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15127500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15611000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5984000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5971500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216248283 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216263272 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.299538 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.299521 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1735874305000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.299538 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081221 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081221 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1735874841000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.299521 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081220 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081220 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1052,12 +1053,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 29884383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 29884383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4931902900 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4931902900 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4961787283 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4961787283 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4961787283 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4961787283 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4948356889 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4948356889 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4978241272 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4978241272 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4978241272 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4978241272 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1076,17 +1077,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 172742.098266 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 172742.098266 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118692.310839 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118692.310839 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118916.411815 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118916.411815 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118916.411815 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118916.411815 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 893 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119088.296327 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119088.296327 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 119310.755470 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119310.755470 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 119310.755470 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119310.755470 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1846 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 14 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 111.625000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 131.857143 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1100,12 +1101,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 21234383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 21234383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2851851307 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2851851307 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2873085690 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2873085690 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2873085690 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2873085690 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2868303297 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2868303297 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2889537680 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2889537680 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2889537680 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2889537680 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1116,74 +1117,74 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 122742.098266 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 122742.098266 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68633.310238 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68633.310238 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68857.655842 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68857.655842 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68857.655842 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68857.655842 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 827515 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 381393 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69029.247617 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69029.247617 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69251.951588 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69251.951588 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69251.951588 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69251.951588 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 827499 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 381391 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 524 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295677 # Transaction distribution +system.membus.trans_dist::ReadResp 295651 # Transaction distribution system.membus.trans_dist::WriteReq 9623 # Transaction distribution system.membus.trans_dist::WriteResp 9623 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118235 # Transaction distribution -system.membus.trans_dist::CleanEvict 262254 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118227 # Transaction distribution +system.membus.trans_dist::CleanEvict 262247 # Transaction distribution system.membus.trans_dist::UpgradeReq 138 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 116510 # Transaction distribution -system.membus.trans_dist::ReadExResp 116510 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288770 # Transaction distribution -system.membus.trans_dist::BadAddressError 23 # Transaction distribution +system.membus.trans_dist::ReadExReq 116518 # Transaction distribution +system.membus.trans_dist::ReadExResp 116518 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288745 # Transaction distribution +system.membus.trans_dist::BadAddressError 24 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 127 # Transaction distribution +system.membus.trans_dist::InvalidateResp 124 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148837 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 46 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181989 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181940 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1265414 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1265365 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30818176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30862524 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30860860 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33520252 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 561 # Total snoops (count) +system.membus.pkt_size::total 33518588 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 558 # Total snoops (count) system.membus.snoopTraffic 27584 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 463523 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001461 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.038189 # Request fanout histogram +system.membus.snoop_fanout::samples 463506 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001454 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038105 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 462846 99.85% 99.85% # Request fanout histogram -system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 462832 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 674 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 463523 # Request fanout histogram -system.membus.reqLayer0.occupancy 29930000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 463506 # Request fanout histogram +system.membus.reqLayer0.occupancy 30386000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319547835 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1319436087 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 29000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160176250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160035750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1081022 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1079521 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1215,28 +1216,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893227633000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893227678500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 53cfb4ebd..1e6aa4a0d 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,125 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.909484 # Number of seconds simulated -sim_ticks 1909483951500 # Number of ticks simulated -final_tick 1909483951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.910457 # Number of seconds simulated +sim_ticks 1910457097500 # Number of ticks simulated +final_tick 1910457097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164890 # Simulator instruction rate (inst/s) -host_op_rate 164890 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5556117262 # Simulator tick rate (ticks/s) -host_mem_usage 341236 # Number of bytes of host memory used -host_seconds 343.67 # Real time elapsed on the host -sim_insts 56668174 # Number of instructions simulated -sim_ops 56668174 # Number of ops (including micro ops) simulated +host_inst_rate 237868 # Simulator instruction rate (inst/s) +host_op_rate 237868 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8017235800 # Simulator tick rate (ticks/s) +host_mem_usage 340828 # Number of bytes of host memory used +host_seconds 238.29 # Real time elapsed on the host +sim_insts 56682446 # Number of instructions simulated +sim_ops 56682446 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24440064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 121024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 888256 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 856512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24438912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 120704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 888384 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26307904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 857600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 121024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 978624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7910400 # Number of bytes written to this memory -system.physmem.bytes_written::total 7910400 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 381876 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1891 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 13879 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26305472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 856512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 120704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 977216 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7909632 # Number of bytes written to this memory +system.physmem.bytes_written::total 7909632 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13383 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 381858 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1886 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 13881 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 411061 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123600 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123600 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 449127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12799303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 63380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 465181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13777494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 449127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 63380 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4142690 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4142690 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4142690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 449127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12799303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 63380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 465181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17920184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 411061 # Number of read requests accepted -system.physmem.writeReqs 123600 # Number of write requests accepted -system.physmem.readBursts 411061 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123600 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26300672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue -system.physmem.bytesWritten 7909120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26307904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7910400 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 411023 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123588 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123588 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 448328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12792180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 63181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 465011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 502 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13769203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 448328 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 63181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 511509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4140178 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4140178 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4140178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 448328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12792180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 63181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 465011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 502 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17909381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 411023 # Number of read requests accepted +system.physmem.writeReqs 123588 # Number of write requests accepted +system.physmem.readBursts 411023 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123588 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26298624 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue +system.physmem.bytesWritten 7907712 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26305472 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7909632 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26241 # Per bank write bursts -system.physmem.perBankRdBursts::1 25988 # Per bank write bursts -system.physmem.perBankRdBursts::2 25972 # Per bank write bursts -system.physmem.perBankRdBursts::3 25684 # Per bank write bursts -system.physmem.perBankRdBursts::4 25579 # Per bank write bursts -system.physmem.perBankRdBursts::5 25567 # Per bank write bursts -system.physmem.perBankRdBursts::6 25634 # Per bank write bursts -system.physmem.perBankRdBursts::7 25346 # Per bank write bursts -system.physmem.perBankRdBursts::8 25590 # Per bank write bursts -system.physmem.perBankRdBursts::9 25694 # Per bank write bursts -system.physmem.perBankRdBursts::10 25928 # Per bank write bursts -system.physmem.perBankRdBursts::11 25514 # Per bank write bursts +system.physmem.perBankRdBursts::0 26243 # Per bank write bursts +system.physmem.perBankRdBursts::1 25982 # Per bank write bursts +system.physmem.perBankRdBursts::2 25968 # Per bank write bursts +system.physmem.perBankRdBursts::3 25688 # Per bank write bursts +system.physmem.perBankRdBursts::4 25576 # Per bank write bursts +system.physmem.perBankRdBursts::5 25569 # Per bank write bursts +system.physmem.perBankRdBursts::6 25629 # Per bank write bursts +system.physmem.perBankRdBursts::7 25342 # Per bank write bursts +system.physmem.perBankRdBursts::8 25591 # Per bank write bursts +system.physmem.perBankRdBursts::9 25697 # Per bank write bursts +system.physmem.perBankRdBursts::10 25920 # Per bank write bursts +system.physmem.perBankRdBursts::11 25515 # Per bank write bursts system.physmem.perBankRdBursts::12 26076 # Per bank write bursts -system.physmem.perBankRdBursts::13 25422 # Per bank write bursts -system.physmem.perBankRdBursts::14 25093 # Per bank write bursts -system.physmem.perBankRdBursts::15 25620 # Per bank write bursts -system.physmem.perBankWrBursts::0 8582 # Per bank write bursts -system.physmem.perBankWrBursts::1 8090 # Per bank write bursts -system.physmem.perBankWrBursts::2 7941 # Per bank write bursts -system.physmem.perBankWrBursts::3 7423 # Per bank write bursts -system.physmem.perBankWrBursts::4 7276 # Per bank write bursts -system.physmem.perBankWrBursts::5 7412 # Per bank write bursts -system.physmem.perBankWrBursts::6 7548 # Per bank write bursts -system.physmem.perBankWrBursts::7 7160 # Per bank write bursts -system.physmem.perBankWrBursts::8 7532 # Per bank write bursts -system.physmem.perBankWrBursts::9 7637 # Per bank write bursts -system.physmem.perBankWrBursts::10 7817 # Per bank write bursts -system.physmem.perBankWrBursts::11 7733 # Per bank write bursts -system.physmem.perBankWrBursts::12 8265 # Per bank write bursts -system.physmem.perBankWrBursts::13 7849 # Per bank write bursts -system.physmem.perBankWrBursts::14 7512 # Per bank write bursts -system.physmem.perBankWrBursts::15 7803 # Per bank write bursts +system.physmem.perBankRdBursts::13 25417 # Per bank write bursts +system.physmem.perBankRdBursts::14 25094 # Per bank write bursts +system.physmem.perBankRdBursts::15 25609 # Per bank write bursts +system.physmem.perBankWrBursts::0 8586 # Per bank write bursts +system.physmem.perBankWrBursts::1 8089 # Per bank write bursts +system.physmem.perBankWrBursts::2 7939 # Per bank write bursts +system.physmem.perBankWrBursts::3 7426 # Per bank write bursts +system.physmem.perBankWrBursts::4 7272 # Per bank write bursts +system.physmem.perBankWrBursts::5 7413 # Per bank write bursts +system.physmem.perBankWrBursts::6 7547 # Per bank write bursts +system.physmem.perBankWrBursts::7 7156 # Per bank write bursts +system.physmem.perBankWrBursts::8 7533 # Per bank write bursts +system.physmem.perBankWrBursts::9 7641 # Per bank write bursts +system.physmem.perBankWrBursts::10 7810 # Per bank write bursts +system.physmem.perBankWrBursts::11 7729 # Per bank write bursts +system.physmem.perBankWrBursts::12 8256 # Per bank write bursts +system.physmem.perBankWrBursts::13 7847 # Per bank write bursts +system.physmem.perBankWrBursts::14 7516 # Per bank write bursts +system.physmem.perBankWrBursts::15 7798 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 80 # Number of times write queue was full causing retry -system.physmem.totGap 1909479571500 # Total gap between requests +system.physmem.numWrRetry 69 # Number of times write queue was full causing retry +system.physmem.totGap 1910452747500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 411061 # Read request sizes (log2) +system.physmem.readPktSize::6 411023 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123600 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 316679 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 38784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123588 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 316637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38767 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see @@ -159,205 +159,206 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 213 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64366 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.481590 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 324.184214 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.960810 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14447 22.45% 22.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11484 17.84% 40.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5025 7.81% 48.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2916 4.53% 52.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2241 3.48% 56.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1886 2.93% 59.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1937 3.01% 62.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1616 2.51% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22814 35.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64366 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5520 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.445833 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2823.039428 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5517 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 160 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64267 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 532.249522 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 325.147595 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.887517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14293 22.24% 22.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11517 17.92% 40.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5102 7.94% 48.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2862 4.45% 52.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2222 3.46% 56.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1875 2.92% 58.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1935 3.01% 61.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1643 2.56% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22818 35.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64267 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5506 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.626952 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2826.578445 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5503 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5520 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5520 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.387681 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.753213 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.953412 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4982 90.25% 90.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 46 0.83% 91.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 181 3.28% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 8 0.14% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 3 0.05% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 15 0.27% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 3 0.05% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 1 0.02% 94.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 37 0.67% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 6 0.11% 95.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 147 2.66% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 11 0.20% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 11 0.20% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 1 0.02% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 13 0.24% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 5 0.09% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.04% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 4 0.07% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.11% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 8 0.14% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 11 0.20% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 8 0.14% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 6 0.11% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5520 # Writes before turning the bus around for reads -system.physmem.totQLat 8180795500 # Total ticks spent queuing -system.physmem.totMemAccLat 15886070500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2054740000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19907.13 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5506 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5506 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.440610 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.769678 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.128904 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4988 90.59% 90.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 40 0.73% 91.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 160 2.91% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 10 0.18% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 4 0.07% 94.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 18 0.33% 94.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 5 0.09% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 6 0.11% 95.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 35 0.64% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.07% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 137 2.49% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 15 0.27% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 13 0.24% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.05% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 8 0.15% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.05% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 5 0.09% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 3 0.05% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 5 0.09% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 9 0.16% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 10 0.18% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 9 0.16% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 8 0.15% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5506 # Writes before turning the bus around for reads +system.physmem.totQLat 8133947000 # Total ticks spent queuing +system.physmem.totMemAccLat 15838622000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2054580000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19794.67 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38657.13 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 38544.67 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.22 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing -system.physmem.readRowHits 370615 # Number of row buffer hits during reads -system.physmem.writeRowHits 99546 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.54 # Row buffer hit rate for writes -system.physmem.avgGap 3571383.68 # Average gap between requests -system.physmem.pageHitRate 87.95 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229044060 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 121739805 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1470918540 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 320675040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3850719600.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4272567240 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 246889440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 8425769640 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 4664365920 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 449143940805 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 472747584480 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.578716 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1899455525250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 389729500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1635812000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1868844860000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 12146835250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7989359750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 18477355000 # Time in different power states -system.physmem_1.actEnergy 230536320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122529165 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1463250180 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 324412560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3755450400.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4276202130 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 236380800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 8298087360 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 4412246880 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 449354887095 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 472475862540 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.436414 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1899482388000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 371395250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1595272000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1869798792500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 11490281750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8030486500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 18197723500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu0.branchPred.lookups 16749334 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14325553 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 462257 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10374415 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4757954 # Number of BTB hits +system.physmem.avgRdQLen 2.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.12 # Average write queue length when enqueuing +system.physmem.readRowHits 370641 # Number of row buffer hits during reads +system.physmem.writeRowHits 99565 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.56 # Row buffer hit rate for writes +system.physmem.avgGap 3573538.04 # Average gap between requests +system.physmem.pageHitRate 87.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 228629940 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 121519695 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1470818580 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 320654160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3862397760.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4332596790 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 252811200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 8421848610 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 4670504160 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 449339904270 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 473022982485 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.596757 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1900281265750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 402747000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1640746000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1869662817000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 12162830000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8118960750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 18468996750 # Time in different power states +system.physmem_1.actEnergy 230243580 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122373570 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1463121660 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 324318600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3740699040.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4231975260 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 230624160 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8237523150 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 4445714880 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 449624008125 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 472652324325 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.402742 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1900567958250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 356565750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1589032000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1870929942000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 11577456000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7939162500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 18064939250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu0.branchPred.lookups 16804357 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14368910 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 476654 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10787243 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4777357 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 45.862384 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 926589 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 34524 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4807269 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 496703 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 4310566 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 206845 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 44.287099 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 929095 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 33008 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 5112942 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 499455 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 4613487 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 206250 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9423503 # DTB read hits -system.cpu0.dtb.read_misses 34044 # DTB read misses -system.cpu0.dtb.read_acv 602 # DTB read access violations -system.cpu0.dtb.read_accesses 567323 # DTB read accesses -system.cpu0.dtb.write_hits 5707426 # DTB write hits -system.cpu0.dtb.write_misses 8375 # DTB write misses -system.cpu0.dtb.write_acv 432 # DTB write access violations -system.cpu0.dtb.write_accesses 185068 # DTB write accesses -system.cpu0.dtb.data_hits 15130929 # DTB hits -system.cpu0.dtb.data_misses 42419 # DTB misses -system.cpu0.dtb.data_acv 1034 # DTB access violations -system.cpu0.dtb.data_accesses 752391 # DTB accesses -system.cpu0.itb.fetch_hits 1309826 # ITB hits -system.cpu0.itb.fetch_misses 6979 # ITB misses -system.cpu0.itb.fetch_acv 608 # ITB acv -system.cpu0.itb.fetch_accesses 1316805 # ITB accesses +system.cpu0.dtb.read_hits 9429395 # DTB read hits +system.cpu0.dtb.read_misses 34826 # DTB read misses +system.cpu0.dtb.read_acv 601 # DTB read access violations +system.cpu0.dtb.read_accesses 567385 # DTB read accesses +system.cpu0.dtb.write_hits 5710239 # DTB write hits +system.cpu0.dtb.write_misses 8500 # DTB write misses +system.cpu0.dtb.write_acv 413 # DTB write access violations +system.cpu0.dtb.write_accesses 185113 # DTB write accesses +system.cpu0.dtb.data_hits 15139634 # DTB hits +system.cpu0.dtb.data_misses 43326 # DTB misses +system.cpu0.dtb.data_acv 1014 # DTB access violations +system.cpu0.dtb.data_accesses 752498 # DTB accesses +system.cpu0.itb.fetch_hits 1313411 # ITB hits +system.cpu0.itb.fetch_misses 6916 # ITB misses +system.cpu0.itb.fetch_acv 613 # ITB acv +system.cpu0.itb.fetch_accesses 1320327 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -370,152 +371,152 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 12955 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6478 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 285544950.833745 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 440803858.104390 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6477 99.98% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 12957 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6479 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 285646442.815249 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 440880288.422179 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 6479 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 39000 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6478 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 59723759999 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849760191501 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 119453997 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 6479 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 59753794500 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1850703303000 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 119514068 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25744550 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 73396662 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16749334 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6181246 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 86853986 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1333740 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 29854 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 138979 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 426939 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8448706 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 314842 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 113861488 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.644614 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.955082 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 25767559 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 73719684 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16804357 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6205907 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 86932839 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1362768 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 60 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 30191 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 137457 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 417781 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 385 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8508507 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 323806 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 113967656 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.646847 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.957898 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 100232411 88.03% 88.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 886423 0.78% 88.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1866278 1.64% 90.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 772305 0.68% 91.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2608424 2.29% 93.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 580288 0.51% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 680998 0.60% 94.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 835244 0.73% 95.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5399117 4.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 100279992 87.99% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 883136 0.77% 88.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1879288 1.65% 90.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 773699 0.68% 91.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2621733 2.30% 93.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 582123 0.51% 93.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 690580 0.61% 94.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 840992 0.74% 95.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5416113 4.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 113861488 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.140216 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.614435 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 20674409 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 82009104 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8737077 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1802336 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 638561 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 612096 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 28873 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 63730808 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 85670 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 638561 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 21537349 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 55655987 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17571911 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9607617 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 8850061 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 61287779 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 195487 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2001492 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 247198 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4966656 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 41332689 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 73998496 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 73867344 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 122420 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33806898 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7525791 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1421231 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 231053 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12310515 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9804371 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6066029 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1436076 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 935297 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 54210960 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1853678 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52617678 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 75373 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9354795 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 4029114 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1289525 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 113861488 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.462120 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.203620 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 113967656 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.140606 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.616829 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 20688539 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 82043348 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8777506 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1804992 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 653270 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 4633985 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 29119 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 64001211 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 84558 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 653270 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 21557209 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 55702323 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17600356 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9645124 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 8809372 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 61498566 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 199219 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2004403 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 243805 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4929982 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 41484246 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 74256527 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 74125426 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 122370 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33821902 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 7662344 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1423361 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 232902 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12334048 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9834851 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6076556 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1449838 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 941199 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 54338035 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1857223 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52670686 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 76725 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9465955 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 4150833 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1293033 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 113967656 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.462155 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.203590 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 92467205 81.21% 81.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9144132 8.03% 89.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3819872 3.35% 92.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2741139 2.41% 95.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2853722 2.51% 97.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1412384 1.24% 98.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 945124 0.83% 99.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 360447 0.32% 99.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 117463 0.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 92547755 81.21% 81.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9157312 8.04% 89.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3826452 3.36% 92.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2741793 2.41% 95.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2858470 2.51% 97.51% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1410754 1.24% 98.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 945179 0.83% 99.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 363161 0.32% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 116780 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 113861488 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 113967656 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 167498 16.72% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 489097 48.82% 65.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 297116 29.66% 95.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemRead 26550 2.65% 97.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemWrite 21561 2.15% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 167135 16.69% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 489044 48.84% 65.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 297041 29.67% 95.20% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemRead 26511 2.65% 97.85% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMemWrite 21568 2.15% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2541 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 36104376 68.62% 68.62% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 55717 0.11% 68.73% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2539 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 36140522 68.62% 68.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 55958 0.11% 68.73% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.73% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 25404 0.05% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 25396 0.05% 68.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued @@ -543,444 +544,444 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9732272 18.50% 87.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5684196 10.80% 98.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemRead 122332 0.23% 98.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemWrite 110816 0.21% 98.52% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 778757 1.48% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9743290 18.50% 87.28% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5689891 10.80% 98.08% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemRead 122252 0.23% 98.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMemWrite 110721 0.21% 98.52% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 778850 1.48% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52617678 # Type of FU issued -system.cpu0.iq.rate 0.440485 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1001822 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019040 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 219604859 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 65162997 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50893555 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 569180 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 274272 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 257685 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 53309029 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 307930 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 608555 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52670686 # Type of FU issued +system.cpu0.iq.rate 0.440707 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1001299 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019011 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 219818324 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 65405263 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50914307 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 568728 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 273845 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 257541 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 53361731 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 307715 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 607759 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1940010 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3457 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18333 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 663404 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1969497 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4520 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18416 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 673256 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18340 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 362661 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18394 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367969 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 638561 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 52164612 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1031418 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 59600447 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 153776 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9804371 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6066029 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1643055 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39666 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 791016 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18333 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 179892 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 504278 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 684170 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51936356 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9483037 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 681322 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 653270 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 52238307 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1038475 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 59749161 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 168806 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9834851 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6076556 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1644704 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40383 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 797635 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18416 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 191736 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 507842 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 699578 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51971663 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9489993 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 699023 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3535809 # number of nop insts executed -system.cpu0.iew.exec_refs 15215766 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8258108 # Number of branches executed -system.cpu0.iew.exec_stores 5732729 # Number of stores executed -system.cpu0.iew.exec_rate 0.434781 # Inst execution rate -system.cpu0.iew.wb_sent 51332154 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51151240 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26231692 # num instructions producing a value -system.cpu0.iew.wb_consumers 36261297 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.428209 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.723407 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 9848757 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 564153 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 610679 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 112148809 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.442210 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.364760 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 3553903 # number of nop insts executed +system.cpu0.iew.exec_refs 15226009 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8258878 # Number of branches executed +system.cpu0.iew.exec_stores 5736016 # Number of stores executed +system.cpu0.iew.exec_rate 0.434858 # Inst execution rate +system.cpu0.iew.wb_sent 51356635 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51171848 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26241416 # num instructions producing a value +system.cpu0.iew.wb_consumers 36276103 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.428166 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.723380 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 9976632 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 564190 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 625296 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 112216183 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.442120 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.363987 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 94602668 84.35% 84.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6980008 6.22% 90.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3776982 3.37% 93.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2002013 1.79% 95.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1561505 1.39% 97.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 569175 0.51% 97.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 418696 0.37% 98.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 452906 0.40% 98.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1784856 1.59% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 94653327 84.35% 84.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6985358 6.22% 90.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3782709 3.37% 93.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2004229 1.79% 95.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1568389 1.40% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 570810 0.51% 97.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 418508 0.37% 98.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 451920 0.40% 98.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1780933 1.59% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 112148809 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 49593272 # Number of instructions committed -system.cpu0.commit.committedOps 49593272 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 112216183 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 49613021 # Number of instructions committed +system.cpu0.commit.committedOps 49613021 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13266986 # Number of memory references committed -system.cpu0.commit.loads 7864361 # Number of loads committed -system.cpu0.commit.membars 192313 # Number of memory barriers committed -system.cpu0.commit.branches 7507748 # Number of branches committed -system.cpu0.commit.fp_insts 248828 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 45902219 # Number of committed integer instructions. -system.cpu0.commit.function_calls 632222 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2885965 5.82% 5.82% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 32382704 65.30% 71.12% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 54404 0.11% 71.23% # Class of committed instruction +system.cpu0.commit.refs 13268654 # Number of memory references committed +system.cpu0.commit.loads 7865354 # Number of loads committed +system.cpu0.commit.membars 192328 # Number of memory barriers committed +system.cpu0.commit.branches 7511599 # Number of branches committed +system.cpu0.commit.fp_insts 248727 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 45921534 # Number of committed integer instructions. +system.cpu0.commit.function_calls 632359 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2886254 5.82% 5.82% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 32400169 65.31% 71.12% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 54625 0.11% 71.23% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.23% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 24932 0.05% 71.28% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 24929 0.05% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.28% # Class of committed instruction system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7943457 16.02% 87.30% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5299157 10.69% 97.98% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemRead 113217 0.23% 98.21% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemWrite 109412 0.22% 98.43% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 778757 1.57% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.29% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7944499 16.01% 87.30% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5299897 10.68% 97.98% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemRead 113183 0.23% 98.21% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMemWrite 109348 0.22% 98.43% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 778850 1.57% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 49593272 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1784856 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 169631516 # The number of ROB reads -system.cpu0.rob.rob_writes 120597460 # The number of ROB writes -system.cpu0.timesIdled 479927 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5592509 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3698912124 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 46709842 # Number of Instructions Simulated -system.cpu0.committedOps 46709842 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.557362 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.557362 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.391028 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.391028 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67996788 # number of integer regfile reads -system.cpu0.int_regfile_writes 37259313 # number of integer regfile writes -system.cpu0.fp_regfile_reads 121463 # number of floating regfile reads -system.cpu0.fp_regfile_writes 130119 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1657761 # number of misc regfile reads -system.cpu0.misc_regfile_writes 782234 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1252644 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.062362 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10655904 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1253074 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.503811 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 28164500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.062362 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988403 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988403 # Average percentage of cache occupancy +system.cpu0.commit.op_class_0::total 49613021 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1780933 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 169850432 # The number of ROB reads +system.cpu0.rob.rob_writes 120933247 # The number of ROB writes +system.cpu0.timesIdled 478916 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5546412 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3700805346 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 46729302 # Number of Instructions Simulated +system.cpu0.committedOps 46729302 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.557583 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.557583 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.390994 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.390994 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 68048969 # number of integer regfile reads +system.cpu0.int_regfile_writes 37279666 # number of integer regfile writes +system.cpu0.fp_regfile_reads 121382 # number of floating regfile reads +system.cpu0.fp_regfile_writes 130068 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1658488 # number of misc regfile reads +system.cpu0.misc_regfile_writes 782262 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1253915 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.032819 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10656048 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1254345 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.495309 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 28054500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.032819 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988345 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988345 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 407 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.839844 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56905298 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56905298 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6776069 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6776069 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3521167 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3521167 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174528 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174528 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 179927 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 179927 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10297236 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10297236 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10297236 # number of overall hits -system.cpu0.dcache.overall_hits::total 10297236 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1551541 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1551541 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1684277 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1684277 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20385 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20385 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3031 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3031 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3235818 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3235818 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3235818 # number of overall misses -system.cpu0.dcache.overall_misses::total 3235818 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41541989000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 41541989000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 84989668522 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 84989668522 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 383673500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 383673500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17049500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 17049500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 126531657522 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 126531657522 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 126531657522 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 126531657522 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8327610 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8327610 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5205444 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5205444 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194913 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 194913 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182958 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 182958 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13533054 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13533054 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13533054 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13533054 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186313 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.186313 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323561 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323561 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104585 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104585 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016567 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016567 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239105 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.239105 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239105 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.239105 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26774.664028 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26774.664028 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50460.624067 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50460.624067 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18821.363748 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18821.363748 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5625.041241 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5625.041241 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39103.453137 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39103.453137 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39103.453137 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4484959 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5749 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 107356 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 120 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.776510 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 47.908333 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 737573 # number of writebacks -system.cpu0.dcache.writebacks::total 737573 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 550277 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 550277 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432731 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1432731 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5546 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5546 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983008 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1983008 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983008 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1983008 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1001264 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1001264 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251546 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251546 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14839 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14839 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3031 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3031 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1252810 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1252810 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1252810 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1252810 # number of overall MSHR misses +system.cpu0.dcache.tags.tag_accesses 56914873 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56914873 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 6773563 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6773563 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3523907 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3523907 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174492 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174492 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 179921 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 179921 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10297470 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10297470 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10297470 # number of overall hits +system.cpu0.dcache.overall_hits::total 10297470 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1555944 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1555944 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1682220 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1682220 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 19936 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19936 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3029 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3029 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3238164 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3238164 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3238164 # number of overall misses +system.cpu0.dcache.overall_misses::total 3238164 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41483749500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 41483749500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85008982052 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 85008982052 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 398193000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 398193000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17043500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 17043500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 126492731552 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 126492731552 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 126492731552 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 126492731552 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8329507 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8329507 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5206127 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5206127 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194428 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 194428 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182950 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 182950 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13535634 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13535634 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13535634 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13535634 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186799 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.186799 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323123 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.323123 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.102537 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.102537 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016556 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016556 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239233 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.239233 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239233 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.239233 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26661.466929 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26661.466929 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50533.807737 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50533.807737 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 19973.565409 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 19973.565409 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5626.774513 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5626.774513 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39063.102286 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39063.102286 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39063.102286 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39063.102286 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4473141 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2637 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 108649 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 100 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.170568 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 26.370000 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 737996 # number of writebacks +system.cpu0.dcache.writebacks::total 737996 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 553324 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 553324 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1430604 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1430604 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5325 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5325 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983928 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1983928 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983928 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1983928 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1002620 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1002620 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251616 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251616 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14611 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14611 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3029 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3029 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1254236 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1254236 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1254236 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1254236 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 6977 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9910 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9910 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16887 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16887 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31631751000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 31631751000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13189939409 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13189939409 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 172118000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 172118000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14018500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14018500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44821690409 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 44821690409 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44821690409 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 44821690409 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1557150500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1557150500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1557150500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1557150500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120234 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120234 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048324 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048324 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.076131 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.076131 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016567 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016567 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092574 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092574 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092574 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31591.818941 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31591.818941 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52435.496525 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52435.496525 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11599.029584 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11599.029584 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4625.041241 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4625.041241 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35776.925798 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35776.925798 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223183.388276 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223183.388276 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92210.013620 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92210.013620 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 892272 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.350681 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7503325 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 892783 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.404422 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 30334536500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.350681 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994826 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994826 # Average percentage of cache occupancy +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9909 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9909 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16886 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16886 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31595131000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 31595131000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13207477923 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13207477923 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 169739500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 169739500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14014500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14014500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44802608923 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 44802608923 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44802608923 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 44802608923 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1557264500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1557264500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1557264500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1557264500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120370 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120370 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048331 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048331 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075149 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075149 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016556 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016556 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092662 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092662 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092662 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092662 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31512.568072 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31512.568072 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52490.612374 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52490.612374 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11617.240435 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11617.240435 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4626.774513 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4626.774513 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35721.035693 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35721.035693 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35721.035693 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35721.035693 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223199.727677 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223199.727677 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92222.225512 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92222.225512 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 891919 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.368701 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7561136 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 892430 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.472526 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 30335024500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.368701 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994861 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994861 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 501 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9341754 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9341754 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 7503325 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7503325 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7503325 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7503325 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7503325 # number of overall hits -system.cpu0.icache.overall_hits::total 7503325 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 945376 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 945376 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 945376 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 945376 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 945376 # number of overall misses -system.cpu0.icache.overall_misses::total 945376 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13858102494 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13858102494 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13858102494 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13858102494 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13858102494 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13858102494 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8448701 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8448701 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8448701 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8448701 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8448701 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8448701 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111896 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.111896 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111896 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.111896 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111896 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.111896 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14658.826217 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14658.826217 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14658.826217 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14658.826217 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14658.826217 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6578 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 9401165 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9401165 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 7561136 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7561136 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7561136 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7561136 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7561136 # number of overall hits +system.cpu0.icache.overall_hits::total 7561136 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 947367 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 947367 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 947367 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 947367 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 947367 # number of overall misses +system.cpu0.icache.overall_misses::total 947367 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13858743493 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13858743493 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13858743493 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13858743493 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13858743493 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13858743493 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8508503 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8508503 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8508503 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8508503 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8508503 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8508503 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111344 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.111344 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111344 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.111344 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111344 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.111344 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14628.695630 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14628.695630 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14628.695630 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14628.695630 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14628.695630 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14628.695630 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 7760 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 245 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 263 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.848980 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.505703 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 892272 # number of writebacks -system.cpu0.icache.writebacks::total 892272 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 52323 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 52323 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 52323 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 52323 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 52323 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 52323 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 893053 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 893053 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 893053 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 893053 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 893053 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 893053 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12259429995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12259429995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12259429995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12259429995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12259429995 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12259429995 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105703 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.105703 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105703 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.105703 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13727.550319 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13727.550319 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13727.550319 # average overall mshr miss latency -system.cpu1.branchPred.lookups 4441555 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3820450 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 114047 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2322340 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 883836 # Number of BTB hits +system.cpu0.icache.writebacks::writebacks 891919 # number of writebacks +system.cpu0.icache.writebacks::total 891919 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54705 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 54705 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 54705 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 54705 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 54705 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 54705 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 892662 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 892662 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 892662 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 892662 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 892662 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 892662 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12247880494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12247880494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12247880494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12247880494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12247880494 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12247880494 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.104914 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.104914 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.104914 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.104914 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.104914 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.104914 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13720.624933 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13720.624933 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13720.624933 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13720.624933 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13720.624933 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13720.624933 # average overall mshr miss latency +system.cpu1.branchPred.lookups 4440494 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3820633 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 114977 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2284731 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 882766 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 38.057993 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 229553 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 8671 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 1262341 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 163265 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1099076 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 40828 # Number of mispredicted indirect branches. +system.cpu1.branchPred.BTBHitPct 38.637634 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 229523 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8540 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 1232926 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 164040 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 1068886 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 40452 # Number of mispredicted indirect branches. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2431988 # DTB read hits -system.cpu1.dtb.read_misses 15687 # DTB read misses -system.cpu1.dtb.read_acv 78 # DTB read access violations -system.cpu1.dtb.read_accesses 432427 # DTB read accesses -system.cpu1.dtb.write_hits 1439876 # DTB write hits -system.cpu1.dtb.write_misses 3853 # DTB write misses -system.cpu1.dtb.write_acv 69 # DTB write access violations -system.cpu1.dtb.write_accesses 163205 # DTB write accesses -system.cpu1.dtb.data_hits 3871864 # DTB hits -system.cpu1.dtb.data_misses 19540 # DTB misses +system.cpu1.dtb.read_hits 2425125 # DTB read hits +system.cpu1.dtb.read_misses 16040 # DTB read misses +system.cpu1.dtb.read_acv 82 # DTB read access violations +system.cpu1.dtb.read_accesses 432289 # DTB read accesses +system.cpu1.dtb.write_hits 1438640 # DTB write hits +system.cpu1.dtb.write_misses 3531 # DTB write misses +system.cpu1.dtb.write_acv 65 # DTB write access violations +system.cpu1.dtb.write_accesses 162605 # DTB write accesses +system.cpu1.dtb.data_hits 3863765 # DTB hits +system.cpu1.dtb.data_misses 19571 # DTB misses system.cpu1.dtb.data_acv 147 # DTB access violations -system.cpu1.dtb.data_accesses 595632 # DTB accesses -system.cpu1.itb.fetch_hits 677957 # ITB hits -system.cpu1.itb.fetch_misses 3440 # ITB misses -system.cpu1.itb.fetch_acv 149 # ITB acv -system.cpu1.itb.fetch_accesses 681397 # ITB accesses +system.cpu1.dtb.data_accesses 594894 # DTB accesses +system.cpu1.itb.fetch_hits 679335 # ITB hits +system.cpu1.itb.fetch_misses 3486 # ITB misses +system.cpu1.itb.fetch_acv 144 # ITB acv +system.cpu1.itb.fetch_accesses 682821 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -993,584 +994,585 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 5092 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2546 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 746545753.142184 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 396892720.756326 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2546 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 350000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 975495000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2546 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 8778464000 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1900705487500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 17559475 # number of cpu cycles simulated +system.cpu1.numPwrStateTransitions 5088 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2544 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 747516916.077044 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 396242813.132808 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2544 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 975504000 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2544 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 8774063000 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1901683034500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 17550671 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 7089129 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 17628986 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4441555 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1276654 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9239971 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 379390 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 26991 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 67759 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 51232 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 58 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1981137 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 84838 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 16664835 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.057855 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.464288 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 7093737 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 17628277 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4440494 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1276329 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9234250 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 381282 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 26389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 68063 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 51076 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1982953 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 84304 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 16664213 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.057852 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.464693 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 13565594 81.40% 81.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 195508 1.17% 82.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 331371 1.99% 84.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 236250 1.42% 85.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 403775 2.42% 88.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 149802 0.90% 89.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 175422 1.05% 90.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 211560 1.27% 91.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1395553 8.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 13566532 81.41% 81.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 196080 1.18% 82.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 329765 1.98% 84.57% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 235529 1.41% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 402874 2.42% 88.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 150126 0.90% 89.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 175137 1.05% 90.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 212228 1.27% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1395942 8.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 16664835 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.252943 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.003959 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5800433 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 8202202 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2197206 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 282756 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 182237 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 153534 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7597 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 14400936 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 23892 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 182237 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5989487 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 906248 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6023778 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2292128 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1270955 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 13634993 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3736 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 109479 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 34532 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 648624 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 9050025 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 16251882 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 16185746 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59544 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 7082137 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1967880 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 511648 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 53659 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2285085 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2543631 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1545283 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 323334 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 171078 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 11953372 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 586667 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 11470583 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 27894 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2581702 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1224765 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 432970 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 16664835 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.688311 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.414763 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 16664213 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.253010 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.004422 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5803889 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8198941 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2195429 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 282754 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 183199 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 845965 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7619 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 14397519 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 23764 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 183199 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5993501 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 917111 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6016357 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2289218 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1264825 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 13624374 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3775 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 108540 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 34178 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 643759 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 9046149 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 16244839 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 16178929 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59321 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 7078981 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1967160 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 511491 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 53621 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2283119 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2539964 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1543921 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 323106 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 168966 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 11939663 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 585885 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 11455956 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 28942 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2572399 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1228155 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 432246 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 16664213 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.687459 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.414504 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 11964424 71.79% 71.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2022081 12.13% 83.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 866450 5.20% 89.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 621081 3.73% 92.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 573042 3.44% 96.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 300412 1.80% 98.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 196836 1.18% 99.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 86957 0.52% 99.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 33552 0.20% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 11970475 71.83% 71.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2021121 12.13% 83.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 863574 5.18% 89.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 618225 3.71% 92.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 572472 3.44% 96.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 300775 1.80% 98.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 197233 1.18% 99.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 86853 0.52% 99.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 33485 0.20% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 16664835 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 16664213 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 33610 10.34% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.34% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 173421 53.34% 63.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 102626 31.57% 95.25% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemRead 8052 2.48% 97.72% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemWrite 7405 2.28% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 33486 10.24% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 173880 53.16% 63.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 104341 31.90% 95.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemRead 7997 2.44% 97.75% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMemWrite 7375 2.25% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 7105969 61.95% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 17120 0.15% 62.14% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 14007 0.12% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.26% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.28% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2511504 21.90% 84.18% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1426032 12.43% 96.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemRead 45143 0.39% 97.00% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemWrite 43776 0.38% 97.39% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 299906 2.61% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 4756 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7097834 61.96% 62.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 17086 0.15% 62.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 14002 0.12% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.29% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2506692 21.88% 84.17% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1424790 12.44% 96.61% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemRead 45041 0.39% 97.00% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMemWrite 43535 0.38% 97.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 299845 2.62% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 11470583 # Type of FU issued -system.cpu1.iq.rate 0.653242 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 325114 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.028343 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 39732906 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 15018676 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 10950208 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 226102 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 108058 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 105069 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 11670188 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 120758 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 118257 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 11455956 # Type of FU issued +system.cpu1.iq.rate 0.652736 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 327079 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.028551 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 39706848 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 14995495 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 10932885 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 225297 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 107483 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 104737 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 11657954 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 120325 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 118525 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 553253 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1093 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 5172 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 179987 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 552207 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1214 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 5210 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 179004 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 535 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 99855 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 539 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 99906 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 182237 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 561579 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 275117 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 13190679 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 58497 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2543631 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1545283 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 532703 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 6805 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 266988 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 5172 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 45989 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 148806 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 194795 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 11280251 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2456871 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 190331 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 183199 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 564470 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 284501 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 13175740 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 58730 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2539964 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1543921 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 532175 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 7107 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 276039 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 5210 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 46730 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 149015 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 195745 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 11262138 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2450359 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 193817 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 650640 # number of nop insts executed -system.cpu1.iew.exec_refs 3907176 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1689156 # Number of branches executed -system.cpu1.iew.exec_stores 1450305 # Number of stores executed -system.cpu1.iew.exec_rate 0.642403 # Inst execution rate -system.cpu1.iew.wb_sent 11110028 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 11055277 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5286560 # num instructions producing a value -system.cpu1.iew.wb_consumers 7445661 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.629590 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.710019 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 2598878 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 153697 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 169517 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 16202334 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.644600 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.619525 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 650192 # number of nop insts executed +system.cpu1.iew.exec_refs 3899095 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1684701 # Number of branches executed +system.cpu1.iew.exec_stores 1448736 # Number of stores executed +system.cpu1.iew.exec_rate 0.641693 # Inst execution rate +system.cpu1.iew.wb_sent 11092333 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 11037622 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5277529 # num instructions producing a value +system.cpu1.iew.wb_consumers 7434192 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.628900 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.709899 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 2589103 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 153639 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 170452 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 16200161 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.644352 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.619659 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 12420063 76.66% 76.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1746761 10.78% 87.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 624490 3.85% 91.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 388127 2.40% 93.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 294767 1.82% 95.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 125393 0.77% 96.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 112323 0.69% 96.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 119344 0.74% 97.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 371066 2.29% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 12420478 76.67% 76.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1746852 10.78% 87.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 623239 3.85% 91.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 386399 2.39% 93.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 294857 1.82% 95.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 125210 0.77% 96.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 112311 0.69% 96.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 119786 0.74% 97.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 371029 2.29% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 16202334 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 10444029 # Number of instructions committed -system.cpu1.commit.committedOps 10444029 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 16200161 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 10438605 # Number of instructions committed +system.cpu1.commit.committedOps 10438605 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3355674 # Number of memory references committed -system.cpu1.commit.loads 1990378 # Number of loads committed -system.cpu1.commit.membars 48933 # Number of memory barriers committed -system.cpu1.commit.branches 1499197 # Number of branches committed -system.cpu1.commit.fp_insts 102946 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 9701123 # Number of committed integer instructions. -system.cpu1.commit.function_calls 163891 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 490447 4.70% 4.70% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 6215282 59.51% 64.21% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 16829 0.16% 64.37% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.37% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 13998 0.13% 64.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.52% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1994471 19.10% 83.62% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1324148 12.68% 96.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemRead 44840 0.43% 96.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemWrite 41733 0.40% 97.13% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 299906 2.87% 100.00% # Class of committed instruction +system.cpu1.commit.refs 3352674 # Number of memory references committed +system.cpu1.commit.loads 1987757 # Number of loads committed +system.cpu1.commit.membars 48909 # Number of memory barriers committed +system.cpu1.commit.branches 1497531 # Number of branches committed +system.cpu1.commit.fp_insts 102779 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 9696003 # Number of committed integer instructions. +system.cpu1.commit.function_calls 163829 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 490211 4.70% 4.70% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 6213226 59.52% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 16788 0.16% 64.38% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.38% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 13993 0.13% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.51% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.54% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1991924 19.08% 83.62% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1323832 12.68% 96.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemRead 44742 0.43% 96.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMemWrite 41669 0.40% 97.13% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 299845 2.87% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 10444029 # Class of committed instruction -system.cpu1.commit.bw_lim_events 371066 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 28763808 # The number of ROB reads -system.cpu1.rob.rob_writes 26546353 # The number of ROB writes -system.cpu1.timesIdled 134909 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 894640 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3801408429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 9958332 # Number of Instructions Simulated -system.cpu1.committedOps 9958332 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.763295 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.763295 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.567120 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.567120 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 14511646 # number of integer regfile reads -system.cpu1.int_regfile_writes 7905629 # number of integer regfile writes -system.cpu1.fp_regfile_reads 58867 # number of floating regfile reads -system.cpu1.fp_regfile_writes 57930 # number of floating regfile writes -system.cpu1.misc_regfile_reads 573957 # number of misc regfile reads -system.cpu1.misc_regfile_writes 245081 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 131073 # number of replacements -system.cpu1.dcache.tags.tagsinuse 488.756113 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3063603 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 131585 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.282312 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 49534380500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.756113 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954602 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.954602 # Average percentage of cache occupancy +system.cpu1.commit.op_class_0::total 10438605 # Class of committed instruction +system.cpu1.commit.bw_lim_events 371029 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 28746473 # The number of ROB reads +system.cpu1.rob.rob_writes 26517839 # The number of ROB writes +system.cpu1.timesIdled 134718 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 886458 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3803363525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9953144 # Number of Instructions Simulated +system.cpu1.committedOps 9953144 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.763329 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.763329 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.567109 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.567109 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 14490611 # number of integer regfile reads +system.cpu1.int_regfile_writes 7893529 # number of integer regfile writes +system.cpu1.fp_regfile_reads 58631 # number of floating regfile reads +system.cpu1.fp_regfile_writes 57835 # number of floating regfile writes +system.cpu1.misc_regfile_reads 573327 # number of misc regfile reads +system.cpu1.misc_regfile_writes 245000 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 130880 # number of replacements +system.cpu1.dcache.tags.tagsinuse 488.755319 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3056587 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 131392 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.263113 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 49534102500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.755319 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954600 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.954600 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14519091 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14519091 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 1948296 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1948296 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1026442 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1026442 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40668 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 40668 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 37243 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 37243 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2974738 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2974738 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2974738 # number of overall hits -system.cpu1.dcache.overall_hits::total 2974738 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 241303 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 241303 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 292103 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 292103 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5304 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5304 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3101 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3101 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 533406 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 533406 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 533406 # number of overall misses -system.cpu1.dcache.overall_misses::total 533406 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3375705500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3375705500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12203212844 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 12203212844 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54365500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 54365500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17261500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 17261500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 15578918344 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 15578918344 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 15578918344 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 15578918344 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2189599 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2189599 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318545 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1318545 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 45972 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 45972 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40344 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 40344 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3508144 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3508144 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3508144 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3508144 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110204 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.110204 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221534 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.221534 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115375 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115375 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076864 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076864 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152048 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.152048 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152048 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.152048 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13989.488320 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13989.488320 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41777.088370 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41777.088370 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10249.905732 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10249.905732 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5566.430184 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5566.430184 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 29206.492510 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29206.492510 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 29206.492510 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 720965 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 386 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 24769 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 29.107554 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 20.315789 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 84598 # number of writebacks -system.cpu1.dcache.writebacks::total 84598 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148074 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 148074 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243671 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 243671 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 852 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 852 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 391745 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 391745 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 391745 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 391745 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93229 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 93229 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48432 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 48432 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4452 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4452 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3100 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3100 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 141661 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 141661 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 141661 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 141661 # number of overall MSHR misses +system.cpu1.dcache.tags.tag_accesses 14487576 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14487576 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 1941589 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1941589 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1026269 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1026269 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40594 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 40594 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 37239 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 37239 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2967858 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2967858 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2967858 # number of overall hits +system.cpu1.dcache.overall_hits::total 2967858 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 240679 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 240679 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 291916 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 291916 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5260 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5260 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3088 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3088 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 532595 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 532595 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 532595 # number of overall misses +system.cpu1.dcache.overall_misses::total 532595 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3354943500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3354943500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12208160588 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 12208160588 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 53604000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 53604000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17137500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 17137500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15563104088 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15563104088 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15563104088 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15563104088 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2182268 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2182268 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318185 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1318185 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 45854 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 45854 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40327 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 40327 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3500453 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3500453 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3500453 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3500453 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110288 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.110288 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221453 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.221453 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.114712 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.114712 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076574 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076574 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152150 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.152150 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152150 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.152150 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13939.494098 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13939.494098 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41820.799778 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41820.799778 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10190.874525 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10190.874525 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5549.708549 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5549.708549 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29221.273365 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 29221.273365 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29221.273365 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 29221.273365 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 720106 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 464 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 24866 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 28.959463 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 33.142857 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 84401 # number of writebacks +system.cpu1.dcache.writebacks::total 84401 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 147677 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 147677 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243516 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 243516 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 792 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 792 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 391193 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 391193 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 391193 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 391193 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93002 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 93002 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48400 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 48400 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4468 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4468 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3088 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 3088 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 141402 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 141402 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 141402 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 141402 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 218 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3157 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3157 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3375 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3375 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1262260500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1262260500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1962212693 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1962212693 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40045500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40045500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14161500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14161500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3224473193 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3224473193 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3224473193 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3224473193 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41860500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41860500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41860500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41860500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042578 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042578 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036731 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036731 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.096842 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.096842 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076839 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076839 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.040381 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040381 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.040381 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13539.354707 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13539.354707 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40514.797923 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40514.797923 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8994.946092 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8994.946092 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4568.225806 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4568.225806 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22761.897721 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22761.897721 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192020.642202 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192020.642202 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12403.111111 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12403.111111 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 256867 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.812016 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1711658 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 257379 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.650341 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1882992885500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.812016 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919555 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.919555 # Average percentage of cache occupancy +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3156 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3156 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3374 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3374 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1257789500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1257789500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1961692747 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1961692747 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 39632000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 39632000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14049500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14049500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3219482247 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3219482247 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3219482247 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3219482247 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41842500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41842500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41842500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41842500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042617 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042617 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036717 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036717 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.097440 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.097440 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076574 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076574 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040395 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.040395 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040395 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.040395 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13524.327434 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13524.327434 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40530.841880 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40530.841880 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8870.188004 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8870.188004 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4549.708549 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4549.708549 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22768.293567 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22768.293567 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22768.293567 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22768.293567 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191938.073394 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191938.073394 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12401.452282 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12401.452282 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 256309 # number of replacements +system.cpu1.icache.tags.tagsinuse 470.814625 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1714023 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 256821 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.673999 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1883968823500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.814625 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919560 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.919560 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2238596 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2238596 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 1711658 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1711658 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1711658 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1711658 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1711658 # number of overall hits -system.cpu1.icache.overall_hits::total 1711658 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 269479 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 269479 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 269479 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 269479 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 269479 # number of overall misses -system.cpu1.icache.overall_misses::total 269479 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3760599998 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3760599998 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3760599998 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3760599998 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3760599998 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3760599998 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1981137 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1981137 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1981137 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1981137 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1981137 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1981137 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.136022 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.136022 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.136022 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.136022 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.136022 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.136022 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13955.076269 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13955.076269 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13955.076269 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13955.076269 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13955.076269 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 535 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 2239848 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2239848 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 1714023 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1714023 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1714023 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1714023 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1714023 # number of overall hits +system.cpu1.icache.overall_hits::total 1714023 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 268930 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 268930 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 268930 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 268930 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 268930 # number of overall misses +system.cpu1.icache.overall_misses::total 268930 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3748012499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 3748012499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 3748012499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 3748012499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 3748012499 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 3748012499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1982953 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1982953 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1982953 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1982953 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1982953 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1982953 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.135621 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.135621 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.135621 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.135621 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.135621 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.135621 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13936.758632 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13936.758632 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13936.758632 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13936.758632 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13936.758632 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13936.758632 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 558 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 47 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 46 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.382979 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.130435 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 256867 # number of writebacks -system.cpu1.icache.writebacks::total 256867 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12020 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 12020 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 12020 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 12020 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 12020 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 12020 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 257459 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 257459 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 257459 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 257459 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 257459 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 257459 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3369785998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3369785998 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3369785998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3369785998 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3369785998 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3369785998 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.129955 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.129955 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.129955 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.129955 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13088.631580 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13088.631580 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13088.631580 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 256309 # number of writebacks +system.cpu1.icache.writebacks::total 256309 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12035 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 12035 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 12035 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 12035 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 12035 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 12035 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 256895 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 256895 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 256895 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 256895 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 256895 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 256895 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3358325499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3358325499 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3358325499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3358325499 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3358325499 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3358325499 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.129552 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.129552 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.129552 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.129552 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.129552 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.129552 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13072.755402 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13072.755402 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13072.755402 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13072.755402 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13072.755402 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13072.755402 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1583,12 +1585,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7374 # Transaction distribution system.iobus.trans_dist::ReadResp 7374 # Transaction distribution -system.iobus.trans_dist::WriteReq 54619 # Transaction distribution -system.iobus.trans_dist::WriteResp 54619 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11924 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 54617 # Transaction distribution +system.iobus.trans_dist::WriteResp 54617 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11920 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1597,11 +1599,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1814 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40524 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40520 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123986 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 123982 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47680 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1610,50 +1612,50 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 73922 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 73906 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2735578 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12373500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2735562 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12368500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 816500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 820500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 176500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14090000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14153500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2829500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2825500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6041501 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6058000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 89000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216274759 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216256520 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27457000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27455000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.506657 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.514549 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1714262526000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.506657 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.031666 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.031666 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1714263350000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.514549 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.032159 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.032159 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375579 # Number of tag accesses system.iocache.tags.data_accesses 375579 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses system.iocache.ReadReq_misses::total 179 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1662,14 +1664,14 @@ system.iocache.demand_misses::tsunami.ide 41731 # n system.iocache.demand_misses::total 41731 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses system.iocache.overall_misses::total 41731 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22653383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22653383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4913989376 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4913989376 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4936642759 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4936642759 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4936642759 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4936642759 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 22652883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22652883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4915863637 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4915863637 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4938516520 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4938516520 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4938516520 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4938516520 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1686,19 +1688,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126555.212291 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126555.212291 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118261.199846 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118261.199846 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118296.775994 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118296.775994 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118296.775994 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 945 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126552.418994 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126552.418994 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118306.306243 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118306.306243 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118341.676931 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118341.676931 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118341.676931 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118341.676931 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 695 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 135 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 173.750000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks @@ -1710,14 +1712,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41731 system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13703383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13703383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2833958851 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2833958851 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2847662234 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2847662234 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2847662234 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2847662234 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13702883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13702883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2835827584 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2835827584 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2849530467 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2849530467 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2849530467 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2849530467 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1726,454 +1728,455 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76555.212291 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76555.212291 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68202.706272 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68202.706272 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68238.533321 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68238.533321 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 345934 # number of replacements -system.l2c.tags.tagsinuse 65423.183339 # Cycle average of tags in use -system.l2c.tags.total_refs 4331268 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 411456 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.526686 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 6416563000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 293.472249 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5322.167822 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58815.337446 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 207.084290 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 785.121532 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.004478 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081210 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.897451 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003160 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011980 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998279 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76552.418994 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76552.418994 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68247.679630 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68247.679630 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68283.301790 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68283.301790 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68283.301790 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68283.301790 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 345895 # number of replacements +system.l2c.tags.tagsinuse 65423.250509 # Cycle average of tags in use +system.l2c.tags.total_refs 4330734 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 411417 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.526386 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 6416604000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 292.398395 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5320.578215 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58825.194930 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 208.100344 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 776.978626 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.004462 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.081186 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.897601 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003175 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011856 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998280 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1689 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1849 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9122 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52734 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1663 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1868 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5665 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56191 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38356372 # Number of tag accesses -system.l2c.tags.data_accesses 38356372 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 822171 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 822171 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 873935 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 873935 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 2863 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1523 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 4386 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 498 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 473 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 971 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 145860 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 30930 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 176790 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 879457 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 255503 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1134960 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 721850 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 84138 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 805988 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 879457 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 867710 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 255503 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 115068 # number of demand (read+write) hits -system.l2c.demand_hits::total 2117738 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 879457 # number of overall hits -system.l2c.overall_hits::cpu0.data 867710 # number of overall hits -system.l2c.overall_hits::cpu1.inst 255503 # number of overall hits -system.l2c.overall_hits::cpu1.data 115068 # number of overall hits -system.l2c.overall_hits::total 2117738 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4 # number of UpgradeReq misses +system.l2c.tags.tag_accesses 38351741 # Number of tag accesses +system.l2c.tags.data_accesses 38351741 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 822397 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 822397 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 872029 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 872029 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 2840 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1502 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 4342 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 501 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 466 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 967 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 145832 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 30945 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 176777 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 879111 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 254952 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1134063 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 723239 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 83990 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 807229 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 879111 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 869071 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 254952 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 114935 # number of demand (read+write) hits +system.l2c.demand_hits::total 2118069 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 879111 # number of overall hits +system.l2c.overall_hits::cpu0.data 869071 # number of overall hits +system.l2c.overall_hits::cpu1.inst 254952 # number of overall hits +system.l2c.overall_hits::cpu1.data 114935 # number of overall hits +system.l2c.overall_hits::total 2118069 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 7 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 5 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 109487 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 12067 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121554 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 13403 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1908 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 15311 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 272678 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1963 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 274641 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 13403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 382165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1908 # number of demand (read+write) misses +system.l2c.ReadExReq_misses::cpu0.data 109607 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 12062 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 121669 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 13385 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 1902 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 15287 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 272541 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1968 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 274509 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 13385 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 382148 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1902 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 14030 # number of demand (read+write) misses -system.l2c.demand_misses::total 411506 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13403 # number of overall misses -system.l2c.overall_misses::cpu0.data 382165 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1908 # number of overall misses +system.l2c.demand_misses::total 411465 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13385 # number of overall misses +system.l2c.overall_misses::cpu0.data 382148 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1902 # number of overall misses system.l2c.overall_misses::cpu1.data 14030 # number of overall misses -system.l2c.overall_misses::total 411506 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 390000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 86500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 476500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 11308218500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1532406000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 12840624500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1352141000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 194316500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1546457500 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 22230634500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 227734000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 22458368500 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1352141000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 33538853000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 194316500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1760140000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 36845450500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1352141000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 33538853000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 194316500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1760140000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 36845450500 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 822171 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 822171 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 873935 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 873935 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2871 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1527 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4398 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 498 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 474 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 972 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 255347 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 42997 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 298344 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 892860 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 257411 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1150271 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 994528 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 86101 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1080629 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 892860 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1249875 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 257411 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 129098 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2529244 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 892860 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1249875 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 257411 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 129098 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2529244 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.002786 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.002620 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.002729 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.002110 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.001029 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.428777 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.280647 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.407429 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.015011 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007412 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013311 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.274178 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.022799 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.254149 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015011 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.305763 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007412 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.108677 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.162699 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015011 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.305763 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007412 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.108677 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.162699 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 48750 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 21625 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 39708.333333 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 103283.663814 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 126991.464324 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 105637.202396 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 100883.458927 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 101843.029350 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 101003.037032 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 81527.055721 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116013.245033 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 81773.546193 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 100883.458927 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 87760.137637 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 101843.029350 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 125455.452602 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 89538.063844 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 100883.458927 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 87760.137637 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 101843.029350 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 125455.452602 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 89538.063844 # average overall miss latency +system.l2c.overall_misses::total 411465 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 361500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 116000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 477500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 11326788500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1531540500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 12858329000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1345659000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 188021500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1533680500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 22177607000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 225042000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 22402649000 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1345659000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 33504395500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 188021500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1756582500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 36794658500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1345659000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 33504395500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 188021500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1756582500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 36794658500 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 822397 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 822397 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 872029 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 872029 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2847 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1507 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4354 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 501 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 467 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 968 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 255439 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 43007 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 298446 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 892496 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 256854 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1149350 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 995780 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 85958 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1081738 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 892496 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1251219 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 256854 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 128965 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2529534 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 892496 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1251219 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 256854 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 128965 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2529534 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.002459 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.003318 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.002756 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.002141 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.001033 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.429093 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.280466 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.407675 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.014997 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007405 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013301 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.273696 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.022895 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.253767 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014997 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.305421 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007405 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.108789 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.162664 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014997 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.305421 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007405 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.108789 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.162664 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 51642.857143 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 23200 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 39791.666667 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 103340.010218 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 126972.351186 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 105682.869096 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 100534.852447 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 98854.626709 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 100325.799699 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 81373.470414 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 114350.609756 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 81609.888929 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 100534.852447 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 87673.873735 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 98854.626709 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 125201.888810 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 89423.543922 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 100534.852447 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 87673.873735 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 98854.626709 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 125201.888810 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 89423.543922 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 82080 # number of writebacks -system.l2c.writebacks::total 82080 # number of writebacks -system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 17 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits +system.l2c.writebacks::writebacks 82068 # number of writebacks +system.l2c.writebacks::total 82068 # number of writebacks +system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 16 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 16 # number of ReadCleanReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 1 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 7 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 5 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 109487 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 12067 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 121554 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13402 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1891 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 15293 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272678 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1963 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 274641 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13402 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 382165 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1891 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 14030 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 411488 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13402 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 382165 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1891 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 14030 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 411488 # number of overall MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 109607 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 12062 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 121669 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 13385 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1886 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 15271 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272541 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1967 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 274508 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13385 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 382148 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1886 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 14029 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 411448 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13385 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 382148 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1886 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 14029 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 411448 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::total 7195 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 9910 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3157 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 13067 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 16887 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3375 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 20262 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 310000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 75000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 385000 # number of UpgradeReq MSHR miss cycles +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 9909 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3156 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 13065 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 16886 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3374 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 20260 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 291500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 94500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 386000 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18500 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 18500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10213348500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1411735501 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 11625084001 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1218034000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 174078000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1392112000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19509738001 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 208104000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 19717842001 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1218034000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 29723086501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 174078000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1619839501 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 32735038002 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1218034000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 29723086501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 174078000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1619839501 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 32735038002 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1469912000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 39135500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1509047500 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1469912000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 39135500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1509047500 # number of overall MSHR uncacheable cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10230718500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1410920500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 11641639000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1211809000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 167908000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1379717000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19458079003 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 205283000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 19663362003 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1211809000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 29688797503 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 167908000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1616203500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 32684718003 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1211809000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 29688797503 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 167908000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1616203500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 32684718003 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1470022500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 39117500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1509140000 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1470022500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 39117500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1509140000 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002786 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.002620 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.002729 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002110 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.428777 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.280647 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.407429 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013295 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.274178 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022799 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254149 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.162692 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015010 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.305763 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007346 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.108677 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.162692 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 38750 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18750 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 32083.333333 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002459 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.003318 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.002756 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002141 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001033 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.429093 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.280466 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.407675 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014997 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007343 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013287 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.273696 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.022883 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.253766 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014997 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.305421 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007343 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.108781 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.162658 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014997 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.305421 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007343 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.108781 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.162658 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 41642.857143 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18900 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 32166.666667 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93283.663814 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116991.422972 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 95637.198290 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 91029.359838 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71548.632457 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106013.245033 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71794.968708 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90884.494852 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77775.532822 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92056.054997 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 115455.417035 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 79552.837512 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210679.661746 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179520.642202 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209735.580264 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87043.998342 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11595.703704 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74476.729839 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 852121 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 399760 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 540 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93340.010218 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116972.351186 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 95682.869096 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 90534.852447 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 89028.632025 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 90348.831118 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 71395.052499 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 104363.497712 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 71631.289445 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90534.852447 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77689.265685 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 89028.632025 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 115204.469314 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 79438.271672 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90534.852447 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77689.265685 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 89028.632025 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 115204.469314 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 79438.271672 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210695.499498 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179438.073394 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209748.436414 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87055.697027 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11593.805572 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74488.647581 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 851998 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 399673 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 538 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7195 # Transaction distribution -system.membus.trans_dist::ReadResp 297263 # Transaction distribution -system.membus.trans_dist::WriteReq 13067 # Transaction distribution -system.membus.trans_dist::WriteResp 13067 # Transaction distribution -system.membus.trans_dist::WritebackDirty 123600 # Transaction distribution -system.membus.trans_dist::CleanEvict 263134 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6631 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5160 # Transaction distribution +system.membus.trans_dist::ReadResp 297108 # Transaction distribution +system.membus.trans_dist::WriteReq 13065 # Transaction distribution +system.membus.trans_dist::WriteResp 13065 # Transaction distribution +system.membus.trans_dist::WritebackDirty 123588 # Transaction distribution +system.membus.trans_dist::CleanEvict 263109 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6612 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5150 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 121851 # Transaction distribution -system.membus.trans_dist::ReadExResp 121443 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 290113 # Transaction distribution +system.membus.trans_dist::ReadExReq 121960 # Transaction distribution +system.membus.trans_dist::ReadExResp 121558 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289958 # Transaction distribution system.membus.trans_dist::BadAddressError 45 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 134 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40524 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179612 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40520 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179462 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 90 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1220226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1220072 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1303671 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73922 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31560064 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31633986 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1303517 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73906 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31556864 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31630770 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34292226 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 12662 # Total snoops (count) -system.membus.snoopTraffic 28800 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 485569 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001425 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.037724 # Request fanout histogram +system.membus.pkt_size::total 34289010 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 12625 # Total snoops (count) +system.membus.snoopTraffic 28672 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 485492 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001421 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.037673 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 484877 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 692 0.14% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 484802 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 690 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 485569 # Request fanout histogram -system.membus.reqLayer0.occupancy 36441999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 485492 # Request fanout histogram +system.membus.reqLayer0.occupancy 36514000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1353891077 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1353680299 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 56500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 56000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2179677750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2179395750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1104580 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1105081 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5103299 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2546186 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 356313 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1076 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1008 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 5103450 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2546310 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 356575 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1007 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2260964 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13067 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13067 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 904251 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1149139 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 825400 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10906 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 6131 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 17037 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 299755 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 299755 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1150512 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1103306 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2260935 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13065 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13065 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 904465 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1148228 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 826225 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10843 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 6117 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 16960 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 299845 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 299845 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1149557 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1104232 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 45 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution system.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2678185 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3810494 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 771737 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 418186 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7678602 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114248448 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127253332 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32913792 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13701358 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 288116930 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 382331 # Total snoops (count) -system.toL2Bus.snoopTraffic 6809920 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2937042 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.126206 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.332589 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2677077 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3814281 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 770058 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 417575 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7678991 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114202560 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127366412 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32842432 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13680230 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 288091634 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 382034 # Total snoops (count) +system.toL2Bus.snoopTraffic 6794496 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 2936985 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.126280 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.332605 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2566846 87.40% 87.40% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 369740 12.59% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 436 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 20 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2566512 87.39% 87.39% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 370085 12.60% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 367 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 21 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2937042 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4539664918 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2936985 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4539093837 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 302885 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 303384 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1341208229 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1340375720 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1910262297 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1912124205 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 387640565 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 386934286 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 217884535 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 217615473 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -2205,142 +2208,142 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1909483951500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1910457097500 # Cumulative time (in ticks) in various power states system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6478 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 176731 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 62783 40.27% 40.27% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6479 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 176756 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 62790 40.27% 40.27% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.08% 40.36% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1927 1.24% 41.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 182 0.12% 41.71% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 90863 58.29% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 155886 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 61769 49.18% 49.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1927 1.53% 50.82% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 182 0.14% 50.96% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 61587 49.04% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 125596 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1864292107000 97.65% 97.65% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 64306500 0.00% 97.65% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 577089500 0.03% 97.68% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 88747000 0.00% 97.69% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 44160796000 2.31% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1909183046000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983849 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_count::22 1928 1.24% 41.59% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 181 0.12% 41.71% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 90883 58.29% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 155913 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 61775 49.18% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1928 1.53% 50.82% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 181 0.14% 50.96% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 61594 49.04% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 125609 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1865241808000 97.65% 97.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 64326000 0.00% 97.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 577244500 0.03% 97.68% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 87620000 0.00% 97.69% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 44188694000 2.31% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1910159692500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983835 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.677801 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.805691 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.677729 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.805635 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 294 0.18% 0.18% # number of callpals executed +system.cpu0.kern.callpal::wripir 293 0.18% 0.18% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3351 2.05% 2.23% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3349 2.05% 2.23% # number of callpals executed system.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed -system.cpu0.kern.callpal::swpipl 149332 91.35% 93.61% # number of callpals executed -system.cpu0.kern.callpal::rdps 5685 3.48% 97.09% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed +system.cpu0.kern.callpal::swpipl 149358 91.35% 93.61% # number of callpals executed +system.cpu0.kern.callpal::rdps 5686 3.48% 97.09% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.09% # number of callpals executed system.cpu0.kern.callpal::wrusp 1 0.00% 97.09% # number of callpals executed system.cpu0.kern.callpal::rdusp 8 0.00% 97.09% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::rti 4313 2.64% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4314 2.64% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 303 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 163481 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6669 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1070 # number of protection mode switches +system.cpu0.kern.callpal::total 163506 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6667 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1071 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1070 -system.cpu0.kern.mode_good::user 1070 +system.cpu0.kern.mode_good::kernel 1071 +system.cpu0.kern.mode_good::user 1071 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.160444 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.160642 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.276522 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1907148784500 99.91% 99.91% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1683022000 0.09% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.276816 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1908119380500 99.91% 99.91% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1686628500 0.09% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3352 # number of times the context was actually changed +system.cpu0.kern.swap_context 3350 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2546 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 62928 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 19570 37.60% 37.60% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 3.70% 41.30% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 294 0.56% 41.86% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 30260 58.14% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 52049 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 19207 47.61% 47.61% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 4.77% 52.39% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 294 0.73% 53.11% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 18913 46.89% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 40339 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1874881279000 98.19% 98.19% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 565111500 0.03% 98.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 141720000 0.01% 98.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 33895004500 1.78% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1909483115000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981451 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2544 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 62917 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 19565 37.60% 37.60% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1926 3.70% 41.30% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 293 0.56% 41.86% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 30256 58.14% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 52040 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 19203 47.61% 47.61% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1926 4.78% 52.39% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 293 0.73% 53.11% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 18910 46.89% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 40332 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1875855078000 98.19% 98.19% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 566007000 0.03% 98.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 141529500 0.01% 98.23% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 33893640500 1.77% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1910456255000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981498 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.625017 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.775020 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.625000 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.775019 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 182 0.33% 0.34% # number of callpals executed +system.cpu1.kern.callpal::wripir 181 0.33% 0.33% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1230 2.25% 2.59% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1228 2.25% 2.59% # number of callpals executed system.cpu1.kern.callpal::tbi 5 0.01% 2.60% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed -system.cpu1.kern.callpal::swpipl 46579 85.30% 87.91% # number of callpals executed -system.cpu1.kern.callpal::rdps 3079 5.64% 93.55% # number of callpals executed +system.cpu1.kern.callpal::swpipl 46571 85.30% 87.91% # number of callpals executed +system.cpu1.kern.callpal::rdps 3080 5.64% 93.55% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 93.55% # number of callpals executed system.cpu1.kern.callpal::wrusp 6 0.01% 93.56% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.56% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.57% # number of callpals executed system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed -system.cpu1.kern.callpal::rti 3250 5.95% 99.52% # number of callpals executed +system.cpu1.kern.callpal::rti 3249 5.95% 99.52% # number of callpals executed system.cpu1.kern.callpal::callsys 212 0.39% 99.91% # number of callpals executed system.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 54607 # number of callpals executed +system.cpu1.kern.callpal::total 54596 # number of callpals executed system.cpu1.kern.mode_switch::kernel 1700 # number of protection mode switches -system.cpu1.kern.mode_switch::user 670 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2433 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 890 -system.cpu1.kern.mode_good::user 670 -system.cpu1.kern.mode_good::idle 220 -system.cpu1.kern.mode_switch_good::kernel 0.523529 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch::user 669 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2431 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 888 +system.cpu1.kern.mode_good::user 669 +system.cpu1.kern.mode_good::idle 219 +system.cpu1.kern.mode_switch_good::kernel 0.522353 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.090423 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.370602 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 5328500500 0.28% 0.28% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1057436000 0.06% 0.33% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1903097170500 99.67% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1231 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.090086 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.370000 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 5325548500 0.28% 0.28% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1057057500 0.06% 0.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1904073641000 99.67% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1229 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 5af666630..df3a97326 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.865010 # Number of seconds simulated -sim_ticks 1865009748000 # Number of ticks simulated -final_tick 1865009748000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.865014 # Number of seconds simulated +sim_ticks 1865014104500 # Number of ticks simulated +final_tick 1865014104500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 235871 # Simulator instruction rate (inst/s) -host_op_rate 235870 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8303287371 # Simulator tick rate (ticks/s) -host_mem_usage 337912 # Number of bytes of host memory used -host_seconds 224.61 # Real time elapsed on the host -sim_insts 52979108 # Number of instructions simulated -sim_ops 52979108 # Number of ops (including micro ops) simulated +host_inst_rate 231832 # Simulator instruction rate (inst/s) +host_op_rate 231832 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8163594872 # Simulator tick rate (ticks/s) +host_mem_usage 339292 # Number of bytes of host memory used +host_seconds 228.46 # Real time elapsed on the host +sim_insts 52963270 # Number of instructions simulated +sim_ops 52963270 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 962240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24880192 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 962304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24880000 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25843392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 962240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 962240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7516224 # Number of bytes written to this memory -system.physmem.bytes_written::total 7516224 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15035 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388753 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25843264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 962304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 962304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7514304 # Number of bytes written to this memory +system.physmem.bytes_written::total 7514304 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15036 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388750 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403803 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117441 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117441 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 515944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13340516 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403801 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117411 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117411 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 515977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13340382 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13856974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 515944 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 515944 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4030126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4030126 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4030126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 515944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13340516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13856873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 515977 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 515977 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4029087 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4029087 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4029087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 515977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13340382 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17887100 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403803 # Number of read requests accepted -system.physmem.writeReqs 117441 # Number of write requests accepted -system.physmem.readBursts 403803 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117441 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25835712 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue -system.physmem.bytesWritten 7515136 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25843392 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7516224 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17885960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403801 # Number of read requests accepted +system.physmem.writeReqs 117411 # Number of write requests accepted +system.physmem.readBursts 403801 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117411 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25836480 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue +system.physmem.bytesWritten 7512704 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25843264 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7514304 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25444 # Per bank write bursts -system.physmem.perBankRdBursts::1 25611 # Per bank write bursts -system.physmem.perBankRdBursts::2 25628 # Per bank write bursts -system.physmem.perBankRdBursts::3 25719 # Per bank write bursts -system.physmem.perBankRdBursts::4 25100 # Per bank write bursts -system.physmem.perBankRdBursts::5 25088 # Per bank write bursts -system.physmem.perBankRdBursts::6 24758 # Per bank write bursts -system.physmem.perBankRdBursts::7 24649 # Per bank write bursts -system.physmem.perBankRdBursts::8 24903 # Per bank write bursts -system.physmem.perBankRdBursts::9 25188 # Per bank write bursts -system.physmem.perBankRdBursts::10 25284 # Per bank write bursts -system.physmem.perBankRdBursts::11 25005 # Per bank write bursts -system.physmem.perBankRdBursts::12 24375 # Per bank write bursts -system.physmem.perBankRdBursts::13 25430 # Per bank write bursts +system.physmem.perBankRdBursts::0 25442 # Per bank write bursts +system.physmem.perBankRdBursts::1 25616 # Per bank write bursts +system.physmem.perBankRdBursts::2 25500 # Per bank write bursts +system.physmem.perBankRdBursts::3 25612 # Per bank write bursts +system.physmem.perBankRdBursts::4 25113 # Per bank write bursts +system.physmem.perBankRdBursts::5 25182 # Per bank write bursts +system.physmem.perBankRdBursts::6 24743 # Per bank write bursts +system.physmem.perBankRdBursts::7 24567 # Per bank write bursts +system.physmem.perBankRdBursts::8 25026 # Per bank write bursts +system.physmem.perBankRdBursts::9 25298 # Per bank write bursts +system.physmem.perBankRdBursts::10 25283 # Per bank write bursts +system.physmem.perBankRdBursts::11 25011 # Per bank write bursts +system.physmem.perBankRdBursts::12 24384 # Per bank write bursts +system.physmem.perBankRdBursts::13 25424 # Per bank write bursts system.physmem.perBankRdBursts::14 25804 # Per bank write bursts -system.physmem.perBankRdBursts::15 25697 # Per bank write bursts -system.physmem.perBankWrBursts::0 7804 # Per bank write bursts -system.physmem.perBankWrBursts::1 7583 # Per bank write bursts -system.physmem.perBankWrBursts::2 7900 # Per bank write bursts -system.physmem.perBankWrBursts::3 7698 # Per bank write bursts -system.physmem.perBankWrBursts::4 7224 # Per bank write bursts -system.physmem.perBankWrBursts::5 7092 # Per bank write bursts -system.physmem.perBankWrBursts::6 6759 # Per bank write bursts -system.physmem.perBankWrBursts::7 6515 # Per bank write bursts -system.physmem.perBankWrBursts::8 7053 # Per bank write bursts -system.physmem.perBankWrBursts::9 6824 # Per bank write bursts +system.physmem.perBankRdBursts::15 25690 # Per bank write bursts +system.physmem.perBankWrBursts::0 7803 # Per bank write bursts +system.physmem.perBankWrBursts::1 7588 # Per bank write bursts +system.physmem.perBankWrBursts::2 7778 # Per bank write bursts +system.physmem.perBankWrBursts::3 7603 # Per bank write bursts +system.physmem.perBankWrBursts::4 7231 # Per bank write bursts +system.physmem.perBankWrBursts::5 7190 # Per bank write bursts +system.physmem.perBankWrBursts::6 6745 # Per bank write bursts +system.physmem.perBankWrBursts::7 6418 # Per bank write bursts +system.physmem.perBankWrBursts::8 7146 # Per bank write bursts +system.physmem.perBankWrBursts::9 6920 # Per bank write bursts system.physmem.perBankWrBursts::10 7197 # Per bank write bursts system.physmem.perBankWrBursts::11 7005 # Per bank write bursts -system.physmem.perBankWrBursts::12 6955 # Per bank write bursts -system.physmem.perBankWrBursts::13 7882 # Per bank write bursts +system.physmem.perBankWrBursts::12 6963 # Per bank write bursts +system.physmem.perBankWrBursts::13 7878 # Per bank write bursts system.physmem.perBankWrBursts::14 8018 # Per bank write bursts -system.physmem.perBankWrBursts::15 7915 # Per bank write bursts +system.physmem.perBankWrBursts::15 7903 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 65 # Number of times write queue was full causing retry -system.physmem.totGap 1865004470500 # Total gap between requests +system.physmem.numWrRetry 61 # Number of times write queue was full causing retry +system.physmem.totGap 1865008869500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403803 # Read request sizes (log2) +system.physmem.readPktSize::6 403801 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117441 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314056 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 36501 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28766 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117411 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314099 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28723 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -149,115 +149,116 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61362 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 543.503536 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 333.365701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.323842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13476 21.96% 21.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10707 17.45% 39.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4479 7.30% 46.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2678 4.36% 51.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2195 3.58% 54.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1843 3.00% 57.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1874 3.05% 60.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1552 2.53% 63.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22558 36.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61362 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.231977 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2938.731055 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5157 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 139 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61269 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 544.301360 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 334.095290 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.294475 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13441 21.94% 21.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10649 17.38% 39.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4420 7.21% 46.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2704 4.41% 50.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2252 3.68% 54.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1833 2.99% 57.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1848 3.02% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1534 2.50% 63.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22588 36.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61269 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5165 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.156438 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2937.375866 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5162 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.756589 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.921420 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.589297 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4641 89.94% 89.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 34 0.66% 90.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 173 3.35% 93.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 9 0.17% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 2 0.04% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 16 0.31% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 8 0.16% 94.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 3 0.06% 94.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 29 0.56% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.08% 95.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 150 2.91% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 19 0.37% 98.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 6 0.12% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 5 0.10% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 7 0.14% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 2 0.04% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.06% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 7 0.14% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 5 0.10% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 10 0.19% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 13 0.25% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 4 0.08% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.08% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads -system.physmem.totQLat 7817102750 # Total ticks spent queuing -system.physmem.totMemAccLat 15386159000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018415000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19364.46 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5165 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5165 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.727202 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.973066 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.761118 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4630 89.64% 89.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 34 0.66% 90.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 183 3.54% 93.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 6 0.12% 93.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 3 0.06% 94.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 17 0.33% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 10 0.19% 94.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 3 0.06% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 30 0.58% 95.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.08% 95.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 158 3.06% 98.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 16 0.31% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 13 0.25% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 4 0.08% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 6 0.12% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 2 0.04% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 3 0.06% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.12% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.12% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 9 0.17% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 8 0.15% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 2 0.04% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 5 0.10% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5165 # Writes before turning the bus around for reads +system.physmem.totQLat 7762770500 # Total ticks spent queuing +system.physmem.totMemAccLat 15332051750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018475000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19229.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38114.46 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 37979.30 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s @@ -266,88 +267,88 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.99 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.83 # Average write queue length when enqueuing -system.physmem.readRowHits 364427 # Number of row buffer hits during reads -system.physmem.writeRowHits 95317 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.83 # Average write queue length when enqueuing +system.physmem.readRowHits 364450 # Number of row buffer hits during reads +system.physmem.writeRowHits 95361 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.28 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.16 # Row buffer hit rate for writes -system.physmem.avgGap 3577987.41 # Average gap between requests -system.physmem.pageHitRate 88.22 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 216106380 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 114863265 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1442258580 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 305761500 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3620229600.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4158564390 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 232346880 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 8004158310 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 4220231520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 438996708360 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 461312299845 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.351146 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1855244620250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 361602000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1537874000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1826739481250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 10990187750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7827619250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 17552983750 # Time in different power states -system.physmem_1.actEnergy 222025440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 118005525 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1440038040 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 307191780 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3620229600.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4104344850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 228211680 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 8096599200 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 4247999520 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 438951182175 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 461336536560 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.364142 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1855407985250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 350582750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1537736000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1826594899250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 11062498750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7708202750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 17755828500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 19556212 # Number of BP lookups -system.cpu.branchPred.condPredicted 16618547 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 593854 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12802975 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5420040 # Number of BTB hits +system.physmem.writeRowHitRate 81.22 # Row buffer hit rate for writes +system.physmem.avgGap 3578215.52 # Average gap between requests +system.physmem.pageHitRate 88.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 215406660 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 114491355 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1440673500 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 304618320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3636824880.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4141323030 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240547200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 8014976340 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 4268063520 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 438971983965 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 461349368400 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.370445 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1855266278000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 380549250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1544966000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1826613361750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 11114845500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7783583250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 17576798750 # Time in different power states +system.physmem_1.actEnergy 222061140 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 118024500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1441708800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 308136600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3631907760.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4166934840 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 235115520 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 8062896810 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 4253243040 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 438933503490 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 461375149740 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.384267 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1855254817500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 370314000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1542730000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1826502260750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 11076094000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7841044250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 17681661500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 19565204 # Number of BP lookups +system.cpu.branchPred.condPredicted 16626727 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 606351 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12911299 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5422453 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 42.334223 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1126473 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 42524 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6261380 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 563797 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5697583 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 265016 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 41.997734 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1125914 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 42947 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 6343232 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 564019 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5779213 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 264491 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 11131129 # DTB read hits -system.cpu.dtb.read_misses 49734 # DTB read misses -system.cpu.dtb.read_acv 613 # DTB read access violations -system.cpu.dtb.read_accesses 995788 # DTB read accesses -system.cpu.dtb.write_hits 6783534 # DTB write hits -system.cpu.dtb.write_misses 12230 # DTB write misses -system.cpu.dtb.write_acv 435 # DTB write access violations -system.cpu.dtb.write_accesses 345368 # DTB write accesses -system.cpu.dtb.data_hits 17914663 # DTB hits -system.cpu.dtb.data_misses 61964 # DTB misses -system.cpu.dtb.data_acv 1048 # DTB access violations -system.cpu.dtb.data_accesses 1341156 # DTB accesses -system.cpu.itb.fetch_hits 1815343 # ITB hits -system.cpu.itb.fetch_misses 10369 # ITB misses -system.cpu.itb.fetch_acv 759 # ITB acv -system.cpu.itb.fetch_accesses 1825712 # ITB accesses +system.cpu.dtb.read_hits 11109232 # DTB read hits +system.cpu.dtb.read_misses 50748 # DTB read misses +system.cpu.dtb.read_acv 615 # DTB read access violations +system.cpu.dtb.read_accesses 993788 # DTB read accesses +system.cpu.dtb.write_hits 6757496 # DTB write hits +system.cpu.dtb.write_misses 12693 # DTB write misses +system.cpu.dtb.write_acv 420 # DTB write access violations +system.cpu.dtb.write_accesses 345501 # DTB write accesses +system.cpu.dtb.data_hits 17866728 # DTB hits +system.cpu.dtb.data_misses 63441 # DTB misses +system.cpu.dtb.data_acv 1035 # DTB access violations +system.cpu.dtb.data_accesses 1339289 # DTB accesses +system.cpu.itb.fetch_hits 1817930 # ITB hits +system.cpu.itb.fetch_misses 10423 # ITB misses +system.cpu.itb.fetch_acv 754 # ITB acv +system.cpu.itb.fetch_accesses 1828353 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -360,270 +361,269 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12878 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6439 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 279575452.943004 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 438968142.754116 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6439 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 71000 # Distribution of time spent in the clock gated state +system.cpu.numPwrStateTransitions 12882 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6441 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 279499621.875485 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 438940062.434372 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6441 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 80500 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6439 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 64823406500 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1800186341500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 129653253 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 6441 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 64757040000 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1800257064500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 129520522 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30226306 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85761758 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19556212 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7110310 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 91828962 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1682802 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 214 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 31116 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 206972 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 428466 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 497 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9929941 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 408418 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 123563934 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.694068 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.023639 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30117726 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85842784 # Number of instructions fetch has processed +system.cpu.fetch.Branches 19565204 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7112386 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 91831627 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1707334 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 94 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 30324 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 206515 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 432806 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9953050 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 416768 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 123473258 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.695234 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.025215 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 107716203 87.17% 87.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1033964 0.84% 88.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2108086 1.71% 89.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 968916 0.78% 90.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2910075 2.36% 92.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 665807 0.54% 93.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 808204 0.65% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1035117 0.84% 94.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6317562 5.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 107617936 87.16% 87.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1029887 0.83% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2106014 1.71% 89.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 969195 0.78% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2907839 2.36% 92.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 668408 0.54% 93.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 818971 0.66% 94.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1034002 0.84% 94.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6321006 5.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 123563934 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.150835 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.661470 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24256271 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86199481 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 10262767 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2038754 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 806660 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 739137 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 35567 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 74091152 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 113387 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 806660 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25262123 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 56608165 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20046193 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11227977 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9612814 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 71075345 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 200089 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2115758 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 264182 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5312560 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 47887128 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 85631010 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 85450068 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168489 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38179018 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9708102 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1730208 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 277739 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13892500 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 11673351 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7232744 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1724750 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1099672 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 62753291 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2208700 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 60568136 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 94532 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11982878 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5316307 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1547451 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 123563934 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.490176 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.236204 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 123473258 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.151059 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.662774 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24152038 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86201336 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 10258063 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2042752 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 819068 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 5235547 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 36008 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 74118733 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 112337 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 819068 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25161583 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 56623083 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20020475 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11228852 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9620195 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 71027053 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 203339 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2122213 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 263594 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5326402 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 47839712 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 85552570 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 85371726 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168391 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38166163 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 9673541 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1731851 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 279206 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13863805 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 11669742 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7218714 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1729922 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1107908 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 62661067 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2212545 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 60426230 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 90696 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11910337 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5399466 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1551308 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 123473258 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.489387 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.234720 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 99014105 80.13% 80.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10422330 8.43% 88.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4419921 3.58% 92.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3179961 2.57% 94.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3252538 2.63% 97.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1603803 1.30% 98.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1099991 0.89% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 433312 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 137973 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 98959132 80.15% 80.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10414953 8.43% 88.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4418122 3.58% 92.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3174360 2.57% 94.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3248671 2.63% 97.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1596633 1.29% 98.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1092968 0.89% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 431056 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 137363 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 123563934 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 123473258 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 206621 16.55% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 610635 48.92% 65.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 372589 29.85% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 31948 2.56% 97.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 26502 2.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 204093 16.54% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 604376 48.98% 65.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 366984 29.74% 95.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 31970 2.59% 97.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 26536 2.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7279 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 40937281 67.59% 67.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62136 0.10% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38562 0.06% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 11522525 19.02% 86.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6750152 11.14% 97.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 156092 0.26% 98.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 141347 0.23% 98.43% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949126 1.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 40835249 67.58% 67.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 62139 0.10% 67.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38557 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 11506324 19.04% 86.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6726484 11.13% 97.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 156184 0.26% 98.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 141292 0.23% 98.43% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949086 1.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 60568136 # Type of FU issued -system.cpu.iq.rate 0.467155 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1248295 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020610 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 245303428 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 76606948 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 58345447 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 739604 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 359470 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 336798 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 61411065 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 398087 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 692317 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 60426230 # Type of FU issued +system.cpu.iq.rate 0.466538 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1233959 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020421 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 244910582 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 76445733 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 58177679 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 739790 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 359586 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 336759 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 61254735 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 398175 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 690768 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2580830 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3930 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 22198 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 854795 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2579745 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4605 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21941 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 842112 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17998 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 456632 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18009 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 459546 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 806660 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 52694504 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1340713 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 68945664 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 202125 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 11673351 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7232744 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1959731 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 45749 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1091638 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 22198 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 229988 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 630611 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 860599 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 59710531 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 11213503 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 857604 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 819068 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 52732826 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1310921 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 68860028 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 210874 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 11669742 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7218714 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1962223 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 46667 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1061185 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 21941 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 239076 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 633747 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 872823 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 59548676 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 11192398 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 877553 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3983673 # number of nop insts executed -system.cpu.iew.exec_refs 18029484 # number of memory reference insts executed -system.cpu.iew.exec_branches 9387402 # Number of branches executed -system.cpu.iew.exec_stores 6815981 # Number of stores executed -system.cpu.iew.exec_rate 0.460540 # Inst execution rate -system.cpu.iew.wb_sent 58927059 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 58682245 # cumulative count of insts written-back -system.cpu.iew.wb_producers 29779151 # num instructions producing a value -system.cpu.iew.wb_consumers 41279871 # num instructions consuming a value -system.cpu.iew.wb_rate 0.452609 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.721396 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12584544 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661249 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 770143 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 121389515 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.462724 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.395132 # Number of insts commited each cycle +system.cpu.iew.exec_nop 3986416 # number of nop insts executed +system.cpu.iew.exec_refs 17982691 # number of memory reference insts executed +system.cpu.iew.exec_branches 9367788 # Number of branches executed +system.cpu.iew.exec_stores 6790293 # Number of stores executed +system.cpu.iew.exec_rate 0.459762 # Inst execution rate +system.cpu.iew.wb_sent 58762094 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 58514438 # cumulative count of insts written-back +system.cpu.iew.wb_producers 29700638 # num instructions producing a value +system.cpu.iew.wb_consumers 41179298 # num instructions consuming a value +system.cpu.iew.wb_rate 0.451777 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.721252 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 12514858 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661237 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 782772 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 121281996 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.462997 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.395862 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 101523124 83.63% 83.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7984339 6.58% 90.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4194668 3.46% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2261790 1.86% 95.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1754136 1.45% 96.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 633873 0.52% 97.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 481376 0.40% 97.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 513083 0.42% 98.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2043126 1.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 101434078 83.63% 83.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7974018 6.57% 90.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4186796 3.45% 93.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2256770 1.86% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1754187 1.45% 96.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 639315 0.53% 97.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 479528 0.40% 97.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 513600 0.42% 98.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2043704 1.69% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 121389515 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56169799 # Number of instructions committed -system.cpu.commit.committedOps 56169799 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 121281996 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56153243 # Number of instructions committed +system.cpu.commit.committedOps 56153243 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470470 # Number of memory references committed -system.cpu.commit.loads 9092521 # Number of loads committed -system.cpu.commit.membars 226360 # Number of memory barriers committed -system.cpu.commit.branches 8440690 # Number of branches committed +system.cpu.commit.refs 15466599 # Number of memory references committed +system.cpu.commit.loads 9089997 # Number of loads committed +system.cpu.commit.membars 226363 # Number of memory barriers committed +system.cpu.commit.branches 8438860 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52019202 # Number of committed integer instructions. -system.cpu.commit.function_calls 740566 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3197964 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36217526 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60675 0.11% 70.28% # Class of committed instruction +system.cpu.commit.int_insts 52003390 # Number of committed integer instructions. +system.cpu.commit.function_calls 740372 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3197246 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36205593 64.48% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60678 0.11% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction @@ -653,39 +653,39 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9174285 16.33% 86.69% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6245839 11.12% 97.81% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9171764 16.33% 86.69% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6244492 11.12% 97.81% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemRead 144596 0.26% 98.06% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemWrite 138067 0.25% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949126 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949086 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56169799 # Class of committed instruction -system.cpu.commit.bw_lim_events 2043126 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 187851195 # The number of ROB reads -system.cpu.rob.rob_writes 139687376 # The number of ROB writes -system.cpu.timesIdled 556781 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6089319 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3600366244 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52979108 # Number of Instructions Simulated -system.cpu.committedOps 52979108 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.447252 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.447252 # CPI: Total CPI of All Threads -system.cpu.ipc 0.408622 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.408622 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 77910051 # number of integer regfile reads -system.cpu.int_regfile_writes 42617580 # number of integer regfile writes -system.cpu.fp_regfile_reads 166665 # number of floating regfile reads -system.cpu.fp_regfile_writes 175716 # number of floating regfile writes -system.cpu.misc_regfile_reads 2001313 # number of misc regfile reads -system.cpu.misc_regfile_writes 939513 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1405851 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994060 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 12629128 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1406363 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.979992 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 28232500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994060 # Average occupied blocks per requestor +system.cpu.commit.op_class_0::total 56153243 # Class of committed instruction +system.cpu.commit.bw_lim_events 2043704 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 187656858 # The number of ROB reads +system.cpu.rob.rob_writes 139533948 # The number of ROB writes +system.cpu.timesIdled 550447 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6047264 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3600507688 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52963270 # Number of Instructions Simulated +system.cpu.committedOps 52963270 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.445478 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.445478 # CPI: Total CPI of All Threads +system.cpu.ipc 0.408918 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.408918 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 77682847 # number of integer regfile reads +system.cpu.int_regfile_writes 42491451 # number of integer regfile writes +system.cpu.fp_regfile_reads 166573 # number of floating regfile reads +system.cpu.fp_regfile_writes 175777 # number of floating regfile writes +system.cpu.misc_regfile_reads 2001872 # number of misc regfile reads +system.cpu.misc_regfile_writes 939479 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1405824 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994108 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 12609719 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1406336 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.966363 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 28054500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994108 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -693,507 +693,501 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 67152661 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 67152661 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 8020035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 8020035 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4180765 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4180765 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 212398 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 212398 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215680 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215680 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 12200800 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 12200800 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 12200800 # number of overall hits -system.cpu.dcache.overall_hits::total 12200800 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1817327 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1817327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1966706 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1966706 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23570 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23570 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 93 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 93 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3784033 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3784033 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3784033 # number of overall misses -system.cpu.dcache.overall_misses::total 3784033 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 45159601500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 45159601500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 92703832258 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 92703832258 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 420302500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 420302500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1299500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 1299500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137863433758 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137863433758 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137863433758 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137863433758 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9837362 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9837362 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147471 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147471 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235968 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 235968 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215773 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215773 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15984833 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15984833 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15984833 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15984833 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184737 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.184737 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319921 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.319921 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.099886 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.099886 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000431 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000431 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.236726 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.236726 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.236726 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.236726 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24849.463800 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24849.463800 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47136.599094 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47136.599094 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17832.095885 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17832.095885 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13973.118280 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13973.118280 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36432.936435 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36432.936435 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36432.936435 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36432.936435 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4933871 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2725 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 132268 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.302076 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 97.321429 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 844182 # number of writebacks -system.cpu.dcache.writebacks::total 844182 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717105 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 717105 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1677249 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1677249 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6763 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6763 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2394354 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2394354 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2394354 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2394354 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100222 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1100222 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289457 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289457 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16807 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16807 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 93 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 93 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1389679 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1389679 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1389679 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1389679 # number of overall MSHR misses +system.cpu.dcache.tags.tag_accesses 67057386 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 67057386 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 8001397 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 8001397 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4179263 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4179263 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 213150 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 213150 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215702 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215702 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 12180660 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 12180660 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 12180660 # number of overall hits +system.cpu.dcache.overall_hits::total 12180660 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1813374 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1813374 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1966870 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1966870 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22944 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22944 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 62 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 62 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3780244 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3780244 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3780244 # number of overall misses +system.cpu.dcache.overall_misses::total 3780244 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 45111482000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 45111482000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 92228872060 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 92228872060 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 421566000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 421566000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 865000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 865000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 137340354060 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 137340354060 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 137340354060 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 137340354060 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9814771 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9814771 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6146133 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6146133 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 236094 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 236094 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215764 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215764 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15960904 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15960904 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15960904 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15960904 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184760 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.184760 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.320017 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.320017 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.097182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.097182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000287 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000287 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.236844 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.236844 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.236844 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.236844 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24877.097609 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24877.097609 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46891.188569 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46891.188569 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18373.692469 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18373.692469 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13951.612903 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13951.612903 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36331.081819 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36331.081819 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36331.081819 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36331.081819 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4936405 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4609 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 132646 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 30 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.214880 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 153.633333 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 843338 # number of writebacks +system.cpu.dcache.writebacks::total 843338 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 712674 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 712674 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1677487 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1677487 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6576 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 6576 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2390161 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2390161 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2390161 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2390161 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100700 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1100700 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289383 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 289383 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16368 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 16368 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 62 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 62 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1390083 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1390083 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1390083 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1390083 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33013560500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33013560500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14384695133 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14384695133 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 210983000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 210983000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1206500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1206500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47398255633 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47398255633 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47398255633 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47398255633 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535352000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535352000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535352000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535352000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111841 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111841 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047086 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047086 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071226 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071226 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000431 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000431 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086937 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.086937 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086937 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.086937 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30006.271916 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30006.271916 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49695.447452 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49695.447452 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12553.281371 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12553.281371 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12973.118280 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12973.118280 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34107.341072 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34107.341072 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34107.341072 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34107.341072 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221551.515152 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221551.515152 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92888.378002 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92888.378002 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1077480 # number of replacements -system.cpu.icache.tags.tagsinuse 509.004193 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8783075 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1077988 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.147656 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 30284131500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.004193 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994149 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994149 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33019179500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33019179500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14332081529 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14332081529 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205108500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205108500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 803000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 803000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47351261029 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47351261029 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47351261029 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47351261029 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535277500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535277500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535277500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535277500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.112147 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.112147 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047084 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047084 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.069328 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.069328 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000287 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000287 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087093 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.087093 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087093 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.087093 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29998.346053 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29998.346053 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49526.342353 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49526.342353 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12531.066716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12531.066716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12951.612903 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12951.612903 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34063.621402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34063.621402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34063.621402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34063.621402 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221540.764791 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221540.764791 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92883.870773 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92883.870773 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 1070370 # number of replacements +system.cpu.icache.tags.tagsinuse 509.026702 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8813001 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1070878 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.229697 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 30284278500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.026702 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994193 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994193 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11008225 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11008225 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 8783075 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8783075 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8783075 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8783075 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8783075 # number of overall hits -system.cpu.icache.overall_hits::total 8783075 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1146854 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1146854 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1146854 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1146854 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1146854 # number of overall misses -system.cpu.icache.overall_misses::total 1146854 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16347552990 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16347552990 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16347552990 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16347552990 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16347552990 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16347552990 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9929929 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9929929 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9929929 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9929929 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9929929 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9929929 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115495 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115495 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115495 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115495 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.115495 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.115495 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14254.258162 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14254.258162 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14254.258162 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14254.258162 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14254.258162 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14254.258162 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8615 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 11024191 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11024191 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 8813002 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8813002 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8813002 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8813002 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8813002 # number of overall hits +system.cpu.icache.overall_hits::total 8813002 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1140039 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1140039 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1140039 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1140039 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1140039 # number of overall misses +system.cpu.icache.overall_misses::total 1140039 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16263731493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16263731493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16263731493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16263731493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16263731493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16263731493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9953041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9953041 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9953041 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9953041 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9953041 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9953041 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.114542 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.114542 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.114542 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.114542 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.114542 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.114542 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14265.943089 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14265.943089 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14265.943089 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14265.943089 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14265.943089 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14265.943089 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8433 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 335 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 25.716418 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.880137 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1077480 # number of writebacks -system.cpu.icache.writebacks::total 1077480 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68558 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68558 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68558 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68558 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68558 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68558 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1078296 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1078296 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1078296 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1078296 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1078296 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1078296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14436755994 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14436755994 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14436755994 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14436755994 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14436755994 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14436755994 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108591 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.108591 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108591 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.108591 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13388.490724 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13388.490724 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13388.490724 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13388.490724 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13388.490724 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13388.490724 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 338614 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65420.361718 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4561143 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 404136 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.286159 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6414386000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 255.267028 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5315.608032 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59849.486658 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.003895 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081110 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.913231 # Average percentage of cache occupancy +system.cpu.icache.writebacks::writebacks 1070370 # number of writebacks +system.cpu.icache.writebacks::total 1070370 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68889 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 68889 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 68889 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 68889 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 68889 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 68889 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071150 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1071150 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1071150 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1071150 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1071150 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1071150 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14349436996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14349436996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14349436996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14349436996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14349436996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14349436996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.107620 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.107620 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.107620 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.107620 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.107620 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.107620 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13396.290899 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13396.290899 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13396.290899 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13396.290899 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13396.290899 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13396.290899 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 338611 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65420.352754 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4547118 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 404133 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 11.251538 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6414124000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 256.173828 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5307.615094 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 59856.563832 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.003909 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080988 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.913339 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998235 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 896 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 446 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5595 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58579 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 439 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5606 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58575 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40130556 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40130556 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 844182 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 844182 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1076791 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1076791 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 68 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 68 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 93 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 93 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185239 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185239 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1062874 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1062874 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 831967 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 831967 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1062874 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1017206 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2080080 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1062874 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1017206 # number of overall hits -system.cpu.l2cache.overall_hits::total 2080080 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 7 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 114698 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 114698 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15038 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 15038 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 274508 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 274508 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15038 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389206 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404244 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15038 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389206 # number of overall misses -system.cpu.l2cache.overall_misses::total 404244 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 357500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 357500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12064669000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12064669000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1519815000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1519815000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22385224000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 22385224000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1519815000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 34449893000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35969708000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1519815000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 34449893000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35969708000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 844182 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 844182 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1076791 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1076791 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 75 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 75 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 93 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 93 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 299937 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 299937 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1077912 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1077912 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1106475 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1106475 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1077912 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1406412 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2484324 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1077912 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1406412 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2484324 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.093333 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.093333 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382407 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.382407 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.013951 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.013951 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248092 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248092 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.013951 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.276737 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.162718 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013951 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.276737 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.162718 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 51071.428571 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 51071.428571 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105186.393834 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105186.393834 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101064.968746 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101064.968746 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81546.709021 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81546.709021 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101064.968746 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88513.262899 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 88980.190182 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101064.968746 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88513.262899 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 88980.190182 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 40018321 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40018321 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 843338 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 843338 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1069837 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1069837 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 60 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 60 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 62 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 62 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 185066 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 185066 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1055887 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1055887 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 832119 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 832119 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1055887 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1017185 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2073072 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1055887 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1017185 # number of overall hits +system.cpu.l2cache.overall_hits::total 2073072 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 114704 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 114704 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 15037 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 15037 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 274496 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 274496 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15037 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389200 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404237 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15037 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389200 # number of overall misses +system.cpu.l2cache.overall_misses::total 404237 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 448000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 448000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12012512000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12012512000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1519237500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1519237500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22383517000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 22383517000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1519237500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 34396029000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35915266500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1519237500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 34396029000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35915266500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 843338 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 843338 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1069837 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1069837 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 70 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 70 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 62 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 62 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 299770 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 299770 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1070924 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1070924 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1106615 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1106615 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1070924 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1406385 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2477309 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1070924 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1406385 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2477309 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.142857 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.142857 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382640 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.382640 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014041 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014041 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.248050 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.248050 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014041 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.276738 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.163176 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014041 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.276738 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.163176 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 44800 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 44800 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104726.182173 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104726.182173 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101033.284565 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101033.284565 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81544.055287 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81544.055287 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101033.284565 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88376.230730 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 88847.053832 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101033.284565 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88376.230730 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 88847.053832 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 75929 # number of writebacks -system.cpu.l2cache.writebacks::total 75929 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114698 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 114698 # number of ReadExReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 75899 # number of writebacks +system.cpu.l2cache.writebacks::total 75899 # number of writebacks +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114704 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 114704 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15037 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15037 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274508 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274508 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274496 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274496 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 15037 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389206 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404243 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389200 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404237 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 15037 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389206 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404243 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389200 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404237 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 287500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 287500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10917688501 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10917688501 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1369353500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1369353500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19646288000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19646288000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1369353500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 30563976501 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31933330001 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1369353500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 30563976501 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31933330001 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448711500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448711500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448711500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448711500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.093333 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.093333 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013950 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248092 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248092 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276737 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.162718 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013950 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276737 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.162718 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 41071.428571 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 41071.428571 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95186.389484 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95186.389484 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 91065.604841 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 91065.604841 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71569.090883 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71569.090883 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 91065.604841 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78529.047602 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78995.381493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 91065.604841 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78529.047602 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78995.381493 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209049.278499 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209049.278499 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87646.651340 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87646.651340 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4968207 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2483449 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 5093 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 951 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 951 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 348000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 348000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10865472000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10865472000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1368867500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1368867500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19644703500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19644703500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1368867500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 30510175500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31879043000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1368867500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 30510175500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31879043000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448637000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448637000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448637000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448637000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.142857 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.142857 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382640 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382640 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014041 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014041 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248050 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248050 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014041 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276738 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.163176 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014041 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276738 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.163176 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 34800 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 34800 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94726.182173 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94726.182173 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 91033.284565 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 91033.284565 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71566.447234 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71566.447234 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 91033.284565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78392.023381 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78862.259021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 91033.284565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78392.023381 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78862.259021 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209038.528139 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209038.528139 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87642.144110 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87642.144110 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4953861 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2476312 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4344 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 953 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 953 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2191810 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2184804 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 920111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1077480 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 824354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 75 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 93 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 168 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 299937 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 299937 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1078296 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106636 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 919237 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1070370 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 825198 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 70 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 62 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 299770 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 299770 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1071150 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106776 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateResp 2 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3233688 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252227 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7485915 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137945088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144089148 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 282034236 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 339553 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4894016 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2840416 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002130 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.046099 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3212444 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252074 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7464518 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137042816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144033404 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 281076220 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 339392 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4881984 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2833204 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001872 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043223 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2834367 99.79% 99.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 6049 0.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2827901 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5303 0.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2840416 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4418829500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2833204 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4403702500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 292883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1618554275 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1607637172 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2121571625 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2121526099 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1207,7 +1201,7 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51151 # Transaction distribution @@ -1238,46 +1232,46 @@ system.iobus.pkt_size_system.bridge.master::total 44156 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5364500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5360000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 813500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 815500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 178500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14114000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14072500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2179500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2178500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6040500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6063000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 88500 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 93500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216207792 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216225034 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.265392 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.265440 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1714257470000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.265392 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.079087 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.079087 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1714255689000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.265440 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.079090 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.079090 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1286,14 +1280,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21940383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21940383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4930799409 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4930799409 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4952739792 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4952739792 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4952739792 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4952739792 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21944883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21944883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4931807151 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4931807151 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4953752034 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4953752034 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4953752034 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4953752034 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1310,19 +1304,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126823.023121 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126823.023121 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118665.753971 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118665.753971 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118699.575602 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118699.575602 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118699.575602 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118699.575602 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1416 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126849.034682 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126849.034682 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118690.006522 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118690.006522 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118723.835446 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118723.835446 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118723.835446 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118723.835446 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1219 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 13 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 12 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 108.923077 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 101.583333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1334,14 +1328,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13290383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13290383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2850780302 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2850780302 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2864070685 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2864070685 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2864070685 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2864070685 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13294883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13294883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2851781783 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2851781783 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2865076666 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2865076666 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2865076666 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2865076666 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1350,76 +1344,76 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76823.023121 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76823.023121 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68607.535185 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68607.535185 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68641.598203 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68641.598203 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68641.598203 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68641.598203 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 825546 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 380389 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 528 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76849.034682 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76849.034682 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68631.637057 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68631.637057 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68665.707993 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68665.707993 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68665.707993 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68665.707993 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 825536 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 380380 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 527 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 296601 # Transaction distribution +system.membus.trans_dist::ReadResp 296589 # Transaction distribution system.membus.trans_dist::WriteReq 9599 # Transaction distribution system.membus.trans_dist::WriteResp 9599 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117441 # Transaction distribution -system.membus.trans_dist::CleanEvict 262065 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117411 # Transaction distribution +system.membus.trans_dist::CleanEvict 262092 # Transaction distribution system.membus.trans_dist::UpgradeReq 137 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 114568 # Transaction distribution -system.membus.trans_dist::ReadExResp 114568 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289718 # Transaction distribution +system.membus.trans_dist::ReadExReq 114577 # Transaction distribution +system.membus.trans_dist::ReadExResp 114577 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289706 # Transaction distribution system.membus.trans_dist::BadAddressError 47 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 124 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 94 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178956 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1262389 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1262381 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701888 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30746044 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30699840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30743996 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33403772 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 563 # Total snoops (count) -system.membus.snoopTraffic 27904 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 462504 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001466 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.038259 # Request fanout histogram +system.membus.pkt_size::total 33401724 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 562 # Total snoops (count) +system.membus.snoopTraffic 27840 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 462501 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001464 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.038231 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 461826 99.85% 99.85% # Request fanout histogram -system.membus.snoop_fanout::1 678 0.15% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 461824 99.85% 99.85% # Request fanout histogram +system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 462504 # Request fanout histogram -system.membus.reqLayer0.occupancy 28800500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 462501 # Request fanout histogram +system.membus.reqLayer0.occupancy 28785000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1313542061 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1313532070 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 57500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 60000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2137882250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2137876500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1056521 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1057021 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1451,52 +1445,52 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865009748000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865014104500 # Cumulative time (in ticks) in various power states system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211030 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74670 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211020 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105578 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182260 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73303 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182250 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73303 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1819124828000 97.54% 97.54% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 67368000 0.00% 97.54% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 565513500 0.03% 97.57% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 45251211500 2.43% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1865008921000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148608 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1819143935000 97.54% 97.54% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 67422000 0.00% 97.54% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 565966500 0.03% 97.57% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 45235960500 2.43% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1865013284000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694302 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815418 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694287 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815407 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed @@ -1504,7 +1498,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175141 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175131 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1513,7 +1507,7 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5106 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191988 # number of callpals executed +system.cpu.kern.callpal::total 191978 # number of callpals executed system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches @@ -1524,9 +1518,9 @@ system.cpu.kern.mode_switch_good::kernel 0.326098 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.393971 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29666586000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2759246500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1832583080500 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 29665976500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2757716000 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832589583500 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- |