diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
| commit | 5b08e211ab35fd6d936dafda45014c78b5e68300 (patch) | |
| tree | 771950b6f1e0c775d83a5f03f2387f2e3850cc58 /tests/long/fs/10.linux-boot/ref/alpha | |
| parent | b085db84afcbb4824d34b8755f4c09c1fcfefcee (diff) | |
| download | gem5-5b08e211ab35fd6d936dafda45014c78b5e68300.tar.xz | |
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
12 files changed, 4486 insertions, 4425 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 01fef3e75..69d3e7023 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -15,17 +15,18 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/binaries/console +console=/home/stever/m5/m5_system_2.0b3/binaries/console eventq_index=0 init_param=0 -kernel=/dist/binaries/vmlinux +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/binaries/ts_osfpal -readfile=tests/halt.sh +pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -131,6 +132,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -636,6 +638,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -1091,7 +1094,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -1114,7 +1117,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -1235,9 +1238,9 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -1248,27 +1251,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[1] [system.simple_disk] @@ -1281,7 +1290,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr index 20fe2d682..c0d08bdf9 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr @@ -2,3 +2,4 @@ warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything +warn: Obsolete M5 ivlb instruction encountered. diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index d125f29b8..d865b26f6 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 19:30:57 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual +gem5 compiled Jun 21 2014 10:36:29 +gem5 started Jun 21 2014 13:05:58 +gem5 executing on phenom +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/vmlinux +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 126320000 -Exiting @ tick 1903338216000 because m5_exit instruction encountered +info: Launching CPU 1 @ 121062000 +Exiting @ tick 1906207240000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 5cabf17a2..2b53a578a 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.905651 # Number of seconds simulated -sim_ticks 1905651402000 # Number of ticks simulated -final_tick 1905651402000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.906207 # Number of seconds simulated +sim_ticks 1906207240000 # Number of ticks simulated +final_tick 1906207240000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124387 # Simulator instruction rate (inst/s) -host_op_rate 124387 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4179760275 # Simulator tick rate (ticks/s) -host_mem_usage 352908 # Number of bytes of host memory used -host_seconds 455.92 # Real time elapsed on the host -sim_insts 56710998 # Number of instructions simulated -sim_ops 56710998 # Number of ops (including micro ops) simulated +host_inst_rate 147655 # Simulator instruction rate (inst/s) +host_op_rate 147655 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5021061637 # Simulator tick rate (ticks/s) +host_mem_usage 308576 # Number of bytes of host memory used +host_seconds 379.64 # Real time elapsed on the host +sim_insts 56056069 # Number of instructions simulated +sim_ops 56056069 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 897600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24800576 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 78720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 431296 # Number of bytes read from this memory -system.physmem.bytes_read::total 28857792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 897600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 78720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 976320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7816896 # Number of bytes written to this memory -system.physmem.bytes_written::total 7816896 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14025 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387509 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1230 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6739 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450903 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122139 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122139 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 471020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13014225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1390391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 41309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 226325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15143269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 471020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 41309 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4101955 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4101955 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4101955 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 471020 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13014225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1390391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 41309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 226325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19245224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450903 # Number of read requests accepted -system.physmem.writeReqs 122139 # Number of write requests accepted -system.physmem.readBursts 450903 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122139 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28848704 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue -system.physmem.bytesWritten 7815360 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28857792 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7816896 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 903488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24906304 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2649664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 74560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 378304 # Number of bytes read from this memory +system.physmem.bytes_read::total 28912320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 903488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 74560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 978048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7848000 # Number of bytes written to this memory +system.physmem.bytes_written::total 7848000 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 14117 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 389161 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41401 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1165 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 5911 # Number of read requests responded to by this memory +system.physmem.num_reads::total 451755 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122625 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122625 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 473972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 13065895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1390019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 39114 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 198459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15167459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 473972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 39114 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4117076 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4117076 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4117076 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 473972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13065895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1390019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 39114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 198459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19284535 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 451755 # Number of read requests accepted +system.physmem.writeReqs 122625 # Number of write requests accepted +system.physmem.readBursts 451755 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122625 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28904128 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue +system.physmem.bytesWritten 7846080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28912320 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7848000 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4858 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28020 # Per bank write bursts -system.physmem.perBankRdBursts::1 28240 # Per bank write bursts -system.physmem.perBankRdBursts::2 28746 # Per bank write bursts -system.physmem.perBankRdBursts::3 28309 # Per bank write bursts -system.physmem.perBankRdBursts::4 27973 # Per bank write bursts -system.physmem.perBankRdBursts::5 28180 # Per bank write bursts -system.physmem.perBankRdBursts::6 28116 # Per bank write bursts -system.physmem.perBankRdBursts::7 27456 # Per bank write bursts -system.physmem.perBankRdBursts::8 27700 # Per bank write bursts -system.physmem.perBankRdBursts::9 28070 # Per bank write bursts -system.physmem.perBankRdBursts::10 27744 # Per bank write bursts -system.physmem.perBankRdBursts::11 28151 # Per bank write bursts -system.physmem.perBankRdBursts::12 28476 # Per bank write bursts -system.physmem.perBankRdBursts::13 28764 # Per bank write bursts -system.physmem.perBankRdBursts::14 28477 # Per bank write bursts -system.physmem.perBankRdBursts::15 28339 # Per bank write bursts -system.physmem.perBankWrBursts::0 7807 # Per bank write bursts -system.physmem.perBankWrBursts::1 7750 # Per bank write bursts -system.physmem.perBankWrBursts::2 8222 # Per bank write bursts -system.physmem.perBankWrBursts::3 7743 # Per bank write bursts -system.physmem.perBankWrBursts::4 7390 # Per bank write bursts -system.physmem.perBankWrBursts::5 7636 # Per bank write bursts -system.physmem.perBankWrBursts::6 7609 # Per bank write bursts -system.physmem.perBankWrBursts::7 6913 # Per bank write bursts -system.physmem.perBankWrBursts::8 6944 # Per bank write bursts -system.physmem.perBankWrBursts::9 7275 # Per bank write bursts -system.physmem.perBankWrBursts::10 7157 # Per bank write bursts -system.physmem.perBankWrBursts::11 7547 # Per bank write bursts -system.physmem.perBankWrBursts::12 7916 # Per bank write bursts -system.physmem.perBankWrBursts::13 8234 # Per bank write bursts -system.physmem.perBankWrBursts::14 8082 # Per bank write bursts -system.physmem.perBankWrBursts::15 7890 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 3217 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28097 # Per bank write bursts +system.physmem.perBankRdBursts::1 28602 # Per bank write bursts +system.physmem.perBankRdBursts::2 29043 # Per bank write bursts +system.physmem.perBankRdBursts::3 27571 # Per bank write bursts +system.physmem.perBankRdBursts::4 27384 # Per bank write bursts +system.physmem.perBankRdBursts::5 27564 # Per bank write bursts +system.physmem.perBankRdBursts::6 27744 # Per bank write bursts +system.physmem.perBankRdBursts::7 27694 # Per bank write bursts +system.physmem.perBankRdBursts::8 27865 # Per bank write bursts +system.physmem.perBankRdBursts::9 28720 # Per bank write bursts +system.physmem.perBankRdBursts::10 28531 # Per bank write bursts +system.physmem.perBankRdBursts::11 28618 # Per bank write bursts +system.physmem.perBankRdBursts::12 28938 # Per bank write bursts +system.physmem.perBankRdBursts::13 28977 # Per bank write bursts +system.physmem.perBankRdBursts::14 28277 # Per bank write bursts +system.physmem.perBankRdBursts::15 28002 # Per bank write bursts +system.physmem.perBankWrBursts::0 7839 # Per bank write bursts +system.physmem.perBankWrBursts::1 8045 # Per bank write bursts +system.physmem.perBankWrBursts::2 8418 # Per bank write bursts +system.physmem.perBankWrBursts::3 7040 # Per bank write bursts +system.physmem.perBankWrBursts::4 6886 # Per bank write bursts +system.physmem.perBankWrBursts::5 7040 # Per bank write bursts +system.physmem.perBankWrBursts::6 7326 # Per bank write bursts +system.physmem.perBankWrBursts::7 7097 # Per bank write bursts +system.physmem.perBankWrBursts::8 7158 # Per bank write bursts +system.physmem.perBankWrBursts::9 7908 # Per bank write bursts +system.physmem.perBankWrBursts::10 7739 # Per bank write bursts +system.physmem.perBankWrBursts::11 7821 # Per bank write bursts +system.physmem.perBankWrBursts::12 8331 # Per bank write bursts +system.physmem.perBankWrBursts::13 8401 # Per bank write bursts +system.physmem.perBankWrBursts::14 7959 # Per bank write bursts +system.physmem.perBankWrBursts::15 7587 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1905651381000 # Total gap between requests +system.physmem.totGap 1906202745000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 450903 # Read request sizes (log2) +system.physmem.readPktSize::6 451755 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 122139 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 319686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 41704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 44614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3971 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2095 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1646 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122625 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 319401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 41325 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 46009 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3967 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 893 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -158,358 +158,359 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66611 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 550.416718 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 337.147598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 420.487836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14710 22.08% 22.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11156 16.75% 38.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5022 7.54% 46.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2851 4.28% 50.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2435 3.66% 54.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1624 2.44% 56.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1521 2.28% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1728 2.59% 61.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25564 38.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66611 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7169 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 62.875994 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2479.971838 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 7166 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66892 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 549.396161 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 336.305192 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 420.466175 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14808 22.14% 22.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11177 16.71% 38.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5157 7.71% 46.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2881 4.31% 50.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2294 3.43% 54.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1713 2.56% 56.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1492 2.23% 59.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1822 2.72% 61.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25548 38.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66892 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7192 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 62.794355 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2475.959084 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 7189 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7169 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7169 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.033756 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.809188 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.694603 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5699 79.50% 79.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 43 0.60% 80.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 713 9.95% 90.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 256 3.57% 93.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 102 1.42% 95.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 22 0.31% 95.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 28 0.39% 95.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 86 1.20% 96.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 18 0.25% 97.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 42 0.59% 97.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 15 0.21% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 21 0.29% 98.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 11 0.15% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 10 0.14% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.04% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 26 0.36% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.03% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.03% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 2 0.03% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.01% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 1 0.01% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 4 0.06% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 3 0.04% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 6 0.08% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.03% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 1 0.01% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 3 0.04% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 5 0.07% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 11 0.15% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 5 0.07% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 4 0.06% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 1 0.01% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 1 0.01% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 1 0.01% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 7 0.10% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 11 0.15% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7192 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7192 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.046023 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.810949 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.823344 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 5742 79.84% 79.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 42 0.58% 80.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 691 9.61% 90.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 254 3.53% 93.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 102 1.42% 94.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 28 0.39% 95.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 28 0.39% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 90 1.25% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 10 0.14% 97.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 32 0.44% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 22 0.31% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 14 0.19% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 15 0.21% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 7 0.10% 98.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 9 0.13% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 23 0.32% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 11 0.15% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.03% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 2 0.03% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.01% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 3 0.04% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 2 0.03% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 4 0.06% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 3 0.04% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 4 0.06% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.03% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 1 0.01% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 2 0.03% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 1 0.01% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 8 0.11% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 1 0.01% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 1 0.01% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 2 0.03% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 4 0.06% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 2 0.03% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 13 0.18% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 13 0.18% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7169 # Writes before turning the bus around for reads -system.physmem.totQLat 8930594750 # Total ticks spent queuing -system.physmem.totMemAccLat 17382363500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2253805000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19812.26 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 7192 # Writes before turning the bus around for reads +system.physmem.totQLat 9007685000 # Total ticks spent queuing +system.physmem.totMemAccLat 17475691250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2258135000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19944.97 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38562.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38694.97 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.12 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.86 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.90 # Average write queue length when enqueuing -system.physmem.readRowHits 407659 # Number of row buffer hits during reads -system.physmem.writeRowHits 98604 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.73 # Row buffer hit rate for writes -system.physmem.avgGap 3325500.37 # Average gap between requests -system.physmem.pageHitRate 88.37 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1804524317000 # Time in different power states -system.physmem.memoryStateTime::REF 63633700000 # Time in different power states +system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.04 # Average write queue length when enqueuing +system.physmem.readRowHits 408104 # Number of row buffer hits during reads +system.physmem.writeRowHits 99226 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.92 # Row buffer hit rate for writes +system.physmem.avgGap 3318713.65 # Average gap between requests +system.physmem.pageHitRate 88.35 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1805036475500 # Time in different power states +system.physmem.memoryStateTime::REF 63652420000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37488657000 # Time in different power states +system.physmem.memoryStateTime::ACT 37517744500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 19303809 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296468 # Transaction distribution -system.membus.trans_dist::ReadResp 296393 # Transaction distribution -system.membus.trans_dist::WriteReq 13039 # Transaction distribution -system.membus.trans_dist::WriteResp 13039 # Transaction distribution -system.membus.trans_dist::Writeback 122139 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9699 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5540 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4861 # Transaction distribution -system.membus.trans_dist::ReadExReq 162690 # Transaction distribution -system.membus.trans_dist::ReadExResp 162297 # Transaction distribution -system.membus.trans_dist::BadAddressError 75 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40466 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 920381 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 150 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 960997 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1085644 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73690 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31367808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31441498 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5306880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36748378 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36748378 # Total data (bytes) -system.membus.snoop_data_through_bus 37952 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 37884500 # Layer occupancy (ticks) +system.membus.throughput 19340215 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296416 # Transaction distribution +system.membus.trans_dist::ReadResp 296338 # Transaction distribution +system.membus.trans_dist::WriteReq 12317 # Transaction distribution +system.membus.trans_dist::WriteResp 12317 # Transaction distribution +system.membus.trans_dist::Writeback 122625 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1033 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3220 # Transaction distribution +system.membus.trans_dist::ReadExReq 163308 # Transaction distribution +system.membus.trans_dist::ReadExResp 163210 # Transaction distribution +system.membus.trans_dist::BadAddressError 78 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39026 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 910934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 950116 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1074769 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 67930 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31453376 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31521306 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306944 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5306944 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36828250 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36828250 # Total data (bytes) +system.membus.snoop_data_through_bus 38208 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 36079499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1609423248 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1585687750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 94500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 97000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3824980631 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3823460772 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376652994 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376710991 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 343977 # number of replacements -system.l2c.tags.tagsinuse 65252.773158 # Cycle average of tags in use -system.l2c.tags.total_refs 2582565 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 408968 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.314834 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7103141750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53523.190376 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5304.878115 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6147.677864 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 207.477812 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 69.548991 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.816699 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080946 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.093806 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003166 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001061 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995678 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64991 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 227 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 3387 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 4556 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4338 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52483 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.991684 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27108862 # Number of tag accesses -system.l2c.tags.data_accesses 27108862 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 867616 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 736617 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 210128 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 67910 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1882271 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 822208 # number of Writeback hits -system.l2c.Writeback_hits::total 822208 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 261 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 430 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 49 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 73 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 154436 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 25581 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 180017 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 867616 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 891053 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 210128 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 93491 # number of demand (read+write) hits -system.l2c.demand_hits::total 2062288 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 867616 # number of overall hits -system.l2c.overall_hits::cpu0.data 891053 # number of overall hits -system.l2c.overall_hits::cpu1.inst 210128 # number of overall hits -system.l2c.overall_hits::cpu1.data 93491 # number of overall hits -system.l2c.overall_hits::total 2062288 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 14035 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273392 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1238 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 452 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289117 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2673 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1056 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3729 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 406 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 434 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 840 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114695 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6342 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121037 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 14035 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 388087 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1238 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6794 # number of demand (read+write) misses -system.l2c.demand_misses::total 410154 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 14035 # number of overall misses -system.l2c.overall_misses::cpu0.data 388087 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1238 # number of overall misses -system.l2c.overall_misses::cpu1.data 6794 # number of overall misses -system.l2c.overall_misses::total 410154 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1067454245 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17881620237 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 96862500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 35356999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 19081293981 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 964468 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 4567794 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 5532262 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 972461 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 114995 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1087456 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9393947733 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 639497214 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10033444947 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1067454245 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 27275567970 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 96862500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 674854213 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 29114738928 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1067454245 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 27275567970 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 96862500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 674854213 # number of overall miss cycles -system.l2c.overall_miss_latency::total 29114738928 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 881651 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1010009 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 211366 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 68362 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2171388 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 822208 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 822208 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2842 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1317 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4159 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 455 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 458 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 913 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 269131 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 31923 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 301054 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 881651 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1279140 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 211366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 100285 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2472442 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 881651 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1279140 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 211366 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 100285 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2472442 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015919 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.270683 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005857 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.006612 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.133148 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940535 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.801822 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.896610 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.892308 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.947598 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.920044 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.426168 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.198666 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.402044 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015919 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.303397 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005857 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.067747 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.165890 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015919 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.303397 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005857 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.067747 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.165890 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76056.590310 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 65406.523369 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78241.114701 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 78223.449115 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 65998.519565 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 360.818556 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4325.562500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1483.577903 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2395.224138 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 264.965438 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1294.590476 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81903.724949 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 100835.259224 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 82895.684353 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 76056.590310 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 70282.096463 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 78241.114701 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 99330.911540 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 70984.895742 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 76056.590310 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 70282.096463 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 78241.114701 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 99330.911540 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 70984.895742 # average overall miss latency +system.l2c.tags.replacements 344852 # number of replacements +system.l2c.tags.tagsinuse 65305.335131 # Cycle average of tags in use +system.l2c.tags.total_refs 2605080 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 409986 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.354071 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7095487750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 53708.677879 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5228.517850 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6139.451939 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 202.418952 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 26.268512 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.819529 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079781 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.093681 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003089 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000401 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996480 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65134 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 2578 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5246 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6338 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 50733 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.993866 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 27313168 # Number of tag accesses +system.l2c.tags.data_accesses 27313168 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 979450 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 788527 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 94097 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 31413 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1893487 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 833565 # number of Writeback hits +system.l2c.Writeback_hits::total 833565 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 46 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 221 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 27 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 47 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 175693 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 7721 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183414 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 979450 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 964220 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 94097 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 39134 # number of demand (read+write) hits +system.l2c.demand_hits::total 2076901 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 979450 # number of overall hits +system.l2c.overall_hits::cpu0.data 964220 # number of overall hits +system.l2c.overall_hits::cpu1.inst 94097 # number of overall hits +system.l2c.overall_hits::cpu1.data 39134 # number of overall hits +system.l2c.overall_hits::total 2076901 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 14127 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 273418 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1173 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 340 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289058 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 511 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2953 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 34 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 76 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 110 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 116199 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 5616 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 121815 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 14127 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 389617 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1173 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 5956 # number of demand (read+write) misses +system.l2c.demand_misses::total 410873 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 14127 # number of overall misses +system.l2c.overall_misses::cpu0.data 389617 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1173 # number of overall misses +system.l2c.overall_misses::cpu1.data 5956 # number of overall misses +system.l2c.overall_misses::total 410873 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 1071252992 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 17895085485 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 90289500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 26594999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 19083222976 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1079964 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 402483 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1482447 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 116495 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 68997 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 185492 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 9654052371 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 606648221 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10260700592 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1071252992 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 27549137856 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 90289500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 633243220 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 29343923568 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1071252992 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 27549137856 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 90289500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 633243220 # number of overall miss cycles +system.l2c.overall_miss_latency::total 29343923568 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 993577 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1061945 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 95270 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 31753 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2182545 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 833565 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 833565 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2617 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 557 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3174 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 61 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 96 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 157 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 291892 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 13337 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 305229 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 993577 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1353837 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 95270 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 45090 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2487774 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 993577 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1353837 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 95270 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 45090 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2487774 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014218 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.257469 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.012312 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.010708 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.132441 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933130 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.917415 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.930372 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.557377 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.791667 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.700637 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.398089 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.421084 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.399094 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014218 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.287787 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.012312 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.132091 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.165157 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014218 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.287787 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.012312 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.132091 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.165157 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 75830.182771 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 65449.551547 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76973.145780 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 78220.585294 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 66018.663991 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 442.245700 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 787.637965 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 502.013884 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3426.323529 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 907.855263 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1686.290909 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83082.060698 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108021.406873 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 84231.831811 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 75830.182771 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 70708.254147 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 76973.145780 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 106320.218267 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 71418.476191 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 75830.182771 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 70708.254147 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 76973.145780 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 106320.218267 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 71418.476191 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,8 +519,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80619 # number of writebacks -system.l2c.writebacks::total 80619 # number of writebacks +system.l2c.writebacks::writebacks 81105 # number of writebacks +system.l2c.writebacks::total 81105 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits @@ -532,111 +533,111 @@ system.l2c.overall_mshr_hits::cpu0.inst 9 # nu system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 14026 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 273392 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1230 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 451 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 289099 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2673 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1056 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3729 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 406 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 434 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 840 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 114695 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 6342 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 121037 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 14026 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 388087 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1230 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 6793 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 410136 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 14026 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 388087 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1230 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 6793 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 410136 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 890067005 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14473617763 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 80840000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 29712501 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15474237269 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 26950129 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 10569046 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 37519175 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 4153902 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4341434 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 8495336 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7989750261 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 560973786 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8550724047 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 890067005 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 22463368024 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 80840000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 590686287 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 24024961316 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 890067005 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 22463368024 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 80840000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 590686287 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 24024961316 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1367392500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 22035500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1389428000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2022747000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 583651500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2606398500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3390139500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 605687000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3995826500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015909 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.270683 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005819 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006597 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.133140 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940535 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.801822 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.896610 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.892308 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.947598 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.920044 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.426168 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.198666 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.402044 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015909 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.303397 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005819 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.067737 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.165883 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015909 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.303397 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005819 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.067737 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.165883 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63458.363397 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52940.897184 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65723.577236 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65881.376940 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 53525.737789 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10082.352787 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.566288 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10061.457495 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10231.285714 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.304147 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10113.495238 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69660.841894 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 88453.766320 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 70645.538530 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63458.363397 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57882.299649 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65723.577236 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86955.143088 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 58578.035861 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63458.363397 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57882.299649 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65723.577236 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86955.143088 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 58578.035861 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 14118 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 273418 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1165 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 339 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289040 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2442 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 511 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2953 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 34 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 76 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 110 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 116199 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 5616 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 121815 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 14118 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 389617 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1165 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 5955 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 410855 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 14118 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 389617 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1165 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 5955 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 410855 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 892690758 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14487194015 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 75058500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 22318999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15477262272 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 24607428 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5172008 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 29779436 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 340034 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 768576 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 1108610 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8237283129 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 537421779 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8774704908 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 892690758 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 22724477144 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 75058500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 559740778 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 24251967180 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 892690758 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 22724477144 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 75058500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 559740778 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 24251967180 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1368893000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 20915000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1389808000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1950614000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 503814500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2454428500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3319507000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 524729500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3844236500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014209 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.257469 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012228 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.010676 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.132433 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933130 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.917415 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.930372 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.557377 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.791667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.700637 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.398089 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.421084 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.399094 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014209 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.287787 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012228 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.132069 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.165150 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014209 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.287787 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012228 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.132069 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.165150 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63230.681258 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52985.516736 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64427.896996 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65837.755162 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 53547.129366 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10076.751843 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10121.346380 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10084.468676 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10112.842105 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.272727 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70889.449384 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 95694.761218 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72033.041153 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63230.681258 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58325.168419 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64427.896996 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93995.092863 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59028.044395 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63230.681258 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58325.168419 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64427.896996 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93995.092863 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59028.044395 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -647,44 +648,44 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.491978 # Cycle average of tags in use +system.iocache.tags.replacements 41700 # number of replacements +system.iocache.tags.tagsinuse 0.491390 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41716 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1712295759000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.491978 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.030749 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.030749 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1711322153000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.491390 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.030712 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.030712 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375543 # Number of tag accesses -system.iocache.tags.data_accesses 375543 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.tags.tag_accesses 375588 # Number of tag accesses +system.iocache.tags.data_accesses 375588 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 180 # number of ReadReq misses +system.iocache.ReadReq_misses::total 180 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21492883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21492883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12499299192 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12499299192 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12520792075 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12520792075 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12520792075 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12520792075 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41732 # number of demand (read+write) misses +system.iocache.demand_misses::total 41732 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41732 # number of overall misses +system.iocache.overall_misses::total 41732 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22063883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22063883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12446165943 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12446165943 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 12468229826 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12468229826 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 12468229826 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12468229826 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 180 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 180 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41732 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41732 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41732 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41732 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -693,40 +694,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122816.474286 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122816.474286 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 300811.012514 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 300811.012514 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 300064.516380 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 300064.516380 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 300064.516380 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 300064.516380 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 367481 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122577.127778 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122577.127778 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299532.295509 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 299532.295509 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 298769.045960 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 298769.045960 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 298769.045960 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 298769.045960 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 366756 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28552 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28394 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.870587 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.916673 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 180 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 180 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12390883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12390883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10336377204 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10336377204 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10348768087 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10348768087 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10348768087 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10348768087 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41732 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41732 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41732 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41732 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12701883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12701883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10283217961 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10283217961 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10295919844 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10295919844 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10295919844 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10295919844 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -735,14 +736,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70805.045714 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70805.045714 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 248757.633905 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 248757.633905 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 248011.313706 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 248011.313706 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70566.016667 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70566.016667 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247478.291322 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 247478.291322 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246715.226780 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 246715.226780 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246715.226780 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 246715.226780 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -756,35 +757,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 12477942 # Number of BP lookups -system.cpu0.branchPred.condPredicted 10513633 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 331474 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8127728 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5283638 # Number of BTB hits +system.cpu0.branchPred.lookups 13535285 # Number of BP lookups +system.cpu0.branchPred.condPredicted 11399113 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 368683 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 9302001 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5741441 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 65.007564 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 797741 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28790 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 61.722644 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 871515 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 32576 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8879185 # DTB read hits -system.cpu0.dtb.read_misses 30734 # DTB read misses -system.cpu0.dtb.read_acv 556 # DTB read access violations -system.cpu0.dtb.read_accesses 627584 # DTB read accesses -system.cpu0.dtb.write_hits 5815647 # DTB write hits -system.cpu0.dtb.write_misses 8173 # DTB write misses -system.cpu0.dtb.write_acv 357 # DTB write access violations -system.cpu0.dtb.write_accesses 210225 # DTB write accesses -system.cpu0.dtb.data_hits 14694832 # DTB hits -system.cpu0.dtb.data_misses 38907 # DTB misses -system.cpu0.dtb.data_acv 913 # DTB access violations -system.cpu0.dtb.data_accesses 837809 # DTB accesses -system.cpu0.itb.fetch_hits 998260 # ITB hits -system.cpu0.itb.fetch_misses 27519 # ITB misses -system.cpu0.itb.fetch_acv 894 # ITB acv -system.cpu0.itb.fetch_accesses 1025779 # ITB accesses +system.cpu0.dtb.read_hits 9655924 # DTB read hits +system.cpu0.dtb.read_misses 34371 # DTB read misses +system.cpu0.dtb.read_acv 569 # DTB read access violations +system.cpu0.dtb.read_accesses 673777 # DTB read accesses +system.cpu0.dtb.write_hits 6329246 # DTB write hits +system.cpu0.dtb.write_misses 8477 # DTB write misses +system.cpu0.dtb.write_acv 351 # DTB write access violations +system.cpu0.dtb.write_accesses 236111 # DTB write accesses +system.cpu0.dtb.data_hits 15985170 # DTB hits +system.cpu0.dtb.data_misses 42848 # DTB misses +system.cpu0.dtb.data_acv 920 # DTB access violations +system.cpu0.dtb.data_accesses 909888 # DTB accesses +system.cpu0.itb.fetch_hits 1092484 # ITB hits +system.cpu0.itb.fetch_misses 31809 # ITB misses +system.cpu0.itb.fetch_acv 996 # ITB acv +system.cpu0.itb.fetch_accesses 1124293 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -797,303 +798,304 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 116074371 # number of cpu cycles simulated +system.cpu0.numCycles 120980731 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25123779 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 63882467 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 12477942 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6081379 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 12010156 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1699076 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 37307525 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 31946 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 195411 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 352959 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 191 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7722540 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 223615 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 76113904 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.839301 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.177052 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 27854466 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 69491073 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 13535285 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6612956 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 12980522 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1985487 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 37586938 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31052 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 209286 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 361146 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 209 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8301805 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 269407 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 80329317 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.865077 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.209142 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 64103748 84.22% 84.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 767865 1.01% 85.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1567652 2.06% 87.29% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 704812 0.93% 88.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2586726 3.40% 91.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 521075 0.68% 92.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 575522 0.76% 93.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 832581 1.09% 94.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4453923 5.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67348795 83.84% 83.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 826622 1.03% 84.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1640547 2.04% 86.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 764329 0.95% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2736993 3.41% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 565546 0.70% 91.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 615994 0.77% 92.74% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1025224 1.28% 94.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4805267 5.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 76113904 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.107500 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.550358 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26378411 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 36826325 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10921760 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 930988 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1056419 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 512680 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35852 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62713959 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 107463 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1056419 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27400432 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 14971568 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 18343259 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10229394 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4112830 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59339079 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7155 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 639099 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1437135 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 39727133 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72236857 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72098194 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 129082 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34929896 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4797229 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1458801 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 212309 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11241570 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9288070 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6084553 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1139915 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 737819 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 52640864 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1816659 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 51478960 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 92665 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5869250 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3045578 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1230018 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 76113904 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.676341 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.327493 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 80329317 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.111880 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.574398 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 28693302 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 37589637 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 12241193 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 539176 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1266008 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 554913 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 40031 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 68046301 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 123637 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1266008 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 29596220 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 13874520 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 19704370 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 11366279 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4521918 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 64294985 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 8881 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 963704 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 49626 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 1581472 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 42969329 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 77993479 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 77835647 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 147432 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36982529 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 5986792 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1597094 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 233553 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 9775023 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10212119 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6719453 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1264075 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 886942 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 56810323 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 2002217 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 55156303 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 107150 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 7195907 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 4115621 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1359252 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 80329317 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.686627 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.367653 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 53257398 69.97% 69.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10376788 13.63% 83.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4704231 6.18% 89.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3091331 4.06% 93.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2445214 3.21% 97.06% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1217468 1.60% 98.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 651050 0.86% 99.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 318171 0.42% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52253 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 56644741 70.52% 70.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10637349 13.24% 83.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4503428 5.61% 89.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3111745 3.87% 93.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2708967 3.37% 96.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1473067 1.83% 98.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 832512 1.04% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 359476 0.45% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 58032 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 76113904 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 80329317 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 82049 12.02% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 319124 46.77% 58.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 281213 41.21% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 91428 11.87% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 367704 47.76% 59.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 310812 40.37% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35464091 68.89% 68.90% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56550 0.11% 69.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.01% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 15746 0.03% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.04% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9235082 17.94% 86.98% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5882526 11.43% 98.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 819301 1.59% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3793 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 37662855 68.28% 68.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 60369 0.11% 68.40% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.40% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 16864 0.03% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 10116560 18.34% 86.78% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6398898 11.60% 98.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 895081 1.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 51478960 # Type of FU issued -system.cpu0.iq.rate 0.443500 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 682386 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013256 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 179291609 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60070073 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50439032 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 555265 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 269219 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 261959 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 51867113 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 290448 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 544569 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 55156303 # Type of FU issued +system.cpu0.iq.rate 0.455910 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 769944 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013959 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 190884663 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 65713674 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 53746277 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 634353 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 307759 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 299045 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 55590646 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 331808 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 587688 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1116578 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3845 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 12782 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 445374 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1466473 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4362 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13302 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 593267 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18457 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 142389 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18777 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 290466 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1056419 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 10732956 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 797506 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 57687159 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 618379 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9288070 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6084553 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1600267 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 582946 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5458 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 12782 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 164537 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 351989 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 516526 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51092894 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8933351 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 386065 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1266008 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 10034082 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1132931 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 62323042 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 565721 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10212119 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6719453 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1762676 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 460962 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 503945 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13302 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 186944 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 388547 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 575491 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 54610252 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9715916 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 546050 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3229636 # number of nop insts executed -system.cpu0.iew.exec_refs 14770817 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8136394 # Number of branches executed -system.cpu0.iew.exec_stores 5837466 # Number of stores executed -system.cpu0.iew.exec_rate 0.440174 # Inst execution rate -system.cpu0.iew.wb_sent 50791046 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 50700991 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25278333 # num instructions producing a value -system.cpu0.iew.wb_consumers 34060542 # num instructions consuming a value +system.cpu0.iew.exec_nop 3510502 # number of nop insts executed +system.cpu0.iew.exec_refs 16068148 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8653897 # Number of branches executed +system.cpu0.iew.exec_stores 6352232 # Number of stores executed +system.cpu0.iew.exec_rate 0.451396 # Inst execution rate +system.cpu0.iew.wb_sent 54145867 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 54045322 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 27468175 # num instructions producing a value +system.cpu0.iew.wb_consumers 37895992 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.436797 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.742159 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.446727 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.724831 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6334928 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 586641 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 480870 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75057485 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.682787 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.597640 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 7798809 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 642965 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 531823 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 79063309 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.688507 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.631609 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 55774455 74.31% 74.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 8026658 10.69% 85.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 4417430 5.89% 90.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2392691 3.19% 94.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1323184 1.76% 95.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 562724 0.75% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 473653 0.63% 97.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 433129 0.58% 97.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1653561 2.20% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 59272342 74.97% 74.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 8075780 10.21% 85.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4311536 5.45% 90.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2381088 3.01% 93.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1583020 2.00% 95.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 598155 0.76% 96.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 490827 0.62% 97.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 478799 0.61% 97.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1871762 2.37% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75057485 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51248256 # Number of instructions committed -system.cpu0.commit.committedOps 51248256 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 79063309 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 54435622 # Number of instructions committed +system.cpu0.commit.committedOps 54435622 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13810671 # Number of memory references committed -system.cpu0.commit.loads 8171492 # Number of loads committed -system.cpu0.commit.membars 199624 # Number of memory barriers committed -system.cpu0.commit.branches 7741114 # Number of branches committed -system.cpu0.commit.fp_insts 259898 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47457125 # Number of committed integer instructions. -system.cpu0.commit.function_calls 657479 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2951389 5.76% 5.76% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 33388118 65.15% 70.91% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55525 0.11% 71.02% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.02% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 15746 0.03% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1879 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.05% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8371116 16.33% 87.39% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5645183 11.02% 98.40% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 819300 1.60% 100.00% # Class of committed instruction +system.cpu0.commit.refs 14871832 # Number of memory references committed +system.cpu0.commit.loads 8745646 # Number of loads committed +system.cpu0.commit.membars 219982 # Number of memory barriers committed +system.cpu0.commit.branches 8204799 # Number of branches committed +system.cpu0.commit.fp_insts 296843 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 50375539 # Number of committed integer instructions. +system.cpu0.commit.function_calls 712916 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 3148922 5.78% 5.78% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 35215746 64.69% 70.48% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 59292 0.11% 70.59% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.59% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 16864 0.03% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.62% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8965628 16.47% 87.09% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 6132206 11.27% 98.36% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 895081 1.64% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51248256 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1653561 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 54435622 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1871762 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 130790454 # The number of ROB reads -system.cpu0.rob.rob_writes 116222813 # The number of ROB writes -system.cpu0.timesIdled 1101169 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 39960467 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3695221845 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48300626 # Number of Instructions Simulated -system.cpu0.committedOps 48300626 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.403165 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.403165 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.416118 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.416118 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67219449 # number of integer regfile reads -system.cpu0.int_regfile_writes 36695614 # number of integer regfile writes -system.cpu0.fp_regfile_reads 128632 # number of floating regfile reads -system.cpu0.fp_regfile_writes 130173 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1801385 # number of misc regfile reads -system.cpu0.misc_regfile_writes 820377 # number of misc regfile writes +system.cpu0.rob.rob_reads 139225703 # The number of ROB reads +system.cpu0.rob.rob_writes 125735253 # The number of ROB writes +system.cpu0.timesIdled 1168278 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 40651414 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3691427340 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 51290467 # Number of Instructions Simulated +system.cpu0.committedOps 51290467 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.358737 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.358737 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.423956 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.423956 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 71570668 # number of integer regfile reads +system.cpu0.int_regfile_writes 39014056 # number of integer regfile writes +system.cpu0.fp_regfile_reads 147010 # number of floating regfile reads +system.cpu0.fp_regfile_writes 148900 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1947197 # number of misc regfile reads +system.cpu0.misc_regfile_writes 897129 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1125,49 +1127,49 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 111416521 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2199115 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2199023 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13039 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13039 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 822208 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 9837 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5613 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 15450 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 343877 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302328 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 75 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1763397 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369225 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 422759 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 294489 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5849870 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56425664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130205428 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13527424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10778278 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 210936794 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 210926490 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 1394560 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4971595549 # Layer occupancy (ticks) +system.toL2Bus.throughput 111935595 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2200566 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2200471 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12317 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12317 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 833565 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 4571 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1080 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 5651 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 347592 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 306043 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1987262 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3563495 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 190571 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 127415 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5868743 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63588928 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 138451052 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 6097280 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4501998 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 212639258 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 212628634 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 743808 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5019455896 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 747000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3972568555 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4476579522 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5889953047 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 6206391842 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 951834487 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 429200431 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 507907991 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 227242208 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1435370 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7369 # Transaction distribution -system.iobus.trans_dist::ReadResp 7369 # Transaction distribution -system.iobus.trans_dist::WriteReq 54591 # Transaction distribution -system.iobus.trans_dist::WriteResp 54591 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11870 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1431950 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7376 # Transaction distribution +system.iobus.trans_dist::ReadResp 7376 # Transaction distribution +system.iobus.trans_dist::WriteReq 53869 # Transaction distribution +system.iobus.trans_dist::WriteResp 53869 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10422 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1178,12 +1180,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123920 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47480 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39026 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83464 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83464 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122490 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41688 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1194,14 +1196,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 73690 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2735314 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2735314 # Total data (bytes) -system.iobus.reqLayer0.occupancy 11225000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 67930 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2729594 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2729594 # Total data (bytes) +system.iobus.reqLayer0.occupancy 9777000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1221,268 +1223,267 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380163081 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380161835 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27427000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26709000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43193006 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43245009 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 881127 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.683312 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6795719 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 881636 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.708078 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26872936250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.683312 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995475 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995475 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 417 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 8604286 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 8604286 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6795719 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6795719 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6795719 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6795719 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6795719 # number of overall hits -system.cpu0.icache.overall_hits::total 6795719 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 926821 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 926821 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 926821 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 926821 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 926821 # number of overall misses -system.cpu0.icache.overall_misses::total 926821 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13137729759 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13137729759 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13137729759 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13137729759 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13137729759 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13137729759 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7722540 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7722540 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7722540 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7722540 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7722540 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7722540 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.120015 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.120015 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.120015 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.120015 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.120015 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.120015 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14175.045407 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14175.045407 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14175.045407 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14175.045407 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14175.045407 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3568 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 70 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 151 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.629139 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked +system.cpu0.icache.tags.replacements 993039 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.694749 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7257459 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 993551 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.304566 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26718502250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.694749 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995498 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995498 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 9295490 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9295490 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7257459 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7257459 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7257459 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7257459 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7257459 # number of overall hits +system.cpu0.icache.overall_hits::total 7257459 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1044346 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1044346 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1044346 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1044346 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1044346 # number of overall misses +system.cpu0.icache.overall_misses::total 1044346 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14667970749 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14667970749 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14667970749 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14667970749 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14667970749 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14667970749 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8301805 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8301805 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8301805 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8301805 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8301805 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8301805 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125797 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.125797 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125797 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.125797 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125797 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.125797 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14045.125609 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14045.125609 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14045.125609 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14045.125609 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14045.125609 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14045.125609 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4303 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 182 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.642857 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45075 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 45075 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 45075 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 45075 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 45075 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 45075 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 881746 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 881746 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 881746 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 881746 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 881746 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 881746 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10814665187 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10814665187 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10814665187 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10814665187 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10814665187 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10814665187 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.114178 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.114178 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.114178 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.114178 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12265.057269 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12265.057269 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12265.057269 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 50661 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 50661 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 50661 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 50661 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 50661 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 50661 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 993685 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 993685 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 993685 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 993685 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 993685 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 993685 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12074149969 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12074149969 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12074149969 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12074149969 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12074149969 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12074149969 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.119695 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.119695 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.119695 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.119695 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12150.882794 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12150.882794 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12150.882794 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12150.882794 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1281204 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.636705 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10489009 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1281716 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.183567 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 26139000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.636705 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.987572 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.987572 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 1357625 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.932074 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11305784 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1358137 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.324480 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 25366000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.932074 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990102 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.990102 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56677841 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56677841 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6448265 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6448265 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3678309 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3678309 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 163487 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 163487 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 188240 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 188240 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10126574 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10126574 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10126574 # number of overall hits -system.cpu0.dcache.overall_hits::total 10126574 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1590441 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1590441 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1755180 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1755180 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20486 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20486 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2716 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2716 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3345621 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3345621 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3345621 # number of overall misses -system.cpu0.dcache.overall_misses::total 3345621 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40624107085 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 40624107085 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 78713383276 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 78713383276 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 300049994 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 300049994 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20153405 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 20153405 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 119337490361 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 119337490361 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 119337490361 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 119337490361 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8038706 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8038706 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5433489 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5433489 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183973 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183973 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190956 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 190956 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13472195 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13472195 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13472195 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13472195 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197848 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197848 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323030 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323030 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.111353 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.111353 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014223 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014223 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248335 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248335 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248335 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248335 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25542.668408 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25542.668408 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44846.331018 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44846.331018 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14646.587621 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14646.587621 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7420.252209 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7420.252209 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35669.757681 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35669.757681 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35669.757681 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2966485 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 566 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 48680 # number of cycles access was blocked +system.cpu0.dcache.tags.tag_accesses 61088591 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 61088591 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6897589 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6897589 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4012977 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4012977 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 181053 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 181053 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 208423 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 208423 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10910566 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10910566 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10910566 # number of overall hits +system.cpu0.dcache.overall_hits::total 10910566 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1718976 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1718976 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1889613 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1889613 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22934 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22934 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 507 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 507 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3608589 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3608589 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3608589 # number of overall misses +system.cpu0.dcache.overall_misses::total 3608589 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42674970043 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 42674970043 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 81294445080 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 81294445080 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 374188245 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 374188245 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3007034 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3007034 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 123969415123 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 123969415123 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 123969415123 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 123969415123 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8616565 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8616565 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5902590 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5902590 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 203987 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203987 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 208930 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 208930 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14519155 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14519155 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14519155 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14519155 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.199497 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.199497 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.320133 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.320133 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112429 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112429 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002427 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002427 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248540 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.248540 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248540 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.248540 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24825.809111 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 24825.809111 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43021.743119 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43021.743119 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16315.873594 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16315.873594 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5931.033531 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5931.033531 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34353.985761 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34353.985761 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34353.985761 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34353.985761 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 3433420 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 538 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 116463 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.938476 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 80.857143 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 29.480779 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 76.857143 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 754427 # number of writebacks -system.cpu0.dcache.writebacks::total 754427 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 586151 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 586151 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1480465 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1480465 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4562 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4562 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2066616 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2066616 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2066616 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2066616 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1004290 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1004290 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 274715 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 274715 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15924 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15924 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2716 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2716 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1279005 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1279005 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1279005 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1279005 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27273016452 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27273016452 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11562486348 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11562486348 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 175781505 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 175781505 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14720595 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14720595 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38835502800 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38835502800 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38835502800 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38835502800 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459363000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459363000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2145424499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2145424499 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3604787499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3604787499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.124932 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.124932 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050560 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050560 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086556 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086556 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014223 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014223 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094937 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094937 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094937 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27156.515003 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27156.515003 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42089.024436 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42089.024436 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11038.778259 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11038.778259 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5419.953976 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5419.953976 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30363.839704 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30363.839704 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 808609 # number of writebacks +system.cpu0.dcache.writebacks::total 808609 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 667238 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 667238 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1594728 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1594728 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5762 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5762 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2261966 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2261966 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2261966 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2261966 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1051738 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1051738 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 294885 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 294885 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 17172 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 17172 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 507 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 507 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1346623 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1346623 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1346623 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1346623 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27880739944 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27880739944 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12002536573 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12002536573 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 202887753 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 202887753 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1992966 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1992966 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 39883276517 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 39883276517 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 39883276517 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 39883276517 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1460997001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1460997001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2069284998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2069284998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3530281999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3530281999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122060 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122060 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049959 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049959 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.084182 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.084182 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002427 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002427 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092748 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092748 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092748 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092748 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26509.206612 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26509.206612 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40702.431704 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40702.431704 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.033368 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.033368 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3930.899408 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3930.899408 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29617.254805 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29617.254805 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29617.254805 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29617.254805 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1490,35 +1491,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 2485884 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2055798 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 72106 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1444173 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 831190 # Number of BTB hits +system.cpu1.branchPred.lookups 1483279 # Number of BP lookups +system.cpu1.branchPred.condPredicted 1227619 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 44770 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 650934 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 463612 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 57.554739 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 170291 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7410 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 71.222582 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 99211 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 4550 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1846757 # DTB read hits -system.cpu1.dtb.read_misses 10485 # DTB read misses -system.cpu1.dtb.read_acv 25 # DTB read access violations -system.cpu1.dtb.read_accesses 320297 # DTB read accesses -system.cpu1.dtb.write_hits 1188866 # DTB write hits -system.cpu1.dtb.write_misses 1998 # DTB write misses -system.cpu1.dtb.write_acv 67 # DTB write access violations -system.cpu1.dtb.write_accesses 130212 # DTB write accesses -system.cpu1.dtb.data_hits 3035623 # DTB hits -system.cpu1.dtb.data_misses 12483 # DTB misses -system.cpu1.dtb.data_acv 92 # DTB access violations -system.cpu1.dtb.data_accesses 450509 # DTB accesses -system.cpu1.itb.fetch_hits 420713 # ITB hits -system.cpu1.itb.fetch_misses 6600 # ITB misses -system.cpu1.itb.fetch_acv 223 # ITB acv -system.cpu1.itb.fetch_accesses 427313 # ITB accesses +system.cpu1.dtb.read_hits 1187167 # DTB read hits +system.cpu1.dtb.read_misses 8989 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 276351 # DTB read accesses +system.cpu1.dtb.write_hits 628916 # DTB write hits +system.cpu1.dtb.write_misses 1890 # DTB write misses +system.cpu1.dtb.write_acv 35 # DTB write access violations +system.cpu1.dtb.write_accesses 104365 # DTB write accesses +system.cpu1.dtb.data_hits 1816083 # DTB hits +system.cpu1.dtb.data_misses 10879 # DTB misses +system.cpu1.dtb.data_acv 41 # DTB access violations +system.cpu1.dtb.data_accesses 380716 # DTB accesses +system.cpu1.itb.fetch_hits 316911 # ITB hits +system.cpu1.itb.fetch_misses 5517 # ITB misses +system.cpu1.itb.fetch_acv 125 # ITB acv +system.cpu1.itb.fetch_accesses 322428 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1531,552 +1532,553 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 14964653 # number of cpu cycles simulated +system.cpu1.numCycles 8637240 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5680448 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 11756636 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 2485884 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1001481 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 2105616 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 381271 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 5937724 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 25803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 62153 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 48156 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1420733 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 48517 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14103634 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.833589 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.209447 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 2818807 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 7093634 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 1483279 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 562823 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 1271731 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 278690 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 3719491 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 23500 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 54196 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 48363 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 894062 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 29430 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 8117811 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.873836 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.252237 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 11998018 85.07% 85.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 134082 0.95% 86.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 225201 1.60% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 169062 1.20% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 292225 2.07% 90.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 115066 0.82% 91.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 124219 0.88% 92.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 190666 1.35% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 855095 6.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 6846080 84.33% 84.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 64163 0.79% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 148479 1.83% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 110798 1.36% 88.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 183312 2.26% 90.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 76211 0.94% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 83539 1.03% 92.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 57250 0.71% 93.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 547979 6.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14103634 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.166117 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.785627 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5621005 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6169812 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1969307 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 106628 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 236881 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 108171 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 6940 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 11535490 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 20476 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 236881 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5819966 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 414819 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5141752 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1873919 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 616295 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10688130 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 72 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 55241 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 150444 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 7038513 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12788456 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 12730882 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 51827 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5999158 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1039355 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 430985 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 39680 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1897434 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1953635 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1261748 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 176061 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 98445 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9382355 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 465021 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9121330 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 28823 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1378008 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 697882 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 334259 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14103634 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.646736 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.322598 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 8117811 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.171731 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.821285 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 2872853 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 3821739 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1206360 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 38891 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 177967 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 63499 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 3800 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 6911640 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 11536 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 177967 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 2981399 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 177384 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 3223332 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1138018 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 419709 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 6319378 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 203 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 45248 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 5428 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 135690 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 4267087 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 7667393 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 7641550 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 21648 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 3453234 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 813853 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 270338 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 17002 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1051064 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1262745 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 687524 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 118324 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 74010 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 5585108 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 271421 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 5341703 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 20645 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1049804 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 612834 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 207573 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 8117811 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.658023 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.347544 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10102268 71.63% 71.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1834449 13.01% 84.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 778460 5.52% 90.16% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 526095 3.73% 93.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 451675 3.20% 97.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 203961 1.45% 98.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 130101 0.92% 99.46% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 68435 0.49% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 8190 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 5813637 71.62% 71.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1034901 12.75% 84.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 447279 5.51% 89.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 322285 3.97% 93.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 244246 3.01% 96.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 126246 1.56% 98.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 72876 0.90% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 50809 0.63% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 5532 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14103634 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 8117811 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3122 1.64% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 102805 54.10% 55.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 84113 44.26% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 4295 3.26% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 3.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 76591 58.14% 61.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 50850 38.60% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5686452 62.34% 62.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 15839 0.17% 62.55% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.55% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10725 0.12% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.69% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1931464 21.18% 83.87% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1211908 13.29% 97.15% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 259653 2.85% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.07% 0.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 3268625 61.19% 61.26% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 9680 0.18% 61.44% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.44% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 8881 0.17% 61.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.03% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.64% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1232456 23.07% 84.71% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 646098 12.10% 96.80% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 170686 3.20% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9121330 # Type of FU issued -system.cpu1.iq.rate 0.609525 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 190040 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020835 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 32366807 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11130082 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8856102 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 198350 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 96900 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 93876 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9204439 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 103405 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 88797 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 5341703 # Type of FU issued +system.cpu1.iq.rate 0.618450 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 131736 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.024662 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 18885884 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 6873502 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 5132762 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 67714 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 33978 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 32480 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 5434957 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 34964 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 63957 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 277499 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1209 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 1676 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 126244 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 266370 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 353 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 1238 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 98626 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 334 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 13648 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 353 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 72939 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 236881 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 252351 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 39276 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10330457 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 142523 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1953635 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1261748 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 421576 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 32385 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1813 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 1676 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 32559 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 96048 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 128607 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9031900 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1864128 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 89430 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 177967 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 80772 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 78093 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 6077668 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 83087 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1262745 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 687524 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 253926 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4593 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 73335 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 1238 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 19913 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 60148 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 80061 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 5287979 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1198929 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 53724 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 483081 # number of nop insts executed -system.cpu1.iew.exec_refs 3060773 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1345265 # Number of branches executed -system.cpu1.iew.exec_stores 1196645 # Number of stores executed -system.cpu1.iew.exec_rate 0.603549 # Inst execution rate -system.cpu1.iew.wb_sent 8976284 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8949978 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4203498 # num instructions producing a value -system.cpu1.iew.wb_consumers 5915948 # num instructions consuming a value +system.cpu1.iew.exec_nop 221139 # number of nop insts executed +system.cpu1.iew.exec_refs 1832774 # number of memory reference insts executed +system.cpu1.iew.exec_branches 762873 # Number of branches executed +system.cpu1.iew.exec_stores 633845 # Number of stores executed +system.cpu1.iew.exec_rate 0.612230 # Inst execution rate +system.cpu1.iew.wb_sent 5189273 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 5165242 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 2532511 # num instructions producing a value +system.cpu1.iew.wb_consumers 3587094 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.598075 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.710537 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.598020 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.706006 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1403439 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 130762 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 120016 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 13866753 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.637072 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.578145 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1065222 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 63848 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 75650 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 7939844 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.623951 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.560784 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10553407 76.11% 76.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1550482 11.18% 87.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 573583 4.14% 91.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 351937 2.54% 93.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 252477 1.82% 95.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 99182 0.72% 96.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 104002 0.75% 97.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 102635 0.74% 97.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 279048 2.01% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 6043541 76.12% 76.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 925286 11.65% 87.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 320402 4.04% 91.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 190890 2.40% 94.21% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 129096 1.63% 95.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 57238 0.72% 96.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 65164 0.82% 97.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 44060 0.55% 97.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 164167 2.07% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 13866753 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8834118 # Number of instructions committed -system.cpu1.commit.committedOps 8834118 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 7939844 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 4954074 # Number of instructions committed +system.cpu1.commit.committedOps 4954074 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2811640 # Number of memory references committed -system.cpu1.commit.loads 1676136 # Number of loads committed -system.cpu1.commit.membars 41495 # Number of memory barriers committed -system.cpu1.commit.branches 1262292 # Number of branches committed -system.cpu1.commit.fp_insts 92546 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8189363 # Number of committed integer instructions. -system.cpu1.commit.function_calls 139415 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 427272 4.84% 4.84% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 5265448 59.60% 64.44% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 15610 0.18% 64.62% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.62% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 10725 0.12% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.74% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1763 0.02% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.76% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1717631 19.44% 84.20% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1136016 12.86% 97.06% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 259653 2.94% 100.00% # Class of committed instruction +system.cpu1.commit.refs 1585273 # Number of memory references committed +system.cpu1.commit.loads 996375 # Number of loads committed +system.cpu1.commit.membars 16576 # Number of memory barriers committed +system.cpu1.commit.branches 700739 # Number of branches committed +system.cpu1.commit.fp_insts 31280 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 4632533 # Number of committed integer instructions. +system.cpu1.commit.function_calls 77324 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 191990 3.88% 3.88% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 2969211 59.93% 63.81% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 9565 0.19% 64.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.00% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 8881 0.18% 64.18% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.18% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.18% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.18% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.04% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.22% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1012951 20.45% 84.66% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 589031 11.89% 96.55% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 170686 3.45% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 8834118 # Class of committed instruction -system.cpu1.commit.bw_lim_events 279048 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 4954074 # Class of committed instruction +system.cpu1.commit.bw_lim_events 164167 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 23736453 # The number of ROB reads -system.cpu1.rob.rob_writes 20710450 # The number of ROB writes -system.cpu1.timesIdled 126022 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 861019 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3795679739 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8410372 # Number of Instructions Simulated -system.cpu1.committedOps 8410372 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.779309 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.779309 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.562016 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.562016 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11653751 # number of integer regfile reads -system.cpu1.int_regfile_writes 6367365 # number of integer regfile writes -system.cpu1.fp_regfile_reads 51509 # number of floating regfile reads -system.cpu1.fp_regfile_writes 51143 # number of floating regfile writes -system.cpu1.misc_regfile_reads 926936 # number of misc regfile reads -system.cpu1.misc_regfile_writes 206554 # number of misc regfile writes -system.cpu1.icache.tags.replacements 210820 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.468430 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1201520 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 211332 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.685462 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1879665276250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.468430 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.918884 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.918884 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 13715407 # The number of ROB reads +system.cpu1.rob.rob_writes 12215098 # The number of ROB writes +system.cpu1.timesIdled 57372 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 519429 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3803095502 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 4765602 # Number of Instructions Simulated +system.cpu1.committedOps 4765602 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.812413 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.812413 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.551751 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.551751 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 6848640 # number of integer regfile reads +system.cpu1.int_regfile_writes 3746417 # number of integer regfile writes +system.cpu1.fp_regfile_reads 21244 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19994 # number of floating regfile writes +system.cpu1.misc_regfile_reads 693471 # number of misc regfile reads +system.cpu1.misc_regfile_writes 115172 # number of misc regfile writes +system.cpu1.icache.tags.replacements 94727 # number of replacements +system.cpu1.icache.tags.tagsinuse 453.369242 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 794363 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 95239 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 8.340732 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1880860642000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.369242 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885487 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.885487 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1632124 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1632124 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1201520 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1201520 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1201520 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1201520 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1201520 # number of overall hits -system.cpu1.icache.overall_hits::total 1201520 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 219211 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 219211 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 219211 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 219211 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 219211 # number of overall misses -system.cpu1.icache.overall_misses::total 219211 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2949137410 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2949137410 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2949137410 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2949137410 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2949137410 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2949137410 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1420731 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1420731 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1420731 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1420731 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1420731 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1420731 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.154295 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.154295 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.154295 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.154295 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.154295 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.154295 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13453.418898 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13453.418898 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13453.418898 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13453.418898 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13453.418898 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13453.418898 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 428 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 989361 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 989361 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 794363 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 794363 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 794363 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 794363 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 794363 # number of overall hits +system.cpu1.icache.overall_hits::total 794363 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 99697 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 99697 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 99697 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 99697 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 99697 # number of overall misses +system.cpu1.icache.overall_misses::total 99697 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1381976879 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1381976879 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1381976879 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1381976879 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1381976879 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1381976879 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 894060 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 894060 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 894060 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 894060 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 894060 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 894060 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.111510 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.111510 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.111510 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.111510 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.111510 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.111510 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13861.769953 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13861.769953 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13861.769953 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13861.769953 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13861.769953 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13861.769953 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 20.380952 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.217391 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7818 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 7818 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 7818 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 7818 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 7818 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 7818 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 211393 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 211393 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 211393 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 211393 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 211393 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 211393 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2447786762 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2447786762 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2447786762 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2447786762 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2447786762 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2447786762 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.148792 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.148792 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.148792 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.148792 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11579.317962 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11579.317962 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11579.317962 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 4396 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 4396 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 4396 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 4396 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 4396 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 4396 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 95301 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 95301 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 95301 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 95301 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 95301 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 95301 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1139734069 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1139734069 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1139734069 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1139734069 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1139734069 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1139734069 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.106594 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.106594 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.106594 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.106594 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11959.308601 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11959.308601 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11959.308601 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11959.308601 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 102235 # number of replacements -system.cpu1.dcache.tags.tagsinuse 491.253867 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2477501 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 102637 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.138478 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 45814117000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.253867 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.959480 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.959480 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 402 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 11642464 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 11642464 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1521331 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1521331 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 890954 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 890954 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 30283 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 30283 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29173 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 29173 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2412285 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2412285 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2412285 # number of overall hits -system.cpu1.dcache.overall_hits::total 2412285 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 196472 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 196472 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 206616 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 206616 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5011 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5011 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2898 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2898 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 403088 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 403088 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 403088 # number of overall misses -system.cpu1.dcache.overall_misses::total 403088 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2745758970 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2745758970 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6806020354 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 6806020354 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 50048997 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 50048997 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 21170434 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 21170434 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 9551779324 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 9551779324 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 9551779324 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 9551779324 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1717803 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1717803 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1097570 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1097570 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 35294 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 35294 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32071 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 32071 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2815373 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2815373 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2815373 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2815373 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114374 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.114374 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.188249 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.188249 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.141979 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.141979 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090362 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.090362 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.143174 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.143174 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.143174 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.143174 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13975.319486 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13975.319486 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32940.432270 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32940.432270 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9987.826182 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9987.826182 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7305.187716 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7305.187716 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23696.511243 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23696.511243 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23696.511243 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23696.511243 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 206242 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 45361 # number of replacements +system.cpu1.dcache.tags.tagsinuse 428.999436 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 1451630 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 45680 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 31.778240 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1880566804000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 428.999436 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.837890 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.837890 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.623047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 6609919 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 6609919 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 960992 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 960992 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 477143 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 477143 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 12504 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 12504 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 10799 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 10799 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1438135 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1438135 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1438135 # number of overall hits +system.cpu1.dcache.overall_hits::total 1438135 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 81302 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 81302 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 95545 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 95545 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1156 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1156 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 573 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 573 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 176847 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 176847 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 176847 # number of overall misses +system.cpu1.dcache.overall_misses::total 176847 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1110177095 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1110177095 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5046033431 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 5046033431 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 13905498 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 13905498 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4132075 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4132075 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6156210526 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6156210526 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6156210526 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6156210526 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1042294 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1042294 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 572688 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 572688 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 13660 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 13660 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 11372 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 11372 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1614982 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1614982 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1614982 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1614982 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078003 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.078003 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.166836 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.166836 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.084627 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.084627 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.050387 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.050387 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.109504 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.109504 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.109504 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.109504 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13654.978906 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13654.978906 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 52813.160615 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 52813.160615 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12028.977509 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12028.977509 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7211.300175 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7211.300175 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34810.941243 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34810.941243 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34810.941243 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34810.941243 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 236601 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3728 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6165 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 55.322425 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 38.378102 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 67781 # number of writebacks -system.cpu1.dcache.writebacks::total 67781 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 121809 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 121809 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 169922 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 169922 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 539 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 539 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 291731 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 291731 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 291731 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 291731 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 74663 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 74663 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 36694 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 36694 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4472 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4472 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2897 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2897 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 111357 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 111357 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 111357 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 111357 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 836811454 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 836811454 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 998585721 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 998585721 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 34130252 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 34130252 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15375566 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15375566 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1835397175 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1835397175 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1835397175 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1835397175 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23621500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23621500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 617644004 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 617644004 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641265504 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641265504 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043464 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043464 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033432 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033432 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.126707 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.126707 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.090331 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.090331 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.039553 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.039553 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.039553 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11207.846644 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11207.846644 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27213.869325 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27213.869325 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7631.988372 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7631.988372 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5307.409734 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5307.409734 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16482.099688 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16482.099688 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 24956 # number of writebacks +system.cpu1.dcache.writebacks::total 24956 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 46173 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 46173 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 80581 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 80581 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 235 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 235 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 126754 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 126754 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 126754 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 126754 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35129 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 35129 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 14964 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 14964 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 921 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 921 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 573 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 573 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 50093 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 50093 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 50093 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 50093 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 398615352 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 398615352 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 730663501 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 730663501 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8358752 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8358752 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2984925 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2984925 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1129278853 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1129278853 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1129278853 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1129278853 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22397000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22397000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 533147000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 533147000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555544000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555544000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033704 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033704 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026129 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026129 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067423 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067423 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.050387 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.050387 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031018 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031018 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031018 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031018 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11347.187566 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11347.187566 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48828.087477 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 48828.087477 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9075.735071 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9075.735071 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5209.293194 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5209.293194 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22543.645879 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22543.645879 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22543.645879 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22543.645879 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2085,170 +2087,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6589 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 184914 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65370 40.53% 40.53% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.61% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1926 1.19% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 186 0.12% 41.92% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 93691 58.08% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 161304 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64362 49.21% 49.21% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1926 1.47% 50.79% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 64176 49.07% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 130781 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1863832959500 97.81% 97.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63684000 0.00% 97.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 569763500 0.03% 97.84% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 89287000 0.00% 97.84% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 41094897500 2.16% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1905650591500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984580 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6410 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 202830 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72673 40.72% 40.72% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.07% 40.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1926 1.08% 41.87% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 6 0.00% 41.88% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 103726 58.12% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 178462 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71304 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.09% 49.38% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1926 1.33% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 6 0.00% 50.72% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 71298 49.28% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 144665 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1863558813000 97.76% 97.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63845500 0.00% 97.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 565237000 0.03% 97.80% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 3385500 0.00% 97.80% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 42015112000 2.20% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1906206393000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981162 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684975 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810773 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed -system.cpu0.kern.syscall::3 17 8.06% 11.37% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed -system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.74% 32.23% # number of syscalls executed -system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed -system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.47% 37.91% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.95% 44.08% # number of syscalls executed -system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed -system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed -system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed -system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 211 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.687369 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810621 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed +system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 277 0.16% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3529 2.08% 2.24% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.27% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed -system.cpu0.kern.callpal::swpipl 154533 90.92% 93.20% # number of callpals executed -system.cpu0.kern.callpal::rdps 6537 3.85% 97.04% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.04% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 97.05% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.05% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.05% # number of callpals executed -system.cpu0.kern.callpal::rti 4527 2.66% 99.72% # number of callpals executed -system.cpu0.kern.callpal::callsys 345 0.20% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 169959 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7072 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1287 # number of protection mode switches +system.cpu0.kern.callpal::wripir 95 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3930 2.10% 2.15% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.18% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.18% # number of callpals executed +system.cpu0.kern.callpal::swpipl 171605 91.48% 93.66% # number of callpals executed +system.cpu0.kern.callpal::rdps 6547 3.49% 97.15% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.15% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 97.15% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.16% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.16% # number of callpals executed +system.cpu0.kern.callpal::rti 4793 2.56% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.21% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 187581 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7378 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1286 -system.cpu0.kern.mode_good::user 1287 +system.cpu0.kern.mode_good::kernel 1369 +system.cpu0.kern.mode_good::user 1370 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.181844 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.185552 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.307812 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1903707301000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1943282500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.313100 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1904135221500 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2071163500 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3530 # number of times the context was actually changed +system.cpu0.kern.swap_context 3931 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2439 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 54740 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 16948 36.40% 36.40% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1925 4.13% 40.53% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 277 0.59% 41.13% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 27412 58.87% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 46562 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16579 47.26% 47.26% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1925 5.49% 52.74% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 277 0.79% 53.53% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 16302 46.47% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 35083 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1874130150000 98.36% 98.36% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 532183000 0.03% 98.39% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 125676500 0.01% 98.40% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 30535391000 1.60% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1905323400500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978228 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2254 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 34590 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 8916 31.91% 31.91% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1925 6.89% 38.80% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 95 0.34% 39.14% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17006 60.86% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 27942 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 8908 45.12% 45.12% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1925 9.75% 54.88% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 95 0.48% 55.36% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 8813 44.64% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 19741 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1876395415500 98.45% 98.45% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 531818000 0.03% 98.48% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 44293500 0.00% 98.48% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 28895956000 1.52% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1905867483000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.999103 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.594703 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.753468 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed -system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed -system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed -system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed -system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed -system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed -system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed -system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed -system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed -system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 115 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.518229 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.706499 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed +system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed +system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed +system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 186 0.39% 0.39% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.39% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1067 2.22% 2.61% # number of callpals executed -system.cpu1.kern.callpal::tbi 6 0.01% 2.63% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.64% # number of callpals executed -system.cpu1.kern.callpal::swpipl 41329 85.97% 88.61% # number of callpals executed -system.cpu1.kern.callpal::rdps 2224 4.63% 93.23% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.23% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.01% 93.24% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.24% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.25% # number of callpals executed -system.cpu1.kern.callpal::rti 3030 6.30% 99.55% # number of callpals executed -system.cpu1.kern.callpal::callsys 172 0.36% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 43 0.09% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 298 1.04% 1.07% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.08% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.11% # number of callpals executed +system.cpu1.kern.callpal::swpipl 23527 82.20% 83.30% # number of callpals executed +system.cpu1.kern.callpal::rdps 2214 7.74% 91.04% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.04% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% 91.05% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.06% # number of callpals executed +system.cpu1.kern.callpal::rti 2394 8.36% 99.43% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.42% 99.85% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.15% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 48076 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1341 # number of protection mode switches -system.cpu1.kern.mode_switch::user 460 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2398 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 662 -system.cpu1.kern.mode_good::user 460 -system.cpu1.kern.mode_good::idle 202 -system.cpu1.kern.mode_switch_good::kernel 0.493661 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 28623 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 659 # number of protection mode switches +system.cpu1.kern.mode_switch::user 367 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2036 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 386 +system.cpu1.kern.mode_good::user 367 +system.cpu1.kern.mode_good::idle 19 +system.cpu1.kern.mode_switch_good::kernel 0.585736 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.084237 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.315313 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4271038500 0.22% 0.22% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 809340000 0.04% 0.27% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1900232555000 99.73% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1068 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.009332 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.252123 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 1444110500 0.08% 0.08% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 692193000 0.04% 0.11% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1903401131500 99.89% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 299 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal index 25fe063e3..15c215278 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal @@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 30 cycles, load miss latency 134 cycles +
4096K Bcache detected; load hit latency 30 cycles, load miss latency 140 cycles
SMP: 2 CPUs probed -- cpu_present_mask = 3
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 80c9d1506..17f1f9290 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -15,17 +15,18 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/binaries/console +console=/home/stever/m5/m5_system_2.0b3/binaries/console eventq_index=0 init_param=0 -kernel=/dist/binaries/vmlinux +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/binaries/ts_osfpal -readfile=tests/halt.sh +pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -131,6 +132,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false @@ -632,7 +634,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -655,7 +657,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -741,9 +743,9 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -754,27 +756,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[1] [system.simple_disk] @@ -787,7 +795,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 6b0c7bafe..e834a5489 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 19:25:00 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 +gem5 compiled Jun 21 2014 10:36:29 +gem5 started Jun 21 2014 13:05:52 +gem5 executing on phenom +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/binaries/vmlinux +info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1860197780500 because m5_exit instruction encountered +Exiting @ tick 1860172195000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index eda12d3cf..f07e7eac0 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,127 +1,127 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.860188 # Number of seconds simulated -sim_ticks 1860187818000 # Number of ticks simulated -final_tick 1860187818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.860172 # Number of seconds simulated +sim_ticks 1860172195000 # Number of ticks simulated +final_tick 1860172195000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129673 # Simulator instruction rate (inst/s) -host_op_rate 129673 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4553007725 # Simulator tick rate (ticks/s) -host_mem_usage 348812 # Number of bytes of host memory used -host_seconds 408.56 # Real time elapsed on the host -sim_insts 52979638 # Number of instructions simulated -sim_ops 52979638 # Number of ops (including micro ops) simulated +host_inst_rate 152063 # Simulator instruction rate (inst/s) +host_op_rate 152063 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5340733222 # Simulator tick rate (ticks/s) +host_mem_usage 304984 # Number of bytes of host memory used +host_seconds 348.30 # Real time elapsed on the host +sim_insts 52963419 # Number of instructions simulated +sim_ops 52963419 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 963200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24881344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 965120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24879104 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28496832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 963200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 963200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7516608 # Number of bytes written to this memory -system.physmem.bytes_written::total 7516608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388771 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28496512 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 965120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 965120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7515712 # Number of bytes written to this memory +system.physmem.bytes_written::total 7515712 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15080 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388736 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445263 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117447 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117447 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 517797 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13375716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1425817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15319331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 517797 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517797 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4040779 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4040779 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4040779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 517797 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13375716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1425817 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19360110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445263 # Number of read requests accepted -system.physmem.writeReqs 117447 # Number of write requests accepted -system.physmem.readBursts 445263 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117447 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28490624 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue -system.physmem.bytesWritten 7515520 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28496832 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7516608 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 445258 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117433 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117433 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 518834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13374624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1425829 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15319287 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 518834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 518834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4040331 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4040331 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4040331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 518834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13374624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1425829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19359618 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445258 # Number of read requests accepted +system.physmem.writeReqs 117433 # Number of write requests accepted +system.physmem.readBursts 445258 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117433 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28490432 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue +system.physmem.bytesWritten 7513664 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28496512 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7515712 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 171 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28211 # Per bank write bursts -system.physmem.perBankRdBursts::1 27992 # Per bank write bursts -system.physmem.perBankRdBursts::2 28433 # Per bank write bursts -system.physmem.perBankRdBursts::3 27987 # Per bank write bursts -system.physmem.perBankRdBursts::4 27796 # Per bank write bursts -system.physmem.perBankRdBursts::5 27217 # Per bank write bursts -system.physmem.perBankRdBursts::6 27269 # Per bank write bursts -system.physmem.perBankRdBursts::7 27319 # Per bank write bursts -system.physmem.perBankRdBursts::8 27690 # Per bank write bursts -system.physmem.perBankRdBursts::9 27272 # Per bank write bursts -system.physmem.perBankRdBursts::10 28021 # Per bank write bursts -system.physmem.perBankRdBursts::11 27509 # Per bank write bursts -system.physmem.perBankRdBursts::12 27548 # Per bank write bursts -system.physmem.perBankRdBursts::13 28237 # Per bank write bursts -system.physmem.perBankRdBursts::14 28335 # Per bank write bursts -system.physmem.perBankRdBursts::15 28330 # Per bank write bursts -system.physmem.perBankWrBursts::0 7921 # Per bank write bursts -system.physmem.perBankWrBursts::1 7511 # Per bank write bursts -system.physmem.perBankWrBursts::2 7946 # Per bank write bursts -system.physmem.perBankWrBursts::3 7492 # Per bank write bursts -system.physmem.perBankWrBursts::4 7346 # Per bank write bursts -system.physmem.perBankWrBursts::5 6678 # Per bank write bursts -system.physmem.perBankWrBursts::6 6778 # Per bank write bursts -system.physmem.perBankWrBursts::7 6711 # Per bank write bursts -system.physmem.perBankWrBursts::8 7130 # Per bank write bursts -system.physmem.perBankWrBursts::9 6681 # Per bank write bursts -system.physmem.perBankWrBursts::10 7414 # Per bank write bursts -system.physmem.perBankWrBursts::11 6966 # Per bank write bursts -system.physmem.perBankWrBursts::12 7109 # Per bank write bursts -system.physmem.perBankWrBursts::13 7879 # Per bank write bursts -system.physmem.perBankWrBursts::14 8056 # Per bank write bursts -system.physmem.perBankWrBursts::15 7812 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 176 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28223 # Per bank write bursts +system.physmem.perBankRdBursts::1 27968 # Per bank write bursts +system.physmem.perBankRdBursts::2 28292 # Per bank write bursts +system.physmem.perBankRdBursts::3 27927 # Per bank write bursts +system.physmem.perBankRdBursts::4 27805 # Per bank write bursts +system.physmem.perBankRdBursts::5 27242 # Per bank write bursts +system.physmem.perBankRdBursts::6 27352 # Per bank write bursts +system.physmem.perBankRdBursts::7 27274 # Per bank write bursts +system.physmem.perBankRdBursts::8 27691 # Per bank write bursts +system.physmem.perBankRdBursts::9 27508 # Per bank write bursts +system.physmem.perBankRdBursts::10 27933 # Per bank write bursts +system.physmem.perBankRdBursts::11 27527 # Per bank write bursts +system.physmem.perBankRdBursts::12 27552 # Per bank write bursts +system.physmem.perBankRdBursts::13 28225 # Per bank write bursts +system.physmem.perBankRdBursts::14 28330 # Per bank write bursts +system.physmem.perBankRdBursts::15 28314 # Per bank write bursts +system.physmem.perBankWrBursts::0 7932 # Per bank write bursts +system.physmem.perBankWrBursts::1 7496 # Per bank write bursts +system.physmem.perBankWrBursts::2 7821 # Per bank write bursts +system.physmem.perBankWrBursts::3 7427 # Per bank write bursts +system.physmem.perBankWrBursts::4 7353 # Per bank write bursts +system.physmem.perBankWrBursts::5 6703 # Per bank write bursts +system.physmem.perBankWrBursts::6 6854 # Per bank write bursts +system.physmem.perBankWrBursts::7 6665 # Per bank write bursts +system.physmem.perBankWrBursts::8 7118 # Per bank write bursts +system.physmem.perBankWrBursts::9 6889 # Per bank write bursts +system.physmem.perBankWrBursts::10 7323 # Per bank write bursts +system.physmem.perBankWrBursts::11 6981 # Per bank write bursts +system.physmem.perBankWrBursts::12 7116 # Per bank write bursts +system.physmem.perBankWrBursts::13 7874 # Per bank write bursts +system.physmem.perBankWrBursts::14 8055 # Per bank write bursts +system.physmem.perBankWrBursts::15 7794 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1860182401000 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 1860166839000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 445263 # Read request sizes (log2) +system.physmem.readPktSize::6 445258 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117447 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 316668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59729 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3992 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2540 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2192 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117433 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 38754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 44609 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9021 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2051 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2195 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 2171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2086 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 986 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 905 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1630 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 984 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 899 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -148,128 +148,128 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63749 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 564.805095 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 351.189585 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.649920 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13350 20.94% 20.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10335 16.21% 37.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4789 7.51% 44.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2797 4.39% 49.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2437 3.82% 52.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1576 2.47% 55.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1469 2.30% 57.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1613 2.53% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25383 39.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63749 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6887 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 64.637723 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 16.523346 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2544.314640 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 6884 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 565.384925 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 351.672479 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 419.574374 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13299 20.88% 20.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10397 16.33% 37.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4628 7.27% 44.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2746 4.31% 48.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2553 4.01% 52.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1655 2.60% 55.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1376 2.16% 57.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1696 2.66% 60.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25330 39.78% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63680 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6888 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 64.625581 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 16.554610 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2544.325145 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 6885 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6887 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6887 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.050966 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.814496 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.834643 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 5493 79.76% 79.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 28 0.41% 80.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 690 10.02% 90.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 216 3.14% 93.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 116 1.68% 95.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 20 0.29% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 25 0.36% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 93 1.35% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 19 0.28% 97.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 44 0.64% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 11 0.16% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 7 0.10% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 8 0.12% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 16 0.23% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.03% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 14 0.20% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 9 0.13% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.01% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.01% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 3 0.04% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 2 0.03% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.01% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 1 0.01% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 2 0.03% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 7 0.10% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 4 0.06% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.03% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 3 0.04% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 1 0.01% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 4 0.06% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 3 0.04% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 3 0.04% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 7 0.10% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 4 0.06% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 1 0.01% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 1 0.01% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54 1 0.01% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 7 0.10% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 17 0.25% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6887 # Writes before turning the bus around for reads -system.physmem.totQLat 8647566500 # Total ticks spent queuing -system.physmem.totMemAccLat 16994429000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2225830000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19425.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6888 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6888 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.044280 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.812634 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.762583 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 5511 80.01% 80.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 31 0.45% 80.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 662 9.61% 90.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 220 3.19% 93.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 110 1.60% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 25 0.36% 95.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 25 0.36% 95.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 91 1.32% 96.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 22 0.32% 97.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 31 0.45% 97.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 12 0.17% 97.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 22 0.32% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 6 0.09% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 14 0.20% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.04% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 16 0.23% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 12 0.17% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 7 0.10% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.01% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.01% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 3 0.04% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 4 0.06% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 4 0.06% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 4 0.06% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 6 0.09% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 3 0.04% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 3 0.04% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 7 0.10% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 2 0.03% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 1 0.01% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 2 0.03% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 2 0.03% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 1 0.01% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 1 0.01% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54 1 0.01% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 1 0.01% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 8 0.12% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 12 0.17% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6888 # Writes before turning the bus around for reads +system.physmem.totQLat 8740437500 # Total ticks spent queuing +system.physmem.totMemAccLat 17087243750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2225815000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19634.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38175.49 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 38384.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s @@ -278,64 +278,65 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.02 # Average write queue length when enqueuing -system.physmem.readRowHits 403062 # Number of row buffer hits during reads -system.physmem.writeRowHits 95784 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.56 # Row buffer hit rate for writes -system.physmem.avgGap 3305756.79 # Average gap between requests -system.physmem.pageHitRate 88.67 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1761433244000 # Time in different power states -system.physmem.memoryStateTime::REF 62115560000 # Time in different power states +system.physmem.avgRdQLen 1.65 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.75 # Average write queue length when enqueuing +system.physmem.readRowHits 403028 # Number of row buffer hits during reads +system.physmem.writeRowHits 95855 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.63 # Row buffer hit rate for writes +system.physmem.avgGap 3305840.75 # Average gap between requests +system.physmem.pageHitRate 88.68 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1761575145500 # Time in different power states +system.physmem.memoryStateTime::REF 62115040000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 36633312250 # Time in different power states +system.physmem.memoryStateTime::ACT 36476358250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 19402968 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295944 # Transaction distribution -system.membus.trans_dist::ReadResp 295866 # Transaction distribution +system.membus.throughput 19402477 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 295985 # Transaction distribution +system.membus.trans_dist::ReadResp 295900 # Transaction distribution system.membus.trans_dist::WriteReq 9597 # Transaction distribution system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117447 # Transaction distribution -system.membus.trans_dist::UpgradeReq 174 # Transaction distribution -system.membus.trans_dist::UpgradeResp 174 # Transaction distribution -system.membus.trans_dist::ReadExReq 156883 # Transaction distribution -system.membus.trans_dist::ReadExResp 156883 # Transaction distribution -system.membus.trans_dist::BadAddressError 78 # Transaction distribution +system.membus.trans_dist::Writeback 117433 # Transaction distribution +system.membus.trans_dist::UpgradeReq 178 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 179 # Transaction distribution +system.membus.trans_dist::ReadExReq 156844 # Transaction distribution +system.membus.trans_dist::ReadExResp 156844 # Transaction distribution +system.membus.trans_dist::BadAddressError 85 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884195 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884181 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917405 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1042084 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704384 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30748524 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30703168 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30747308 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36057580 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36057580 # Total data (bytes) +system.membus.tot_pkt_size::total 36056364 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36056364 # Total data (bytes) system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29864500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 29838500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1548275500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1526200750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 98000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 104500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3770327047 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3755175800 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376611244 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376659242 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.261115 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.260971 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710335896000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.261115 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078820 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078820 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710335831000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.260971 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078811 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078811 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -349,14 +350,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21272883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21272883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12456693929 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12456693929 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12477966812 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12477966812 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12477966812 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12477966812 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12441682213 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12441682213 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 12462816596 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12462816596 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 12462816596 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12462816596 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -373,19 +374,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122964.641618 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122964.641618 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299785.664445 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 299785.664445 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 299052.529946 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 299052.529946 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 299052.529946 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 299052.529946 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 365915 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299424.389031 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 299424.389031 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 298689.433098 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 298689.433098 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 298689.433098 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 298689.433098 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 366119 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28370 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28395 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.897956 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.893784 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -399,14 +400,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12274883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12274883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10293819441 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10293819441 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10306094324 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10306094324 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10306094324 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10306094324 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10278710729 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10278710729 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10290848112 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10290848112 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10290848112 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10290848112 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -415,14 +416,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70953.080925 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70953.080925 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247733.428981 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 247733.428981 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 247000.463128 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 247000.463128 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 247000.463128 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 247000.463128 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247369.819239 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 247369.819239 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246635.065596 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 246635.065596 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246635.065596 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 246635.065596 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -436,36 +437,36 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13846630 # Number of BP lookups -system.cpu.branchPred.condPredicted 11622667 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 398238 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9513264 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5817388 # Number of BTB hits +system.cpu.branchPred.lookups 13973676 # Number of BP lookups +system.cpu.branchPred.condPredicted 11739131 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 397652 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9590938 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5932533 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.150284 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 900921 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39034 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.855608 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 905503 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 38808 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9912884 # DTB read hits -system.cpu.dtb.read_misses 41215 # DTB read misses -system.cpu.dtb.read_acv 553 # DTB read access violations -system.cpu.dtb.read_accesses 941108 # DTB read accesses -system.cpu.dtb.write_hits 6599017 # DTB write hits -system.cpu.dtb.write_misses 10339 # DTB write misses -system.cpu.dtb.write_acv 401 # DTB write access violations -system.cpu.dtb.write_accesses 338138 # DTB write accesses -system.cpu.dtb.data_hits 16511901 # DTB hits -system.cpu.dtb.data_misses 51554 # DTB misses -system.cpu.dtb.data_acv 954 # DTB access violations -system.cpu.dtb.data_accesses 1279246 # DTB accesses -system.cpu.itb.fetch_hits 1308304 # ITB hits -system.cpu.itb.fetch_misses 36786 # ITB misses -system.cpu.itb.fetch_acv 1079 # ITB acv -system.cpu.itb.fetch_accesses 1345090 # ITB accesses +system.cpu.dtb.read_hits 10112222 # DTB read hits +system.cpu.dtb.read_misses 41745 # DTB read misses +system.cpu.dtb.read_acv 542 # DTB read access violations +system.cpu.dtb.read_accesses 945441 # DTB read accesses +system.cpu.dtb.write_hits 6611008 # DTB write hits +system.cpu.dtb.write_misses 10791 # DTB write misses +system.cpu.dtb.write_acv 413 # DTB write access violations +system.cpu.dtb.write_accesses 339727 # DTB write accesses +system.cpu.dtb.data_hits 16723230 # DTB hits +system.cpu.dtb.data_misses 52536 # DTB misses +system.cpu.dtb.data_acv 955 # DTB access violations +system.cpu.dtb.data_accesses 1285168 # DTB accesses +system.cpu.itb.fetch_hits 1309723 # ITB hits +system.cpu.itb.fetch_misses 39683 # ITB misses +system.cpu.itb.fetch_acv 1073 # ITB acv +system.cpu.itb.fetch_accesses 1349406 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -478,303 +479,304 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 121969353 # number of cpu cycles simulated +system.cpu.numCycles 121578156 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28022459 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70674133 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13846630 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6718309 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13243332 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1983249 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37995640 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32164 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 254581 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 364654 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8542175 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 264688 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81194854 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.870426 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.213908 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28154197 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 72069959 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13973676 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6838036 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13462286 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2111809 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 36504135 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32813 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 258219 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 367287 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 202 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8654218 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 283642 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80169891 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.898965 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.245398 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67951522 83.69% 83.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 854853 1.05% 84.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1698258 2.09% 86.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 823227 1.01% 87.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2753963 3.39% 91.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 558188 0.69% 91.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 642929 0.79% 92.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1006595 1.24% 93.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4905319 6.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66707605 83.21% 83.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 850391 1.06% 84.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1701562 2.12% 86.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 829510 1.03% 87.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2814732 3.51% 90.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 566680 0.71% 91.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 649069 0.81% 92.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1061564 1.32% 93.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4988778 6.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81194854 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.113525 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.579442 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29206421 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37679452 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12104138 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 965352 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1239490 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 585042 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42720 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69357398 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129450 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1239490 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30354385 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13996332 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19984766 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11324382 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4295497 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65588313 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7118 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 505148 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1530678 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43795306 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79617271 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79438234 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 166586 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38180209 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5615089 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682372 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239607 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12205686 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10422971 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6895231 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1319326 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 854507 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58152614 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2049745 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56795087 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 97937 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6861282 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3503589 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1388801 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81194854 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.699491 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.361721 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80169891 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.114936 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.592787 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 28969141 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36597720 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12749238 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 505228 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1348563 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 587502 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42619 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 70583559 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129875 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1348563 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 29902418 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12633582 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20046715 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11807818 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4430793 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 66640171 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8986 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 787429 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 47943 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1601274 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 44565634 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 80920867 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 80741427 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 166989 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38166970 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6398656 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1681821 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 238696 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9832739 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10696003 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7004082 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1336985 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 877203 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58981840 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2047452 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57223975 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 117650 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7712570 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4365148 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1386476 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80169891 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.713784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.404933 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56519522 69.61% 69.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10856431 13.37% 82.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5145956 6.34% 89.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3402319 4.19% 93.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2626681 3.24% 96.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1459376 1.80% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 753323 0.93% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 333723 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 97523 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56166624 70.06% 70.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10391261 12.96% 83.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4679899 5.84% 88.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3142763 3.92% 92.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2796032 3.49% 96.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1647190 2.05% 98.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 895238 1.12% 99.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 353951 0.44% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96933 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81194854 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80169891 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 92642 11.69% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 372744 47.05% 58.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 326922 41.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 98738 11.92% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 400158 48.30% 60.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 329520 39.78% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38726894 68.19% 68.20% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61723 0.11% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10344006 18.21% 86.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6676923 11.76% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949012 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38901419 67.98% 67.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61759 0.11% 68.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.04% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10584317 18.50% 86.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6690891 11.69% 98.34% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949060 1.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56795087 # Type of FU issued -system.cpu.iq.rate 0.465650 # Inst issue rate -system.cpu.iq.fu_busy_cnt 792308 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013950 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194982001 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66741051 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55566428 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 693271 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336387 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327889 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57217918 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 362191 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 598643 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57223975 # Type of FU issued +system.cpu.iq.rate 0.470676 # Inst issue rate +system.cpu.iq.fu_busy_cnt 828416 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014477 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194870458 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 68419457 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55733530 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 693448 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 335810 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328249 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57682446 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 362659 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 614531 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1330641 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3245 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14147 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 517313 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1606237 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3745 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13777 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 627539 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17932 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 166827 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18239 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 375591 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1239490 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10213175 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 697716 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63724678 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 681593 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10422971 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6895231 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1805950 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512370 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16905 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14147 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 202448 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 409860 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 612308 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56329043 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9982328 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 466043 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1348563 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9312966 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 978337 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64604997 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 590069 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10696003 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 7004082 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1802911 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 468863 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 377382 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13777 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 204854 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411482 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 616336 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56685901 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10182131 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 538073 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3522319 # number of nop insts executed -system.cpu.iew.exec_refs 16606918 # number of memory reference insts executed -system.cpu.iew.exec_branches 8922931 # Number of branches executed -system.cpu.iew.exec_stores 6624590 # Number of stores executed -system.cpu.iew.exec_rate 0.461829 # Inst execution rate -system.cpu.iew.wb_sent 56008659 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55894317 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27713107 # num instructions producing a value -system.cpu.iew.wb_consumers 37520284 # num instructions consuming a value +system.cpu.iew.exec_nop 3575705 # number of nop insts executed +system.cpu.iew.exec_refs 16819167 # number of memory reference insts executed +system.cpu.iew.exec_branches 8947461 # Number of branches executed +system.cpu.iew.exec_stores 6637036 # Number of stores executed +system.cpu.iew.exec_rate 0.466251 # Inst execution rate +system.cpu.iew.wb_sent 56177988 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56061779 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28606216 # num instructions producing a value +system.cpu.iew.wb_consumers 39617780 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.458265 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738617 # average fanout of values written-back +system.cpu.iew.wb_rate 0.461117 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.722055 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7436889 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660944 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 566942 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79955364 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.702522 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.631936 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8325898 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660976 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 566478 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 78821328 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.712415 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.665597 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59166975 74.00% 74.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8627079 10.79% 84.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4603678 5.76% 90.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2536989 3.17% 93.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1507337 1.89% 95.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 611638 0.76% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 523619 0.65% 97.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 528614 0.66% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1849435 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58682621 74.45% 74.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8193641 10.40% 84.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4257107 5.40% 90.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2319840 2.94% 93.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1767395 2.24% 95.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 615421 0.78% 96.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 496583 0.63% 96.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 549859 0.70% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1938861 2.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79955364 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56170432 # Number of instructions committed -system.cpu.commit.committedOps 56170432 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 78821328 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56153459 # Number of instructions committed +system.cpu.commit.committedOps 56153459 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470248 # Number of memory references committed -system.cpu.commit.loads 9092330 # Number of loads committed -system.cpu.commit.membars 226348 # Number of memory barriers committed -system.cpu.commit.branches 8439871 # Number of branches committed +system.cpu.commit.refs 15466309 # Number of memory references committed +system.cpu.commit.loads 9089766 # Number of loads committed +system.cpu.commit.membars 226357 # Number of memory barriers committed +system.cpu.commit.branches 8438044 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52020070 # Number of committed integer instructions. -system.cpu.commit.function_calls 740568 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3198067 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36230888 64.50% 70.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60673 0.11% 70.30% # Class of committed instruction +system.cpu.commit.int_insts 52003822 # Number of committed integer instructions. +system.cpu.commit.function_calls 740374 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3197313 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36218566 64.50% 70.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60658 0.11% 70.30% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.30% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 25607 0.05% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9318678 16.59% 86.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6383871 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949012 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9316123 16.59% 86.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6382496 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949060 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56170432 # Class of committed instruction -system.cpu.commit.bw_lim_events 1849435 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 56153459 # Class of committed instruction +system.cpu.commit.bw_lim_events 1938861 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141463709 # The number of ROB reads -system.cpu.rob.rob_writes 128455843 # The number of ROB writes -system.cpu.timesIdled 1197783 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 40774499 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598399845 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52979638 # Number of Instructions Simulated -system.cpu.committedOps 52979638 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.302193 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.302193 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434368 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434368 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73867254 # number of integer regfile reads -system.cpu.int_regfile_writes 40307997 # number of integer regfile writes -system.cpu.fp_regfile_reads 166020 # number of floating regfile reads -system.cpu.fp_regfile_writes 167441 # number of floating regfile writes -system.cpu.misc_regfile_reads 2027897 # number of misc regfile reads -system.cpu.misc_regfile_writes 938938 # number of misc regfile writes +system.cpu.rob.rob_reads 141112277 # The number of ROB reads +system.cpu.rob.rob_writes 130308588 # The number of ROB writes +system.cpu.timesIdled 1194216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 41408265 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598759795 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52963419 # Number of Instructions Simulated +system.cpu.committedOps 52963419 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.295512 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.295512 # CPI: Total CPI of All Threads +system.cpu.ipc 0.435633 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.435633 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74250743 # number of integer regfile reads +system.cpu.int_regfile_writes 40442410 # number of integer regfile writes +system.cpu.fp_regfile_reads 166399 # number of floating regfile reads +system.cpu.fp_regfile_writes 167429 # number of floating regfile writes +system.cpu.misc_regfile_reads 2028427 # number of misc regfile reads +system.cpu.misc_regfile_writes 938976 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -806,7 +808,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1454556 # Throughput (bytes/s) +system.iobus.throughput 1454569 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51149 # Transaction distribution @@ -866,241 +868,245 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380172568 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380163354 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43172756 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43205758 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 111944057 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2118154 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2118059 # Transaction distribution +system.cpu.toL2Bus.throughput 111909594 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2117185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2117083 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 840946 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 62 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 840753 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 64 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 342489 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 300938 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020220 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677927 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5698147 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64643392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143586284 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 208229676 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 208219628 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 17344 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2480508998 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 342629 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301078 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 85 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2018148 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3678150 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5696298 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64577024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143586668 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 208163692 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 208153644 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 17472 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2479804999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1518532368 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1516964420 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2189805164 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2185370157 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1009436 # number of replacements -system.cpu.icache.tags.tagsinuse 509.668112 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7476172 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1009944 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.402561 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26651967250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.668112 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995446 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995446 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1008400 # number of replacements +system.cpu.icache.tags.tagsinuse 509.648597 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7589401 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1008908 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.522392 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26586363250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.648597 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995407 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9552342 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9552342 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7476173 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7476173 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7476173 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7476173 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7476173 # number of overall hits -system.cpu.icache.overall_hits::total 7476173 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1066002 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1066002 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1066002 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1066002 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1066002 # number of overall misses -system.cpu.icache.overall_misses::total 1066002 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14786308436 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14786308436 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14786308436 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14786308436 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14786308436 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14786308436 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8542175 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8542175 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8542175 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8542175 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8542175 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8542175 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124793 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124793 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124793 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124793 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124793 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124793 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13870.807406 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13870.807406 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13870.807406 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13870.807406 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13870.807406 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13870.807406 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4221 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 9663349 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9663349 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7589402 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7589402 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7589402 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7589402 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7589402 # number of overall hits +system.cpu.icache.overall_hits::total 7589402 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1064815 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1064815 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1064815 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1064815 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1064815 # number of overall misses +system.cpu.icache.overall_misses::total 1064815 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14788071318 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14788071318 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14788071318 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14788071318 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14788071318 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14788071318 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8654217 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8654217 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8654217 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8654217 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8654217 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8654217 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123040 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.123040 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.123040 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.123040 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.123040 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.123040 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13887.925431 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13887.925431 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13887.925431 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13887.925431 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13887.925431 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13887.925431 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4640 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 182 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 23.065574 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 25.494505 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55835 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 55835 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 55835 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 55835 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 55835 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 55835 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010167 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1010167 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1010167 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1010167 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1010167 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1010167 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12133097628 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12133097628 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12133097628 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12133097628 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12133097628 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12133097628 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118256 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118256 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118256 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.118256 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118256 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.118256 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12010.981974 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12010.981974 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12010.981974 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12010.981974 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12010.981974 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12010.981974 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55683 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 55683 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 55683 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 55683 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 55683 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 55683 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009132 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1009132 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1009132 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1009132 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1009132 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1009132 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12130132326 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12130132326 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12130132326 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12130132326 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12130132326 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12130132326 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116606 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116606 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116606 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116606 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116606 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116606 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12020.362377 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12020.362377 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12020.362377 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12020.362377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12020.362377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12020.362377 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338321 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65341.789916 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2546336 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403490 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.310778 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5544203750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53907.448463 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5292.784095 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6141.557358 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.822562 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080761 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.093713 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997037 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65169 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3494 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3325 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2414 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55443 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994400 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26727783 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26727783 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 995001 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 827094 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1822095 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 840946 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 840946 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 27 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 27 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 185467 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 185467 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 995001 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1012561 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2007562 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 995001 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1012561 # number of overall hits -system.cpu.l2cache.overall_hits::total 2007562 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15052 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273790 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 288842 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 35 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115470 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115470 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15052 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389260 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404312 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15052 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389260 # number of overall misses -system.cpu.l2cache.overall_misses::total 404312 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1147195743 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17910681229 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19057876972 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 262998 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 262998 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9445420357 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9445420357 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1147195743 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 27356101586 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28503297329 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1147195743 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 27356101586 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28503297329 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1010053 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1100884 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2110937 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 840946 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 840946 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 62 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 62 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.tags.replacements 338319 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65340.875442 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2545143 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 403486 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.307884 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 5540956750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 53842.334774 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5321.183862 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6177.356806 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.821569 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081195 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.094259 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997023 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3496 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3313 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2397 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55469 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 26719739 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26719739 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 993934 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 827149 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1821083 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 840753 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 840753 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 185645 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 185645 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 993934 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1012794 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2006728 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 993934 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1012794 # number of overall hits +system.cpu.l2cache.overall_hits::total 2006728 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 15082 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 273801 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 288883 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 38 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 38 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 115432 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 115432 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15082 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389233 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404315 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15082 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389233 # number of overall misses +system.cpu.l2cache.overall_misses::total 404315 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1156562743 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17908390235 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19064952978 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 285997 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 285997 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9622114357 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9622114357 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1156562743 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 27530504592 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28687067335 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1156562743 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 27530504592 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28687067335 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1009016 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1100950 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2109966 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 840753 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 840753 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 64 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 64 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 300937 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 300937 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1010053 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1401821 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2411874 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1010053 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1401821 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2411874 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014902 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248700 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.136831 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.564516 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.564516 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383702 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383702 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014902 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277682 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.167634 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014902 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277682 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.167634 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76215.502458 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65417.587308 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 65980.283241 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7514.228571 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7514.228571 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81799.777925 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81799.777925 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76215.502458 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70277.196696 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70498.271951 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76215.502458 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70277.196696 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70498.271951 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 301077 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 301077 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1009016 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1402027 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2411043 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1009016 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1402027 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2411043 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014947 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248695 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.136914 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.593750 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.593750 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383397 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383397 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014947 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.277622 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.167693 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014947 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.277622 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.167693 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76684.971688 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65406.591777 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 65995.413292 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7526.236842 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7526.236842 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83357.425645 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83357.425645 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76684.971688 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70730.140024 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70952.270717 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76684.971688 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70730.140024 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70952.270717 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1109,72 +1115,80 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75935 # number of writebacks -system.cpu.l2cache.writebacks::total 75935 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75921 # number of writebacks +system.cpu.l2cache.writebacks::total 75921 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15051 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273790 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288841 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115470 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115470 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15051 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389260 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404311 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15051 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389260 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404311 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 957328507 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14497719271 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15455047778 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 500032 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 500032 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8018115143 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8018115143 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 957328507 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22515834414 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23473162921 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 957328507 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22515834414 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23473162921 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333977500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333977500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882390000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882390000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216367500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216367500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014901 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248700 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136831 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.564516 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.564516 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383702 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383702 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014901 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277682 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.167634 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014901 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277682 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.167634 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63605.641286 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52951.967826 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53507.112141 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14286.628571 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14286.628571 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69438.946419 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69438.946419 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63605.641286 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57842.661496 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58057.195874 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63605.641286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57842.661496 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58057.195874 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15081 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273801 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288882 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 38 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115432 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115432 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15081 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389233 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404314 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15081 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389233 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404314 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 966321757 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14496174265 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15462496022 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 531034 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 531034 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 10001 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8215113143 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8215113143 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 966321757 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22711287408 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23677609165 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 966321757 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22711287408 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23677609165 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333995500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333995500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882363500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882363500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216359000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216359000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248695 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136913 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.593750 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.593750 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383397 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383397 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277622 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.167693 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014946 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277622 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.167693 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64075.443074 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52944.197665 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53525.301064 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13974.578947 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13974.578947 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71168.420741 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71168.420741 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64075.443074 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58348.822962 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58562.427136 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64075.443074 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58348.822962 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58562.427136 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1182,168 +1196,168 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1401230 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994514 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11803041 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1401742 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.420266 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25812000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994514 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1401429 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994598 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11820645 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1401941 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.431628 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25377000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994598 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 417 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63715251 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63715251 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7198260 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7198260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4203038 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4203038 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186010 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186010 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215511 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215511 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11401298 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11401298 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11401298 # number of overall hits -system.cpu.dcache.overall_hits::total 11401298 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1808147 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1808147 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1944666 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1944666 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22743 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22743 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 63732446 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63732446 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7221951 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7221951 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4197394 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4197394 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 185535 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 185535 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215521 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215521 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11419345 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11419345 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11419345 # number of overall hits +system.cpu.dcache.overall_hits::total 11419345 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1789877 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1789877 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1948925 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1948925 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23421 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23421 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3752813 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3752813 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3752813 # number of overall misses -system.cpu.dcache.overall_misses::total 3752813 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 40323855155 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 40323855155 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 76523868035 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 76523868035 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 322545000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 322545000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 116847723190 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 116847723190 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 116847723190 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 116847723190 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9006407 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9006407 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147704 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147704 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208753 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 208753 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215513 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215513 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15154111 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15154111 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15154111 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15154111 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200762 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.200762 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316324 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316324 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108947 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108947 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 3738802 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3738802 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3738802 # number of overall misses +system.cpu.dcache.overall_misses::total 3738802 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40163370133 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40163370133 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 77928512640 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77928512640 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 358310999 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 358310999 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 38001 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 38001 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 118091882773 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 118091882773 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 118091882773 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 118091882773 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9011828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9011828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6146319 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6146319 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208956 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 208956 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215523 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215523 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15158147 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15158147 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15158147 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15158147 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198614 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.198614 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.317088 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.317088 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.112086 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.112086 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247643 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247643 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247643 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247643 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22301.204025 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22301.204025 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39350.648407 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39350.648407 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14182.165941 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14182.165941 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31136.036672 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31136.036672 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31136.036672 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31136.036672 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3013190 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 80012 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.659226 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 118.428571 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.246653 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.246653 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.246653 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.246653 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22439.178856 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22439.178856 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39985.383039 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39985.383039 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15298.706247 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15298.706247 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19000.500000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19000.500000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31585.487216 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31585.487216 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31585.487216 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31585.487216 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3437281 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 992 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 114395 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.047476 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 124 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840946 # number of writebacks -system.cpu.dcache.writebacks::total 840946 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 724204 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 724204 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1644324 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1644324 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5146 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5146 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2368528 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2368528 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2368528 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2368528 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083943 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083943 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300342 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300342 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17597 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17597 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 840753 # number of writebacks +system.cpu.dcache.writebacks::total 840753 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705849 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 705849 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1648446 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1648446 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5839 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5839 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2354295 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2354295 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2354295 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2354295 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084028 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1084028 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300479 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300479 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17582 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17582 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384285 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384285 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384285 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384285 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27275514507 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27275514507 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11674414609 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11674414609 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201282500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201282500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38949929116 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 38949929116 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38949929116 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 38949929116 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424067500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424067500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997567998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997567998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421635498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421635498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120352 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120352 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048854 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048854 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084296 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084296 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384507 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384507 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384507 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384507 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27275332511 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27275332511 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11834545572 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11834545572 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200445001 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200445001 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 33999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 33999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39109878083 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 39109878083 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39109878083 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 39109878083 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424085500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424085500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997539998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997539998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421625498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421625498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120289 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120289 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048888 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048888 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084142 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084142 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091347 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091347 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091347 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091347 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25163.236911 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25163.236911 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38870.403104 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38870.403104 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11438.455419 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11438.455419 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28137.218214 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28137.218214 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28137.218214 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28137.218214 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091337 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091337 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091337 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25161.095941 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25161.095941 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39385.599566 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39385.599566 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11400.580196 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11400.580196 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16999.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16999.500000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28248.234269 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28248.234269 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28248.234269 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28248.234269 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1352,28 +1366,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211003 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211015 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74666 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105563 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182234 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105570 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182246 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73299 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817873983000 97.73% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64184500 0.00% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 553817500 0.03% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41694992500 2.24% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860186977500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73299 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148608 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817910535000 97.73% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64222000 0.00% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 554846000 0.03% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41641763000 2.24% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860171366000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694315 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815424 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694317 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815425 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1412,7 +1426,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175119 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175131 91.23% 93.44% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1421,20 +1435,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191963 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches +system.cpu.kern.callpal::total 191975 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326384 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29561208000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2704677000 0.15% 1.73% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827921084500 98.27% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 29515260500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2703792500 0.15% 1.73% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827952305000 98.27% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal index f09f72d29..075c19401 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal @@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 30 cycles, load miss latency 134 cycles +
4096K Bcache detected; load hit latency 30 cycles, load miss latency 140 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini index 933f62fba..e60af9d92 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini @@ -15,17 +15,18 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/dist/binaries/console +console=/home/stever/m5/m5_system_2.0b3/binaries/console eventq_index=0 init_param=0 -kernel=/dist/binaries/vmlinux +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux load_addr_mask=1099511627775 +load_offset=0 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/dist/binaries/ts_osfpal -readfile=tests/halt.sh +pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -58,6 +59,7 @@ voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU children=dcache dtb icache interrupts isa itb tracer +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -85,6 +87,7 @@ simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +socket_id=0 switched_out=false system=system tracer=system.cpu0.tracer @@ -189,6 +192,7 @@ eventq_index=0 [system.cpu1] type=TimingSimpleCPU children=dtb isa itb tracer +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -210,6 +214,7 @@ numThreads=1 profile=0 progress_interval=0 simpoint_start_insts= +socket_id=0 switched_out=true system=system tracer=system.cpu1.tracer @@ -310,6 +315,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=true @@ -689,7 +695,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -712,7 +718,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-bigswap2.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -833,9 +839,9 @@ warn_access= pio=system.membus.default [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -846,27 +852,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[1] [system.simple_disk] @@ -879,7 +891,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-latest.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout index ecd39bc4a..f92b070f8 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 19:37:21 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full +gem5 compiled Jun 21 2014 10:36:29 +gem5 started Jun 21 2014 13:11:51 +gem5 executing on phenom +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full Global frequency set at 1000000000000 ticks per second 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index d0b0c157e..de36b122c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,147 +1,147 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.843672 # Number of seconds simulated -sim_ticks 1843672389000 # Number of ticks simulated -final_tick 1843672389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.842688 # Number of seconds simulated +sim_ticks 1842688380000 # Number of ticks simulated +final_tick 1842688380000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 195444 # Simulator instruction rate (inst/s) -host_op_rate 195444 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4916161077 # Simulator tick rate (ticks/s) -host_mem_usage 347768 # Number of bytes of host memory used -host_seconds 375.02 # Real time elapsed on the host -sim_insts 73296119 # Number of instructions simulated -sim_ops 73296119 # Number of ops (including micro ops) simulated +host_inst_rate 219315 # Simulator instruction rate (inst/s) +host_op_rate 219315 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5608158508 # Simulator tick rate (ticks/s) +host_mem_usage 303992 # Number of bytes of host memory used +host_seconds 328.57 # Real time elapsed on the host +sim_insts 72060922 # Number of instructions simulated +sim_ops 72060922 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 488384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20120896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 480512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20113024 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 147840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2228608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 281856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2520448 # Number of bytes read from this memory -system.physmem.bytes_read::total 28440384 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 488384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 147840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 281856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 918080 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7465920 # Number of bytes written to this memory -system.physmem.bytes_written::total 7465920 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7631 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 314389 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 147456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2236096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 291264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2520128 # Number of bytes read from this memory +system.physmem.bytes_read::total 28440832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 480512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 291264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 919232 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7466176 # Number of bytes written to this memory +system.physmem.bytes_written::total 7466176 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7508 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 314266 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2310 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 34822 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4404 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39382 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444381 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116655 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116655 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 264897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10913488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1438624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 80188 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1208787 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 152877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1367080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15425942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 264897 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 80188 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 152877 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 497963 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4049483 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4049483 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4049483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 264897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10913488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1438624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 80188 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1208787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 152877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1367080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19475425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 98065 # Number of read requests accepted -system.physmem.writeReqs 44647 # Number of write requests accepted -system.physmem.readBursts 98065 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 44647 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6274880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1280 # Total number of bytes read from write queue -system.physmem.bytesWritten 2856000 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6276160 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2857408 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 20 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu1.inst 2304 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 34939 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4551 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39377 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444388 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116659 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116659 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 260767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10915044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1439393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 80022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1213497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 158065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1367637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15434423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 260767 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 80022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 158065 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4051784 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4051784 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4051784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 260767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10915044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1439393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 80022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1213497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 158065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1367637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19486207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 98062 # Number of read requests accepted +system.physmem.writeReqs 44473 # Number of write requests accepted +system.physmem.readBursts 98062 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 44473 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6274816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1152 # Total number of bytes read from write queue +system.physmem.bytesWritten 2845184 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6275968 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2846272 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 18 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 43 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6107 # Per bank write bursts -system.physmem.perBankRdBursts::1 5922 # Per bank write bursts -system.physmem.perBankRdBursts::2 6220 # Per bank write bursts -system.physmem.perBankRdBursts::3 6321 # Per bank write bursts -system.physmem.perBankRdBursts::4 5635 # Per bank write bursts -system.physmem.perBankRdBursts::5 6235 # Per bank write bursts -system.physmem.perBankRdBursts::6 5931 # Per bank write bursts -system.physmem.perBankRdBursts::7 6044 # Per bank write bursts -system.physmem.perBankRdBursts::8 6533 # Per bank write bursts -system.physmem.perBankRdBursts::9 6108 # Per bank write bursts -system.physmem.perBankRdBursts::10 6507 # Per bank write bursts -system.physmem.perBankRdBursts::11 5966 # Per bank write bursts -system.physmem.perBankRdBursts::12 5866 # Per bank write bursts -system.physmem.perBankRdBursts::13 6273 # Per bank write bursts -system.physmem.perBankRdBursts::14 6336 # Per bank write bursts -system.physmem.perBankRdBursts::15 6041 # Per bank write bursts -system.physmem.perBankWrBursts::0 2748 # Per bank write bursts -system.physmem.perBankWrBursts::1 2555 # Per bank write bursts -system.physmem.perBankWrBursts::2 2839 # Per bank write bursts -system.physmem.perBankWrBursts::3 3065 # Per bank write bursts -system.physmem.perBankWrBursts::4 2620 # Per bank write bursts -system.physmem.perBankWrBursts::5 2963 # Per bank write bursts -system.physmem.perBankWrBursts::6 2854 # Per bank write bursts -system.physmem.perBankWrBursts::7 2670 # Per bank write bursts -system.physmem.perBankWrBursts::8 3259 # Per bank write bursts -system.physmem.perBankWrBursts::9 2627 # Per bank write bursts -system.physmem.perBankWrBursts::10 3029 # Per bank write bursts -system.physmem.perBankWrBursts::11 2539 # Per bank write bursts -system.physmem.perBankWrBursts::12 2431 # Per bank write bursts -system.physmem.perBankWrBursts::13 2744 # Per bank write bursts -system.physmem.perBankWrBursts::14 2948 # Per bank write bursts -system.physmem.perBankWrBursts::15 2734 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 40 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6096 # Per bank write bursts +system.physmem.perBankRdBursts::1 5927 # Per bank write bursts +system.physmem.perBankRdBursts::2 6222 # Per bank write bursts +system.physmem.perBankRdBursts::3 6258 # Per bank write bursts +system.physmem.perBankRdBursts::4 5693 # Per bank write bursts +system.physmem.perBankRdBursts::5 6247 # Per bank write bursts +system.physmem.perBankRdBursts::6 5971 # Per bank write bursts +system.physmem.perBankRdBursts::7 5980 # Per bank write bursts +system.physmem.perBankRdBursts::8 6426 # Per bank write bursts +system.physmem.perBankRdBursts::9 5994 # Per bank write bursts +system.physmem.perBankRdBursts::10 6527 # Per bank write bursts +system.physmem.perBankRdBursts::11 6117 # Per bank write bursts +system.physmem.perBankRdBursts::12 5881 # Per bank write bursts +system.physmem.perBankRdBursts::13 6322 # Per bank write bursts +system.physmem.perBankRdBursts::14 6340 # Per bank write bursts +system.physmem.perBankRdBursts::15 6043 # Per bank write bursts +system.physmem.perBankWrBursts::0 2729 # Per bank write bursts +system.physmem.perBankWrBursts::1 2556 # Per bank write bursts +system.physmem.perBankWrBursts::2 2841 # Per bank write bursts +system.physmem.perBankWrBursts::3 3001 # Per bank write bursts +system.physmem.perBankWrBursts::4 2678 # Per bank write bursts +system.physmem.perBankWrBursts::5 2962 # Per bank write bursts +system.physmem.perBankWrBursts::6 2867 # Per bank write bursts +system.physmem.perBankWrBursts::7 2601 # Per bank write bursts +system.physmem.perBankWrBursts::8 3150 # Per bank write bursts +system.physmem.perBankWrBursts::9 2533 # Per bank write bursts +system.physmem.perBankWrBursts::10 3049 # Per bank write bursts +system.physmem.perBankWrBursts::11 2640 # Per bank write bursts +system.physmem.perBankWrBursts::12 2384 # Per bank write bursts +system.physmem.perBankWrBursts::13 2771 # Per bank write bursts +system.physmem.perBankWrBursts::14 2950 # Per bank write bursts +system.physmem.perBankWrBursts::15 2744 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 1842660063500 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 1841676054500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 98065 # Read request sizes (log2) +system.physmem.readPktSize::6 98062 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 44647 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 65397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8078 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 817 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 896 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 393 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 44473 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 65686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2064 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1814 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1613 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1004 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 871 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 653 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 362 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -153,12 +153,12 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 76 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 43 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 41 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see @@ -168,368 +168,385 @@ system.physmem.wrQLenPdf::11 35 # Wh system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21868 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 417.545272 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 236.447646 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 397.078129 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 6878 31.45% 31.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4663 21.32% 52.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1715 7.84% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 976 4.46% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 897 4.10% 69.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 495 2.26% 71.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 365 1.67% 73.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 382 1.75% 74.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5497 25.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21868 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2618 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.446906 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 907.093650 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2616 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21822 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 417.926863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 236.963090 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 396.574874 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 6839 31.34% 31.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4667 21.39% 52.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1650 7.56% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1022 4.68% 64.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 930 4.26% 69.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 496 2.27% 71.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 383 1.76% 73.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 375 1.72% 74.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5460 25.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21822 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2614 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.504973 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 907.786867 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2612 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.04% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.04% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2618 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2618 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.045455 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.392541 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 4.534822 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-1 25 0.95% 0.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2-3 9 0.34% 1.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-5 2 0.08% 1.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6-7 3 0.11% 1.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-9 2 0.08% 1.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10-11 1 0.04% 1.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14-15 1 0.04% 1.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 1908 72.88% 74.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 472 18.03% 92.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 41 1.57% 94.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 56 2.14% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 26 0.99% 97.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 16 0.61% 97.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 10 0.38% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 14 0.53% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 7 0.27% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.04% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 1 0.04% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 3 0.11% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 4 0.15% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 1 0.04% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 1 0.04% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 11 0.42% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 1 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 1 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-65 1 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2618 # Writes before turning the bus around for reads -system.physmem.totQLat 2942753000 # Total ticks spent queuing -system.physmem.totMemAccLat 4781096750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 490225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 30014.31 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2614 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.006886 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.398766 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 4.165807 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 24 0.92% 0.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 7 0.27% 1.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 2 0.08% 1.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 1 0.04% 1.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 1 0.04% 1.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 3 0.11% 1.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 2 0.08% 1.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 1 0.04% 1.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 1 0.04% 1.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 1 0.04% 1.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1860 71.16% 72.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 26 0.99% 73.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 431 16.49% 90.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 74 2.83% 93.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 23 0.88% 93.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 9 0.34% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 11 0.42% 94.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 40 1.53% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.31% 96.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 18 0.69% 97.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 8 0.31% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 7 0.27% 97.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.11% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 5 0.19% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 6 0.23% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 9 0.34% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 5 0.19% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.04% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.04% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.04% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.04% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.04% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 4 0.15% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 3 0.11% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.08% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 1 0.04% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 1 0.04% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 4 0.15% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 1 0.04% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 1 0.04% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 3 0.11% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 2 0.08% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58 1 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2614 # Writes before turning the bus around for reads +system.physmem.totQLat 2880597750 # Total ticks spent queuing +system.physmem.totMemAccLat 4718922750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 490220000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29380.66 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48764.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.40 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48130.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.41 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.22 # Average write queue length when enqueuing -system.physmem.readRowHits 85384 # Number of row buffer hits during reads -system.physmem.writeRowHits 35418 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 4.05 # Average write queue length when enqueuing +system.physmem.readRowHits 85382 # Number of row buffer hits during reads +system.physmem.writeRowHits 35296 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.33 # Row buffer hit rate for writes -system.physmem.avgGap 12911738.77 # Average gap between requests -system.physmem.pageHitRate 84.66 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1768578867000 # Time in different power states -system.physmem.memoryStateTime::REF 61564100000 # Time in different power states +system.physmem.writeRowHitRate 79.37 # Row buffer hit rate for writes +system.physmem.avgGap 12920868.94 # Average gap between requests +system.physmem.pageHitRate 84.68 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1767714784750 # Time in different power states +system.physmem.memoryStateTime::REF 61531340000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 13524513000 # Time in different power states +system.physmem.memoryStateTime::ACT 13440274000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 19519346 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 44419 # Transaction distribution -system.membus.trans_dist::ReadResp 44389 # Transaction distribution -system.membus.trans_dist::WriteReq 3765 # Transaction distribution -system.membus.trans_dist::WriteResp 3765 # Transaction distribution -system.membus.trans_dist::Writeback 44647 # Transaction distribution -system.membus.trans_dist::UpgradeReq 46 # Transaction distribution -system.membus.trans_dist::UpgradeResp 46 # Transaction distribution -system.membus.trans_dist::ReadExReq 56746 # Transaction distribution -system.membus.trans_dist::ReadExResp 56746 # Transaction distribution -system.membus.trans_dist::BadAddressError 30 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13356 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189542 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 202958 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 51481 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 51481 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 254439 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15715 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6940992 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 6956707 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2192576 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2192576 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 9149283 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35977232 # Total data (bytes) -system.membus.snoop_data_through_bus 10048 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12506000 # Layer occupancy (ticks) +system.membus.throughput 19530148 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 44582 # Transaction distribution +system.membus.trans_dist::ReadResp 44547 # Transaction distribution +system.membus.trans_dist::WriteReq 3734 # Transaction distribution +system.membus.trans_dist::WriteResp 3734 # Transaction distribution +system.membus.trans_dist::Writeback 44473 # Transaction distribution +system.membus.trans_dist::UpgradeReq 43 # Transaction distribution +system.membus.trans_dist::UpgradeResp 43 # Transaction distribution +system.membus.trans_dist::ReadExReq 56556 # Transaction distribution +system.membus.trans_dist::ReadExResp 56556 # Transaction distribution +system.membus.trans_dist::BadAddressError 35 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13238 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 190124 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 70 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 203432 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 50712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 50712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 254144 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15652 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6962432 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 6978084 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2159808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2159808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 9137892 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35977992 # Total data (bytes) +system.membus.snoop_data_through_bus 9984 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 12394500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 516947250 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 511002500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 37500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 45000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 762242703 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 763523207 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 155440000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 153153250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 337456 # number of replacements -system.l2c.tags.tagsinuse 65422.465864 # Cycle average of tags in use -system.l2c.tags.total_refs 2473240 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402619 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.142879 # Average number of references to valid blocks. +system.l2c.tags.replacements 337462 # number of replacements +system.l2c.tags.tagsinuse 65424.483078 # Cycle average of tags in use +system.l2c.tags.total_refs 2473806 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402625 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.144194 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54816.531838 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2443.286445 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2722.487240 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 580.950396 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 624.587700 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2109.099829 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2125.522416 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.836434 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.037282 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041542 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008865 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009530 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.032182 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.032433 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998268 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54864.362424 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2329.333896 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2645.609154 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 576.513665 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 589.890909 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2235.608932 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2183.164099 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.837164 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.035543 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.040369 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008797 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.034113 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.033312 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998298 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1026 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5608 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2978 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55383 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1028 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5611 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55380 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26151122 # Number of tag accesses -system.l2c.tags.data_accesses 26151122 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 519486 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 493287 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 124779 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 84464 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 292648 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 239510 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1754174 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 836240 # number of Writeback hits -system.l2c.Writeback_hits::total 836240 # number of Writeback hits +system.l2c.tags.tag_accesses 26155869 # Number of tag accesses +system.l2c.tags.data_accesses 26155869 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 519275 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 492761 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 124644 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 83355 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 294324 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 240703 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1755062 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835893 # number of Writeback hits +system.l2c.Writeback_hits::total 835893 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 92910 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 26171 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 67815 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186896 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 519486 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 586197 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 124779 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 110635 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 292648 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 307325 # number of demand (read+write) hits -system.l2c.demand_hits::total 1941070 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 519486 # number of overall hits -system.l2c.overall_hits::cpu0.data 586197 # number of overall hits -system.l2c.overall_hits::cpu1.inst 124779 # number of overall hits -system.l2c.overall_hits::cpu1.data 110635 # number of overall hits -system.l2c.overall_hits::cpu2.inst 292648 # number of overall hits -system.l2c.overall_hits::cpu2.data 307325 # number of overall hits -system.l2c.overall_hits::total 1941070 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 7631 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 238513 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2310 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 16826 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4404 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 17896 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287580 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu0.data 92934 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 26300 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 67701 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 186935 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 519275 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 585695 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 124644 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 109655 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 294324 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 308404 # number of demand (read+write) hits +system.l2c.demand_hits::total 1941997 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 519275 # number of overall hits +system.l2c.overall_hits::cpu0.data 585695 # number of overall hits +system.l2c.overall_hits::cpu1.inst 124644 # number of overall hits +system.l2c.overall_hits::cpu1.data 109655 # number of overall hits +system.l2c.overall_hits::cpu2.inst 294324 # number of overall hits +system.l2c.overall_hits::cpu2.data 308404 # number of overall hits +system.l2c.overall_hits::total 1941997 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 7508 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 238474 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2304 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 16794 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 4551 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 17979 # number of ReadReq misses +system.l2c.ReadReq_misses::total 287610 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 12 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 9 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 17 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 76151 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 18045 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 21583 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115779 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 7631 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 314664 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2310 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 34871 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 4404 # number of demand (read+write) misses +system.l2c.ReadExReq_misses::cpu0.data 76068 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 18194 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 21500 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115762 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 7508 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 314542 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2304 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 34988 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 4551 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 39479 # number of demand (read+write) misses -system.l2c.demand_misses::total 403359 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 7631 # number of overall misses -system.l2c.overall_misses::cpu0.data 314664 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2310 # number of overall misses -system.l2c.overall_misses::cpu1.data 34871 # number of overall misses -system.l2c.overall_misses::cpu2.inst 4404 # number of overall misses +system.l2c.demand_misses::total 403372 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 7508 # number of overall misses +system.l2c.overall_misses::cpu0.data 314542 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2304 # number of overall misses +system.l2c.overall_misses::cpu1.data 34988 # number of overall misses +system.l2c.overall_misses::cpu2.inst 4551 # number of overall misses system.l2c.overall_misses::cpu2.data 39479 # number of overall misses -system.l2c.overall_misses::total 403359 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 168327497 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 1121769250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 335079500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1193124499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2818300746 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 318496 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 318496 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1237365240 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1750671726 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2988036966 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 168327497 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2359134490 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 335079500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 2943796225 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 5806337712 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 168327497 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2359134490 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 335079500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 2943796225 # number of overall miss cycles -system.l2c.overall_miss_latency::total 5806337712 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 527117 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 731800 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 127089 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 101290 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 297052 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 257406 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2041754 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 836240 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 836240 # number of Writeback accesses(hits+misses) +system.l2c.overall_misses::total 403372 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 169555248 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 1119867750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 344601500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 1200068749 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2834093247 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 263498 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 263498 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1245576490 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1752401476 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2997977966 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 169555248 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2365444240 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 344601500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 2952470225 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 5832071213 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 169555248 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2365444240 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 344601500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 2952470225 # number of overall miss cycles +system.l2c.overall_miss_latency::total 5832071213 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 526783 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 731235 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 126948 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 100149 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 298875 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 258682 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2042672 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 835893 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835893 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 27 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 12 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 24 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu2.data 1 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 169061 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 44216 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 89398 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 302675 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 527117 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 900861 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 127089 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 145506 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 297052 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 346804 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2344429 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 527117 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 900861 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 127089 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 145506 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 297052 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 346804 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2344429 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014477 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.325926 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.018176 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.166117 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.014826 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.069524 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.140849 # miss rate for ReadReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 169002 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 44494 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 89201 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 302697 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 526783 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 900237 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 126948 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 144643 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 298875 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 347883 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2345369 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 526783 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 900237 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 126948 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 144643 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 298875 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 347883 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2345369 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014253 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.326125 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.018149 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.167690 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.015227 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.069502 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.140801 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.800000 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.740741 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.750000 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.708333 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.450435 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.408110 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.241426 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.382519 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014477 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.349293 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.018176 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.239653 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.014826 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.113837 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.172050 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014477 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.349293 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.018176 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.239653 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.014826 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.113837 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.172050 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72869.046320 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 66668.801260 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76085.263397 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 66669.898245 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 9800.058231 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 26541.333333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 15924.800000 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68571.085619 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81113.456239 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 25808.108258 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 72869.046320 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 67653.192911 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 76085.263397 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 74566.129461 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 14394.962582 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 72869.046320 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 67653.192911 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 76085.263397 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 74566.129461 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 14394.962582 # average overall miss latency +system.l2c.ReadExReq_miss_rate::cpu0.data 0.450101 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.408909 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.241029 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.382435 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014253 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.349399 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.018149 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.241892 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.015227 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.113484 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.171987 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014253 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.349399 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.018149 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.241892 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.015227 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.113484 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.171987 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73591.687500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 66682.609861 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75719.951659 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 66748.359141 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 9853.945437 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 29277.555556 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 15499.882353 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68460.838188 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81507.045395 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 25897.772723 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 73591.687500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 67607.300789 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 75719.951659 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 74785.841207 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 14458.294609 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 73591.687500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 67607.300789 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 75719.951659 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 74785.841207 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 14458.294609 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,97 +555,97 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 75143 # number of writebacks -system.l2c.writebacks::total 75143 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu1.inst 2310 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 16826 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 4404 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 17896 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 41436 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 12 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 12 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 18045 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 21583 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 39628 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2310 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 34871 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 4404 # number of demand (read+write) MSHR misses +system.l2c.writebacks::writebacks 75147 # number of writebacks +system.l2c.writebacks::total 75147 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu1.inst 2304 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 16794 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 4551 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 17979 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 41628 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 9 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 18194 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 21500 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 39694 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2304 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 34988 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 4551 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu2.data 39479 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 81064 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2310 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 34871 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 4404 # number of overall MSHR misses +system.l2c.demand_mshr_misses::total 81322 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2304 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 34988 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 4551 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu2.data 39479 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 81064 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 138909503 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 911100250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 279632500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 972656001 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2302298254 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 279009 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 279009 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1010621760 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1486000274 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2496622034 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 138909503 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1921722010 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 279632500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2458656275 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 4798920288 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 138909503 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1921722010 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 279632500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2458656275 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 4798920288 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 277729500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 292749000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 570478500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 344555500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 403769000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 748324500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 622285000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 696518000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1318803000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018176 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.166117 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014826 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.069524 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.020294 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.444444 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408110 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.241426 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.130926 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018176 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.239653 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014826 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.113837 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.034577 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018176 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.239653 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014826 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.113837 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034577 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60133.983983 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54148.356710 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63495.118074 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54350.469435 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 55562.753499 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 23250.750000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23250.750000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56005.639235 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68850.496873 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63001.464470 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60133.983983 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55109.460870 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63495.118074 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62277.572254 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59199.154841 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60133.983983 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55109.460870 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63495.118074 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62277.572254 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59199.154841 # average overall mshr miss latency +system.l2c.overall_mshr_misses::total 81322 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 140206252 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 909595750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 287277500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 979239251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2316318753 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 241006 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 241006 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1016974010 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1489833024 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 2506807034 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 140206252 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1926569760 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 287277500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2469072275 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 4823125787 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 140206252 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1926569760 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 287277500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2469072275 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 4823125787 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 272308500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 292895500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 565204000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 339653500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 403064000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 742717500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 611962000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 695959500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1307921500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018149 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.167690 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015227 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.069502 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020379 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.750000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.375000 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408909 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.241029 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.131134 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018149 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.241892 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015227 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.113484 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034673 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018149 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.241892 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015227 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.113484 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034673 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60853.407986 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54161.947719 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63124.038673 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54465.723956 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 55643.287042 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 26778.444444 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 26778.444444 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55896.120149 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69294.559256 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63153.298584 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60853.407986 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55063.729279 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63124.038673 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62541.408724 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59308.991257 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60853.407986 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55063.729279 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63124.038673 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62541.408724 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59308.991257 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -640,14 +657,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.262765 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254888 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694865594000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.262765 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078923 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078923 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1694865618000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254888 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078431 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078431 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -661,14 +678,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9418062 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9418062 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5145673458 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5145673458 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5155091520 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5155091520 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5155091520 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5155091520 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9303463 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9303463 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5047462530 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5047462530 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5056765993 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5056765993 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5056765993 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5056765993 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -685,56 +702,56 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54439.664740 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 54439.664740 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 123836.962312 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 123836.962312 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 123549.227561 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123549.227561 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 123549.227561 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123549.227561 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 151978 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53777.242775 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 53777.242775 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 121473.395504 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 121473.395504 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 121192.714032 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 121192.714032 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 121192.714032 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 121192.714032 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 149207 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11614 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11483 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.085759 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.993730 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::tsunami.ide 17152 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 17152 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 17222 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 17222 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 17222 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 17222 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5777062 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5777062 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4252886458 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4252886458 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 4258663520 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4258663520 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 4258663520 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4258663520 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.412784 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.412784 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.412750 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.412750 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.412750 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.412750 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82529.457143 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82529.457143 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247952.801889 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 247952.801889 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 247280.427360 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 247280.427360 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 247280.427360 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 247280.427360 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::tsunami.ide 16896 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 16896 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 16965 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 16965 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 16965 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5714463 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5714463 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4167935030 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4167935030 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 4173649493 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4173649493 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 4173649493 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4173649493 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.406623 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.406623 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.406591 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82818.304348 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82818.304348 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 246681.760772 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 246681.760772 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246015.295785 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 246015.295785 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246015.295785 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 246015.295785 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -752,22 +769,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4916751 # DTB read hits -system.cpu0.dtb.read_misses 6099 # DTB read misses +system.cpu0.dtb.read_hits 4913708 # DTB read hits +system.cpu0.dtb.read_misses 6100 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 428233 # DTB read accesses -system.cpu0.dtb.write_hits 3511411 # DTB write hits -system.cpu0.dtb.write_misses 670 # DTB write misses +system.cpu0.dtb.read_accesses 428235 # DTB read accesses +system.cpu0.dtb.write_hits 3510172 # DTB write hits +system.cpu0.dtb.write_misses 671 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations -system.cpu0.dtb.write_accesses 163777 # DTB write accesses -system.cpu0.dtb.data_hits 8428162 # DTB hits -system.cpu0.dtb.data_misses 6769 # DTB misses +system.cpu0.dtb.write_accesses 163990 # DTB write accesses +system.cpu0.dtb.data_hits 8423880 # DTB hits +system.cpu0.dtb.data_misses 6771 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations -system.cpu0.dtb.data_accesses 592010 # DTB accesses -system.cpu0.itb.fetch_hits 2761691 # ITB hits +system.cpu0.dtb.data_accesses 592225 # DTB accesses +system.cpu0.itb.fetch_hits 2758823 # ITB hits system.cpu0.itb.fetch_misses 3034 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2764725 # ITB accesses +system.cpu0.itb.fetch_accesses 2761857 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -780,87 +797,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928579533 # number of cpu cycles simulated +system.cpu0.numCycles 928196841 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33817210 # Number of instructions committed -system.cpu0.committedOps 33817210 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 31677975 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 169596 # Number of float alu accesses -system.cpu0.num_func_calls 812570 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4683135 # number of instructions that are conditional controls -system.cpu0.num_int_insts 31677975 # number of integer instructions -system.cpu0.num_fp_insts 169596 # number of float instructions -system.cpu0.num_int_register_reads 44495639 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23114141 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87595 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 89102 # number of times the floating registers were written -system.cpu0.num_mem_refs 8458293 # number of memory refs -system.cpu0.num_load_insts 4938120 # Number of load instructions -system.cpu0.num_store_insts 3520173 # Number of store instructions -system.cpu0.num_idle_cycles 904460149.841647 # Number of idle cycles -system.cpu0.num_busy_cycles 24119383.158353 # Number of busy cycles -system.cpu0.not_idle_fraction 0.025974 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.974026 # Percentage of idle cycles -system.cpu0.Branches 5759211 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1618304 4.78% 4.78% # Class of executed instruction -system.cpu0.op_class::IntAlu 23033604 68.10% 72.88% # Class of executed instruction -system.cpu0.op_class::IntMult 32432 0.10% 72.98% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 72.98% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12174 0.04% 73.01% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 73.01% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 73.01% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 73.01% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1606 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 73.02% # Class of executed instruction -system.cpu0.op_class::MemRead 5072252 15.00% 88.02% # Class of executed instruction -system.cpu0.op_class::MemWrite 3523323 10.42% 98.43% # Class of executed instruction -system.cpu0.op_class::IprAccess 530494 1.57% 100.00% # Class of executed instruction +system.cpu0.committedInsts 33463552 # Number of instructions committed +system.cpu0.committedOps 33463552 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 31328637 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 169756 # Number of float alu accesses +system.cpu0.num_func_calls 812549 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4574772 # number of instructions that are conditional controls +system.cpu0.num_int_insts 31328637 # number of integer instructions +system.cpu0.num_fp_insts 169756 # number of float instructions +system.cpu0.num_int_register_reads 43916482 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22873823 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87693 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 89172 # number of times the floating registers were written +system.cpu0.num_mem_refs 8454037 # number of memory refs +system.cpu0.num_load_insts 4935095 # Number of load instructions +system.cpu0.num_store_insts 3518942 # Number of store instructions +system.cpu0.num_idle_cycles 904607153.884767 # Number of idle cycles +system.cpu0.num_busy_cycles 23589687.115233 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025415 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974585 # Percentage of idle cycles +system.cpu0.Branches 5650356 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1614853 4.82% 4.82% # Class of executed instruction +system.cpu0.op_class::IntAlu 22689020 67.79% 72.61% # Class of executed instruction +system.cpu0.op_class::IntMult 32419 0.10% 72.71% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 72.71% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12179 0.04% 72.75% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1606 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.75% # Class of executed instruction +system.cpu0.op_class::MemRead 5069147 15.15% 87.90% # Class of executed instruction +system.cpu0.op_class::MemWrite 3522084 10.52% 98.42% # Class of executed instruction +system.cpu0.op_class::IprAccess 529225 1.58% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 33824189 # Class of executed instruction +system.cpu0.op_class::total 33470533 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6417 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211389 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74803 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211388 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74806 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1880 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105703 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182589 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73436 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182585 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73439 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1880 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73436 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148955 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1820445327500 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38826000 0.00% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 365496000 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22821970000 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1843671619500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73439 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148960 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1819515986000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38828500 0.00% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 364353500 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22768442500 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842687610500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694739 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815794 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694807 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815839 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -896,33 +913,33 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175328 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6784 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175326 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5177 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192243 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1908 -system.cpu0.kern.mode_good::user 1739 -system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.322134 # fraction of useful protection mode switches +system.cpu0.kern.callpal::total 192241 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1907 +system.cpu0.kern.mode_good::user 1737 +system.cpu0.kern.mode_good::idle 170 +system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29786667000 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2578002500 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1811306945500 98.24% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4175 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.390979 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29751992000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2580511000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810355103000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -954,460 +971,460 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 110441912 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 785832 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 785787 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 3765 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 3765 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 372222 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution +system.toL2Bus.throughput 110521342 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 787621 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 787571 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3734 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3734 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 372342 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 150766 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 133614 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 30 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 848294 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370287 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 2218581 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27145024 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55347363 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 82492387 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 203607824 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 10880 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2138460500 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 150591 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 133695 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 35 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 851659 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370714 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 2222373 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27252672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55368420 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 82621092 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 203645448 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 10944 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2139903500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1910550337 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1918103434 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2233740752 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2234598905 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1468369 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 2983 # Transaction distribution -system.iobus.trans_dist::ReadResp 2983 # Transaction distribution -system.iobus.trans_dist::WriteReq 20917 # Transaction distribution -system.iobus.trans_dist::WriteResp 20917 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2330 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1469149 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 2954 # Transaction distribution +system.iobus.trans_dist::ReadResp 2954 # Transaction distribution +system.iobus.trans_dist::WriteReq 20630 # Transaction distribution +system.iobus.trans_dist::WriteResp 20630 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2332 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8382 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2408 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 13356 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34444 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 34444 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 47800 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8304 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2378 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 22 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 13238 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 47168 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9328 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4191 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 15715 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1099184 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1099184 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1114899 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2707192 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2199000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1550 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 17 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15652 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1098444 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2707184 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2201000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6246000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6188000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 1819000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 1792000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 156921520 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 154562743 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9591000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9504000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17887000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17636750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 950608 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.189792 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43374256 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 951119 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 45.603396 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10403794250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.164377 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 98.345392 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 161.680023 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.490555 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.192081 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.315781 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998418 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 951958 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.193866 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 42822968 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 952469 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 44.959960 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10341081250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 254.383910 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 92.394710 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 164.415245 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.496844 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.180458 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.321124 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998426 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 45292775 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 45292775 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 33297051 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7835821 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2241384 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43374256 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 33297051 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7835821 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2241384 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43374256 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 33297051 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7835821 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2241384 # number of overall hits -system.cpu0.icache.overall_hits::total 43374256 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 527138 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 127089 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 313001 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 967228 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 527138 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 127089 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 313001 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 967228 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 527138 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 127089 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 313001 # number of overall misses -system.cpu0.icache.overall_misses::total 967228 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1805503003 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4394679722 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6200182725 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1805503003 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4394679722 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6200182725 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1805503003 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4394679722 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6200182725 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 33824189 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7962910 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2554385 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 44341484 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 33824189 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7962910 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2554385 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 44341484 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 33824189 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7962910 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2554385 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 44341484 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015585 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015960 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122535 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.021813 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015585 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015960 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122535 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.021813 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015585 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015960 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122535 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.021813 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14206.603270 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14040.465436 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6410.259758 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14206.603270 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14040.465436 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6410.259758 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14206.603270 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14040.465436 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6410.259758 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2211 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 139 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.906475 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 44744661 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 44744661 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 32943729 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7613321 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2265918 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 42822968 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 32943729 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7613321 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2265918 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 42822968 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 32943729 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7613321 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2265918 # number of overall hits +system.cpu0.icache.overall_hits::total 42822968 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 526804 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 126948 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 315301 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 969053 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 526804 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 126948 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 315301 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 969053 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 526804 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 126948 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 315301 # number of overall misses +system.cpu0.icache.overall_misses::total 969053 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1804971752 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4436657422 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6241629174 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1804971752 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4436657422 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6241629174 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1804971752 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4436657422 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6241629174 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 33470533 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7740269 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2581219 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 43792021 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 33470533 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7740269 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2581219 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 43792021 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 33470533 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7740269 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2581219 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43792021 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015739 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016401 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122152 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.022129 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015739 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016401 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122152 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.022129 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015739 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016401 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122152 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.022129 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14218.197624 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14071.180941 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6440.957485 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14218.197624 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14071.180941 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6440.957485 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14218.197624 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14071.180941 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6440.957485 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2807 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 180 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 158 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.765823 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 180 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 15937 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 15937 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 15937 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 15937 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 15937 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 15937 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 127089 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 297064 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 424153 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 127089 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 297064 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 424153 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 127089 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 297064 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 424153 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1550405997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3623912160 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5174318157 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1550405997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3623912160 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5174318157 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1550405997 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3623912160 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5174318157 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015960 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116296 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009566 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015960 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116296 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009566 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015960 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116296 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009566 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12199.372070 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12199.095683 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12199.178497 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12199.372070 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12199.095683 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12199.178497 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12199.372070 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12199.095683 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12199.178497 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16413 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16413 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16413 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16413 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16413 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16413 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 126948 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 298888 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 425836 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 126948 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 298888 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 425836 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 126948 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 298888 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 425836 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1550155248 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3653520809 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5203676057 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1550155248 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3653520809 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5203676057 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1550155248 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3653520809 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5203676057 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016401 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.115793 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009724 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016401 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.115793 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009724 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016401 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.115793 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009724 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12210.946592 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12223.711922 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12219.906389 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12210.946592 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12223.711922 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12219.906389 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12210.946592 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12223.711922 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12219.906389 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1392627 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997813 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13291421 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393139 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.540628 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1392214 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13295925 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1392726 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.546691 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 251.446594 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 129.524111 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 131.027107 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.491107 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.252977 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.255912 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.443226 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 126.415700 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 131.138886 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.496959 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.246906 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.256131 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63293161 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63293161 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4078776 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1086651 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2400445 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7565872 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3215108 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 831895 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1295006 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5342009 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117088 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19357 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47741 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184186 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126296 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21393 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51592 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7293884 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1918546 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3695451 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12907881 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7293884 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1918546 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3695451 # number of overall hits -system.cpu0.dcache.overall_hits::total 12907881 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 722029 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 99123 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 533441 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1354593 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 169072 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 44217 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 597048 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 810337 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9771 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2167 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6787 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18725 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 63306620 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63306620 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4076279 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1084544 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2409625 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7570448 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3214036 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 832568 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1295168 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5341772 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117096 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19328 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47935 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184359 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126165 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21357 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51769 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199291 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7290315 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1917112 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3704793 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12912220 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7290315 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1917112 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3704793 # number of overall hits +system.cpu0.dcache.overall_hits::total 12912220 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 721601 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 97990 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 534145 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1353736 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 169013 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 44495 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 596516 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 810024 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9634 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2159 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7048 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 18841 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu2.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 891101 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 143340 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1130489 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2164930 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 891101 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 143340 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1130489 # number of overall misses -system.cpu0.dcache.overall_misses::total 2164930 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2252505500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9329560863 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11582066363 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1640569260 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 17995165012 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19635734272 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28565250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 103170749 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 131735999 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 890614 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 142485 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1130661 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2163760 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 890614 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 142485 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1130661 # number of overall misses +system.cpu0.dcache.overall_misses::total 2163760 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2236149750 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9408423500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11644573250 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1650986010 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18036124563 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 19687110573 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28476000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 115371499 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 143847499 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 13000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 3893074760 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 27324725875 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 31217800635 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3893074760 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 27324725875 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 31217800635 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4800805 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1185774 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 2933886 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8920465 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3384180 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 876112 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1892054 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6152346 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126859 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21524 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54528 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 202911 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126297 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21393 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 51593 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199283 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8184985 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2061886 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 4825940 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15072811 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8184985 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2061886 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 4825940 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15072811 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150397 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083594 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181821 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.151852 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049960 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050470 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315555 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.131712 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077023 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100678 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.124468 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092282 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_latency::cpu1.data 3887135760 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 27444548063 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 31331683823 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 3887135760 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 27444548063 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 31331683823 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4797880 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1182534 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 2943770 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8924184 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3383049 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 877063 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 1891684 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6151796 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126730 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21487 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 54983 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203200 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126166 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21357 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 51770 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 199293 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8180929 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 2059597 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 4835454 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15075980 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8180929 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 2059597 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 4835454 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15075980 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150400 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082864 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.181449 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.151693 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049959 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050732 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315336 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.131673 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076020 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100479 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.128185 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092721 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000019 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000010 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108870 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069519 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.234253 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.143631 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108870 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069519 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.234253 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.143631 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22724.347528 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17489.395946 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8550.218673 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37102.681322 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30140.231626 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 24231.565721 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13181.933549 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15201.230146 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7035.300347 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.108865 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069181 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233827 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.143524 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108865 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069181 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.233827 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.143524 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22820.183182 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17613.987775 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8601.805116 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37104.978312 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30235.776682 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 24304.354652 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13189.439555 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16369.395431 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7634.812324 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6500 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27159.723455 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24170.713625 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14419.773681 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27159.723455 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24170.713625 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14419.773681 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 573016 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 707 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 17657 # number of cycles access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27281.017370 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24273.012037 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14480.202898 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27281.017370 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24273.012037 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14480.202898 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 642685 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 913 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 30067 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 32.452625 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 101 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.375096 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 130.428571 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 836240 # number of writebacks -system.cpu0.dcache.writebacks::total 836240 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 281234 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 281234 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 507881 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 507881 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1344 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 789115 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 789115 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 789115 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 789115 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 99123 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 252207 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 351330 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 44217 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 89167 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 133384 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2167 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5443 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7610 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 835893 # number of writebacks +system.cpu0.dcache.writebacks::total 835893 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 280644 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 280644 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 507552 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 507552 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1619 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1619 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 788196 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 788196 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 788196 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 788196 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 97990 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 253501 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 351491 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 44495 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 88964 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 133459 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2159 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5429 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7588 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 1 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 143340 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 341374 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 484714 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 143340 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 341374 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 484714 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2046709500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4236520898 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6283230398 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1543938740 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2600534498 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4144473238 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24229750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66769000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90998750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu1.data 142485 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 342465 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 484950 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 142485 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 342465 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 484950 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2032617250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4252838742 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6285455992 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1553735990 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2601199489 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4154935479 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24156000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 66182251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90338251 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3590648240 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6837055396 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10427703636 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3590648240 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6837055396 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10427703636 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296463000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 311893000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 608356000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 365040500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 428466000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 793506500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 661503500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 740359000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1401862500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083594 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.085963 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039385 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050470 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047127 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021680 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100678 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099820 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037504 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3586353240 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6854038231 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10440391471 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3586353240 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6854038231 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10440391471 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 290678000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 312039500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 602717500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 359850500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 427676500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 787527000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 650528500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 739716000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1390244500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082864 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086114 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039386 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050732 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047029 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021694 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100479 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.098740 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037343 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069519 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070737 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032158 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069519 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070737 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032158 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20648.179535 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16797.792678 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17884.127168 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34917.310989 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29164.763848 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31071.742023 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11181.241347 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12266.948374 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.785808 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069181 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070824 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032167 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069181 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070824 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032167 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20743.108991 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16776.418010 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17882.267233 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34919.339027 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29238.787476 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31132.673548 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11188.513201 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12190.504881 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.409989 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25049.869122 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20028.049576 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21513.105947 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25049.869122 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20028.049576 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21513.105947 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25170.040636 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20013.835665 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21528.799816 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25170.040636 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20013.835665 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21528.799816 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1422,22 +1439,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1205243 # DTB read hits +system.cpu1.dtb.read_hits 1201953 # DTB read hits system.cpu1.dtb.read_misses 1367 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations system.cpu1.dtb.read_accesses 142945 # DTB read accesses -system.cpu1.dtb.write_hits 897974 # DTB write hits +system.cpu1.dtb.write_hits 898873 # DTB write hits system.cpu1.dtb.write_misses 185 # DTB write misses system.cpu1.dtb.write_acv 23 # DTB write access violations -system.cpu1.dtb.write_accesses 58533 # DTB write accesses -system.cpu1.dtb.data_hits 2103217 # DTB hits +system.cpu1.dtb.write_accesses 58321 # DTB write accesses +system.cpu1.dtb.data_hits 2100826 # DTB hits system.cpu1.dtb.data_misses 1552 # DTB misses system.cpu1.dtb.data_acv 57 # DTB access violations -system.cpu1.dtb.data_accesses 201478 # DTB accesses -system.cpu1.itb.fetch_hits 859888 # ITB hits +system.cpu1.dtb.data_accesses 201266 # DTB accesses +system.cpu1.itb.fetch_hits 861128 # ITB hits system.cpu1.itb.fetch_misses 693 # ITB misses system.cpu1.itb.fetch_acv 30 # ITB acv -system.cpu1.itb.fetch_accesses 860581 # ITB accesses +system.cpu1.itb.fetch_accesses 861821 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1450,64 +1467,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953622390 # number of cpu cycles simulated +system.cpu1.numCycles 953604102 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7961300 # Number of instructions committed -system.cpu1.committedOps 7961300 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7416956 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 45099 # Number of float alu accesses -system.cpu1.num_func_calls 213358 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1019863 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7416956 # number of integer instructions -system.cpu1.num_fp_insts 45099 # number of float instructions -system.cpu1.num_int_register_reads 10395465 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5394572 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24307 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24707 # number of times the floating registers were written -system.cpu1.num_mem_refs 2110464 # number of memory refs -system.cpu1.num_load_insts 1210140 # Number of load instructions -system.cpu1.num_store_insts 900324 # Number of store instructions -system.cpu1.num_idle_cycles 923192460.103175 # Number of idle cycles -system.cpu1.num_busy_cycles 30429929.896825 # Number of busy cycles -system.cpu1.not_idle_fraction 0.031910 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.968090 # Percentage of idle cycles -system.cpu1.Branches 1300058 # Number of branches fetched -system.cpu1.op_class::No_OpClass 413905 5.20% 5.20% # Class of executed instruction -system.cpu1.op_class::IntAlu 5261386 66.07% 71.27% # Class of executed instruction -system.cpu1.op_class::IntMult 8416 0.11% 71.38% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 71.38% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5003 0.06% 71.44% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 71.44% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 71.44% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 71.44% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 71.45% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.45% # Class of executed instruction -system.cpu1.op_class::MemRead 1239389 15.56% 87.01% # Class of executed instruction -system.cpu1.op_class::MemWrite 901545 11.32% 98.34% # Class of executed instruction -system.cpu1.op_class::IprAccess 132455 1.66% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7738659 # Number of instructions committed +system.cpu1.committedOps 7738659 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7195320 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 44971 # Number of float alu accesses +system.cpu1.num_func_calls 212104 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 948894 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7195320 # number of integer instructions +system.cpu1.num_fp_insts 44971 # number of float instructions +system.cpu1.num_int_register_reads 10028277 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5244710 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24303 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24579 # number of times the floating registers were written +system.cpu1.num_mem_refs 2108049 # number of memory refs +system.cpu1.num_load_insts 1206835 # Number of load instructions +system.cpu1.num_store_insts 901214 # Number of store instructions +system.cpu1.num_idle_cycles 922268722.786044 # Number of idle cycles +system.cpu1.num_busy_cycles 31335379.213956 # Number of busy cycles +system.cpu1.not_idle_fraction 0.032860 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.967140 # Percentage of idle cycles +system.cpu1.Branches 1227675 # Number of branches fetched +system.cpu1.op_class::No_OpClass 413043 5.34% 5.34% # Class of executed instruction +system.cpu1.op_class::IntAlu 5041451 65.13% 70.47% # Class of executed instruction +system.cpu1.op_class::IntMult 8548 0.11% 70.58% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.58% # Class of executed instruction +system.cpu1.op_class::FloatAdd 4999 0.06% 70.64% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.64% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.64% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.64% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 70.65% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.65% # Class of executed instruction +system.cpu1.op_class::MemRead 1235944 15.97% 86.62% # Class of executed instruction +system.cpu1.op_class::MemWrite 902434 11.66% 98.28% # Class of executed instruction +system.cpu1.op_class::IprAccess 133039 1.72% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7962909 # Class of executed instruction +system.cpu1.op_class::total 7740268 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1525,35 +1542,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9178120 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8499449 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 123200 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7695654 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6571533 # Number of BTB hits +system.cpu2.branchPred.lookups 8997141 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8310458 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 125233 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7551874 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6369180 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 85.392781 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 282084 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 12342 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 84.339066 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 284910 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 13175 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3191151 # DTB read hits -system.cpu2.dtb.read_misses 11650 # DTB read misses -system.cpu2.dtb.read_acv 122 # DTB read access violations -system.cpu2.dtb.read_accesses 216295 # DTB read accesses -system.cpu2.dtb.write_hits 2013879 # DTB write hits -system.cpu2.dtb.write_misses 2626 # DTB write misses -system.cpu2.dtb.write_acv 104 # DTB write access violations -system.cpu2.dtb.write_accesses 81955 # DTB write accesses -system.cpu2.dtb.data_hits 5205030 # DTB hits -system.cpu2.dtb.data_misses 14276 # DTB misses +system.cpu2.dtb.read_hits 3232647 # DTB read hits +system.cpu2.dtb.read_misses 11674 # DTB read misses +system.cpu2.dtb.read_acv 117 # DTB read access violations +system.cpu2.dtb.read_accesses 217551 # DTB read accesses +system.cpu2.dtb.write_hits 2020818 # DTB write hits +system.cpu2.dtb.write_misses 2669 # DTB write misses +system.cpu2.dtb.write_acv 109 # DTB write access violations +system.cpu2.dtb.write_accesses 82591 # DTB write accesses +system.cpu2.dtb.data_hits 5253465 # DTB hits +system.cpu2.dtb.data_misses 14343 # DTB misses system.cpu2.dtb.data_acv 226 # DTB access violations -system.cpu2.dtb.data_accesses 298250 # DTB accesses -system.cpu2.itb.fetch_hits 370022 # ITB hits -system.cpu2.itb.fetch_misses 5569 # ITB misses -system.cpu2.itb.fetch_acv 246 # ITB acv -system.cpu2.itb.fetch_accesses 375591 # ITB accesses +system.cpu2.dtb.data_accesses 300142 # DTB accesses +system.cpu2.itb.fetch_hits 371576 # ITB hits +system.cpu2.itb.fetch_misses 5695 # ITB misses +system.cpu2.itb.fetch_acv 235 # ITB acv +system.cpu2.itb.fetch_accesses 377271 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1566,304 +1583,305 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 31335688 # number of cpu cycles simulated +system.cpu2.numCycles 31002313 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8331242 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 37157937 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9178120 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6853617 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8899845 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 601293 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9656250 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 10264 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1927 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 62491 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 87858 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 258 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2554389 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 85437 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27441825 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.354062 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.292990 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8393929 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 36824229 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8997141 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6654090 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8723757 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 635832 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9323842 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 10747 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1941 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 64126 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 88179 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 311 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2581223 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 87099 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27026118 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.362542 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.315525 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18541980 67.57% 67.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 269924 0.98% 68.55% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 430608 1.57% 70.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 5041958 18.37% 88.49% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 762355 2.78% 91.27% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 165901 0.60% 91.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 191104 0.70% 92.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 428586 1.56% 94.14% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1609409 5.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18302361 67.72% 67.72% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 270640 1.00% 68.72% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 435105 1.61% 70.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4809867 17.80% 88.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 769933 2.85% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 167503 0.62% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 192346 0.71% 92.31% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 444449 1.64% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1633914 6.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27441825 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.292897 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.185802 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8480872 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9736053 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8290323 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 308881 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 379812 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 165178 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12521 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36770346 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 39237 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 379812 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8839767 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2783657 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5759458 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8162466 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1270789 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35635356 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2433 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 230404 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 445807 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 23881418 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 44614948 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 44558512 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 52675 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 22098169 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1783249 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 500707 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 58904 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3714662 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3352351 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2102718 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 368829 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 261079 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 33144056 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 620028 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32694445 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 35243 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2135274 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1079120 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 437376 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27441825 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.191409 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.576872 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27026118 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.290209 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.187790 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8441173 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9512814 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8253964 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 165145 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 407122 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 167309 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12818 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36409694 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 40311 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 407122 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8734574 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2556870 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5774789 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8067686 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1239186 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35224318 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 3572 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 388506 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 20310 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 316059 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 23620864 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 44017646 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 43961139 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 52746 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21667069 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1953795 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 502665 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 59694 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 2961257 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3405802 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2124807 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 397929 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 274147 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32669106 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 622861 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32140552 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 36002 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2321360 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1217953 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 439629 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27026118 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.189240 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.607686 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15111094 55.07% 55.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3067205 11.18% 66.24% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1556680 5.67% 71.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5872597 21.40% 93.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 904620 3.30% 96.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 481374 1.75% 98.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 286422 1.04% 99.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 142457 0.52% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 19376 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15119064 55.94% 55.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2962463 10.96% 66.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1396485 5.17% 72.07% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5591038 20.69% 92.76% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 885243 3.28% 96.03% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 550698 2.04% 98.07% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 348435 1.29% 99.36% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 154603 0.57% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18089 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27441825 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27026118 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 33866 13.68% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 112679 45.53% 59.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 100956 40.79% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 38019 14.73% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 14.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 117677 45.59% 60.31% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 102444 39.69% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 27019317 82.64% 82.65% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20282 0.06% 82.71% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.71% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8426 0.03% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.74% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3318398 10.15% 92.89% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2035966 6.23% 99.12% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 288396 0.88% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26413495 82.18% 82.19% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 20160 0.06% 82.25% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.25% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8429 0.03% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.28% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3362943 10.46% 92.74% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2042777 6.36% 99.10% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 289088 0.90% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32694445 # Type of FU issued -system.cpu2.iq.rate 1.043361 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 247501 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007570 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 92879210 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 35788610 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 32300559 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 234249 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114557 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110717 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32817438 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 122068 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 187489 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32140552 # Type of FU issued +system.cpu2.iq.rate 1.036715 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 258140 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.008032 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 91366801 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 35502508 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 31706710 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 234563 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114868 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110893 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32274032 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 122220 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 191624 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 409544 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 984 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3929 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 155635 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 457264 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1199 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4154 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 177923 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4136 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 26287 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4195 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 54966 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 379812 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2011431 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 204809 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 35034427 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 220433 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3352351 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2102718 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 550753 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 142349 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2108 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3929 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 63003 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 127121 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 190124 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 32537756 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3211080 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 156689 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 407122 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 1875775 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 219548 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34577439 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 209711 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3405802 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2124807 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 553318 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 48768 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 120434 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4154 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 65270 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 127814 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 193084 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 31975437 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3252613 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 165115 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1270343 # number of nop insts executed -system.cpu2.iew.exec_refs 5232018 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7610407 # Number of branches executed -system.cpu2.iew.exec_stores 2020938 # Number of stores executed -system.cpu2.iew.exec_rate 1.038361 # Inst execution rate -system.cpu2.iew.wb_sent 32444193 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 32411276 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18891849 # num instructions producing a value -system.cpu2.iew.wb_consumers 22089477 # num instructions consuming a value +system.cpu2.iew.exec_nop 1285472 # number of nop insts executed +system.cpu2.iew.exec_refs 5280547 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7393667 # Number of branches executed +system.cpu2.iew.exec_stores 2027934 # Number of stores executed +system.cpu2.iew.exec_rate 1.031389 # Inst execution rate +system.cpu2.iew.wb_sent 31851458 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 31817603 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18729651 # num instructions producing a value +system.cpu2.iew.wb_consumers 22311181 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.034325 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.855242 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.026298 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.839474 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2305077 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 182652 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 175963 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 27062013 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.207707 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.849174 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2502130 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 183232 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 177866 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26618996 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.203206 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.875540 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16121128 59.57% 59.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2330838 8.61% 68.18% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1224813 4.53% 72.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5615394 20.75% 93.46% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 503174 1.86% 95.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 185895 0.69% 96.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 176248 0.65% 96.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 179513 0.66% 97.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 725010 2.68% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16042703 60.27% 60.27% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2256116 8.48% 68.74% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1167560 4.39% 73.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5327635 20.01% 93.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 518833 1.95% 95.09% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 187130 0.70% 95.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 168998 0.63% 96.43% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 171142 0.64% 97.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 778879 2.93% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 27062013 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32682976 # Number of instructions committed -system.cpu2.commit.committedOps 32682976 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26618996 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32028137 # Number of instructions committed +system.cpu2.commit.committedOps 32028137 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4889890 # Number of memory references committed -system.cpu2.commit.loads 2942807 # Number of loads committed -system.cpu2.commit.membars 63964 # Number of memory barriers committed -system.cpu2.commit.branches 7465437 # Number of branches committed -system.cpu2.commit.fp_insts 109562 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 31237309 # Number of committed integer instructions. -system.cpu2.commit.function_calls 229028 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1167807 3.57% 3.57% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 26241804 80.29% 83.87% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 19886 0.06% 83.93% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 8426 0.03% 83.95% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.95% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.95% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.95% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.96% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3006771 9.20% 93.16% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 1948666 5.96% 99.12% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 288396 0.88% 100.00% # Class of committed instruction +system.cpu2.commit.refs 4895422 # Number of memory references committed +system.cpu2.commit.loads 2948538 # Number of loads committed +system.cpu2.commit.membars 64184 # Number of memory barriers committed +system.cpu2.commit.branches 7237241 # Number of branches committed +system.cpu2.commit.fp_insts 109664 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 30577389 # Number of committed integer instructions. +system.cpu2.commit.function_calls 229570 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1171866 3.66% 3.66% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 25576585 79.86% 83.52% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 19753 0.06% 83.58% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.58% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 8429 0.03% 83.60% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.60% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.60% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.60% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.61% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3012722 9.41% 93.01% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 1948474 6.08% 99.10% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 289088 0.90% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 32682976 # Class of committed instruction -system.cpu2.commit.bw_lim_events 725010 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 32028137 # Class of committed instruction +system.cpu2.commit.bw_lim_events 778879 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 61251181 # The number of ROB reads -system.cpu2.rob.rob_writes 70355425 # The number of ROB writes -system.cpu2.timesIdled 245354 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3893863 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1748379581 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 31517609 # Number of Instructions Simulated -system.cpu2.committedOps 31517609 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.994228 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.994228 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.005806 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.005806 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42812311 # number of integer regfile reads -system.cpu2.int_regfile_writes 22772429 # number of integer regfile writes -system.cpu2.fp_regfile_reads 67678 # number of floating regfile reads -system.cpu2.fp_regfile_writes 67966 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5406368 # number of misc regfile reads -system.cpu2.misc_regfile_writes 257490 # number of misc regfile writes +system.cpu2.rob.rob_reads 60296509 # The number of ROB reads +system.cpu2.rob.rob_writes 69467378 # The number of ROB writes +system.cpu2.timesIdled 246541 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3976195 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746763449 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 30858711 # Number of Instructions Simulated +system.cpu2.committedOps 30858711 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.004654 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.004654 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.995368 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.995368 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42053824 # number of integer regfile reads +system.cpu2.int_regfile_writes 22390255 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67731 # number of floating regfile reads +system.cpu2.fp_regfile_writes 68085 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5172203 # number of misc regfile reads +system.cpu2.misc_regfile_writes 258202 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed |