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authorNilay Vaish <nilay@cs.wisc.edu>2013-11-26 17:05:25 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2013-11-26 17:05:25 -0600
commit2823982a3cbd60a1b21db1a73b78440468df158a (patch)
treeb955647023da451506138be5a325dfaa2bfd8ee5 /tests/long/fs/10.linux-boot/ref/alpha
parent9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff)
downloadgem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
-rw-r--r--tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini250
-rw-r--r--tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt3760
-rw-r--r--tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini194
-rw-r--r--tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt2074
-rw-r--r--tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini204
-rw-r--r--tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt2603
6 files changed, 4856 insertions, 4229 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index dfd7f9bb3..38f343beb 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
+eventq_index=0
full_system=true
+sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -13,15 +15,16 @@ boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/dist/m5/system/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
+eventq_index=0
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
@@ -39,6 +42,7 @@ system_port=system.membus.slave[0]
type=Bridge
clk_domain=system.clk_domain
delay=50000
+eventq_index=0
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
@@ -48,6 +52,7 @@ slave=system.membus.master[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu0]
@@ -79,6 +84,8 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
+eventq_index=0
+fetchBufferSize=64
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -143,6 +150,7 @@ BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
+eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
@@ -158,6 +166,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -180,26 +189,31 @@ type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
size=32768
[system.cpu0.dtb]
type=AlphaTLB
+eventq_index=0
size=64
[system.cpu0.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
+eventq_index=0
[system.cpu0.fuPool.FUList0]
type=FUDesc
children=opList
count=6
+eventq_index=0
opList=system.cpu0.fuPool.FUList0.opList
[system.cpu0.fuPool.FUList0.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
@@ -208,16 +222,19 @@ opLat=1
type=FUDesc
children=opList0 opList1
count=2
+eventq_index=0
opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
[system.cpu0.fuPool.FUList1.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
[system.cpu0.fuPool.FUList1.opList1]
type=OpDesc
+eventq_index=0
issueLat=19
opClass=IntDiv
opLat=20
@@ -226,22 +243,26 @@ opLat=20
type=FUDesc
children=opList0 opList1 opList2
count=4
+eventq_index=0
opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
[system.cpu0.fuPool.FUList2.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu0.fuPool.FUList2.opList1]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu0.fuPool.FUList2.opList2]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=2
@@ -250,22 +271,26 @@ opLat=2
type=FUDesc
children=opList0 opList1 opList2
count=2
+eventq_index=0
opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
[system.cpu0.fuPool.FUList3.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu0.fuPool.FUList3.opList1]
type=OpDesc
+eventq_index=0
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu0.fuPool.FUList3.opList2]
type=OpDesc
+eventq_index=0
issueLat=24
opClass=FloatSqrt
opLat=24
@@ -274,10 +299,12 @@ opLat=24
type=FUDesc
children=opList
count=0
+eventq_index=0
opList=system.cpu0.fuPool.FUList4.opList
[system.cpu0.fuPool.FUList4.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
@@ -286,124 +313,145 @@ opLat=1
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
+eventq_index=0
opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
[system.cpu0.fuPool.FUList5.opList00]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu0.fuPool.FUList5.opList01]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu0.fuPool.FUList5.opList02]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu0.fuPool.FUList5.opList03]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu0.fuPool.FUList5.opList04]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu0.fuPool.FUList5.opList05]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu0.fuPool.FUList5.opList06]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu0.fuPool.FUList5.opList07]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu0.fuPool.FUList5.opList08]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu0.fuPool.FUList5.opList09]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu0.fuPool.FUList5.opList10]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu0.fuPool.FUList5.opList11]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu0.fuPool.FUList5.opList12]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu0.fuPool.FUList5.opList13]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu0.fuPool.FUList5.opList14]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu0.fuPool.FUList5.opList15]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu0.fuPool.FUList5.opList16]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu0.fuPool.FUList5.opList17]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu0.fuPool.FUList5.opList18]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu0.fuPool.FUList5.opList19]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=1
@@ -412,10 +460,12 @@ opLat=1
type=FUDesc
children=opList
count=0
+eventq_index=0
opList=system.cpu0.fuPool.FUList6.opList
[system.cpu0.fuPool.FUList6.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
@@ -424,16 +474,19 @@ opLat=1
type=FUDesc
children=opList0 opList1
count=4
+eventq_index=0
opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
[system.cpu0.fuPool.FUList7.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
[system.cpu0.fuPool.FUList7.opList1]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
@@ -442,10 +495,12 @@ opLat=1
type=FUDesc
children=opList
count=1
+eventq_index=0
opList=system.cpu0.fuPool.FUList8.opList
[system.cpu0.fuPool.FUList8.opList]
type=OpDesc
+eventq_index=0
issueLat=3
opClass=IprAccess
opLat=3
@@ -456,6 +511,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -478,21 +534,26 @@ type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
size=32768
[system.cpu0.interrupts]
type=AlphaInterrupts
+eventq_index=0
[system.cpu0.isa]
type=AlphaISA
+eventq_index=0
[system.cpu0.itb]
type=AlphaTLB
+eventq_index=0
size=48
[system.cpu0.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu1]
type=DerivO3CPU
@@ -523,6 +584,8 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
+eventq_index=0
+fetchBufferSize=64
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -587,6 +650,7 @@ BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
+eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
@@ -602,6 +666,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -624,26 +689,31 @@ type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
size=32768
[system.cpu1.dtb]
type=AlphaTLB
+eventq_index=0
size=64
[system.cpu1.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
+eventq_index=0
[system.cpu1.fuPool.FUList0]
type=FUDesc
children=opList
count=6
+eventq_index=0
opList=system.cpu1.fuPool.FUList0.opList
[system.cpu1.fuPool.FUList0.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
@@ -652,16 +722,19 @@ opLat=1
type=FUDesc
children=opList0 opList1
count=2
+eventq_index=0
opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
[system.cpu1.fuPool.FUList1.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
[system.cpu1.fuPool.FUList1.opList1]
type=OpDesc
+eventq_index=0
issueLat=19
opClass=IntDiv
opLat=20
@@ -670,22 +743,26 @@ opLat=20
type=FUDesc
children=opList0 opList1 opList2
count=4
+eventq_index=0
opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
[system.cpu1.fuPool.FUList2.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu1.fuPool.FUList2.opList1]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu1.fuPool.FUList2.opList2]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=2
@@ -694,22 +771,26 @@ opLat=2
type=FUDesc
children=opList0 opList1 opList2
count=2
+eventq_index=0
opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
[system.cpu1.fuPool.FUList3.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu1.fuPool.FUList3.opList1]
type=OpDesc
+eventq_index=0
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu1.fuPool.FUList3.opList2]
type=OpDesc
+eventq_index=0
issueLat=24
opClass=FloatSqrt
opLat=24
@@ -718,10 +799,12 @@ opLat=24
type=FUDesc
children=opList
count=0
+eventq_index=0
opList=system.cpu1.fuPool.FUList4.opList
[system.cpu1.fuPool.FUList4.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
@@ -730,124 +813,145 @@ opLat=1
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
+eventq_index=0
opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
[system.cpu1.fuPool.FUList5.opList00]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu1.fuPool.FUList5.opList01]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu1.fuPool.FUList5.opList02]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu1.fuPool.FUList5.opList03]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu1.fuPool.FUList5.opList04]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu1.fuPool.FUList5.opList05]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu1.fuPool.FUList5.opList06]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu1.fuPool.FUList5.opList07]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu1.fuPool.FUList5.opList08]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu1.fuPool.FUList5.opList09]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu1.fuPool.FUList5.opList10]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu1.fuPool.FUList5.opList11]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu1.fuPool.FUList5.opList12]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu1.fuPool.FUList5.opList13]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu1.fuPool.FUList5.opList14]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu1.fuPool.FUList5.opList15]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu1.fuPool.FUList5.opList16]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu1.fuPool.FUList5.opList17]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu1.fuPool.FUList5.opList18]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu1.fuPool.FUList5.opList19]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=1
@@ -856,10 +960,12 @@ opLat=1
type=FUDesc
children=opList
count=0
+eventq_index=0
opList=system.cpu1.fuPool.FUList6.opList
[system.cpu1.fuPool.FUList6.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
@@ -868,16 +974,19 @@ opLat=1
type=FUDesc
children=opList0 opList1
count=4
+eventq_index=0
opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
[system.cpu1.fuPool.FUList7.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
[system.cpu1.fuPool.FUList7.opList1]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
@@ -886,10 +995,12 @@ opLat=1
type=FUDesc
children=opList
count=1
+eventq_index=0
opList=system.cpu1.fuPool.FUList8.opList
[system.cpu1.fuPool.FUList8.opList]
type=OpDesc
+eventq_index=0
issueLat=3
opClass=IprAccess
opLat=3
@@ -900,6 +1011,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -922,25 +1034,31 @@ type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
size=32768
[system.cpu1.interrupts]
type=AlphaInterrupts
+eventq_index=0
[system.cpu1.isa]
type=AlphaISA
+eventq_index=0
[system.cpu1.itb]
type=AlphaTLB
+eventq_index=0
size=48
[system.cpu1.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+eventq_index=0
voltage_domain=system.voltage_domain
[system.disk0]
@@ -948,19 +1066,22 @@ type=IdeDisk
children=image
delay=1000000
driveID=master
+eventq_index=0
image=system.disk0.image
[system.disk0.image]
type=CowDiskImage
children=child
child=system.disk0.image.child
+eventq_index=0
image_file=
read_only=false
table_size=65536
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
@@ -968,28 +1089,33 @@ type=IdeDisk
children=image
delay=1000000
driveID=master
+eventq_index=0
image=system.disk2.image
[system.disk2.image]
type=CowDiskImage
children=child
child=system.disk2.image.child
+eventq_index=0
image_file=
read_only=false
table_size=65536
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
type=IntrControl
+eventq_index=0
sys=system
[system.iobus]
type=NoncoherentBus
clk_domain=system.clk_domain
+eventq_index=0
header_cycles=1
use_default_range=true
width=8
@@ -1003,6 +1129,7 @@ children=tags
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
+eventq_index=0
forward_snoops=false
hit_latency=50
is_top_level=true
@@ -1025,6 +1152,7 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
+eventq_index=0
hit_latency=50
size=1024
@@ -1034,6 +1162,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
@@ -1056,6 +1185,7 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=20
size=4194304
@@ -1063,6 +1193,7 @@ size=4194304
type=CoherentBus
children=badaddr_responder
clk_domain=system.clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -1074,6 +1205,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=0
pio_latency=100000
@@ -1100,6 +1232,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+eventq_index=0
in_addr_map=true
mem_sched_policy=frfcfs
null=false
@@ -1111,29 +1244,35 @@ static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCL=13750
+tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=300000
tRP=13750
+tRRD=6250
tWTR=7500
tXAW=40000
write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
port=system.membus.master[1]
[system.simple_disk]
type=SimpleDisk
children=disk
disk=system.simple_disk.disk
+eventq_index=0
system=system
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
type=Terminal
+eventq_index=0
intr_control=system.intrctrl
number=0
output=true
@@ -1142,6 +1281,7 @@ port=3456
[system.toL2Bus]
type=CoherentBus
clk_domain=system.cpu_clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -1152,6 +1292,7 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache
[system.tsunami]
type=Tsunami
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+eventq_index=0
intrctrl=system.intrctrl
system=system
@@ -1160,6 +1301,7 @@ type=AlphaBackdoor
clk_domain=system.clk_domain
cpu=system.cpu0
disk=system.simple_disk
+eventq_index=0
pio_addr=8804682956800
pio_latency=100000
platform=system.tsunami
@@ -1170,6 +1312,7 @@ pio=system.iobus.master[24]
[system.tsunami.cchip]
type=TsunamiCChip
clk_domain=system.clk_domain
+eventq_index=0
pio_addr=8803072344064
pio_latency=100000
system=system
@@ -1198,6 +1341,7 @@ BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
+CapabilityPtr=0
CardbusCIS=0
ClassCode=2
Command=0
@@ -1207,8 +1351,40 @@ HeaderType=0
InterruptLine=30
InterruptPin=1
LatencyTimer=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
MaximumLatency=52
MinimumGrant=176
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
ProgIF=0
Revision=0
Status=656
@@ -1225,6 +1401,7 @@ dma_read_delay=0
dma_read_factor=0
dma_write_delay=0
dma_write_factor=0
+eventq_index=0
hardware_address=00:90:00:00:00:01
intr_delay=10000000
pci_bus=0
@@ -1248,6 +1425,7 @@ pio=system.iobus.master[27]
[system.tsunami.fake_OROM]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8796093677568
pio_latency=100000
@@ -1265,6 +1443,7 @@ pio=system.iobus.master[8]
[system.tsunami.fake_ata0]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848432
pio_latency=100000
@@ -1282,6 +1461,7 @@ pio=system.iobus.master[19]
[system.tsunami.fake_ata1]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848304
pio_latency=100000
@@ -1299,6 +1479,7 @@ pio=system.iobus.master[20]
[system.tsunami.fake_pnp_addr]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848569
pio_latency=100000
@@ -1316,6 +1497,7 @@ pio=system.iobus.master[9]
[system.tsunami.fake_pnp_read0]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848451
pio_latency=100000
@@ -1333,6 +1515,7 @@ pio=system.iobus.master[11]
[system.tsunami.fake_pnp_read1]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848515
pio_latency=100000
@@ -1350,6 +1533,7 @@ pio=system.iobus.master[12]
[system.tsunami.fake_pnp_read2]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848579
pio_latency=100000
@@ -1367,6 +1551,7 @@ pio=system.iobus.master[13]
[system.tsunami.fake_pnp_read3]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848643
pio_latency=100000
@@ -1384,6 +1569,7 @@ pio=system.iobus.master[14]
[system.tsunami.fake_pnp_read4]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848707
pio_latency=100000
@@ -1401,6 +1587,7 @@ pio=system.iobus.master[15]
[system.tsunami.fake_pnp_read5]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848771
pio_latency=100000
@@ -1418,6 +1605,7 @@ pio=system.iobus.master[16]
[system.tsunami.fake_pnp_read6]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848835
pio_latency=100000
@@ -1435,6 +1623,7 @@ pio=system.iobus.master[17]
[system.tsunami.fake_pnp_read7]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848899
pio_latency=100000
@@ -1452,6 +1641,7 @@ pio=system.iobus.master[18]
[system.tsunami.fake_pnp_write]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615850617
pio_latency=100000
@@ -1469,6 +1659,7 @@ pio=system.iobus.master[10]
[system.tsunami.fake_ppc]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848891
pio_latency=100000
@@ -1486,6 +1677,7 @@ pio=system.iobus.master[7]
[system.tsunami.fake_sm_chip]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848816
pio_latency=100000
@@ -1503,6 +1695,7 @@ pio=system.iobus.master[2]
[system.tsunami.fake_uart1]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848696
pio_latency=100000
@@ -1520,6 +1713,7 @@ pio=system.iobus.master[3]
[system.tsunami.fake_uart2]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848936
pio_latency=100000
@@ -1537,6 +1731,7 @@ pio=system.iobus.master[4]
[system.tsunami.fake_uart3]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848680
pio_latency=100000
@@ -1554,6 +1749,7 @@ pio=system.iobus.master[5]
[system.tsunami.fake_uart4]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848944
pio_latency=100000
@@ -1572,6 +1768,7 @@ pio=system.iobus.master[6]
type=BadDevice
clk_domain=system.clk_domain
devicename=FrameBuffer
+eventq_index=0
pio_addr=8804615848912
pio_latency=100000
system=system
@@ -1599,6 +1796,7 @@ BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
+CapabilityPtr=0
CardbusCIS=0
ClassCode=1
Command=0
@@ -1608,8 +1806,40 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
MaximumLatency=0
MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
ProgIF=133
Revision=0
Status=640
@@ -1621,6 +1851,7 @@ clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=0
disks=system.disk0 system.disk2
+eventq_index=0
io_shift=0
pci_bus=0
pci_dev=0
@@ -1635,6 +1866,7 @@ pio=system.iobus.master[25]
[system.tsunami.io]
type=TsunamiIO
clk_domain=system.clk_domain
+eventq_index=0
frequency=976562500
pio_addr=8804615847936
pio_latency=100000
@@ -1647,6 +1879,7 @@ pio=system.iobus.master[22]
[system.tsunami.pchip]
type=TsunamiPChip
clk_domain=system.clk_domain
+eventq_index=0
pio_addr=8802535473152
pio_latency=100000
system=system
@@ -1657,6 +1890,7 @@ pio=system.iobus.master[1]
type=PciConfigAll
bus=0
clk_domain=system.clk_domain
+eventq_index=0
pio_addr=0
pio_latency=30000
platform=system.tsunami
@@ -1667,6 +1901,7 @@ pio=system.iobus.default
[system.tsunami.uart]
type=Uart8250
clk_domain=system.clk_domain
+eventq_index=0
pio_addr=8804615848952
pio_latency=100000
platform=system.tsunami
@@ -1676,5 +1911,6 @@ pio=system.iobus.master[23]
[system.voltage_domain]
type=VoltageDomain
+eventq_index=0
voltage=1.000000
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
index fc255dc72..3ddbcdbc7 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
@@ -1,138 +1,138 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.904665 # Number of seconds simulated
-sim_ticks 1904665099500 # Number of ticks simulated
-final_tick 1904665099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.903338 # Number of seconds simulated
+sim_ticks 1903338216000 # Number of ticks simulated
+final_tick 1903338216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 126318 # Simulator instruction rate (inst/s)
-host_op_rate 126318 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4285588150 # Simulator tick rate (ticks/s)
-host_mem_usage 339596 # Number of bytes of host memory used
-host_seconds 444.44 # Real time elapsed on the host
-sim_insts 56140339 # Number of instructions simulated
-sim_ops 56140339 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 734400 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24199744 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2650304 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 243008 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1012480 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28839936 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 734400 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 243008 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 977408 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7811840 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7811840 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 11475 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 378121 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41411 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 3797 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 15820 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 450624 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 122060 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 122060 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 385580 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12705511 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1391480 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 127586 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 531579 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15141736 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 385580 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 127586 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 513165 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4101424 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4101424 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4101424 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 385580 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12705511 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1391480 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 127586 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 531579 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19243160 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 450624 # Number of read requests accepted
-system.physmem.writeReqs 122060 # Number of write requests accepted
-system.physmem.readBursts 450624 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 122060 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 28836416 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 3520 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7811520 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 28839936 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7811840 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by the write queue
+host_inst_rate 100362 # Simulator instruction rate (inst/s)
+host_op_rate 100362 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3404824916 # Simulator tick rate (ticks/s)
+host_mem_usage 359096 # Number of bytes of host memory used
+host_seconds 559.01 # Real time elapsed on the host
+sim_insts 56103611 # Number of instructions simulated
+sim_ops 56103611 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 740992 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24346432 # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2650176 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 236544 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 996032 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28970176 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 740992 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 236544 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 977536 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7923904 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7923904 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 11578 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 380413 # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 41409 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 3696 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 15563 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 452659 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 123811 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 123811 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 389312 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12791438 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1392383 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 124278 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 523308 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15220719 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 389312 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 124278 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 513590 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4163161 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4163161 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4163161 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::total 19383880 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 452659 # Number of read requests accepted
+system.physmem.writeReqs 123811 # Number of write requests accepted
+system.physmem.readBursts 452659 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 123811 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 28966400 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 3776 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7923264 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 28970176 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7923904 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 59 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 3409 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 28171 # Per bank write bursts
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+system.physmem.neitherReadNorWriteReqs 3474 # Number of requests that are neither read nor write
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
-system.physmem.totGap 1904663535000 # Total gap between requests
+system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
+system.physmem.totGap 1903333578000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 450624 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 122060 # Write request sizes (log2)
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@@ -141,458 +141,451 @@ system.physmem.rdQLenPdf::28 0 # Wh
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system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::samples 46334 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 790.933310 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 228.010271 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 1879.334417 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-67 16305 35.19% 35.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-131 6714 14.49% 49.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-195 4888 10.55% 60.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-259 2813 6.07% 66.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-323 1747 3.77% 70.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-387 1443 3.11% 73.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-451 1071 2.31% 75.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-515 878 1.89% 77.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-579 653 1.41% 78.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-643 584 1.26% 80.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-707 640 1.38% 81.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-771 489 1.06% 82.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-835 295 0.64% 83.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-899 293 0.63% 83.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-963 217 0.47% 84.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1027 380 0.82% 85.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1091 150 0.32% 85.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1152-1155 199 0.43% 85.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1219 125 0.27% 86.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1283 135 0.29% 86.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1347 141 0.30% 86.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1411 397 0.86% 87.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1475 230 0.50% 88.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1539 690 1.49% 89.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1603 125 0.27% 89.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1667 87 0.19% 89.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1731 68 0.15% 90.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1792-1795 129 0.28% 90.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1856-1859 56 0.12% 90.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1923 91 0.20% 90.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1987 45 0.10% 90.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2051 78 0.17% 90.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2112-2115 66 0.14% 91.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2176-2179 92 0.20% 91.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2243 29 0.06% 91.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2304-2307 29 0.06% 91.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2368-2371 53 0.11% 91.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2435 51 0.11% 91.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2496-2499 26 0.06% 91.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2560-2563 27 0.06% 91.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2627 25 0.05% 91.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2691 53 0.11% 91.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2755 52 0.11% 92.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2816-2819 16 0.03% 92.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2880-2883 30 0.06% 92.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2944-2947 83 0.18% 92.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3008-3011 42 0.09% 92.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3072-3075 33 0.07% 92.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3136-3139 42 0.09% 92.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3203 86 0.19% 92.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3267 27 0.06% 92.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3328-3331 14 0.03% 92.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3392-3395 51 0.11% 92.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3456-3459 53 0.11% 93.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3520-3523 26 0.06% 93.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3584-3587 25 0.05% 93.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3648-3651 24 0.05% 93.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3712-3715 50 0.11% 93.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3776-3779 51 0.11% 93.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3840-3843 12 0.03% 93.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3904-3907 28 0.06% 93.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3968-3971 84 0.18% 93.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4032-4035 42 0.09% 93.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4160-4163 39 0.08% 93.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4224-4227 87 0.19% 94.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4291 25 0.05% 94.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4352-4355 14 0.03% 94.26% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::4480-4483 50 0.11% 94.49% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::4672-4675 23 0.05% 94.63% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::4992-4995 86 0.19% 95.11% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::5248-5251 84 0.18% 95.53% # Bytes accessed per row activation
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+system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see
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+system.physmem.bytesPerActivate::mean 782.856367 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::9856-9859 3 0.01% 99.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::11328-11331 2 0.00% 99.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::11584-11587 2 0.00% 99.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.44% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::11904-11907 2 0.00% 99.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13696-13699 2 0.00% 99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14211 5 0.01% 99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.52% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15363 38 0.08% 99.61% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.62% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::16384-16387 173 0.37% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 46334 # Bytes accessed per row activation
-system.physmem.totQLat 8608105750 # Total ticks spent queuing
-system.physmem.totMemAccLat 16109367000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2252845000 # Total ticks spent in databus transfers
-system.physmem.totBankLat 5248416250 # Total ticks spent accessing banks
-system.physmem.avgQLat 19104.97 # Average queueing delay per DRAM burst
-system.physmem.avgBankLat 11648.42 # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.53% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::16384-16387 175 0.37% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 47120 # Bytes accessed per row activation
+system.physmem.totQLat 8783315250 # Total ticks spent queuing
+system.physmem.totMemAccLat 16310447750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2263000000 # Total ticks spent in databus transfers
+system.physmem.totBankLat 5264132500 # Total ticks spent accessing banks
+system.physmem.avgQLat 19406.35 # Average queueing delay per DRAM burst
+system.physmem.avgBankLat 11630.87 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 35753.39 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 15.14 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 15.14 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 36037.22 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 15.22 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 4.16 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 15.22 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 4.16 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 10.81 # Average write queue length when enqueuing
-system.physmem.readRowHits 429097 # Number of row buffer hits during reads
-system.physmem.writeRowHits 97193 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 95.23 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 79.63 # Row buffer hit rate for writes
-system.physmem.avgGap 3325854.28 # Average gap between requests
-system.physmem.pageHitRate 91.91 # Row buffer hit rate, read and write combined
+system.physmem.avgWrQLen 9.32 # Average write queue length when enqueuing
+system.physmem.readRowHits 430734 # Number of row buffer hits during reads
+system.physmem.writeRowHits 98547 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 95.17 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 79.59 # Row buffer hit rate for writes
+system.physmem.avgGap 3301704.47 # Average gap between requests
+system.physmem.pageHitRate 91.82 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput 19299112 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 296504 # Transaction distribution
-system.membus.trans_dist::ReadResp 296255 # Transaction distribution
-system.membus.trans_dist::WriteReq 12358 # Transaction distribution
-system.membus.trans_dist::WriteResp 12358 # Transaction distribution
-system.membus.trans_dist::Writeback 122060 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 5288 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 1522 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 3409 # Transaction distribution
-system.membus.trans_dist::ReadExReq 162296 # Transaction distribution
-system.membus.trans_dist::ReadExResp 162161 # Transaction distribution
+system.membus.throughput 19439855 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 296479 # Transaction distribution
+system.membus.trans_dist::ReadResp 296230 # Transaction distribution
+system.membus.trans_dist::WriteReq 12351 # Transaction distribution
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+system.membus.trans_dist::Writeback 123811 # Transaction distribution
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+system.membus.trans_dist::UpgradeResp 3474 # Transaction distribution
+system.membus.trans_dist::ReadExReq 164353 # Transaction distribution
+system.membus.trans_dist::ReadExResp 164224 # Transaction distribution
system.membus.trans_dist::BadAddressError 249 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39102 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 909601 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39094 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 915454 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 498 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 949201 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124660 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 124660 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1073861 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68234 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31344192 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 31412426 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307584 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.iocache.mem_side::total 5307584 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 36720010 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 36720010 # Total data (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 955046 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124656 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 124656 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1079702 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68202 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31586624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total 31654826 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307456 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 5307456 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 36962282 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 36962282 # Total data (bytes)
system.membus.snoop_data_through_bus 38336 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 36331000 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 36252500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 1605524497 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 1624596499 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 312000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 317500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3818350840 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 3836772510 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 376337493 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 376321991 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.l2c.tags.replacements 343738 # number of replacements
-system.l2c.tags.tagsinuse 65291.635140 # Cycle average of tags in use
-system.l2c.tags.total_refs 2609074 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 408707 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 6.383727 # Average number of references to valid blocks.
+system.l2c.tags.replacements 345713 # number of replacements
+system.l2c.tags.tagsinuse 65292.619294 # Cycle average of tags in use
+system.l2c.tags.total_refs 2607692 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 410924 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 6.345923 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 7069563750 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 53622.087129 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 4120.650208 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 5604.001242 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 1368.077401 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 576.819161 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.818208 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.062876 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.085510 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.020875 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.008802 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.996271 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst 744945 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 568804 # number of ReadReq hits
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-system.l2c.ReadReq_hits::cpu1.data 253262 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1892383 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 840158 # number of Writeback hits
-system.l2c.Writeback_hits::total 840158 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 141 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 87 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 228 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 35 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits
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-system.l2c.ReadExReq_hits::total 190597 # number of ReadExReq hits
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-system.l2c.demand_hits::cpu0.data 712300 # number of demand (read+write) hits
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system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 1712302770000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide 0.224170 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide 0.014011 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.014011 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 177 # number of ReadReq misses
+system.iocache.tags.warmup_cycle 1712301131000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide 0.213166 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide 0.013323 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.013323 # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide 41729 # number of demand (read+write) misses
-system.iocache.demand_misses::total 41729 # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide 41729 # number of overall misses
-system.iocache.overall_misses::total 41729 # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide 21589383 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 21589383 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 12994516805 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 12994516805 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 13016106188 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 13016106188 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 13016106188 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 13016106188 # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
+system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
+system.iocache.overall_misses::total 41727 # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide 21368383 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 21368383 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 13021515788 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 13021515788 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 13042884171 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 13042884171 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 13042884171 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 13042884171 # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide 41729 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 41729 # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide 41729 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 41729 # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
@@ -771,40 +764,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121973.915254 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 121973.915254 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312729.033621 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 312729.033621 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 311919.916317 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 311919.916317 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 311919.916317 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 404619 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122105.045714 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 122105.045714 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 313378.797362 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 313378.797362 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 312576.609174 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 312576.609174 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 312576.609174 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 312576.609174 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 407057 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 29217 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 29358 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 13.848752 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 13.865284 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12384383 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 12384383 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10832260819 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 10832260819 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 10844645202 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 10844645202 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 10844645202 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 10844645202 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12267383 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 12267383 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10859254806 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 10859254806 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 10871522189 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 10871522189 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 10871522189 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 10871522189 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
@@ -813,14 +806,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69968.265537 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 69968.265537 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260691.683168 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 260691.683168 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259882.700328 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 259882.700328 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70099.331429 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70099.331429 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 261341.326675 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 261341.326675 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 260539.271671 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 260539.271671 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 260539.271671 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 260539.271671 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
@@ -834,35 +827,35 @@ system.disk2.dma_read_txs 0 # Nu
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 10889682 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 9229516 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 284462 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 7161619 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 4680131 # Number of BTB hits
+system.cpu0.branchPred.lookups 11006012 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 9319545 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 291548 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 7161716 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 4729334 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 65.350181 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 674122 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 25966 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 66.036324 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 682987 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 26515 # Number of incorrect RAS predictions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 7794998 # DTB read hits
-system.cpu0.dtb.read_misses 29740 # DTB read misses
-system.cpu0.dtb.read_acv 552 # DTB read access violations
-system.cpu0.dtb.read_accesses 624038 # DTB read accesses
-system.cpu0.dtb.write_hits 5176736 # DTB write hits
-system.cpu0.dtb.write_misses 7776 # DTB write misses
-system.cpu0.dtb.write_acv 327 # DTB write access violations
-system.cpu0.dtb.write_accesses 207382 # DTB write accesses
-system.cpu0.dtb.data_hits 12971734 # DTB hits
-system.cpu0.dtb.data_misses 37516 # DTB misses
-system.cpu0.dtb.data_acv 879 # DTB access violations
-system.cpu0.dtb.data_accesses 831420 # DTB accesses
-system.cpu0.itb.fetch_hits 929400 # ITB hits
-system.cpu0.itb.fetch_misses 28175 # ITB misses
-system.cpu0.itb.fetch_acv 908 # ITB acv
-system.cpu0.itb.fetch_accesses 957575 # ITB accesses
+system.cpu0.dtb.read_hits 7888949 # DTB read hits
+system.cpu0.dtb.read_misses 30101 # DTB read misses
+system.cpu0.dtb.read_acv 574 # DTB read access violations
+system.cpu0.dtb.read_accesses 665608 # DTB read accesses
+system.cpu0.dtb.write_hits 5247941 # DTB write hits
+system.cpu0.dtb.write_misses 8093 # DTB write misses
+system.cpu0.dtb.write_acv 365 # DTB write access violations
+system.cpu0.dtb.write_accesses 232480 # DTB write accesses
+system.cpu0.dtb.data_hits 13136890 # DTB hits
+system.cpu0.dtb.data_misses 38194 # DTB misses
+system.cpu0.dtb.data_acv 939 # DTB access violations
+system.cpu0.dtb.data_accesses 898088 # DTB accesses
+system.cpu0.itb.fetch_hits 973403 # ITB hits
+system.cpu0.itb.fetch_misses 31216 # ITB misses
+system.cpu0.itb.fetch_acv 1004 # ITB acv
+system.cpu0.itb.fetch_accesses 1004619 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
@@ -875,269 +868,269 @@ system.cpu0.itb.data_hits 0 # DT
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 103787820 # number of cpu cycles simulated
+system.cpu0.numCycles 104578589 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 21704485 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 55964987 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 10889682 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 5354253 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 10541115 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1495269 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 32108430 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 29198 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 196165 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 243475 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 129 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 6808420 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 194219 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 65778101 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.850815 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.187217 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 21960114 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 56555379 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 11006012 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 5412321 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 10656012 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1518801 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 32354382 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 30030 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 204805 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 243991 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 6896028 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 198863 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 66418859 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.851496 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.187669 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 55236986 83.97% 83.97% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 687368 1.04% 85.02% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 1350712 2.05% 87.07% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 596944 0.91% 87.98% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 2343219 3.56% 91.54% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 450390 0.68% 92.23% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 484863 0.74% 92.96% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 769593 1.17% 94.13% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 3858026 5.87% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 55762847 83.96% 83.96% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 696881 1.05% 85.01% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 1363707 2.05% 87.06% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 607827 0.92% 87.97% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 2362378 3.56% 91.53% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 460793 0.69% 92.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 493104 0.74% 92.97% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 775074 1.17% 94.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 3896248 5.87% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 65778101 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.104923 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.539225 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 22868260 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 31583202 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 9551685 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 850413 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 924540 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 430365 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 30891 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 54921627 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 95919 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 924540 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 23764379 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 12229388 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 16273784 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 8983229 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 3602779 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 51919548 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 6908 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 427524 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1365609 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 34775855 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 63273064 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 63154051 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 110251 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 30610760 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 4165087 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1306243 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 192817 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 9794386 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 8157712 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5414054 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 996311 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 651476 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 46072688 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1607529 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 45052642 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 77910 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 5101692 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 2707567 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 1088536 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 65778101 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.684919 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.328831 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 66418859 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.105242 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.540793 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 23145338 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 31820288 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 9657130 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 858074 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 938028 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 439220 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 31710 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 55497748 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 98418 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 938028 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 24047696 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 12280609 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 16434779 # count of cycles rename stalled for serializing inst
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+system.cpu0.rename.UnblockCycles 3628542 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 52477613 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 6876 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 427894 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1374075 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands 35152162 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 63950241 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 63830636 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 110747 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 30925813 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 4226341 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1321793 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 195129 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 9844333 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 8256385 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5476723 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1002198 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 667476 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 46574896 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1622063 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 45553168 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 69417 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 5159281 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 2712846 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 1098313 # Number of squashed non-spec instructions that were removed
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+system.cpu0.iq.issued_per_cycle::mean 0.685847 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.329893 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 45611929 69.34% 69.34% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 9242272 14.05% 83.39% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 4206709 6.40% 89.79% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2691383 4.09% 93.88% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2059923 3.13% 97.01% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1077701 1.64% 98.65% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 567124 0.86% 99.51% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 276618 0.42% 99.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 44442 0.07% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 46042875 69.32% 69.32% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 9328009 14.04% 83.37% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 4252197 6.40% 89.77% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2720710 4.10% 93.86% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2085310 3.14% 97.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1089347 1.64% 98.64% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 576580 0.87% 99.51% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 279468 0.42% 99.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 44363 0.07% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 65778101 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 66418859 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 64943 10.84% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 279384 46.63% 57.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 254855 42.53% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 65077 10.66% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 10.66% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.66% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.66% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 284948 46.66% 57.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 260601 42.68% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 3777 0.01% 0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 30907747 68.60% 68.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 47065 0.10% 68.72% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.72% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 14613 0.03% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 8107891 18.00% 86.75% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5235503 11.62% 98.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess 734167 1.63% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 31229788 68.56% 68.57% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 47289 0.10% 68.67% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.67% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 14649 0.03% 68.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 8205422 18.01% 86.72% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5307142 11.65% 98.37% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess 743210 1.63% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 45052642 # Type of FU issued
-system.cpu0.iq.rate 0.434084 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 599182 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.013300 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 156086675 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 52562386 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 44135345 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 473801 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 230205 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 223474 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 45400371 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 247676 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 493959 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 45553168 # Type of FU issued
+system.cpu0.iq.rate 0.435588 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 610626 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.013405 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 157729759 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 53136035 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 44625486 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 475478 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 231159 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 224228 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 45911492 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 248517 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 497947 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 994643 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 3486 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 10933 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 382957 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1006840 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3517 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 11189 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 378910 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 13548 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 145981 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 13584 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 146356 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 924540 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 8545801 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 700799 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 50460891 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 559365 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 8157712 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5414054 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 1419298 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 572111 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 4914 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 10933 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 138244 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 310094 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 448338 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 44721018 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 7845228 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 331623 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 938028 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 8572601 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 702117 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 50999649 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 565079 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 8256385 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 5476723 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 1432117 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 572819 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 5269 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 11189 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 141170 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 315582 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 456752 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 45215846 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 7939970 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 337321 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 2780674 # number of nop insts executed
-system.cpu0.iew.exec_refs 13041346 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 7066025 # Number of branches executed
-system.cpu0.iew.exec_stores 5196118 # Number of stores executed
-system.cpu0.iew.exec_rate 0.430889 # Inst execution rate
-system.cpu0.iew.wb_sent 44442278 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 44358819 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 22095606 # num instructions producing a value
-system.cpu0.iew.wb_consumers 29563187 # num instructions consuming a value
+system.cpu0.iew.exec_nop 2802690 # number of nop insts executed
+system.cpu0.iew.exec_refs 13207799 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 7146234 # Number of branches executed
+system.cpu0.iew.exec_stores 5267829 # Number of stores executed
+system.cpu0.iew.exec_rate 0.432362 # Inst execution rate
+system.cpu0.iew.wb_sent 44934571 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 44849714 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 22315831 # num instructions producing a value
+system.cpu0.iew.wb_consumers 29845824 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.427399 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.747403 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.428861 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.747704 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 5494607 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 518993 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 418437 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 64853561 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.691924 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.608025 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 5562563 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 523750 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 426483 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 65480831 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.692465 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.608721 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 47955107 73.94% 73.94% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 7091089 10.93% 84.88% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 3807248 5.87% 90.75% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 2121571 3.27% 94.02% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1151711 1.78% 95.80% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 474089 0.73% 96.53% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 405970 0.63% 97.15% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 383893 0.59% 97.74% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1462883 2.26% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 48404249 73.92% 73.92% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 7174588 10.96% 84.88% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 3839849 5.86% 90.74% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 2141053 3.27% 94.01% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1161993 1.77% 95.79% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 481151 0.73% 96.52% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 411214 0.63% 97.15% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 389126 0.59% 97.74% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1477608 2.26% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 64853561 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 44873722 # Number of instructions committed
-system.cpu0.commit.committedOps 44873722 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 65480831 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 45343202 # Number of instructions committed
+system.cpu0.commit.committedOps 45343202 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 12194166 # Number of memory references committed
-system.cpu0.commit.loads 7163069 # Number of loads committed
-system.cpu0.commit.membars 173899 # Number of memory barriers committed
-system.cpu0.commit.branches 6736138 # Number of branches committed
-system.cpu0.commit.fp_insts 221634 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 41596674 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 557213 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1462883 # number cycles where commit BW limit reached
+system.cpu0.commit.refs 12347358 # Number of memory references committed
+system.cpu0.commit.loads 7249545 # Number of loads committed
+system.cpu0.commit.membars 175312 # Number of memory barriers committed
+system.cpu0.commit.branches 6808554 # Number of branches committed
+system.cpu0.commit.fp_insts 222342 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 42040123 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 564734 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1477608 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 113567039 # The number of ROB reads
-system.cpu0.rob.rob_writes 101661188 # The number of ROB writes
-system.cpu0.timesIdled 942687 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 38009719 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 3705537551 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 42330060 # Number of Instructions Simulated
-system.cpu0.committedOps 42330060 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 42330060 # Number of Instructions Simulated
-system.cpu0.cpi 2.451870 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.451870 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.407852 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.407852 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 58864464 # number of integer regfile reads
-system.cpu0.int_regfile_writes 32110567 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 109878 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 110737 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 1513799 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 739168 # number of misc regfile writes
+system.cpu0.rob.rob_reads 114710793 # The number of ROB reads
+system.cpu0.rob.rob_writes 102749676 # The number of ROB writes
+system.cpu0.timesIdled 949561 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 38159730 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 3702093008 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 42781436 # Number of Instructions Simulated
+system.cpu0.committedOps 42781436 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 42781436 # Number of Instructions Simulated
+system.cpu0.cpi 2.444485 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.444485 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.409084 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.409084 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 59516377 # number of integer regfile reads
+system.cpu0.int_regfile_writes 32453910 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 110308 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 111090 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 1526243 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 747832 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
@@ -1169,49 +1162,49 @@ system.tsunami.ethernet.totalRxOrn 0 # to
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.throughput 112875870 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 2213010 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2212746 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 12358 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 12358 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 840158 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 5353 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 1588 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 6941 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 354001 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 312453 # Transaction distribution
+system.toL2Bus.throughput 112873708 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2210500 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2210236 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 12351 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 12351 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 840492 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 5351 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 1545 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 6896 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 353777 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 312228 # Transaction distribution
system.toL2Bus.trans_dist::BadAddressError 249 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1512954 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2808902 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 658389 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 920655 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 5900900 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 48411392 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 107554025 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21067456 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 36346017 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 213378890 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 213368266 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 1622464 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 5059270351 # Layer occupancy (ticks)
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1532372 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2827999 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 634560 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 901176 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5896107 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 49032512 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 108336621 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20304832 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 35573309 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 213247274 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 213236842 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 1600000 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 5059383343 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 747000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 733500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 3408360184 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 3452114362 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 5017953643 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 5048329138 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 1482953497 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 1429282335 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 1519289016 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 1486623569 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%)
-system.iobus.throughput 1433257 # Throughput (bytes/s)
-system.iobus.trans_dist::ReadReq 7370 # Transaction distribution
-system.iobus.trans_dist::ReadResp 7370 # Transaction distribution
-system.iobus.trans_dist::WriteReq 53910 # Transaction distribution
-system.iobus.trans_dist::WriteResp 53910 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10510 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 468 # Packet count per connected master and slave (bytes)
+system.iobus.throughput 1434231 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 7371 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7371 # Transaction distribution
+system.iobus.trans_dist::WriteReq 53903 # Transaction distribution
+system.iobus.trans_dist::WriteResp 53903 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10490 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
@@ -1222,12 +1215,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 39102 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 122560 # Packet count per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42040 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1872 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 39094 # Packet count per connected master and slave (bytes)
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@@ -1238,14 +1231,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf
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@@ -1265,253 +1258,253 @@ system.iobus.reqLayer27.occupancy 76000 # La
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu0.dcache.demand_mshr_miss_latency::total 35871716472 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35871716472 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 35871716472 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 993486001 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 993486001 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1673832998 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1673832998 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2667318999 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2667318999 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117783 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117783 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052229 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052229 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.076170 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.076170 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004359 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004359 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091006 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.091006 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091006 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.091006 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29730.024473 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29730.024473 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42787.527981 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42787.527981 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11874.922248 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11874.922248 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4213.930628 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4213.930628 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32791.121748 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32791.121748 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32791.121748 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32791.121748 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
@@ -1519,35 +1512,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 4005476 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 3286567 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 126561 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 2463252 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 1409799 # Number of BTB hits
+system.cpu1.branchPred.lookups 3875512 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 3181518 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 119538 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 2413999 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 1363069 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 57.233243 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 290076 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 11654 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 56.465185 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 281270 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 11131 # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 2861061 # DTB read hits
-system.cpu1.dtb.read_misses 13171 # DTB read misses
-system.cpu1.dtb.read_acv 26 # DTB read access violations
-system.cpu1.dtb.read_accesses 327320 # DTB read accesses
-system.cpu1.dtb.write_hits 1771736 # DTB write hits
-system.cpu1.dtb.write_misses 2413 # DTB write misses
-system.cpu1.dtb.write_acv 61 # DTB write access violations
-system.cpu1.dtb.write_accesses 133954 # DTB write accesses
-system.cpu1.dtb.data_hits 4632797 # DTB hits
-system.cpu1.dtb.data_misses 15584 # DTB misses
-system.cpu1.dtb.data_acv 87 # DTB access violations
-system.cpu1.dtb.data_accesses 461274 # DTB accesses
-system.cpu1.itb.fetch_hits 484886 # ITB hits
-system.cpu1.itb.fetch_misses 6783 # ITB misses
-system.cpu1.itb.fetch_acv 213 # ITB acv
-system.cpu1.itb.fetch_accesses 491669 # ITB accesses
+system.cpu1.dtb.read_hits 2756439 # DTB read hits
+system.cpu1.dtb.read_misses 11971 # DTB read misses
+system.cpu1.dtb.read_acv 6 # DTB read access violations
+system.cpu1.dtb.read_accesses 281635 # DTB read accesses
+system.cpu1.dtb.write_hits 1697476 # DTB write hits
+system.cpu1.dtb.write_misses 2261 # DTB write misses
+system.cpu1.dtb.write_acv 35 # DTB write access violations
+system.cpu1.dtb.write_accesses 106637 # DTB write accesses
+system.cpu1.dtb.data_hits 4453915 # DTB hits
+system.cpu1.dtb.data_misses 14232 # DTB misses
+system.cpu1.dtb.data_acv 41 # DTB access violations
+system.cpu1.dtb.data_accesses 388272 # DTB accesses
+system.cpu1.itb.fetch_hits 435796 # ITB hits
+system.cpu1.itb.fetch_misses 5916 # ITB misses
+system.cpu1.itb.fetch_acv 132 # ITB acv
+system.cpu1.itb.fetch_accesses 441712 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
@@ -1560,508 +1553,508 @@ system.cpu1.itb.data_hits 0 # DT
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 26365345 # number of cpu cycles simulated
+system.cpu1.numCycles 25703316 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 8788859 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 19229785 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 4005476 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 1699875 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 3495206 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 620790 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 10702778 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 24531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 65519 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 161249 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 2272198 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 84032 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 23644267 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.813296 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.175765 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 8513027 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 18550498 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 3875512 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 1644339 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 3370867 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 594419 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 10509044 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 24053 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 56236 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 158916 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 118 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 2181303 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 77306 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 23021613 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.805786 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.167146 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 20149061 85.22% 85.22% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 201364 0.85% 86.07% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 434975 1.84% 87.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 271433 1.15% 89.06% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 534220 2.26% 91.32% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 181805 0.77% 92.09% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 209247 0.88% 92.97% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 254511 1.08% 94.05% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 1407651 5.95% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 19650746 85.36% 85.36% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 192109 0.83% 86.19% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 424155 1.84% 88.03% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 258878 1.12% 89.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 512227 2.22% 91.38% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 176251 0.77% 92.15% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 202668 0.88% 93.03% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 249358 1.08% 94.11% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 1355221 5.89% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 23644267 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.151922 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.729358 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 8879389 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 10928600 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 3243065 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 199967 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 393245 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 183870 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 12999 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 18844715 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 38529 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 393245 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 9206755 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 3122476 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 6754638 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 3034107 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 1133044 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 17630254 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 270 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 267231 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 248854 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 11666322 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 21081705 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 21016911 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 58919 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 9884504 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 1781818 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 561630 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 56869 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 3357033 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 3030330 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 1870850 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 319037 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 184061 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 15497472 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 666578 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 15021403 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 38685 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 2244261 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 1133404 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 478003 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 23644267 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.635308 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.316901 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 23021613 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.150779 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.721716 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 8599650 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 10723354 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 3129491 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 191921 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 377196 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 176309 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 12258 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 18185515 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 36387 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 377196 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 8917984 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 3106321 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 6595327 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 2921217 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 1103566 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 17011608 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 230 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 267059 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 236234 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands 11254383 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 20310939 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 20246817 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 58360 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 9542826 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 1711557 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 544600 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 54677 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 3272980 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 2918733 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 1792509 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 312208 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 170960 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 14943030 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 650638 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 14484391 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 37394 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 2166782 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 1088105 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 467114 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 23021613 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.629165 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.310842 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 17155384 72.56% 72.56% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 2869349 12.14% 84.69% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 1269974 5.37% 90.06% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 909350 3.85% 93.91% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 787037 3.33% 97.24% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 325991 1.38% 98.62% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 202457 0.86% 99.47% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 106589 0.45% 99.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 18136 0.08% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 16750827 72.76% 72.76% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 2784830 12.10% 84.86% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 1224236 5.32% 90.18% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 874900 3.80% 93.98% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 759442 3.30% 97.27% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 313710 1.36% 98.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 192948 0.84% 99.48% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 103377 0.45% 99.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 17343 0.08% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 23644267 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 23021613 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 18902 7.17% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 136410 51.75% 58.92% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 108303 41.08% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 19111 7.55% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.55% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 130840 51.68% 59.23% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 103199 40.77% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 3526 0.02% 0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 9862540 65.66% 65.68% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 23545 0.16% 65.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.84% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 11158 0.07% 65.91% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.91% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.91% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.91% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 1763 0.01% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 2986833 19.88% 85.81% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 1799237 11.98% 97.78% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess 332801 2.22% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 9521262 65.73% 65.76% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 23052 0.16% 65.92% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.92% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 11116 0.08% 65.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.99% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 2876494 19.86% 85.87% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 1724250 11.90% 97.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess 322940 2.23% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 15021403 # Type of FU issued
-system.cpu1.iq.rate 0.569740 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 263615 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.017549 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 53759316 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 18299643 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 14636122 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 230057 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 112007 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 108764 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 15161393 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 120099 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 139894 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 14484391 # Type of FU issued
+system.cpu1.iq.rate 0.563522 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 253150 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.017477 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 52052620 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 17652734 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 14115090 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 228319 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 110924 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 107745 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 14614655 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 119368 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 134347 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 437460 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 1072 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 3446 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 176357 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 418294 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 981 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 3304 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 169372 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 5243 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 21515 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 5236 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 20861 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 393245 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 2412385 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 142199 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 17062579 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 198140 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 3030330 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 1870850 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 597759 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 52684 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 2595 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 3446 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 61011 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 139338 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 200349 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 14878419 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 2882425 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 142984 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 377196 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 2407064 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 140680 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 16469424 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 189598 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 2918733 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 1792509 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 583051 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 52184 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 2431 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 3304 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 57543 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 133828 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 191371 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 14348807 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 2776029 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 135584 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 898529 # number of nop insts executed
-system.cpu1.iew.exec_refs 4662637 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 2338044 # Number of branches executed
-system.cpu1.iew.exec_stores 1780212 # Number of stores executed
-system.cpu1.iew.exec_rate 0.564317 # Inst execution rate
-system.cpu1.iew.wb_sent 14784457 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 14744886 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 7139948 # num instructions producing a value
-system.cpu1.iew.wb_consumers 10043269 # num instructions consuming a value
+system.cpu1.iew.exec_nop 875756 # number of nop insts executed
+system.cpu1.iew.exec_refs 4481633 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 2254475 # Number of branches executed
+system.cpu1.iew.exec_stores 1705604 # Number of stores executed
+system.cpu1.iew.exec_rate 0.558247 # Inst execution rate
+system.cpu1.iew.wb_sent 14259530 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 14222835 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 6903248 # num instructions producing a value
+system.cpu1.iew.wb_consumers 9726426 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.559253 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.710919 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.553346 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.709741 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 2396118 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 188575 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 186792 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 23251022 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.628108 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.559407 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 2312839 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 183524 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 178531 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 22644417 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.622505 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.551942 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 17812881 76.61% 76.61% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 2343231 10.08% 86.69% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 1160626 4.99% 91.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 598215 2.57% 94.25% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 379804 1.63% 95.89% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 180518 0.78% 96.66% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 173796 0.75% 97.41% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 135154 0.58% 97.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 466797 2.01% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 17386197 76.78% 76.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 2263939 10.00% 86.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 1130304 4.99% 91.77% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 578693 2.56% 94.32% # Number of insts commited each cycle
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system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
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system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
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-system.cpu1.commit.int_insts 13494360 # Number of committed integer instructions.
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system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu1.quiesceCycles 3782349185 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 13810279 # Number of Instructions Simulated
-system.cpu1.committedOps 13810279 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 13810279 # Number of Instructions Simulated
-system.cpu1.cpi 1.909110 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.909110 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.523804 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.523804 # IPC: Total IPC of All Threads
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-system.cpu1.icache.tags.occ_percent::total 0.984863 # Average percentage of cache occupancy
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-system.cpu1.icache.overall_hits::total 1927863 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 344335 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 344335 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 344335 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 344335 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 344335 # number of overall misses
-system.cpu1.icache.overall_misses::total 344335 # number of overall misses
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-system.cpu1.icache.ReadReq_avg_miss_latency::total 13984.040289 # average ReadReq miss latency
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-system.cpu1.icache.demand_avg_miss_latency::total 13984.040289 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13984.040289 # average overall miss latency
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+system.cpu1.committedInsts 13322175 # Number of Instructions Simulated
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+system.cpu1.committedInsts_total 13322175 # Number of Instructions Simulated
+system.cpu1.cpi 1.929363 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 1.929363 # CPI: Total CPI of All Threads
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+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14018.125048 # average overall miss latency
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system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu1.icache.ReadReq_mshr_misses::total 329210 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 329210 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 329210 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 329210 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 329210 # number of overall MSHR misses
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-system.cpu1.icache.ReadReq_mshr_miss_latency::total 3979739752 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3979739752 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 3979739752 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3979739752 # number of overall MSHR miss cycles
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-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12088.757182 # average overall mshr miss latency
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+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 12108.662903 # average overall mshr miss latency
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-system.cpu1.dcache.StoreCondReq_hits::total 46255 # number of StoreCondReq hits
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-system.cpu1.dcache.LoadLockedReq_misses::total 7995 # number of LoadLockedReq misses
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system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70443003 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4174394 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4174394 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5410381808 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 5410381808 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5410381808 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 5410381808 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 489946000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 489946000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 936242002 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 936242002 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1426188002 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1426188002 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.103165 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.103165 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038387 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038387 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128362 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128362 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.017286 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.017286 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.078515 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.078515 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.078515 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.078515 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12803.485036 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12803.485036 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33713.570367 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33713.570367 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11163.708875 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11163.708875 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5344.934699 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5344.934699 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16693.814493 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16693.814493 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16693.814493 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16693.814493 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
@@ -2070,170 +2063,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 4829 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 164539 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 56531 39.74% 39.74% # number of times we switched to this ipl
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-system.cpu0.kern.ipl_count::22 1925 1.35% 41.18% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 16 0.01% 41.20% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 83653 58.80% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 142256 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 55584 49.09% 49.09% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 131 0.12% 49.21% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1925 1.70% 50.91% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 16 0.01% 50.92% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 55568 49.08% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 113224 # number of times we switched to this ipl from a different ipl
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-system.cpu0.kern.ipl_ticks::21 62415000 0.00% 98.02% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 563852000 0.03% 98.05% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 8731500 0.00% 98.05% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 37224635500 1.95% 100.00% # number of cycles we spent at this ipl
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system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
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-system.cpu0.kern.ipl_used::total 0.795917 # fraction of swpipl calls that actually changed the ipl
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-system.cpu0.kern.syscall::59 5 2.48% 74.26% # number of syscalls executed
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-system.cpu0.kern.syscall::73 3 1.49% 88.12% # number of syscalls executed
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system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 108 0.07% 0.07% # number of callpals executed
+system.cpu0.kern.callpal::wripir 104 0.07% 0.07% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 2969 1.98% 2.05% # number of callpals executed
-system.cpu0.kern.callpal::tbi 48 0.03% 2.09% # number of callpals executed
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-system.cpu0.kern.callpal::swpipl 135909 90.65% 92.74% # number of callpals executed
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-system.cpu0.kern.callpal::total 149930 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 6311 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1258 # number of protection mode switches
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system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1257
-system.cpu0.kern.mode_good::user 1258
+system.cpu0.kern.mode_good::kernel 1342
+system.cpu0.kern.mode_good::user 1343
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.199176 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.208515 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.332276 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1902741106000 99.90% 99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 1923139500 0.10% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.345160 # fraction of useful protection mode switches
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system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 2970 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3011 # number of times the context was actually changed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 3864 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 73072 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 25114 39.08% 39.08% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1924 2.99% 42.08% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 108 0.17% 42.25% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 37111 57.75% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 64257 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 24684 48.12% 48.12% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1924 3.75% 51.88% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 108 0.21% 52.09% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 24576 47.91% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 51292 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1870089135500 98.20% 98.20% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 533638000 0.03% 98.23% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 50840000 0.00% 98.23% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 33685568500 1.77% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1904359182000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.982878 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 3850 # number of quiesce instructions executed
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+system.cpu1.kern.ipl_count::30 104 0.16% 42.13% # number of times we switched to this ipl
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+system.cpu1.kern.ipl_good::22 1923 3.83% 51.92% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 104 0.21% 52.12% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 24033 47.88% 100.00% # number of times we switched to this ipl from a different ipl
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+system.cpu1.kern.ipl_ticks::0 1869107624500 98.20% 98.20% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 533184500 0.03% 98.23% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 48972500 0.00% 98.23% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 33633158500 1.77% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1903322940000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.982497 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.662230 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.798232 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::2 1 0.81% 0.81% # number of syscalls executed
-system.cpu1.kern.syscall::3 14 11.29% 12.10% # number of syscalls executed
-system.cpu1.kern.syscall::6 13 10.48% 22.58% # number of syscalls executed
-system.cpu1.kern.syscall::15 1 0.81% 23.39% # number of syscalls executed
-system.cpu1.kern.syscall::17 6 4.84% 28.23% # number of syscalls executed
-system.cpu1.kern.syscall::19 3 2.42% 30.65% # number of syscalls executed
-system.cpu1.kern.syscall::20 2 1.61% 32.26% # number of syscalls executed
-system.cpu1.kern.syscall::23 3 2.42% 34.68% # number of syscalls executed
-system.cpu1.kern.syscall::24 3 2.42% 37.10% # number of syscalls executed
-system.cpu1.kern.syscall::33 4 3.23% 40.32% # number of syscalls executed
-system.cpu1.kern.syscall::45 20 16.13% 56.45% # number of syscalls executed
-system.cpu1.kern.syscall::47 3 2.42% 58.87% # number of syscalls executed
-system.cpu1.kern.syscall::48 2 1.61% 60.48% # number of syscalls executed
-system.cpu1.kern.syscall::54 1 0.81% 61.29% # number of syscalls executed
-system.cpu1.kern.syscall::59 2 1.61% 62.90% # number of syscalls executed
-system.cpu1.kern.syscall::71 29 23.39% 86.29% # number of syscalls executed
-system.cpu1.kern.syscall::74 10 8.06% 94.35% # number of syscalls executed
-system.cpu1.kern.syscall::90 1 0.81% 95.16% # number of syscalls executed
-system.cpu1.kern.syscall::92 2 1.61% 96.77% # number of syscalls executed
-system.cpu1.kern.syscall::132 3 2.42% 99.19% # number of syscalls executed
-system.cpu1.kern.syscall::144 1 0.81% 100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total 124 # number of syscalls executed
+system.cpu1.kern.ipl_used::31 0.657916 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.795225 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed
+system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed
+system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed
+system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed
+system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed
+system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed
+system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed
+system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed
+system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed
+system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed
+system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed
+system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed
+system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total 101 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu1.kern.callpal::wripir 16 0.02% 0.03% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 1277 1.92% 1.95% # number of callpals executed
-system.cpu1.kern.callpal::tbi 6 0.01% 1.96% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.01% 1.97% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 59282 89.28% 91.25% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2633 3.97% 95.21% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 95.21% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 4 0.01% 95.22% # number of callpals executed
-system.cpu1.kern.callpal::rdusp 1 0.00% 95.22% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.00% 95.23% # number of callpals executed
-system.cpu1.kern.callpal::rti 2942 4.43% 99.66% # number of callpals executed
-system.cpu1.kern.callpal::callsys 184 0.28% 99.93% # number of callpals executed
-system.cpu1.kern.callpal::imb 43 0.06% 100.00% # number of callpals executed
+system.cpu1.kern.callpal::swpctx 1228 1.89% 1.92% # number of callpals executed
+system.cpu1.kern.callpal::tbi 3 0.00% 1.92% # number of callpals executed
+system.cpu1.kern.callpal::wrent 7 0.01% 1.93% # number of callpals executed
+system.cpu1.kern.callpal::swpipl 58251 89.62% 91.55% # number of callpals executed
+system.cpu1.kern.callpal::rdps 2464 3.79% 95.34% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp 1 0.00% 95.34% # number of callpals executed
+system.cpu1.kern.callpal::wrusp 4 0.01% 95.35% # number of callpals executed
+system.cpu1.kern.callpal::whami 3 0.00% 95.35% # number of callpals executed
+system.cpu1.kern.callpal::rti 2844 4.38% 99.73% # number of callpals executed
+system.cpu1.kern.callpal::callsys 133 0.20% 99.93% # number of callpals executed
+system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 66403 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 1747 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 488 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2062 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 557
-system.cpu1.kern.mode_good::user 488
-system.cpu1.kern.mode_good::idle 69
-system.cpu1.kern.mode_switch_good::kernel 0.318832 # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total 65000 # number of callpals executed
+system.cpu1.kern.mode_switch::kernel 1608 # number of protection mode switches
+system.cpu1.kern.mode_switch::user 397 # number of protection mode switches
+system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches
+system.cpu1.kern.mode_good::kernel 463
+system.cpu1.kern.mode_good::user 397
+system.cpu1.kern.mode_good::idle 66
+system.cpu1.kern.mode_switch_good::kernel 0.287935 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.033463 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 0.259251 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 38709369000 2.03% 2.03% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 835914500 0.04% 2.08% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1864803541000 97.92% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 1278 # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle 0.032132 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total 0.228135 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel 38501499500 2.02% 2.02% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user 724848000 0.04% 2.06% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle 1863406690000 97.94% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 1229 # number of times the context was actually changed
---------- End Simulation Statistics ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index 4bc22a482..275c9f168 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
+eventq_index=0
full_system=true
+sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -13,15 +15,16 @@ boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/dist/m5/system/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
+eventq_index=0
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
@@ -39,6 +42,7 @@ system_port=system.membus.slave[0]
type=Bridge
clk_domain=system.clk_domain
delay=50000
+eventq_index=0
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
@@ -48,6 +52,7 @@ slave=system.membus.master[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -79,6 +84,8 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
+eventq_index=0
+fetchBufferSize=64
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -143,6 +150,7 @@ BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
+eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
@@ -158,6 +166,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -180,26 +189,31 @@ type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
size=32768
[system.cpu.dtb]
type=AlphaTLB
+eventq_index=0
size=64
[system.cpu.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
count=6
+eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
[system.cpu.fuPool.FUList0.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
@@ -208,16 +222,19 @@ opLat=1
type=FUDesc
children=opList0 opList1
count=2
+eventq_index=0
opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
+eventq_index=0
issueLat=19
opClass=IntDiv
opLat=20
@@ -226,22 +243,26 @@ opLat=20
type=FUDesc
children=opList0 opList1 opList2
count=4
+eventq_index=0
opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu.fuPool.FUList2.opList1]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu.fuPool.FUList2.opList2]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=2
@@ -250,22 +271,26 @@ opLat=2
type=FUDesc
children=opList0 opList1 opList2
count=2
+eventq_index=0
opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
+eventq_index=0
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu.fuPool.FUList3.opList2]
type=OpDesc
+eventq_index=0
issueLat=24
opClass=FloatSqrt
opLat=24
@@ -274,10 +299,12 @@ opLat=24
type=FUDesc
children=opList
count=0
+eventq_index=0
opList=system.cpu.fuPool.FUList4.opList
[system.cpu.fuPool.FUList4.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
@@ -286,124 +313,145 @@ opLat=1
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
+eventq_index=0
opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
[system.cpu.fuPool.FUList5.opList00]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu.fuPool.FUList5.opList01]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu.fuPool.FUList5.opList02]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu.fuPool.FUList5.opList03]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu.fuPool.FUList5.opList04]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu.fuPool.FUList5.opList05]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu.fuPool.FUList5.opList06]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu.fuPool.FUList5.opList07]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList08]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu.fuPool.FUList5.opList09]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu.fuPool.FUList5.opList10]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu.fuPool.FUList5.opList11]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu.fuPool.FUList5.opList12]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu.fuPool.FUList5.opList13]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu.fuPool.FUList5.opList14]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu.fuPool.FUList5.opList15]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu.fuPool.FUList5.opList16]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu.fuPool.FUList5.opList17]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu.fuPool.FUList5.opList18]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu.fuPool.FUList5.opList19]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=1
@@ -412,10 +460,12 @@ opLat=1
type=FUDesc
children=opList
count=0
+eventq_index=0
opList=system.cpu.fuPool.FUList6.opList
[system.cpu.fuPool.FUList6.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
@@ -424,16 +474,19 @@ opLat=1
type=FUDesc
children=opList0 opList1
count=4
+eventq_index=0
opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
[system.cpu.fuPool.FUList7.opList1]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
@@ -442,10 +495,12 @@ opLat=1
type=FUDesc
children=opList
count=1
+eventq_index=0
opList=system.cpu.fuPool.FUList8.opList
[system.cpu.fuPool.FUList8.opList]
type=OpDesc
+eventq_index=0
issueLat=3
opClass=IprAccess
opLat=3
@@ -456,6 +511,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -478,17 +534,21 @@ type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
size=32768
[system.cpu.interrupts]
type=AlphaInterrupts
+eventq_index=0
[system.cpu.isa]
type=AlphaISA
+eventq_index=0
[system.cpu.itb]
type=AlphaTLB
+eventq_index=0
size=48
[system.cpu.l2cache]
@@ -497,6 +557,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
@@ -519,12 +580,14 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=20
size=4194304
[system.cpu.toL2Bus]
type=CoherentBus
clk_domain=system.cpu_clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -534,10 +597,12 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+eventq_index=0
voltage_domain=system.voltage_domain
[system.disk0]
@@ -545,19 +610,22 @@ type=IdeDisk
children=image
delay=1000000
driveID=master
+eventq_index=0
image=system.disk0.image
[system.disk0.image]
type=CowDiskImage
children=child
child=system.disk0.image.child
+eventq_index=0
image_file=
read_only=false
table_size=65536
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
@@ -565,28 +633,33 @@ type=IdeDisk
children=image
delay=1000000
driveID=master
+eventq_index=0
image=system.disk2.image
[system.disk2.image]
type=CowDiskImage
children=child
child=system.disk2.image.child
+eventq_index=0
image_file=
read_only=false
table_size=65536
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
type=IntrControl
+eventq_index=0
sys=system
[system.iobus]
type=NoncoherentBus
clk_domain=system.clk_domain
+eventq_index=0
header_cycles=1
use_default_range=true
width=8
@@ -600,6 +673,7 @@ children=tags
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
+eventq_index=0
forward_snoops=false
hit_latency=50
is_top_level=true
@@ -622,6 +696,7 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
+eventq_index=0
hit_latency=50
size=1024
@@ -629,6 +704,7 @@ size=1024
type=CoherentBus
children=badaddr_responder
clk_domain=system.clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -640,6 +716,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=0
pio_latency=100000
@@ -666,6 +743,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+eventq_index=0
in_addr_map=true
mem_sched_policy=frfcfs
null=false
@@ -677,29 +755,35 @@ static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCL=13750
+tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=300000
tRP=13750
+tRRD=6250
tWTR=7500
tXAW=40000
write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
port=system.membus.master[1]
[system.simple_disk]
type=SimpleDisk
children=disk
disk=system.simple_disk.disk
+eventq_index=0
system=system
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
type=Terminal
+eventq_index=0
intr_control=system.intrctrl
number=0
output=true
@@ -708,6 +792,7 @@ port=3456
[system.tsunami]
type=Tsunami
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+eventq_index=0
intrctrl=system.intrctrl
system=system
@@ -716,6 +801,7 @@ type=AlphaBackdoor
clk_domain=system.clk_domain
cpu=system.cpu
disk=system.simple_disk
+eventq_index=0
pio_addr=8804682956800
pio_latency=100000
platform=system.tsunami
@@ -726,6 +812,7 @@ pio=system.iobus.master[24]
[system.tsunami.cchip]
type=TsunamiCChip
clk_domain=system.clk_domain
+eventq_index=0
pio_addr=8803072344064
pio_latency=100000
system=system
@@ -754,6 +841,7 @@ BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
+CapabilityPtr=0
CardbusCIS=0
ClassCode=2
Command=0
@@ -763,8 +851,40 @@ HeaderType=0
InterruptLine=30
InterruptPin=1
LatencyTimer=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
MaximumLatency=52
MinimumGrant=176
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
ProgIF=0
Revision=0
Status=656
@@ -781,6 +901,7 @@ dma_read_delay=0
dma_read_factor=0
dma_write_delay=0
dma_write_factor=0
+eventq_index=0
hardware_address=00:90:00:00:00:01
intr_delay=10000000
pci_bus=0
@@ -804,6 +925,7 @@ pio=system.iobus.master[27]
[system.tsunami.fake_OROM]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8796093677568
pio_latency=100000
@@ -821,6 +943,7 @@ pio=system.iobus.master[8]
[system.tsunami.fake_ata0]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848432
pio_latency=100000
@@ -838,6 +961,7 @@ pio=system.iobus.master[19]
[system.tsunami.fake_ata1]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848304
pio_latency=100000
@@ -855,6 +979,7 @@ pio=system.iobus.master[20]
[system.tsunami.fake_pnp_addr]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848569
pio_latency=100000
@@ -872,6 +997,7 @@ pio=system.iobus.master[9]
[system.tsunami.fake_pnp_read0]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848451
pio_latency=100000
@@ -889,6 +1015,7 @@ pio=system.iobus.master[11]
[system.tsunami.fake_pnp_read1]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848515
pio_latency=100000
@@ -906,6 +1033,7 @@ pio=system.iobus.master[12]
[system.tsunami.fake_pnp_read2]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848579
pio_latency=100000
@@ -923,6 +1051,7 @@ pio=system.iobus.master[13]
[system.tsunami.fake_pnp_read3]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848643
pio_latency=100000
@@ -940,6 +1069,7 @@ pio=system.iobus.master[14]
[system.tsunami.fake_pnp_read4]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848707
pio_latency=100000
@@ -957,6 +1087,7 @@ pio=system.iobus.master[15]
[system.tsunami.fake_pnp_read5]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848771
pio_latency=100000
@@ -974,6 +1105,7 @@ pio=system.iobus.master[16]
[system.tsunami.fake_pnp_read6]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848835
pio_latency=100000
@@ -991,6 +1123,7 @@ pio=system.iobus.master[17]
[system.tsunami.fake_pnp_read7]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848899
pio_latency=100000
@@ -1008,6 +1141,7 @@ pio=system.iobus.master[18]
[system.tsunami.fake_pnp_write]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615850617
pio_latency=100000
@@ -1025,6 +1159,7 @@ pio=system.iobus.master[10]
[system.tsunami.fake_ppc]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848891
pio_latency=100000
@@ -1042,6 +1177,7 @@ pio=system.iobus.master[7]
[system.tsunami.fake_sm_chip]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848816
pio_latency=100000
@@ -1059,6 +1195,7 @@ pio=system.iobus.master[2]
[system.tsunami.fake_uart1]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848696
pio_latency=100000
@@ -1076,6 +1213,7 @@ pio=system.iobus.master[3]
[system.tsunami.fake_uart2]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848936
pio_latency=100000
@@ -1093,6 +1231,7 @@ pio=system.iobus.master[4]
[system.tsunami.fake_uart3]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848680
pio_latency=100000
@@ -1110,6 +1249,7 @@ pio=system.iobus.master[5]
[system.tsunami.fake_uart4]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848944
pio_latency=100000
@@ -1128,6 +1268,7 @@ pio=system.iobus.master[6]
type=BadDevice
clk_domain=system.clk_domain
devicename=FrameBuffer
+eventq_index=0
pio_addr=8804615848912
pio_latency=100000
system=system
@@ -1155,6 +1296,7 @@ BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
+CapabilityPtr=0
CardbusCIS=0
ClassCode=1
Command=0
@@ -1164,8 +1306,40 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
MaximumLatency=0
MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
ProgIF=133
Revision=0
Status=640
@@ -1177,6 +1351,7 @@ clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=0
disks=system.disk0 system.disk2
+eventq_index=0
io_shift=0
pci_bus=0
pci_dev=0
@@ -1191,6 +1366,7 @@ pio=system.iobus.master[25]
[system.tsunami.io]
type=TsunamiIO
clk_domain=system.clk_domain
+eventq_index=0
frequency=976562500
pio_addr=8804615847936
pio_latency=100000
@@ -1203,6 +1379,7 @@ pio=system.iobus.master[22]
[system.tsunami.pchip]
type=TsunamiPChip
clk_domain=system.clk_domain
+eventq_index=0
pio_addr=8802535473152
pio_latency=100000
system=system
@@ -1213,6 +1390,7 @@ pio=system.iobus.master[1]
type=PciConfigAll
bus=0
clk_domain=system.clk_domain
+eventq_index=0
pio_addr=0
pio_latency=30000
platform=system.tsunami
@@ -1223,6 +1401,7 @@ pio=system.iobus.default
[system.tsunami.uart]
type=Uart8250
clk_domain=system.clk_domain
+eventq_index=0
pio_addr=8804615848952
pio_latency=100000
platform=system.tsunami
@@ -1232,5 +1411,6 @@ pio=system.iobus.master[23]
[system.voltage_domain]
type=VoltageDomain
+eventq_index=0
voltage=1.000000
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
index cb131fc03..c08f75535 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
@@ -1,126 +1,126 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.860198 # Number of seconds simulated
-sim_ticks 1860197608000 # Number of ticks simulated
-final_tick 1860197608000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 1860197780500 # Number of ticks simulated
+final_tick 1860197780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 128608 # Simulator instruction rate (inst/s)
-host_op_rate 128608 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4515644283 # Simulator tick rate (ticks/s)
-host_mem_usage 336512 # Number of bytes of host memory used
-host_seconds 411.95 # Real time elapsed on the host
-sim_insts 52979573 # Number of instructions simulated
-sim_ops 52979573 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 964544 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24879808 # Number of bytes read from this memory
+host_inst_rate 103834 # Simulator instruction rate (inst/s)
+host_op_rate 103834 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3645751305 # Simulator tick rate (ticks/s)
+host_mem_usage 355004 # Number of bytes of host memory used
+host_seconds 510.24 # Real time elapsed on the host
+sim_insts 52979882 # Number of instructions simulated
+sim_ops 52979882 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24878976 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28496640 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 964544 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 964544 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7516672 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7516672 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 15071 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 388747 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 28495232 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7515456 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7515456 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 388734 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 445260 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 117448 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 117448 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 518517 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 13374820 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total 445238 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 117429 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 117429 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 518207 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 13374371 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1425810 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15319147 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 518517 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 518517 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4040792 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4040792 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4040792 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 518517 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 13374820 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total 15318388 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 518207 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 518207 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4040138 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4040138 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4040138 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 518207 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 13374371 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1425810 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19359939 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 445260 # Number of read requests accepted
-system.physmem.writeReqs 117448 # Number of write requests accepted
-system.physmem.readBursts 445260 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 117448 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 28493888 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 2752 # Total number of bytes read from write queue
-system.physmem.bytesWritten 7515904 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 28496640 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 7516672 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total 19358526 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 445238 # Number of read requests accepted
+system.physmem.writeReqs 117429 # Number of write requests accepted
+system.physmem.readBursts 445238 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 117429 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 28492032 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 3200 # Total number of bytes read from write queue
+system.physmem.bytesWritten 7514752 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 28495232 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 7515456 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 177 # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs 179 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 28229 # Per bank write bursts
system.physmem.perBankRdBursts::1 27970 # Per bank write bursts
-system.physmem.perBankRdBursts::2 28438 # Per bank write bursts
-system.physmem.perBankRdBursts::3 28034 # Per bank write bursts
-system.physmem.perBankRdBursts::4 27800 # Per bank write bursts
-system.physmem.perBankRdBursts::5 27233 # Per bank write bursts
+system.physmem.perBankRdBursts::2 28433 # Per bank write bursts
+system.physmem.perBankRdBursts::3 28029 # Per bank write bursts
+system.physmem.perBankRdBursts::4 27802 # Per bank write bursts
+system.physmem.perBankRdBursts::5 27222 # Per bank write bursts
system.physmem.perBankRdBursts::6 27248 # Per bank write bursts
-system.physmem.perBankRdBursts::7 27300 # Per bank write bursts
-system.physmem.perBankRdBursts::8 27656 # Per bank write bursts
-system.physmem.perBankRdBursts::9 27404 # Per bank write bursts
-system.physmem.perBankRdBursts::10 27929 # Per bank write bursts
-system.physmem.perBankRdBursts::11 27540 # Per bank write bursts
-system.physmem.perBankRdBursts::12 27555 # Per bank write bursts
-system.physmem.perBankRdBursts::13 28228 # Per bank write bursts
-system.physmem.perBankRdBursts::14 28334 # Per bank write bursts
-system.physmem.perBankRdBursts::15 28319 # Per bank write bursts
-system.physmem.perBankWrBursts::0 7929 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7498 # Per bank write bursts
-system.physmem.perBankWrBursts::2 7947 # Per bank write bursts
+system.physmem.perBankRdBursts::7 27296 # Per bank write bursts
+system.physmem.perBankRdBursts::8 27665 # Per bank write bursts
+system.physmem.perBankRdBursts::9 27395 # Per bank write bursts
+system.physmem.perBankRdBursts::10 27922 # Per bank write bursts
+system.physmem.perBankRdBursts::11 27539 # Per bank write bursts
+system.physmem.perBankRdBursts::12 27561 # Per bank write bursts
+system.physmem.perBankRdBursts::13 28227 # Per bank write bursts
+system.physmem.perBankRdBursts::14 28327 # Per bank write bursts
+system.physmem.perBankRdBursts::15 28323 # Per bank write bursts
+system.physmem.perBankWrBursts::0 7932 # Per bank write bursts
+system.physmem.perBankWrBursts::1 7497 # Per bank write bursts
+system.physmem.perBankWrBursts::2 7944 # Per bank write bursts
system.physmem.perBankWrBursts::3 7517 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7338 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6689 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6763 # Per bank write bursts
-system.physmem.perBankWrBursts::7 6689 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7098 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6803 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7320 # Per bank write bursts
-system.physmem.perBankWrBursts::11 6984 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7119 # Per bank write bursts
-system.physmem.perBankWrBursts::13 7873 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8054 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7815 # Per bank write bursts
+system.physmem.perBankWrBursts::4 7343 # Per bank write bursts
+system.physmem.perBankWrBursts::5 6680 # Per bank write bursts
+system.physmem.perBankWrBursts::6 6761 # Per bank write bursts
+system.physmem.perBankWrBursts::7 6683 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7104 # Per bank write bursts
+system.physmem.perBankWrBursts::9 6801 # Per bank write bursts
+system.physmem.perBankWrBursts::10 7313 # Per bank write bursts
+system.physmem.perBankWrBursts::11 6981 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7123 # Per bank write bursts
+system.physmem.perBankWrBursts::13 7875 # Per bank write bursts
+system.physmem.perBankWrBursts::14 8050 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7814 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
-system.physmem.totGap 1860192151000 # Total gap between requests
+system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
+system.physmem.totGap 1860192344000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
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@@ -131,226 +131,229 @@ system.physmem.rdQLenPdf::28 0 # Wh
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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+system.physmem.bytesPerActivate::768-771 623 1.44% 81.67% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::896-899 262 0.61% 82.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-963 268 0.62% 83.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1027 398 0.92% 84.47% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1152-1155 163 0.38% 85.32% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1536-1539 655 1.51% 88.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1603 89 0.21% 89.18% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1920-1923 79 0.18% 90.01% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::6208-6211 82 0.19% 96.56% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::6976-6979 14 0.03% 97.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7040-7043 66 0.15% 97.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7104-7107 80 0.18% 97.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7168-7171 307 0.71% 98.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7360-7363 1 0.00% 98.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7424-7427 17 0.04% 98.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7488-7491 2 0.00% 98.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7552-7555 1 0.00% 98.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7680-7683 5 0.01% 98.49% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::7872-7875 1 0.00% 98.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7936-7939 16 0.04% 98.53% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::8192-8195 330 0.76% 99.30% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9408-9411 1 0.00% 99.34% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.34% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11008-11011 3 0.01% 99.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11840-11843 3 0.01% 99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11904-11907 2 0.00% 99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.41% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12928-12931 2 0.00% 99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13120-13123 2 0.00% 99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14144-14147 1 0.00% 99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14528-14531 2 0.00% 99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14656-14659 3 0.01% 99.48% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.49% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::15360-15363 37 0.09% 99.58% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::15360-15363 40 0.09% 99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15808-15811 1 0.00% 99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15808-15811 2 0.00% 99.59% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16387 176 0.41% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 43193 # Bytes accessed per row activation
-system.physmem.totQLat 8380902250 # Total ticks spent queuing
-system.physmem.totMemAccLat 15783312250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2226085000 # Total ticks spent in databus transfers
-system.physmem.totBankLat 5176325000 # Total ticks spent accessing banks
-system.physmem.avgQLat 18824.31 # Average queueing delay per DRAM burst
-system.physmem.avgBankLat 11626.52 # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16384-16387 174 0.40% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 43301 # Bytes accessed per row activation
+system.physmem.totQLat 8362787000 # Total ticks spent queuing
+system.physmem.totMemAccLat 15768695750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2225940000 # Total ticks spent in databus transfers
+system.physmem.totBankLat 5179968750 # Total ticks spent accessing banks
+system.physmem.avgQLat 18784.84 # Average queueing delay per DRAM burst
+system.physmem.avgBankLat 11635.46 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 35450.83 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 35420.31 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s
@@ -360,59 +363,60 @@ system.physmem.busUtil 0.15 # Da
system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 9.37 # Average write queue length when enqueuing
-system.physmem.readRowHits 424661 # Number of row buffer hits during reads
-system.physmem.writeRowHits 94799 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 95.38 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 80.72 # Row buffer hit rate for writes
-system.physmem.avgGap 3305785.86 # Average gap between requests
-system.physmem.pageHitRate 92.32 # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent 0.40 # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput 19402801 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 295960 # Transaction distribution
-system.membus.trans_dist::ReadResp 295877 # Transaction distribution
+system.physmem.avgWrQLen 11.24 # Average write queue length when enqueuing
+system.physmem.readRowHits 424550 # Number of row buffer hits during reads
+system.physmem.writeRowHits 94755 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 95.36 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 80.69 # Row buffer hit rate for writes
+system.physmem.avgGap 3306027.09 # Average gap between requests
+system.physmem.pageHitRate 92.30 # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent 0.39 # Percentage of time for which DRAM has all the banks in precharge state
+system.membus.throughput 19401389 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 295980 # Transaction distribution
+system.membus.trans_dist::ReadResp 295901 # Transaction distribution
system.membus.trans_dist::WriteReq 9598 # Transaction distribution
system.membus.trans_dist::WriteResp 9598 # Transaction distribution
-system.membus.trans_dist::Writeback 117448 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 180 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 180 # Transaction distribution
-system.membus.trans_dist::ReadExReq 156869 # Transaction distribution
-system.membus.trans_dist::ReadExResp 156869 # Transaction distribution
-system.membus.trans_dist::BadAddressError 83 # Transaction distribution
+system.membus.trans_dist::Writeback 117429 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 181 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 182 # Transaction distribution
+system.membus.trans_dist::ReadExReq 156823 # Transaction distribution
+system.membus.trans_dist::ReadExResp 156823 # Transaction distribution
+system.membus.trans_dist::BadAddressError 79 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884202 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 166 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917424 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884143 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 158 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917357 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1042103 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1042036 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704256 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30748404 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701632 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30745780 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 36057460 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 36057460 # Total data (bytes)
+system.membus.tot_pkt_size::total 36054836 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 36054836 # Total data (bytes)
system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 29954500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 29837500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 1551414500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 1551324500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 106000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 96500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3763341794 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 3763216294 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 376305243 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 376313495 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41685 # number of replacements
-system.iocache.tags.tagsinuse 1.261102 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 1.261116 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 1710341438000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide 1.261102 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide 0.078819 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.078819 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 1710341603000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide 1.261116 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide 0.078820 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.078820 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
@@ -423,12 +427,12 @@ system.iocache.overall_misses::tsunami.ide 41725 #
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21133883 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21133883 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 12983817806 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 12983817806 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 13004951689 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 13004951689 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 13004951689 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 13004951689 # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 12974928560 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 12974928560 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 12996062443 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 12996062443 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 12996062443 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 12996062443 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
@@ -447,17 +451,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 122161.173410 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312471.549047 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 312471.549047 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 311682.485057 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 311682.485057 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 311682.485057 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 311682.485057 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 402476 # number of cycles access was blocked
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312257.618406 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 312257.618406 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 311469.441414 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 311469.441414 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 311469.441414 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 311469.441414 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 401483 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 29170 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 29284 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 13.797600 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 13.709978 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@@ -473,12 +477,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136883 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12136883 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10821554320 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 10821554320 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 10833691203 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 10833691203 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 10833691203 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 10833691203 # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10812648570 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 10812648570 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 10824785453 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 10824785453 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 10824785453 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 10824785453 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
@@ -489,12 +493,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260434.018098 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 260434.018098 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259645.085752 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 259645.085752 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259645.085752 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 259645.085752 # average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260219.690268 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 260219.690268 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259431.646567 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 259431.646567 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259431.646567 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 259431.646567 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
@@ -508,35 +512,35 @@ system.disk2.dma_read_txs 0 # Nu
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 13864479 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11634507 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 398117 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9551974 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 5822395 # Number of BTB hits
+system.cpu.branchPred.lookups 13863448 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11631259 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 399718 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9400932 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 5821857 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 60.954887 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 906213 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 38605 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 61.928509 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 906521 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 39211 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9930859 # DTB read hits
-system.cpu.dtb.read_misses 42001 # DTB read misses
-system.cpu.dtb.read_acv 541 # DTB read access violations
-system.cpu.dtb.read_accesses 942214 # DTB read accesses
-system.cpu.dtb.write_hits 6592411 # DTB write hits
-system.cpu.dtb.write_misses 10345 # DTB write misses
+system.cpu.dtb.read_hits 9926517 # DTB read hits
+system.cpu.dtb.read_misses 41406 # DTB read misses
+system.cpu.dtb.read_acv 531 # DTB read access violations
+system.cpu.dtb.read_accesses 940700 # DTB read accesses
+system.cpu.dtb.write_hits 6593963 # DTB write hits
+system.cpu.dtb.write_misses 10630 # DTB write misses
system.cpu.dtb.write_acv 410 # DTB write access violations
-system.cpu.dtb.write_accesses 337923 # DTB write accesses
-system.cpu.dtb.data_hits 16523270 # DTB hits
-system.cpu.dtb.data_misses 52346 # DTB misses
-system.cpu.dtb.data_acv 951 # DTB access violations
-system.cpu.dtb.data_accesses 1280137 # DTB accesses
-system.cpu.itb.fetch_hits 1308071 # ITB hits
-system.cpu.itb.fetch_misses 36703 # ITB misses
-system.cpu.itb.fetch_acv 1058 # ITB acv
-system.cpu.itb.fetch_accesses 1344774 # ITB accesses
+system.cpu.dtb.write_accesses 338096 # DTB write accesses
+system.cpu.dtb.data_hits 16520480 # DTB hits
+system.cpu.dtb.data_misses 52036 # DTB misses
+system.cpu.dtb.data_acv 941 # DTB access violations
+system.cpu.dtb.data_accesses 1278796 # DTB accesses
+system.cpu.itb.fetch_hits 1306353 # ITB hits
+system.cpu.itb.fetch_misses 36823 # ITB misses
+system.cpu.itb.fetch_acv 1069 # ITB acv
+system.cpu.itb.fetch_accesses 1343176 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -549,269 +553,269 @@ system.cpu.itb.data_hits 0 # DT
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 121927488 # number of cpu cycles simulated
+system.cpu.numCycles 121966998 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 28039089 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 70847333 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 13864479 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 6728608 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 13268188 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1998523 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 38187764 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 33374 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 253703 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 358378 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 313 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 8556240 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 264321 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 81433386 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.870004 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.213508 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 28067964 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 70813073 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 13863448 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 6728378 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 13263425 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1999195 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 38181411 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 33091 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 255000 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 364206 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 297 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 8556045 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 264477 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 81457086 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.869330 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.212823 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 68165198 83.71% 83.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 850053 1.04% 84.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1699284 2.09% 86.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 821371 1.01% 87.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2763942 3.39% 91.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 562061 0.69% 91.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 645266 0.79% 92.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1012758 1.24% 93.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 4913453 6.03% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 68193661 83.72% 83.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 852857 1.05% 84.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1696439 2.08% 86.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 825181 1.01% 87.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2758325 3.39% 91.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 561473 0.69% 91.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 645881 0.79% 92.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1010308 1.24% 93.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 4912961 6.03% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 81433386 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.113711 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.581061 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 29221081 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 37872240 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 12130703 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 959021 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1250340 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 583021 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 42672 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 69509272 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 129850 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1250340 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 30372674 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 14147971 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 20014852 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 11335195 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4312352 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 65701425 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 7084 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 503729 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 1544223 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 43873094 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 79768312 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 79589398 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 166462 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 38180112 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 5692974 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1682864 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 240315 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12255388 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 10448429 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 6906827 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1318660 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 851527 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 58223534 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2050984 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 56812947 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 113805 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6931173 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3605221 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1390018 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 81433386 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.697662 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.359692 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 81457086 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.113666 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.580592 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 29256938 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 37863691 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 12127839 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 959156 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1249461 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 584263 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 42640 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 69481989 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 129319 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1249461 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 30407522 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 14148846 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 20005990 # count of cycles rename stalled for serializing inst
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+system.cpu.rename.UnblockCycles 4312891 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 65679549 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 7211 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 504797 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 1541440 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 43855166 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 79746051 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 79567055 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 166544 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 38180329 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 5674829 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1682909 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 240455 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12257327 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 10441163 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 6908790 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1318239 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 851396 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 58211664 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2050007 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 56814932 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 114609 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 6922962 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3587498 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1389025 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 81457086 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.697483 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.359485 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 56726750 69.66% 69.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 10882649 13.36% 83.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 5163201 6.34% 89.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 3388782 4.16% 93.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 2628492 3.23% 96.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 1462722 1.80% 98.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 751690 0.92% 99.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 332968 0.41% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 96132 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 56746030 69.66% 69.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 10887232 13.37% 83.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 5162469 6.34% 89.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 3392471 4.16% 93.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 2625915 3.22% 96.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 1461124 1.79% 98.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 753330 0.92% 99.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 332031 0.41% 99.88% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 81433386 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 81457086 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 91250 11.56% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 372174 47.14% 58.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 326051 41.30% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 91940 11.62% 11.62% # attempts to use FU when none available
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+system.cpu.iq.fu_full::IntDiv 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 373423 47.20% 58.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 325849 41.18% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 38733166 68.18% 68.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 61715 0.11% 68.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 38737583 68.18% 68.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 61738 0.11% 68.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 10362094 18.24% 86.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 6670366 11.74% 98.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 10357242 18.23% 86.58% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 6672763 11.74% 98.33% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 56812947 # Type of FU issued
-system.cpu.iq.rate 0.465957 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 789475 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.013896 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 195270080 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 66882864 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 55570085 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 692479 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 336490 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 327821 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 57233809 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 361327 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 596971 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 56814932 # Type of FU issued
+system.cpu.iq.rate 0.465822 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 791212 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.013926 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 195300199 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 66861892 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 55573336 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 692571 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 336551 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 327871 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 57237458 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 361400 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 598272 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1356016 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 3236 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14012 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 528856 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1348718 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 3201 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 14139 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 530806 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 17919 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 183461 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 17937 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 182742 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1250340 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 10233655 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 702274 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 63801966 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 688802 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 10448429 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 6906827 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1805093 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 512952 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 17454 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14012 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 201109 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 411560 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 612669 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 56346471 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 10001011 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 466475 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1249461 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 10237116 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 702035 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 63785040 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 690324 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 10441163 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 6908790 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1805677 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 512237 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 17569 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 14139 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 202047 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 411314 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 613361 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 56348369 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 9996094 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 466562 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 3527448 # number of nop insts executed
-system.cpu.iew.exec_refs 16619020 # number of memory reference insts executed
-system.cpu.iew.exec_branches 8923746 # Number of branches executed
-system.cpu.iew.exec_stores 6618009 # Number of stores executed
-system.cpu.iew.exec_rate 0.462131 # Inst execution rate
-system.cpu.iew.wb_sent 56013491 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 55897906 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 27708487 # num instructions producing a value
-system.cpu.iew.wb_consumers 37528450 # num instructions consuming a value
+system.cpu.iew.exec_nop 3523369 # number of nop insts executed
+system.cpu.iew.exec_refs 16615920 # number of memory reference insts executed
+system.cpu.iew.exec_branches 8927027 # Number of branches executed
+system.cpu.iew.exec_stores 6619826 # Number of stores executed
+system.cpu.iew.exec_rate 0.461997 # Inst execution rate
+system.cpu.iew.wb_sent 56016387 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 55901207 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 27709617 # num instructions producing a value
+system.cpu.iew.wb_consumers 37531222 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.458452 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.738333 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.458331 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.738308 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 7515002 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 660966 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 566897 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 80183046 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.700527 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.629598 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 7496348 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 660982 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 568504 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 80207625 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.700316 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.629380 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 59370328 74.04% 74.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 8654728 10.79% 84.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4617014 5.76% 90.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2519187 3.14% 93.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1509953 1.88% 95.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 613300 0.76% 96.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 523538 0.65% 97.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 523484 0.65% 97.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1851514 2.31% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 59390670 74.05% 74.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 8659340 10.80% 84.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4620197 5.76% 90.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2517886 3.14% 93.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1507376 1.88% 95.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 612052 0.76% 96.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 525608 0.66% 97.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 522089 0.65% 97.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 1852407 2.31% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 80183046 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 56170357 # Number of instructions committed
-system.cpu.commit.committedOps 56170357 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 80207625 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 56170683 # Number of instructions committed
+system.cpu.commit.committedOps 56170683 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 15470384 # Number of memory references committed
-system.cpu.commit.loads 9092413 # Number of loads committed
-system.cpu.commit.membars 226354 # Number of memory barriers committed
-system.cpu.commit.branches 8439829 # Number of branches committed
+system.cpu.commit.refs 15470429 # Number of memory references committed
+system.cpu.commit.loads 9092445 # Number of loads committed
+system.cpu.commit.membars 226358 # Number of memory barriers committed
+system.cpu.commit.branches 8439899 # Number of branches committed
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 52019973 # Number of committed integer instructions.
-system.cpu.commit.function_calls 740579 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 1851514 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 52020266 # Number of committed integer instructions.
+system.cpu.commit.function_calls 740581 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 1852407 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 141767299 # The number of ROB reads
-system.cpu.rob.rob_writes 128622610 # The number of ROB writes
-system.cpu.timesIdled 1192878 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 40494102 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 3598461292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 52979573 # Number of Instructions Simulated
-system.cpu.committedOps 52979573 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 52979573 # Number of Instructions Simulated
-system.cpu.cpi 2.301406 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.301406 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.434517 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.434517 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 73879526 # number of integer regfile reads
-system.cpu.int_regfile_writes 40317649 # number of integer regfile writes
-system.cpu.fp_regfile_reads 165968 # number of floating regfile reads
-system.cpu.fp_regfile_writes 167427 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1984782 # number of misc regfile reads
-system.cpu.misc_regfile_writes 938976 # number of misc regfile writes
+system.cpu.rob.rob_reads 141772543 # The number of ROB reads
+system.cpu.rob.rob_writes 128585215 # The number of ROB writes
+system.cpu.timesIdled 1193212 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 40509912 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 3598422122 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 52979882 # Number of Instructions Simulated
+system.cpu.committedOps 52979882 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 52979882 # Number of Instructions Simulated
+system.cpu.cpi 2.302138 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.302138 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.434379 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.434379 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 73881277 # number of integer regfile reads
+system.cpu.int_regfile_writes 40316653 # number of integer regfile writes
+system.cpu.fp_regfile_reads 166009 # number of floating regfile reads
+system.cpu.fp_regfile_writes 167434 # number of floating regfile writes
+system.cpu.misc_regfile_reads 1986207 # number of misc regfile reads
+system.cpu.misc_regfile_writes 938984 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
@@ -903,225 +907,233 @@ system.iobus.reqLayer27.occupancy 76000 # La
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer29.occupancy 377740446 # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy 377738948 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 42670757 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 42679505 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.throughput 111891693 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 2116597 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2116497 # Transaction distribution
+system.cpu.toL2Bus.throughput 111941811 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 2118263 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2118167 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 840887 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 63 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 840743 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 65 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 342605 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 301054 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError 83 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2016984 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3678218 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 5695202 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64539584 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143593268 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 208132852 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 208122804 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 17856 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 2479701498 # Layer occupancy (ticks)
+system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 342536 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 300985 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError 79 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020543 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677710 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 5698253 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64653440 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143572596 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 208226036 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 208215988 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 17920 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 2480284498 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1516139861 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1518802860 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2192873665 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 2192631666 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.icache.tags.replacements 1007825 # number of replacements
-system.cpu.icache.tags.tagsinuse 509.660233 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 7491263 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1008333 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 7.429354 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 1009602 # number of replacements
+system.cpu.icache.tags.tagsinuse 509.660060 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 7489391 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 1010110 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 7.414431 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 26489829250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 509.660233 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst 509.660060 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.995430 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.995430 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 7491264 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 7491264 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 7491264 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 7491264 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 7491264 # number of overall hits
-system.cpu.icache.overall_hits::total 7491264 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1064974 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1064974 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1064974 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1064974 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1064974 # number of overall misses
-system.cpu.icache.overall_misses::total 1064974 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14872208186 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 14872208186 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 14872208186 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 14872208186 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 14872208186 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 14872208186 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 8556238 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 8556238 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 8556238 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 8556238 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 8556238 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 8556238 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124468 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.124468 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.124468 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.124468 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.124468 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.124468 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13964.855655 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13964.855655 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13964.855655 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13964.855655 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13964.855655 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13964.855655 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 5226 # number of cycles access was blocked
+system.cpu.icache.ReadReq_hits::cpu.inst 7489392 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 7489392 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 7489392 # number of demand (read+write) hits
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1130,72 +1142,80 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@@ -1203,161 +1223,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.dcache.tags.tagsinuse 511.994568 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 11815525 # Total number of references to valid blocks.
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-system.cpu.dcache.tags.avg_refs 8.428162 # Average number of references to valid blocks.
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system.cpu.dcache.tags.warmup_cycle 25477000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.994568 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy
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-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28129.619637 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28129.619637 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28129.619637 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28129.619637 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091317 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.091317 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091317 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.091317 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25077.643957 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25077.643957 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39153.633782 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39153.633782 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11469.174506 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11469.174506 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17499.500000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17499.500000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28131.999004 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28131.999004 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28131.999004 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28131.999004 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@@ -1366,7 +1386,7 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6437 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed
system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
@@ -1378,11 +1398,11 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.41% # nu
system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1818037303500 97.73% 97.73% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 64303500 0.00% 97.74% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 561270000 0.03% 97.77% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 41533903500 2.23% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1860196780500 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0 1818029044000 97.73% 97.73% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 64103000 0.00% 97.74% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 561251500 0.03% 97.77% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 41542545500 2.23% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1860196944000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
@@ -1446,9 +1466,9 @@ system.cpu.kern.mode_switch_good::kernel 0.326384 # fr
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 29638597000 1.59% 1.59% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 2732860000 0.15% 1.74% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1827825315500 98.26% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::kernel 29636227500 1.59% 1.59% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 2736556500 0.15% 1.74% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1827824152000 98.26% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
---------- End Simulation Statistics ----------
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
index 8b5822c19..8069712e0 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
+eventq_index=0
full_system=true
+sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -13,15 +15,16 @@ boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/dist/m5/system/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
+eventq_index=0
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
@@ -39,6 +42,7 @@ system_port=system.membus.slave[0]
type=Bridge
clk_domain=system.clk_domain
delay=50000
+eventq_index=0
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
@@ -48,6 +52,7 @@ slave=system.membus.master[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu0]
@@ -60,6 +65,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
+eventq_index=0
fastmem=false
function_trace=false
function_trace_start=0
@@ -93,6 +99,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -115,11 +122,13 @@ type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
size=32768
[system.cpu0.dtb]
type=AlphaTLB
+eventq_index=0
size=64
[system.cpu0.icache]
@@ -128,6 +137,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
@@ -150,21 +160,26 @@ type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=2
size=32768
[system.cpu0.interrupts]
type=AlphaInterrupts
+eventq_index=0
[system.cpu0.isa]
type=AlphaISA
+eventq_index=0
[system.cpu0.itb]
type=AlphaTLB
+eventq_index=0
size=48
[system.cpu0.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu1]
type=TimingSimpleCPU
@@ -176,6 +191,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
+eventq_index=0
function_trace=false
function_trace_start=0
interrupts=Null
@@ -196,17 +212,21 @@ workload=
[system.cpu1.dtb]
type=AlphaTLB
+eventq_index=0
size=64
[system.cpu1.isa]
type=AlphaISA
+eventq_index=0
[system.cpu1.itb]
type=AlphaTLB
+eventq_index=0
size=48
[system.cpu1.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu2]
type=DerivO3CPU
@@ -237,6 +257,8 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu2.dtb
+eventq_index=0
+fetchBufferSize=64
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -299,6 +321,7 @@ BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
+eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
@@ -310,21 +333,25 @@ predType=tournament
[system.cpu2.dtb]
type=AlphaTLB
+eventq_index=0
size=64
[system.cpu2.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
+eventq_index=0
[system.cpu2.fuPool.FUList0]
type=FUDesc
children=opList
count=6
+eventq_index=0
opList=system.cpu2.fuPool.FUList0.opList
[system.cpu2.fuPool.FUList0.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=IntAlu
opLat=1
@@ -333,16 +360,19 @@ opLat=1
type=FUDesc
children=opList0 opList1
count=2
+eventq_index=0
opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
[system.cpu2.fuPool.FUList1.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=IntMult
opLat=3
[system.cpu2.fuPool.FUList1.opList1]
type=OpDesc
+eventq_index=0
issueLat=19
opClass=IntDiv
opLat=20
@@ -351,22 +381,26 @@ opLat=20
type=FUDesc
children=opList0 opList1 opList2
count=4
+eventq_index=0
opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
[system.cpu2.fuPool.FUList2.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu2.fuPool.FUList2.opList1]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu2.fuPool.FUList2.opList2]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatCvt
opLat=2
@@ -375,22 +409,26 @@ opLat=2
type=FUDesc
children=opList0 opList1 opList2
count=2
+eventq_index=0
opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
[system.cpu2.fuPool.FUList3.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu2.fuPool.FUList3.opList1]
type=OpDesc
+eventq_index=0
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu2.fuPool.FUList3.opList2]
type=OpDesc
+eventq_index=0
issueLat=24
opClass=FloatSqrt
opLat=24
@@ -399,10 +437,12 @@ opLat=24
type=FUDesc
children=opList
count=0
+eventq_index=0
opList=system.cpu2.fuPool.FUList4.opList
[system.cpu2.fuPool.FUList4.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
@@ -411,124 +451,145 @@ opLat=1
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
+eventq_index=0
opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
[system.cpu2.fuPool.FUList5.opList00]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu2.fuPool.FUList5.opList01]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu2.fuPool.FUList5.opList02]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu2.fuPool.FUList5.opList03]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu2.fuPool.FUList5.opList04]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu2.fuPool.FUList5.opList05]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu2.fuPool.FUList5.opList06]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu2.fuPool.FUList5.opList07]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu2.fuPool.FUList5.opList08]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu2.fuPool.FUList5.opList09]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu2.fuPool.FUList5.opList10]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu2.fuPool.FUList5.opList11]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu2.fuPool.FUList5.opList12]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu2.fuPool.FUList5.opList13]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu2.fuPool.FUList5.opList14]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu2.fuPool.FUList5.opList15]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu2.fuPool.FUList5.opList16]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu2.fuPool.FUList5.opList17]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu2.fuPool.FUList5.opList18]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu2.fuPool.FUList5.opList19]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
opLat=1
@@ -537,10 +598,12 @@ opLat=1
type=FUDesc
children=opList
count=0
+eventq_index=0
opList=system.cpu2.fuPool.FUList6.opList
[system.cpu2.fuPool.FUList6.opList]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
@@ -549,16 +612,19 @@ opLat=1
type=FUDesc
children=opList0 opList1
count=4
+eventq_index=0
opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
[system.cpu2.fuPool.FUList7.opList0]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemRead
opLat=1
[system.cpu2.fuPool.FUList7.opList1]
type=OpDesc
+eventq_index=0
issueLat=1
opClass=MemWrite
opLat=1
@@ -567,27 +633,33 @@ opLat=1
type=FUDesc
children=opList
count=1
+eventq_index=0
opList=system.cpu2.fuPool.FUList8.opList
[system.cpu2.fuPool.FUList8.opList]
type=OpDesc
+eventq_index=0
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu2.isa]
type=AlphaISA
+eventq_index=0
[system.cpu2.itb]
type=AlphaTLB
+eventq_index=0
size=48
[system.cpu2.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
+eventq_index=0
voltage_domain=system.voltage_domain
[system.disk0]
@@ -595,19 +667,22 @@ type=IdeDisk
children=image
delay=1000000
driveID=master
+eventq_index=0
image=system.disk0.image
[system.disk0.image]
type=CowDiskImage
children=child
child=system.disk0.image.child
+eventq_index=0
image_file=
read_only=false
table_size=65536
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
@@ -615,28 +690,33 @@ type=IdeDisk
children=image
delay=1000000
driveID=master
+eventq_index=0
image=system.disk2.image
[system.disk2.image]
type=CowDiskImage
children=child
child=system.disk2.image.child
+eventq_index=0
image_file=
read_only=false
table_size=65536
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
type=IntrControl
+eventq_index=0
sys=system
[system.iobus]
type=NoncoherentBus
clk_domain=system.clk_domain
+eventq_index=0
header_cycles=1
use_default_range=true
width=8
@@ -650,6 +730,7 @@ children=tags
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
+eventq_index=0
forward_snoops=false
hit_latency=50
is_top_level=true
@@ -672,6 +753,7 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
+eventq_index=0
hit_latency=50
size=1024
@@ -681,6 +763,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
@@ -703,6 +786,7 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+eventq_index=0
hit_latency=20
size=4194304
@@ -710,6 +794,7 @@ size=4194304
type=CoherentBus
children=badaddr_responder
clk_domain=system.clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -721,6 +806,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=0
pio_latency=100000
@@ -747,6 +833,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+eventq_index=0
in_addr_map=true
mem_sched_policy=frfcfs
null=false
@@ -758,29 +845,35 @@ static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCL=13750
+tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=300000
tRP=13750
+tRRD=6250
tWTR=7500
tXAW=40000
write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
port=system.membus.master[1]
[system.simple_disk]
type=SimpleDisk
children=disk
disk=system.simple_disk.disk
+eventq_index=0
system=system
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+eventq_index=0
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
type=Terminal
+eventq_index=0
intr_control=system.intrctrl
number=0
output=true
@@ -789,6 +882,7 @@ port=3456
[system.toL2Bus]
type=CoherentBus
clk_domain=system.cpu_clk_domain
+eventq_index=0
header_cycles=1
system=system
use_default_range=false
@@ -799,6 +893,7 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side
[system.tsunami]
type=Tsunami
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
+eventq_index=0
intrctrl=system.intrctrl
system=system
@@ -807,6 +902,7 @@ type=AlphaBackdoor
clk_domain=system.clk_domain
cpu=system.cpu0
disk=system.simple_disk
+eventq_index=0
pio_addr=8804682956800
pio_latency=100000
platform=system.tsunami
@@ -817,6 +913,7 @@ pio=system.iobus.master[24]
[system.tsunami.cchip]
type=TsunamiCChip
clk_domain=system.clk_domain
+eventq_index=0
pio_addr=8803072344064
pio_latency=100000
system=system
@@ -845,6 +942,7 @@ BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
+CapabilityPtr=0
CardbusCIS=0
ClassCode=2
Command=0
@@ -854,8 +952,40 @@ HeaderType=0
InterruptLine=30
InterruptPin=1
LatencyTimer=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
MaximumLatency=52
MinimumGrant=176
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
ProgIF=0
Revision=0
Status=656
@@ -872,6 +1002,7 @@ dma_read_delay=0
dma_read_factor=0
dma_write_delay=0
dma_write_factor=0
+eventq_index=0
hardware_address=00:90:00:00:00:01
intr_delay=10000000
pci_bus=0
@@ -895,6 +1026,7 @@ pio=system.iobus.master[27]
[system.tsunami.fake_OROM]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8796093677568
pio_latency=100000
@@ -912,6 +1044,7 @@ pio=system.iobus.master[8]
[system.tsunami.fake_ata0]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848432
pio_latency=100000
@@ -929,6 +1062,7 @@ pio=system.iobus.master[19]
[system.tsunami.fake_ata1]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848304
pio_latency=100000
@@ -946,6 +1080,7 @@ pio=system.iobus.master[20]
[system.tsunami.fake_pnp_addr]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848569
pio_latency=100000
@@ -963,6 +1098,7 @@ pio=system.iobus.master[9]
[system.tsunami.fake_pnp_read0]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848451
pio_latency=100000
@@ -980,6 +1116,7 @@ pio=system.iobus.master[11]
[system.tsunami.fake_pnp_read1]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848515
pio_latency=100000
@@ -997,6 +1134,7 @@ pio=system.iobus.master[12]
[system.tsunami.fake_pnp_read2]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848579
pio_latency=100000
@@ -1014,6 +1152,7 @@ pio=system.iobus.master[13]
[system.tsunami.fake_pnp_read3]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848643
pio_latency=100000
@@ -1031,6 +1170,7 @@ pio=system.iobus.master[14]
[system.tsunami.fake_pnp_read4]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848707
pio_latency=100000
@@ -1048,6 +1188,7 @@ pio=system.iobus.master[15]
[system.tsunami.fake_pnp_read5]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848771
pio_latency=100000
@@ -1065,6 +1206,7 @@ pio=system.iobus.master[16]
[system.tsunami.fake_pnp_read6]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848835
pio_latency=100000
@@ -1082,6 +1224,7 @@ pio=system.iobus.master[17]
[system.tsunami.fake_pnp_read7]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848899
pio_latency=100000
@@ -1099,6 +1242,7 @@ pio=system.iobus.master[18]
[system.tsunami.fake_pnp_write]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615850617
pio_latency=100000
@@ -1116,6 +1260,7 @@ pio=system.iobus.master[10]
[system.tsunami.fake_ppc]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848891
pio_latency=100000
@@ -1133,6 +1278,7 @@ pio=system.iobus.master[7]
[system.tsunami.fake_sm_chip]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848816
pio_latency=100000
@@ -1150,6 +1296,7 @@ pio=system.iobus.master[2]
[system.tsunami.fake_uart1]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848696
pio_latency=100000
@@ -1167,6 +1314,7 @@ pio=system.iobus.master[3]
[system.tsunami.fake_uart2]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848936
pio_latency=100000
@@ -1184,6 +1332,7 @@ pio=system.iobus.master[4]
[system.tsunami.fake_uart3]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848680
pio_latency=100000
@@ -1201,6 +1350,7 @@ pio=system.iobus.master[5]
[system.tsunami.fake_uart4]
type=IsaFake
clk_domain=system.clk_domain
+eventq_index=0
fake_mem=false
pio_addr=8804615848944
pio_latency=100000
@@ -1219,6 +1369,7 @@ pio=system.iobus.master[6]
type=BadDevice
clk_domain=system.clk_domain
devicename=FrameBuffer
+eventq_index=0
pio_addr=8804615848912
pio_latency=100000
system=system
@@ -1246,6 +1397,7 @@ BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
+CapabilityPtr=0
CardbusCIS=0
ClassCode=1
Command=0
@@ -1255,8 +1407,40 @@ HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
+MSICAPBaseOffset=0
+MSICAPCapId=0
+MSICAPMaskBits=0
+MSICAPMsgAddr=0
+MSICAPMsgCtrl=0
+MSICAPMsgData=0
+MSICAPMsgUpperAddr=0
+MSICAPNextCapability=0
+MSICAPPendingBits=0
+MSIXCAPBaseOffset=0
+MSIXCAPCapId=0
+MSIXCAPNextCapability=0
+MSIXMsgCtrl=0
+MSIXPbaOffset=0
+MSIXTableOffset=0
MaximumLatency=0
MinimumGrant=0
+PMCAPBaseOffset=0
+PMCAPCapId=0
+PMCAPCapabilities=0
+PMCAPCtrlStatus=0
+PMCAPNextCapability=0
+PXCAPBaseOffset=0
+PXCAPCapId=0
+PXCAPCapabilities=0
+PXCAPDevCap2=0
+PXCAPDevCapabilities=0
+PXCAPDevCtrl=0
+PXCAPDevCtrl2=0
+PXCAPDevStatus=0
+PXCAPLinkCap=0
+PXCAPLinkCtrl=0
+PXCAPLinkStatus=0
+PXCAPNextCapability=0
ProgIF=133
Revision=0
Status=640
@@ -1268,6 +1452,7 @@ clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=0
disks=system.disk0 system.disk2
+eventq_index=0
io_shift=0
pci_bus=0
pci_dev=0
@@ -1282,6 +1467,7 @@ pio=system.iobus.master[25]
[system.tsunami.io]
type=TsunamiIO
clk_domain=system.clk_domain
+eventq_index=0
frequency=976562500
pio_addr=8804615847936
pio_latency=100000
@@ -1294,6 +1480,7 @@ pio=system.iobus.master[22]
[system.tsunami.pchip]
type=TsunamiPChip
clk_domain=system.clk_domain
+eventq_index=0
pio_addr=8802535473152
pio_latency=100000
system=system
@@ -1304,6 +1491,7 @@ pio=system.iobus.master[1]
type=PciConfigAll
bus=0
clk_domain=system.clk_domain
+eventq_index=0
pio_addr=0
pio_latency=30000
platform=system.tsunami
@@ -1314,6 +1502,7 @@ pio=system.iobus.default
[system.tsunami.uart]
type=Uart8250
clk_domain=system.clk_domain
+eventq_index=0
pio_addr=8804615848952
pio_latency=100000
platform=system.tsunami
@@ -1323,5 +1512,6 @@ pio=system.iobus.master[23]
[system.voltage_domain]
type=VoltageDomain
+eventq_index=0
voltage=1.000000
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
index 739cb26e4..caa1e9081 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
@@ -1,145 +1,145 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.842698 # Number of seconds simulated
-sim_ticks 1842698476000 # Number of ticks simulated
-final_tick 1842698476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.842697 # Number of seconds simulated
+sim_ticks 1842697218000 # Number of ticks simulated
+final_tick 1842697218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 222585 # Simulator instruction rate (inst/s)
-host_op_rate 222585 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5605413242 # Simulator tick rate (ticks/s)
-host_mem_usage 334468 # Number of bytes of host memory used
-host_seconds 328.74 # Real time elapsed on the host
-sim_insts 73171582 # Number of instructions simulated
-sim_ops 73171582 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 489344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 20103680 # Number of bytes read from this memory
+host_inst_rate 189301 # Simulator instruction rate (inst/s)
+host_op_rate 189301 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4767309141 # Simulator tick rate (ticks/s)
+host_mem_usage 353980 # Number of bytes of host memory used
+host_seconds 386.53 # Real time elapsed on the host
+sim_insts 73170192 # Number of instructions simulated
+sim_ops 73170192 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 489152 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 20102912 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 144384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 2235712 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 284736 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 2526400 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28436608 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 489344 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 144384 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 284736 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 918464 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7460736 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7460736 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 7646 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 314120 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu1.inst 144448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 2236224 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 284928 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 2526528 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28436544 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 489152 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 144448 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 284928 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 918528 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7459712 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7459712 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 7643 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 314108 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2256 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 34933 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 4449 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 39475 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 444322 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 116574 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 116574 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 265558 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 10909913 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1439385 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 78355 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1213282 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 154521 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 1371033 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15432046 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 265558 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 78355 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 154521 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 498434 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4048810 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4048810 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4048810 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 265558 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 10909913 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1439385 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 78355 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 1213282 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 154521 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 1371033 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19480856 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 98004 # Number of read requests accepted
-system.physmem.writeReqs 44399 # Number of write requests accepted
-system.physmem.readBursts 98004 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 44399 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 6271808 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue
-system.physmem.bytesWritten 2840768 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 6272256 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 2841536 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::cpu1.inst 2257 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 34941 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 4452 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 39477 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 444321 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 116558 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 116558 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 265454 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 10909504 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1439386 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 78389 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1213560 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 154626 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 1371103 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15432022 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 265454 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 78389 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 154626 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 498469 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4048257 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4048257 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4048257 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 265454 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 10909504 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1439386 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 78389 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 1213560 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 154626 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 1371103 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19480279 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 98018 # Number of read requests accepted
+system.physmem.writeReqs 44365 # Number of write requests accepted
+system.physmem.readBursts 98018 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 44365 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 6272576 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue
+system.physmem.bytesWritten 2838464 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 6273152 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 2839360 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 40 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 6232 # Per bank write bursts
-system.physmem.perBankRdBursts::1 6028 # Per bank write bursts
-system.physmem.perBankRdBursts::2 6221 # Per bank write bursts
-system.physmem.perBankRdBursts::3 6513 # Per bank write bursts
-system.physmem.perBankRdBursts::4 5794 # Per bank write bursts
-system.physmem.perBankRdBursts::5 6242 # Per bank write bursts
-system.physmem.perBankRdBursts::6 5925 # Per bank write bursts
-system.physmem.perBankRdBursts::7 6039 # Per bank write bursts
-system.physmem.perBankRdBursts::8 6348 # Per bank write bursts
-system.physmem.perBankRdBursts::9 6026 # Per bank write bursts
-system.physmem.perBankRdBursts::10 6373 # Per bank write bursts
-system.physmem.perBankRdBursts::11 5867 # Per bank write bursts
-system.physmem.perBankRdBursts::12 5876 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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-system.physmem.totGap 1841686150500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
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@@ -151,181 +151,177 @@ system.physmem.rdQLenPdf::28 0 # Wh
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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-system.physmem.bytesPerActivate::mean 508.141439 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::stdev 1572.275953 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1088-1091 35 0.20% 92.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1155 50 0.28% 92.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1219 54 0.30% 92.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1283 63 0.35% 93.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1347 30 0.17% 93.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1411 123 0.69% 94.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1475 74 0.41% 94.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1539 80 0.45% 94.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1603 19 0.11% 95.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1667 17 0.09% 95.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1731 7 0.04% 95.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1795 37 0.21% 95.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1859 7 0.04% 95.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1923 18 0.10% 95.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1987 6 0.03% 95.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2051 15 0.08% 95.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2115 9 0.05% 95.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2179 16 0.09% 95.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2243 1 0.01% 95.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2307 23 0.13% 95.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2435 12 0.07% 95.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2499 4 0.02% 95.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2563 9 0.05% 96.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2691 15 0.08% 96.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2819 22 0.12% 96.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2883 1 0.01% 96.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2947 14 0.08% 96.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3011 3 0.02% 96.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3075 12 0.07% 96.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3139 2 0.01% 96.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3203 12 0.07% 96.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3267 2 0.01% 96.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3331 20 0.11% 96.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3459 11 0.06% 96.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3523 2 0.01% 96.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3587 9 0.05% 96.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3715 13 0.07% 96.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3843 21 0.12% 96.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3907 1 0.01% 96.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968-3971 13 0.07% 97.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4035 2 0.01% 97.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4099 8 0.04% 97.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4163 3 0.02% 97.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224-4227 14 0.08% 97.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352-4355 22 0.12% 97.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480-4483 13 0.07% 97.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544-4547 1 0.01% 97.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4608-4611 77 0.43% 97.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4736-4739 3 0.02% 97.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4867 19 0.11% 97.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992-4995 5 0.03% 97.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5056-5059 2 0.01% 97.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120-5123 8 0.04% 98.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5248-5251 4 0.02% 98.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376-5379 21 0.12% 98.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5504-5507 6 0.03% 98.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632-5635 9 0.05% 98.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5696-5699 2 0.01% 98.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5760-5763 3 0.02% 98.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5891 21 0.12% 98.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6016-6019 3 0.02% 98.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6144-6147 5 0.03% 98.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6016-6019 3 0.02% 98.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6147 6 0.03% 98.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6275 5 0.03% 98.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6403 19 0.11% 98.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6531 6 0.03% 98.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6592-6595 1 0.01% 98.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6659 6 0.03% 98.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6787 25 0.14% 98.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6848-6851 1 0.01% 98.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6915 15 0.08% 98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6979 1 0.01% 98.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7168-7171 20 0.11% 98.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7488-7491 2 0.01% 98.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7680-7683 2 0.01% 98.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::7936-7939 1 0.01% 98.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8000-8003 2 0.01% 99.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8192-8195 52 0.29% 99.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8384-8387 1 0.01% 99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8448-8451 1 0.01% 99.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::8896-8899 2 0.01% 99.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9216-9219 1 0.01% 99.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9408-9411 1 0.01% 99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9792-9795 1 0.01% 99.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::9856-9859 1 0.01% 99.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10048-10051 1 0.01% 99.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10240-10243 1 0.01% 99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10688-10691 1 0.01% 99.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::10880-10883 4 0.02% 99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11264-11267 1 0.01% 99.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::11840-11843 1 0.01% 99.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12032-12035 2 0.01% 99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::12736-12739 1 0.01% 99.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13056-13059 1 0.01% 99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13120-13123 1 0.01% 99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13248-13251 2 0.01% 99.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14272-14275 1 0.01% 99.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14400-14403 1 0.01% 99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14592-14595 1 0.01% 99.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14656-14659 1 0.01% 99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14912-14915 1 0.01% 99.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::14976-14979 1 0.01% 99.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15040-15043 1 0.01% 99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15168-15171 1 0.01% 99.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15360-15363 14 0.08% 99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15424-15427 1 0.01% 99.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::15552-15555 1 0.01% 99.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16064-16067 1 0.01% 99.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::16384-16387 76 0.42% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 17930 # Bytes accessed per row activation
-system.physmem.totQLat 2684942500 # Total ticks spent queuing
-system.physmem.totMemAccLat 4336678750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 489985000 # Total ticks spent in databus transfers
-system.physmem.totBankLat 1161751250 # Total ticks spent accessing banks
-system.physmem.avgQLat 27398.21 # Average queueing delay per DRAM burst
-system.physmem.avgBankLat 11854.97 # Average bank access latency per DRAM burst
+system.physmem.bytesPerActivate::7040-7043 1 0.01% 98.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7168-7171 21 0.12% 98.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7424-7427 1 0.01% 98.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7680-7683 4 0.02% 99.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8000-8003 1 0.01% 99.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8195 52 0.29% 99.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8960-8963 1 0.01% 99.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9216-9219 1 0.01% 99.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9344-9347 1 0.01% 99.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9408-9411 1 0.01% 99.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9536-9539 1 0.01% 99.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9856-9859 1 0.01% 99.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::10880-10883 2 0.01% 99.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::11008-11011 1 0.01% 99.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::11328-11331 1 0.01% 99.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::11392-11395 1 0.01% 99.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::11776-11779 1 0.01% 99.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::12032-12035 1 0.01% 99.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::12096-12099 1 0.01% 99.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::12672-12675 1 0.01% 99.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::12800-12803 2 0.01% 99.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::13056-13059 1 0.01% 99.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::13312-13315 2 0.01% 99.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14208-14211 1 0.01% 99.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14272-14275 1 0.01% 99.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14336-14339 2 0.01% 99.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14464-14467 1 0.01% 99.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14656-14659 1 0.01% 99.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14976-14979 1 0.01% 99.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15104-15107 1 0.01% 99.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15168-15171 1 0.01% 99.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15232-15235 1 0.01% 99.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15360-15363 16 0.09% 99.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15488-15491 1 0.01% 99.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15680-15683 1 0.01% 99.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16128-16131 1 0.01% 99.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16384-16387 75 0.42% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 17929 # Bytes accessed per row activation
+system.physmem.totQLat 2679388500 # Total ticks spent queuing
+system.physmem.totMemAccLat 4331514750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 490045000 # Total ticks spent in databus transfers
+system.physmem.totBankLat 1162081250 # Total ticks spent accessing banks
+system.physmem.avgQLat 27338.19 # Average queueing delay per DRAM burst
+system.physmem.avgBankLat 11856.88 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44253.18 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 44195.07 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.40 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.40 # Average system read bandwidth in MiByte/s
@@ -335,229 +331,233 @@ system.physmem.busUtil 0.04 # Da
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.18 # Average write queue length when enqueuing
-system.physmem.readRowHits 89612 # Number of row buffer hits during reads
-system.physmem.writeRowHits 34842 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 91.44 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 78.47 # Row buffer hit rate for writes
-system.physmem.avgGap 12932916.80 # Average gap between requests
+system.physmem.avgWrQLen 0.16 # Average write queue length when enqueuing
+system.physmem.readRowHits 89637 # Number of row buffer hits during reads
+system.physmem.writeRowHits 34794 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 91.46 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 78.43 # Row buffer hit rate for writes
+system.physmem.avgGap 12934724.60 # Average gap between requests
system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state
-system.membus.throughput 19524796 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 44746 # Transaction distribution
-system.membus.trans_dist::ReadResp 44539 # Transaction distribution
-system.membus.trans_dist::WriteReq 3750 # Transaction distribution
-system.membus.trans_dist::WriteResp 3750 # Transaction distribution
-system.membus.trans_dist::Writeback 44399 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 43 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 43 # Transaction distribution
-system.membus.trans_dist::ReadExReq 56527 # Transaction distribution
-system.membus.trans_dist::ReadExResp 56527 # Transaction distribution
-system.membus.trans_dist::BadAddressError 207 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13312 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189934 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 414 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 203660 # Packet count per connected master and slave (bytes)
+system.membus.throughput 19524219 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 44737 # Transaction distribution
+system.membus.trans_dist::ReadResp 44533 # Transaction distribution
+system.membus.trans_dist::WriteReq 3749 # Transaction distribution
+system.membus.trans_dist::WriteResp 3749 # Transaction distribution
+system.membus.trans_dist::Writeback 44365 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 45 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 45 # Transaction distribution
+system.membus.trans_dist::ReadExReq 56547 # Transaction distribution
+system.membus.trans_dist::ReadExResp 56547 # Transaction distribution
+system.membus.trans_dist::BadAddressError 204 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13310 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189932 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 408 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 203650 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 50712 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 50712 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 254372 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15690 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6953984 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.l2c.mem_side::total 6969674 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total 254362 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15689 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6952704 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total 6968393 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2159808 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 2159808 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 9129482 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 35968328 # Total data (bytes)
+system.membus.tot_pkt_size::total 9128201 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 35967240 # Total data (bytes)
system.membus.snoop_data_through_bus 9984 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 12460500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 12468500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 511769750 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 514332500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 256500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 252500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 762797456 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 764298954 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 153003500 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 152995500 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.l2c.tags.replacements 337399 # number of replacements
-system.l2c.tags.tagsinuse 65421.710089 # Cycle average of tags in use
-system.l2c.tags.total_refs 2471820 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 402562 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 6.140222 # Average number of references to valid blocks.
+system.l2c.tags.replacements 337398 # number of replacements
+system.l2c.tags.tagsinuse 65420.701532 # Cycle average of tags in use
+system.l2c.tags.total_refs 2472173 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 402561 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 6.141114 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 54901.425298 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 2456.924718 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 2698.289857 # Average occupied blocks per requestor
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65421.910944 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54375.613506 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 67930.199910 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 55074.275218 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 56721.086251 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 23250.750000 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23250.750000 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56835.449663 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69927.324539 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 63963.336181 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65421.910944 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55646.553460 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 67930.199910 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63148.014366 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65421.910944 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55646.553460 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 67930.199910 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63148.014366 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 60249.822422 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@@ -668,14 +668,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.tags.replacements 41685 # number of replacements
-system.iocache.tags.tagsinuse 1.254914 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 1.254904 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 1694870261000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide 1.254914 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide 0.078432 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.078432 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 1694870354000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide 1.254904 # Average occupied blocks per requestor
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+system.iocache.tags.occ_percent::total 0.078431 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
@@ -684,14 +684,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide 9304463 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 9304463 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 5314395237 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 5314395237 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 5323699700 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 5323699700 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 5323699700 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 5323699700 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide 9303463 # number of ReadReq miss cycles
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+system.iocache.WriteReq_miss_latency::tsunami.ide 5314732731 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 5314732731 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 5324036194 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 5324036194 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 5324036194 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 5324036194 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
@@ -708,19 +708,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53783.023121 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 53783.023121 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 127897.459497 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 127897.459497 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 127590.166567 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 127590.166567 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 127590.166567 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 127590.166567 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 168405 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53777.242775 # average ReadReq miss latency
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+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 127905.581705 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 127905.581705 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 127598.231132 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 127598.231132 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 127598.231132 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 127598.231132 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 168308 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 12345 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 12241 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 13.641555 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 13.749530 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@@ -734,14 +734,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 16965
system.iocache.demand_mshr_misses::total 16965 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 16965 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5715463 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 5715463 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4435167237 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 4435167237 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 4440882700 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 4440882700 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 4440882700 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 4440882700 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5714463 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 5714463 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4435520731 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 4435520731 # number of WriteReq MSHR miss cycles
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+system.iocache.demand_mshr_miss_latency::total 4441235194 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 4441235194 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 4441235194 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.406623 # mshr miss rate for WriteReq accesses
@@ -750,14 +750,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 0.406591
system.iocache.demand_mshr_miss_rate::total 0.406591 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82832.797101 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 82832.797101 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 262498.060902 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 262498.060902 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 261767.326849 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 261767.326849 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 261767.326849 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 261767.326849 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82818.304348 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 82818.304348 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 262518.982659 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 262518.982659 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 261788.104568 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 261788.104568 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 261788.104568 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 261788.104568 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
@@ -775,22 +775,22 @@ system.cpu0.dtb.fetch_hits 0 # IT
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 4920992 # DTB read hits
+system.cpu0.dtb.read_hits 4920578 # DTB read hits
system.cpu0.dtb.read_misses 6099 # DTB read misses
system.cpu0.dtb.read_acv 126 # DTB read access violations
-system.cpu0.dtb.read_accesses 428234 # DTB read accesses
-system.cpu0.dtb.write_hits 3511178 # DTB write hits
+system.cpu0.dtb.read_accesses 428233 # DTB read accesses
+system.cpu0.dtb.write_hits 3510258 # DTB write hits
system.cpu0.dtb.write_misses 670 # DTB write misses
system.cpu0.dtb.write_acv 84 # DTB write access violations
system.cpu0.dtb.write_accesses 163777 # DTB write accesses
-system.cpu0.dtb.data_hits 8432170 # DTB hits
+system.cpu0.dtb.data_hits 8430836 # DTB hits
system.cpu0.dtb.data_misses 6769 # DTB misses
system.cpu0.dtb.data_acv 210 # DTB access violations
-system.cpu0.dtb.data_accesses 592011 # DTB accesses
-system.cpu0.itb.fetch_hits 2763046 # ITB hits
+system.cpu0.dtb.data_accesses 592010 # DTB accesses
+system.cpu0.itb.fetch_hits 2762930 # ITB hits
system.cpu0.itb.fetch_misses 3034 # ITB misses
system.cpu0.itb.fetch_acv 104 # ITB acv
-system.cpu0.itb.fetch_accesses 2766080 # ITB accesses
+system.cpu0.itb.fetch_accesses 2765964 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
@@ -803,51 +803,51 @@ system.cpu0.itb.data_hits 0 # DT
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 928344318 # number of cpu cycles simulated
+system.cpu0.numCycles 928345000 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 33880492 # Number of instructions committed
-system.cpu0.committedOps 33880492 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 31739536 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 169894 # Number of float alu accesses
-system.cpu0.num_func_calls 813170 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4699422 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 31739536 # number of integer instructions
-system.cpu0.num_fp_insts 169894 # number of float instructions
-system.cpu0.num_int_register_reads 44596322 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 23159667 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 87728 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 89270 # number of times the floating registers were written
-system.cpu0.num_mem_refs 8462332 # number of memory refs
-system.cpu0.num_load_insts 4942381 # Number of load instructions
-system.cpu0.num_store_insts 3519951 # Number of store instructions
-system.cpu0.num_idle_cycles 904625586.132235 # Number of idle cycles
-system.cpu0.num_busy_cycles 23718731.867765 # Number of busy cycles
+system.cpu0.committedInsts 33879417 # Number of instructions committed
+system.cpu0.committedOps 33879417 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 31738664 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 170028 # Number of float alu accesses
+system.cpu0.num_func_calls 812853 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 4700164 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 31738664 # number of integer instructions
+system.cpu0.num_fp_insts 170028 # number of float instructions
+system.cpu0.num_int_register_reads 44595421 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 23158595 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 87794 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 89338 # number of times the floating registers were written
+system.cpu0.num_mem_refs 8461010 # number of memory refs
+system.cpu0.num_load_insts 4941975 # Number of load instructions
+system.cpu0.num_store_insts 3519035 # Number of store instructions
+system.cpu0.num_idle_cycles 904626845.998199 # Number of idle cycles
+system.cpu0.num_busy_cycles 23718154.001801 # Number of busy cycles
system.cpu0.not_idle_fraction 0.025549 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.974451 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6416 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 211386 # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce 6418 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 211383 # number of hwrei instructions executed
system.cpu0.kern.ipl_count::0 74805 40.97% 40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 105698 57.89% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 182585 # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 182584 # number of times we switched to this ipl
system.cpu0.kern.ipl_good::0 73438 49.30% 49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 73438 49.30% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 148958 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1819501633500 98.74% 98.74% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 38918500 0.00% 98.74% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 365019000 0.02% 98.76% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 22792135500 1.24% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1842697706500 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::0 1819507118500 98.74% 98.74% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 38781000 0.00% 98.74% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 365071000 0.02% 98.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 22785478000 1.24% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1842696448500 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.694791 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.815828 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31 0.694797 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.815833 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
@@ -883,10 +883,10 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu
system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed
+system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 175326 91.20% 93.41% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 175325 91.20% 93.41% # number of callpals executed
system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
@@ -895,21 +895,21 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu
system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 192241 # number of callpals executed
+system.cpu0.kern.callpal::total 192238 # number of callpals executed
system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1739 # number of protection mode switches
-system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1909
-system.cpu0.kern.mode_good::user 1739
-system.cpu0.kern.mode_good::idle 170
-system.cpu0.kern.mode_switch_good::kernel 0.322357 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches
+system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches
+system.cpu0.kern.mode_good::kernel 1907
+system.cpu0.kern.mode_good::user 1738
+system.cpu0.kern.mode_good::idle 169
+system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.391309 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 29773270000 1.62% 1.62% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 2593332500 0.14% 1.76% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle 1810331099500 98.24% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 4177 # number of times the context was actually changed
+system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total 0.391019 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 29794763000 1.62% 1.62% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 2592746500 0.14% 1.76% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle 1810308934500 98.24% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.swap_context 4175 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
@@ -941,58 +941,59 @@ system.tsunami.ethernet.totalRxOrn 0 # to
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.throughput 110448008 # Throughput (bytes/s)
-system.toL2Bus.trans_dist::ReadReq 784800 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 784578 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 3750 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 3750 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 371852 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 150627 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 133731 # Transaction distribution
-system.toL2Bus.trans_dist::BadAddressError 207 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 846719 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1369630 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 2216349 # Packet count per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27094720 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55304714 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.tot_pkt_size::total 82399434 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.data_through_bus 203511688 # Total data (bytes)
-system.toL2Bus.snoop_data_through_bus 10688 # Total snoop data (bytes)
-system.toL2Bus.reqLayer0.occupancy 2136322000 # Layer occupancy (ticks)
+system.toL2Bus.throughput 110459996 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 784722 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 784503 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 3749 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 3749 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 371354 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 150558 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 133662 # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError 204 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 847542 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1368014 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 2215556 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27120896 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55237129 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 82358025 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 203533320 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 11008 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 2134008000 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 1907046997 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 1908780020 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 2233138904 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 2230620167 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.iobus.throughput 1469141 # Throughput (bytes/s)
+system.iobus.throughput 1469142 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 2975 # Transaction distribution
system.iobus.trans_dist::ReadResp 2975 # Transaction distribution
-system.iobus.trans_dist::WriteReq 20646 # Transaction distribution
-system.iobus.trans_dist::WriteResp 20646 # Transaction distribution
+system.iobus.trans_dist::WriteReq 20645 # Transaction distribution
+system.iobus.trans_dist::WriteResp 20645 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2330 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8372 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8370 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2374 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 13312 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 13310 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 47242 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 47240 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9320 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4186 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4185 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1548 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size_system.bridge.master::total 15690 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 15689 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.tot_pkt_size::total 1098482 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 1098481 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 2707184 # Total data (bytes)
system.iobus.reqLayer0.occupancy 2199000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
@@ -1000,368 +1001,384 @@ system.iobus.reqLayer1.occupancy 102000 # La
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 6239000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 6237000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 1789000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer29.occupancy 153606200 # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy 153613694 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 9562000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 9561000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 17411500 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 17409500 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.icache.tags.replacements 950723 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.190316 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 43428114 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 951234 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 45.654501 # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements 951005 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.190319 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 43429541 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 951516 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 45.642471 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 10399272250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.695807 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 99.603495 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst 159.891014 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.491593 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.194538 # Average percentage of cache occupancy
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-system.cpu0.icache.overall_avg_miss_latency::total 6452.263416 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 4969 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 740 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 199 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
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-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039373 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050580 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047212 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021711 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100862 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099697 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037414 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069556 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070849 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.032165 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069556 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070849 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.032165 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20769.786353 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16910.272766 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17998.451318 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35250.039245 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29537.732081 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31435.972269 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11180.946882 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12184.806630 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11898.650428 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25250.718423 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20208.564310 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21700.133982 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25250.718423 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20208.564310 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21700.133982 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 98671 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 251974 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 350645 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 44296 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 89132 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 133428 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2152 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5420 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7572 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 1 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 142967 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data 341106 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 484073 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 142967 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data 341106 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 484073 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2050323500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4260770982 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6311094482 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1561811741 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2625415492 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4187227233 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24184000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 65650250 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89834250 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 11000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3612135241 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6886186474 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 10498321715 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3612135241 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6886186474 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 10498321715 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296522000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 310560000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 607082000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 364175500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 426698000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 790873500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 660697500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 737258000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1397955500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083348 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086014 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039320 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050507 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047221 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021705 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099981 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099910 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037342 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000019 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069372 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070813 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.032132 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069372 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070813 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.032132 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20779.393135 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16909.565995 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17998.529801 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35258.527655 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29455.363865 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31381.923082 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11237.918216 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12112.592251 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11864.005547 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25265.517504 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20187.819839 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21687.476300 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25265.517504 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20187.819839 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21687.476300 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@@ -1376,22 +1393,22 @@ system.cpu1.dtb.fetch_hits 0 # IT
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1203387 # DTB read hits
+system.cpu1.dtb.read_hits 1203332 # DTB read hits
system.cpu1.dtb.read_misses 1366 # DTB read misses
system.cpu1.dtb.read_acv 34 # DTB read access violations
-system.cpu1.dtb.read_accesses 142939 # DTB read accesses
-system.cpu1.dtb.write_hits 898859 # DTB write hits
+system.cpu1.dtb.read_accesses 142940 # DTB read accesses
+system.cpu1.dtb.write_hits 898898 # DTB write hits
system.cpu1.dtb.write_misses 183 # DTB write misses
system.cpu1.dtb.write_acv 22 # DTB write access violations
system.cpu1.dtb.write_accesses 58529 # DTB write accesses
-system.cpu1.dtb.data_hits 2102246 # DTB hits
+system.cpu1.dtb.data_hits 2102230 # DTB hits
system.cpu1.dtb.data_misses 1549 # DTB misses
system.cpu1.dtb.data_acv 56 # DTB access violations
-system.cpu1.dtb.data_accesses 201468 # DTB accesses
-system.cpu1.itb.fetch_hits 859133 # ITB hits
+system.cpu1.dtb.data_accesses 201469 # DTB accesses
+system.cpu1.itb.fetch_hits 859402 # ITB hits
system.cpu1.itb.fetch_misses 692 # ITB misses
system.cpu1.itb.fetch_acv 30 # ITB acv
-system.cpu1.itb.fetch_accesses 859825 # ITB accesses
+system.cpu1.itb.fetch_accesses 860094 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
@@ -1404,28 +1421,28 @@ system.cpu1.itb.data_hits 0 # DT
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 953620014 # number of cpu cycles simulated
+system.cpu1.numCycles 953617285 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 7953643 # Number of instructions committed
-system.cpu1.committedOps 7953643 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 7410219 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 45003 # Number of float alu accesses
-system.cpu1.num_func_calls 212713 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1020267 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 7410219 # number of integer instructions
-system.cpu1.num_fp_insts 45003 # number of float instructions
-system.cpu1.num_int_register_reads 10384111 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 5386902 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 24304 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 24611 # number of times the floating registers were written
-system.cpu1.num_mem_refs 2109479 # number of memory refs
-system.cpu1.num_load_insts 1208276 # Number of load instructions
-system.cpu1.num_store_insts 901203 # Number of store instructions
-system.cpu1.num_idle_cycles 922135498.680812 # Number of idle cycles
-system.cpu1.num_busy_cycles 31484515.319188 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.033016 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.966984 # Percentage of idle cycles
+system.cpu1.committedInsts 7956345 # Number of instructions committed
+system.cpu1.committedOps 7956345 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 7412681 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 44901 # Number of float alu accesses
+system.cpu1.num_func_calls 213028 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1020887 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 7412681 # number of integer instructions
+system.cpu1.num_fp_insts 44901 # number of float instructions
+system.cpu1.num_int_register_reads 10388601 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 5388855 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 24208 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 24605 # number of times the floating registers were written
+system.cpu1.num_mem_refs 2109439 # number of memory refs
+system.cpu1.num_load_insts 1208206 # Number of load instructions
+system.cpu1.num_store_insts 901233 # Number of store instructions
+system.cpu1.num_idle_cycles 922131579.439540 # Number of idle cycles
+system.cpu1.num_busy_cycles 31485705.560460 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.033017 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.966983 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
@@ -1443,35 +1460,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
-system.cpu2.branchPred.lookups 9128355 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 8449925 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 124319 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 7461780 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 6520544 # Number of BTB hits
+system.cpu2.branchPred.lookups 9131296 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 8453261 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 124867 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 7606484 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 6524985 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 87.385905 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 281902 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 13317 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 85.781880 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 282035 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 13344 # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
-system.cpu2.dtb.read_hits 3185589 # DTB read hits
-system.cpu2.dtb.read_misses 11798 # DTB read misses
-system.cpu2.dtb.read_acv 121 # DTB read access violations
-system.cpu2.dtb.read_accesses 217406 # DTB read accesses
-system.cpu2.dtb.write_hits 2009886 # DTB write hits
-system.cpu2.dtb.write_misses 2608 # DTB write misses
-system.cpu2.dtb.write_acv 106 # DTB write access violations
-system.cpu2.dtb.write_accesses 82301 # DTB write accesses
-system.cpu2.dtb.data_hits 5195475 # DTB hits
-system.cpu2.dtb.data_misses 14406 # DTB misses
-system.cpu2.dtb.data_acv 227 # DTB access violations
-system.cpu2.dtb.data_accesses 299707 # DTB accesses
-system.cpu2.itb.fetch_hits 369992 # ITB hits
-system.cpu2.itb.fetch_misses 5727 # ITB misses
-system.cpu2.itb.fetch_acv 273 # ITB acv
-system.cpu2.itb.fetch_accesses 375719 # ITB accesses
+system.cpu2.dtb.read_hits 3186348 # DTB read hits
+system.cpu2.dtb.read_misses 11810 # DTB read misses
+system.cpu2.dtb.read_acv 124 # DTB read access violations
+system.cpu2.dtb.read_accesses 217745 # DTB read accesses
+system.cpu2.dtb.write_hits 2009701 # DTB write hits
+system.cpu2.dtb.write_misses 2606 # DTB write misses
+system.cpu2.dtb.write_acv 109 # DTB write access violations
+system.cpu2.dtb.write_accesses 82375 # DTB write accesses
+system.cpu2.dtb.data_hits 5196049 # DTB hits
+system.cpu2.dtb.data_misses 14416 # DTB misses
+system.cpu2.dtb.data_acv 233 # DTB access violations
+system.cpu2.dtb.data_accesses 300120 # DTB accesses
+system.cpu2.itb.fetch_hits 370442 # ITB hits
+system.cpu2.itb.fetch_misses 5628 # ITB misses
+system.cpu2.itb.fetch_acv 253 # ITB acv
+system.cpu2.itb.fetch_accesses 376070 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
@@ -1484,137 +1501,137 @@ system.cpu2.itb.data_hits 0 # DT
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
-system.cpu2.numCycles 31308710 # number of cpu cycles simulated
+system.cpu2.numCycles 31313073 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 8320877 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 36988805 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 9128355 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 6802446 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 8846835 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 603748 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles 9639992 # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles 11047 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 1973 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 63718 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 87241 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 497 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 2552980 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 86276 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 27364450 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.351710 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.294118 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 8328585 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 37006400 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 9131296 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 6807020 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 8851345 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 606644 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles 9641968 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles 10046 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 1931 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 63228 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 87070 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 340 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 2553376 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 86779 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 27379324 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.351618 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.293970 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 18517615 67.67% 67.67% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 268760 0.98% 68.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 429758 1.57% 70.22% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 4997201 18.26% 88.48% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 759565 2.78% 91.26% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 164512 0.60% 91.86% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 190396 0.70% 92.56% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 427414 1.56% 94.12% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 1609229 5.88% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 18527979 67.67% 67.67% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 269262 0.98% 68.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 428968 1.57% 70.22% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 5000608 18.26% 88.49% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 759354 2.77% 91.26% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 165275 0.60% 91.86% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 190932 0.70% 92.56% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 427573 1.56% 94.12% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 1609373 5.88% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 27364450 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.291560 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.181422 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 8471005 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 9721532 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 8236973 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 308822 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 380199 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 165870 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 12770 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 36596033 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 40157 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 380199 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 8829996 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 2781091 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 5750095 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 8109315 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 1267845 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 35455371 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 2432 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 230458 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 443882 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands 23756988 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 44373855 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 44317462 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 52634 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 21971271 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 1785717 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 500561 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 59005 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 3706520 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 3341982 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 2099682 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 368903 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 258103 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 32963824 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 619272 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 32519364 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 32677 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 2138512 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 1074729 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 437003 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 27364450 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.188380 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.575952 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 27379324 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.291613 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.181819 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 8475609 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 9724872 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 8241247 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 308907 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 382752 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 165606 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 12712 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 36612854 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 39749 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 382752 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 8834671 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 2773280 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 5760129 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 8113478 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 1269087 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 35472103 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 2436 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 230799 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents 444723 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands 23769376 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 44394567 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 44338159 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 52651 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 21967508 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 1801868 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 500326 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 58967 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 3713170 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 3346051 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 2099971 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 366369 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 258671 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 32979578 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 619087 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 32529976 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 34753 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 2147129 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 1082645 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 436861 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 27379324 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.188122 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.575744 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 15094542 55.16% 55.16% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 3058510 11.18% 66.34% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 1555503 5.68% 72.02% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 5825063 21.29% 93.31% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 904805 3.31% 96.62% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 480018 1.75% 98.37% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 285628 1.04% 99.41% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 141467 0.52% 99.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 18914 0.07% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 15104518 55.17% 55.17% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 3059496 11.17% 66.34% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 1557193 5.69% 72.03% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 5827645 21.28% 93.31% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 904106 3.30% 96.62% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 480512 1.76% 98.37% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 285612 1.04% 99.41% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 141433 0.52% 99.93% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 18809 0.07% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 27364450 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 27379324 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 33388 13.55% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.55% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 112327 45.58% 59.13% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 100703 40.87% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 32920 13.41% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.41% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 112185 45.69% 59.09% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 100449 40.91% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 26855600 82.58% 82.59% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 20032 0.06% 82.65% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 26864472 82.58% 82.59% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 20045 0.06% 82.65% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.65% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 8424 0.03% 82.68% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 8419 0.03% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.68% # Type of FU issued
@@ -1640,114 +1657,114 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.68% # Ty
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.68% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.68% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 3311528 10.18% 92.87% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 2031960 6.25% 99.11% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess 288160 0.89% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 3313279 10.19% 92.87% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 2032055 6.25% 99.11% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess 288046 0.89% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 32519364 # Type of FU issued
-system.cpu2.iq.rate 1.038668 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 246418 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.007578 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 92448223 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 35610975 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 32122316 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 234050 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 114559 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 110669 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 32641435 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 121907 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 186593 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 32529976 # Type of FU issued
+system.cpu2.iq.rate 1.038862 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 245554 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.007549 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 92485827 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 35635212 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 32132884 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 233756 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 114401 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 110529 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 32651329 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 121761 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 186414 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 407978 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 1104 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 4025 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 156833 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 413956 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 1112 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 3936 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 157547 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 4157 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 26970 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 4151 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 27254 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 380199 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 2010765 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 204147 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 34852291 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 222063 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 3341982 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 2099682 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 549953 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 141753 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 1988 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 4025 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 63582 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 127875 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 191457 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 32361861 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 3205658 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 157503 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 382752 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 2003866 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 204399 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 34866454 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 220221 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 3346051 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 2099971 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 549960 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 142228 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 1969 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 3936 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 63951 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 128015 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 191966 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 32372492 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 3206448 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 157484 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 1269195 # number of nop insts executed
-system.cpu2.iew.exec_refs 5222587 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 7560841 # Number of branches executed
-system.cpu2.iew.exec_stores 2016929 # Number of stores executed
-system.cpu2.iew.exec_rate 1.033638 # Inst execution rate
-system.cpu2.iew.wb_sent 32266608 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 32232985 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 18776213 # num instructions producing a value
-system.cpu2.iew.wb_consumers 21965918 # num instructions consuming a value
+system.cpu2.iew.exec_nop 1267789 # number of nop insts executed
+system.cpu2.iew.exec_refs 5223192 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 7564928 # Number of branches executed
+system.cpu2.iew.exec_stores 2016744 # Number of stores executed
+system.cpu2.iew.exec_rate 1.033833 # Inst execution rate
+system.cpu2.iew.wb_sent 32276755 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 32243413 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 18781769 # num instructions producing a value
+system.cpu2.iew.wb_consumers 21976070 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.029521 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.854788 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.029711 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.854646 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 2305690 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 182269 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 176747 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 26984251 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.204438 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.848007 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 2322975 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 182226 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 177336 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 26996572 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.203754 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.846865 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 16102351 59.67% 59.67% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 2321930 8.60% 68.28% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1225737 4.54% 72.82% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 5569081 20.64% 93.46% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 502606 1.86% 95.32% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 185666 0.69% 96.01% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 176683 0.65% 96.66% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 180209 0.67% 97.33% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 719988 2.67% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 16110852 59.68% 59.68% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 2323792 8.61% 68.29% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1227035 4.55% 72.83% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 5572191 20.64% 93.47% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 501625 1.86% 95.33% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 185779 0.69% 96.02% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 177561 0.66% 96.67% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 179863 0.67% 97.34% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 717874 2.66% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 26984251 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 32500866 # Number of instructions committed
-system.cpu2.commit.committedOps 32500866 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 26996572 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 32497229 # Number of instructions committed
+system.cpu2.commit.committedOps 32497229 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 4876853 # Number of memory references committed
-system.cpu2.commit.loads 2934004 # Number of loads committed
-system.cpu2.commit.membars 63840 # Number of memory barriers committed
-system.cpu2.commit.branches 7415854 # Number of branches committed
-system.cpu2.commit.fp_insts 109494 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 31057555 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 228510 # Number of function calls committed.
-system.cpu2.commit.bw_lim_events 719988 # number cycles where commit BW limit reached
+system.cpu2.commit.refs 4874519 # Number of memory references committed
+system.cpu2.commit.loads 2932095 # Number of loads committed
+system.cpu2.commit.membars 63814 # Number of memory barriers committed
+system.cpu2.commit.branches 7417113 # Number of branches committed
+system.cpu2.commit.fp_insts 109328 # Number of committed floating point instructions.
+system.cpu2.commit.int_insts 31054650 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 228340 # Number of function calls committed.
+system.cpu2.commit.bw_lim_events 717874 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 60996891 # The number of ROB reads
-system.cpu2.rob.rob_writes 69992925 # The number of ROB writes
-system.cpu2.timesIdled 244953 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 3944260 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 1746464525 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 31337447 # Number of Instructions Simulated
-system.cpu2.committedOps 31337447 # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total 31337447 # Number of Instructions Simulated
-system.cpu2.cpi 0.999083 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 0.999083 # CPI: Total CPI of All Threads
-system.cpu2.ipc 1.000918 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 1.000918 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 42570866 # number of integer regfile reads
-system.cpu2.int_regfile_writes 22648106 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 67644 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 67951 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 5345306 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 257045 # number of misc regfile writes
+system.cpu2.rob.rob_reads 61024976 # The number of ROB reads
+system.cpu2.rob.rob_writes 70022633 # The number of ROB writes
+system.cpu2.timesIdled 244840 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 3933749 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 1746460059 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 31334430 # Number of Instructions Simulated
+system.cpu2.committedOps 31334430 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 31334430 # Number of Instructions Simulated
+system.cpu2.cpi 0.999318 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 0.999318 # CPI: Total CPI of All Threads
+system.cpu2.ipc 1.000682 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 1.000682 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 42582766 # number of integer regfile reads
+system.cpu2.int_regfile_writes 22654603 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 67639 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 67817 # number of floating regfile writes
+system.cpu2.misc_regfile_reads 5347337 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 256988 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 09:03:11 +0000