diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/fs/10.linux-boot/ref/alpha | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
4 files changed, 5227 insertions, 5220 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index e432f371b..421497f85 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.884236 # Number of seconds simulated -sim_ticks 1884235597000 # Number of ticks simulated -final_tick 1884235597000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.887184 # Number of seconds simulated +sim_ticks 1887184463000 # Number of ticks simulated +final_tick 1887184463000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167027 # Simulator instruction rate (inst/s) -host_op_rate 167027 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5607682389 # Simulator tick rate (ticks/s) -host_mem_usage 359752 # Number of bytes of host memory used -host_seconds 336.01 # Real time elapsed on the host -sim_insts 56122640 # Number of instructions simulated -sim_ops 56122640 # Number of ops (including micro ops) simulated +host_inst_rate 275099 # Simulator instruction rate (inst/s) +host_op_rate 275099 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9249537203 # Simulator tick rate (ticks/s) +host_mem_usage 373576 # Number of bytes of host memory used +host_seconds 204.03 # Real time elapsed on the host +sim_insts 56128524 # Number of instructions simulated +sim_ops 56128524 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1053184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24861632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1052352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24860224 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25915776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1053184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1053184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7561856 # Number of bytes written to this memory -system.physmem.bytes_written::total 7561856 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388463 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25913536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1052352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1052352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7558400 # Number of bytes written to this memory +system.physmem.bytes_written::total 7558400 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388441 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404934 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118154 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118154 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 558945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13194545 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404899 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118100 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118100 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 557631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13173182 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13754000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 558945 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 558945 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4013222 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4013222 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4013222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 558945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13194545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13731321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 557631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 557631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4005120 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4005120 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4005120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 557631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13173182 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17767222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404934 # Number of read requests accepted -system.physmem.writeReqs 159706 # Number of write requests accepted -system.physmem.readBursts 404934 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159706 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25910208 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5568 # Total number of bytes read from write queue -system.physmem.bytesWritten 10081344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25915776 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10221184 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 87 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2165 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25481 # Per bank write bursts -system.physmem.perBankRdBursts::1 25742 # Per bank write bursts -system.physmem.perBankRdBursts::2 25839 # Per bank write bursts -system.physmem.perBankRdBursts::3 25784 # Per bank write bursts -system.physmem.perBankRdBursts::4 25228 # Per bank write bursts -system.physmem.perBankRdBursts::5 24953 # Per bank write bursts -system.physmem.perBankRdBursts::6 24817 # Per bank write bursts -system.physmem.perBankRdBursts::7 24560 # Per bank write bursts -system.physmem.perBankRdBursts::8 25102 # Per bank write bursts -system.physmem.perBankRdBursts::9 25274 # Per bank write bursts -system.physmem.perBankRdBursts::10 25530 # Per bank write bursts -system.physmem.perBankRdBursts::11 24856 # Per bank write bursts -system.physmem.perBankRdBursts::12 24523 # Per bank write bursts -system.physmem.perBankRdBursts::13 25574 # Per bank write bursts -system.physmem.perBankRdBursts::14 25845 # Per bank write bursts +system.physmem.bw_total::total 17736441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404899 # Number of read requests accepted +system.physmem.writeReqs 159652 # Number of write requests accepted +system.physmem.readBursts 404899 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159652 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25907328 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue +system.physmem.bytesWritten 8556800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25913536 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10217728 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 25922 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25492 # Per bank write bursts +system.physmem.perBankRdBursts::1 25732 # Per bank write bursts +system.physmem.perBankRdBursts::2 25844 # Per bank write bursts +system.physmem.perBankRdBursts::3 25788 # Per bank write bursts +system.physmem.perBankRdBursts::4 25096 # Per bank write bursts +system.physmem.perBankRdBursts::5 25019 # Per bank write bursts +system.physmem.perBankRdBursts::6 24724 # Per bank write bursts +system.physmem.perBankRdBursts::7 24556 # Per bank write bursts +system.physmem.perBankRdBursts::8 25196 # Per bank write bursts +system.physmem.perBankRdBursts::9 25300 # Per bank write bursts +system.physmem.perBankRdBursts::10 25394 # Per bank write bursts +system.physmem.perBankRdBursts::11 24993 # Per bank write bursts +system.physmem.perBankRdBursts::12 24525 # Per bank write bursts +system.physmem.perBankRdBursts::13 25570 # Per bank write bursts +system.physmem.perBankRdBursts::14 25834 # Per bank write bursts system.physmem.perBankRdBursts::15 25739 # Per bank write bursts -system.physmem.perBankWrBursts::0 10323 # Per bank write bursts -system.physmem.perBankWrBursts::1 10094 # Per bank write bursts -system.physmem.perBankWrBursts::2 10597 # Per bank write bursts -system.physmem.perBankWrBursts::3 9998 # Per bank write bursts -system.physmem.perBankWrBursts::4 9794 # Per bank write bursts -system.physmem.perBankWrBursts::5 9430 # Per bank write bursts -system.physmem.perBankWrBursts::6 9122 # Per bank write bursts -system.physmem.perBankWrBursts::7 8746 # Per bank write bursts -system.physmem.perBankWrBursts::8 9866 # Per bank write bursts -system.physmem.perBankWrBursts::9 8965 # Per bank write bursts -system.physmem.perBankWrBursts::10 9841 # Per bank write bursts -system.physmem.perBankWrBursts::11 9391 # Per bank write bursts -system.physmem.perBankWrBursts::12 9895 # Per bank write bursts -system.physmem.perBankWrBursts::13 10602 # Per bank write bursts -system.physmem.perBankWrBursts::14 10396 # Per bank write bursts -system.physmem.perBankWrBursts::15 10461 # Per bank write bursts +system.physmem.perBankWrBursts::0 8904 # Per bank write bursts +system.physmem.perBankWrBursts::1 8550 # Per bank write bursts +system.physmem.perBankWrBursts::2 9125 # Per bank write bursts +system.physmem.perBankWrBursts::3 8822 # Per bank write bursts +system.physmem.perBankWrBursts::4 8179 # Per bank write bursts +system.physmem.perBankWrBursts::5 8016 # Per bank write bursts +system.physmem.perBankWrBursts::6 7555 # Per bank write bursts +system.physmem.perBankWrBursts::7 7379 # Per bank write bursts +system.physmem.perBankWrBursts::8 8271 # Per bank write bursts +system.physmem.perBankWrBursts::9 7751 # Per bank write bursts +system.physmem.perBankWrBursts::10 8147 # Per bank write bursts +system.physmem.perBankWrBursts::11 7873 # Per bank write bursts +system.physmem.perBankWrBursts::12 8188 # Per bank write bursts +system.physmem.perBankWrBursts::13 9058 # Per bank write bursts +system.physmem.perBankWrBursts::14 9003 # Per bank write bursts +system.physmem.perBankWrBursts::15 8879 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1884226862500 # Total gap between requests +system.physmem.numWrRetry 49 # Number of times write queue was full causing retry +system.physmem.totGap 1887175688500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404934 # Read request sizes (log2) +system.physmem.readPktSize::6 404899 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 159706 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see +system.physmem.writePktSize::6 159652 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -148,193 +148,182 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65747 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 547.425008 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 336.336786 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.790126 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14590 22.19% 22.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10813 16.45% 38.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4856 7.39% 46.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3188 4.85% 50.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2531 3.85% 54.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1959 2.98% 57.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1455 2.21% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1675 2.55% 62.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24680 37.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65747 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5741 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.518028 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2788.038880 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5738 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64790 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 531.935916 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 325.040765 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.485108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14695 22.68% 22.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10955 16.91% 39.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5460 8.43% 48.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3097 4.78% 52.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2483 3.83% 56.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1877 2.90% 59.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1493 2.30% 61.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1431 2.21% 64.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23299 35.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64790 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4900 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 82.608776 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3017.174786 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4897 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5741 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5741 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.437903 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.774518 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 33.753883 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4686 81.62% 81.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 175 3.05% 84.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 305 5.31% 89.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 60 1.05% 91.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 91 1.59% 92.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 55 0.96% 93.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 13 0.23% 93.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 10 0.17% 93.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 19 0.33% 94.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.09% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 16 0.28% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 10 0.17% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 11 0.19% 95.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 3 0.05% 95.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 17 0.30% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 40 0.70% 96.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 20 0.35% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 16 0.28% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 94 1.64% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 33 0.57% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 16 0.28% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 17 0.30% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 9 0.16% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.09% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.05% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5741 # Writes before turning the bus around for reads -system.physmem.totQLat 2143675250 # Total ticks spent queuing -system.physmem.totMemAccLat 9734556500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2024235000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5295.03 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4900 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4900 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.285714 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.337905 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 63.692079 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 4662 95.14% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 56 1.14% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 11 0.22% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 6 0.12% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 26 0.53% 97.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 25 0.51% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 16 0.33% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 2 0.04% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 6 0.12% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 8 0.16% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 21 0.43% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 21 0.43% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 2 0.04% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 6 0.12% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 7 0.14% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 9 0.18% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-575 5 0.10% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-703 3 0.06% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-735 7 0.14% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1088-1119 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4900 # Writes before turning the bus around for reads +system.physmem.totQLat 2145870750 # Total ticks spent queuing +system.physmem.totMemAccLat 9735908250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2024010000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5301.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24045.03 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.75 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.75 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.42 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 24051.04 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.53 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.41 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage +system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.52 # Average write queue length when enqueuing -system.physmem.readRowHits 364210 # Number of row buffer hits during reads -system.physmem.writeRowHits 132411 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.05 # Row buffer hit rate for writes -system.physmem.avgGap 3337041.06 # Average gap between requests -system.physmem.pageHitRate 88.31 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 243152280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132672375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1578751200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 506113920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 123068977200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 59789504475 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1078093355250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1263412526700 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.517914 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1793297401750 # Time in different power states -system.physmem_0.memoryStateTime::REF 62918700000 # Time in different power states +system.physmem.avgWrQLen 25.13 # Average write queue length when enqueuing +system.physmem.readRowHits 363622 # Number of row buffer hits during reads +system.physmem.writeRowHits 110090 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.32 # Row buffer hit rate for writes +system.physmem.avgGap 3342790.44 # Average gap between requests +system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 238971600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130391250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577557800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 431114400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 60578040195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1079167578750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1265384866875 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.517315 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1795079554966 # Time in different power states +system.physmem_0.memoryStateTime::REF 63016980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28017727000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29080496284 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 253895040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 138534000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579055400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 514622160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 123068977200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 60612218820 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1077371684250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1263538986870 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.585024 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1792097761500 # Time in different power states -system.physmem_1.memoryStateTime::REF 62918700000 # Time in different power states +system.physmem_1.actEnergy 250840800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136867500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579897800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 435261600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61601133195 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1078270137000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1265535350775 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.597050 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1793586337716 # Time in different power states +system.physmem_1.memoryStateTime::REF 63016980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 29217381000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30573727284 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 15006303 # Number of BP lookups -system.cpu.branchPred.condPredicted 13014667 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 375459 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9787101 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5202858 # Number of BTB hits +system.cpu.branchPred.lookups 15007831 # Number of BP lookups +system.cpu.branchPred.condPredicted 13016266 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 375462 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9968114 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5203851 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 53.160359 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 808926 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32598 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 52.204971 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 809053 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32834 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9241313 # DTB read hits -system.cpu.dtb.read_misses 17796 # DTB read misses +system.cpu.dtb.read_hits 9242509 # DTB read hits +system.cpu.dtb.read_misses 17824 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766310 # DTB read accesses -system.cpu.dtb.write_hits 6385986 # DTB write hits -system.cpu.dtb.write_misses 2327 # DTB write misses -system.cpu.dtb.write_acv 160 # DTB write access violations -system.cpu.dtb.write_accesses 298447 # DTB write accesses -system.cpu.dtb.data_hits 15627299 # DTB hits -system.cpu.dtb.data_misses 20123 # DTB misses -system.cpu.dtb.data_acv 371 # DTB access violations -system.cpu.dtb.data_accesses 1064757 # DTB accesses -system.cpu.itb.fetch_hits 4016976 # ITB hits -system.cpu.itb.fetch_misses 6883 # ITB misses -system.cpu.itb.fetch_acv 674 # ITB acv -system.cpu.itb.fetch_accesses 4023859 # ITB accesses +system.cpu.dtb.read_accesses 766347 # DTB read accesses +system.cpu.dtb.write_hits 6385998 # DTB write hits +system.cpu.dtb.write_misses 2322 # DTB write misses +system.cpu.dtb.write_acv 159 # DTB write access violations +system.cpu.dtb.write_accesses 298454 # DTB write accesses +system.cpu.dtb.data_hits 15628507 # DTB hits +system.cpu.dtb.data_misses 20146 # DTB misses +system.cpu.dtb.data_acv 370 # DTB access violations +system.cpu.dtb.data_accesses 1064801 # DTB accesses +system.cpu.itb.fetch_hits 4019475 # ITB hits +system.cpu.itb.fetch_misses 6849 # ITB misses +system.cpu.itb.fetch_acv 693 # ITB acv +system.cpu.itb.fetch_accesses 4026324 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -347,39 +336,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 175257245 # number of cpu cycles simulated +system.cpu.numCycles 180833283 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56122640 # Number of instructions committed -system.cpu.committedOps 56122640 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2496382 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5595 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593213949 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.122755 # CPI: cycles per instruction -system.cpu.ipc 0.320230 # IPC: instructions per cycle +system.cpu.committedInsts 56128524 # Number of instructions committed +system.cpu.committedOps 56128524 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2493053 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5493 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3593535643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.221772 # CPI: cycles per instruction +system.cpu.ipc 0.310388 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211475 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74790 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211489 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74799 40.94% 40.94% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105864 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182686 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73423 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105874 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182705 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73432 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73423 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148878 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1833807390500 97.32% 97.32% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 80545000 0.00% 97.33% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 673176000 0.04% 97.36% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 49673506000 2.64% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1884234617500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73432 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148896 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1834551091000 97.21% 97.21% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 80458000 0.00% 97.22% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 676198500 0.04% 97.25% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 51875728000 2.75% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1887183475500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693560 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814939 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814953 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -415,115 +404,115 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4170 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175527 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175546 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6805 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192413 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5870 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.325383 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 192427 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5873 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2089 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1906 +system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_good::idle 167 +system.cpu.kern.mode_switch_good::kernel 0.324536 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393490 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36258202500 1.92% 1.92% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4079939000 0.22% 2.14% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1843896466000 97.86% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.tickCycles 84474734 # Number of cycles that the object actually ticked -system.cpu.idleCycles 90782511 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395383 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.982334 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13772439 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395895 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.866386 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 86820250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.982334 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999965 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy +system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392949 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 36591764000 1.94% 1.94% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4134630500 0.22% 2.16% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1846457071000 97.84% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4171 # number of times the context was actually changed +system.cpu.tickCycles 84552258 # Number of cycles that the object actually ticked +system.cpu.idleCycles 96281025 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395325 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.981737 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13774282 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395837 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.868116 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 90985250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.981737 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63656284 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63656284 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7814297 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7814297 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5576378 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5576378 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182732 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182732 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 198999 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 198999 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13390675 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13390675 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13390675 # number of overall hits -system.cpu.dcache.overall_hits::total 13390675 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201640 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201640 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 573763 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573763 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17288 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17288 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1775403 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1775403 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1775403 # number of overall misses -system.cpu.dcache.overall_misses::total 1775403 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31034654250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31034654250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20679395543 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20679395543 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 231275750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 231275750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 51714049793 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51714049793 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 51714049793 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51714049793 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9015937 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9015937 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6150141 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6150141 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200020 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200020 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 198999 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 198999 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15166078 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15166078 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15166078 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15166078 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133280 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133280 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093293 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093293 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086431 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086431 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117064 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117064 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117064 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117064 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25826.915091 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25826.915091 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36041.702834 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36041.702834 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13377.819875 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13377.819875 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29128.062639 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29128.062639 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29128.062639 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29128.062639 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63660758 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63660758 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7815437 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815437 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5576995 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5576995 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182818 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182818 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 198995 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 198995 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13392432 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13392432 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13392432 # number of overall hits +system.cpu.dcache.overall_hits::total 13392432 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201539 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201539 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 573249 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573249 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17197 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17197 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1774788 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1774788 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1774788 # number of overall misses +system.cpu.dcache.overall_misses::total 1774788 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32999838250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32999838250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22461596052 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22461596052 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230671750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 230671750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 55461434302 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 55461434302 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 55461434302 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 55461434302 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9016976 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9016976 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6150244 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6150244 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200015 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200015 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 198995 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 198995 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15167220 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15167220 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15167220 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15167220 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133253 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133253 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093208 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093208 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085979 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085979 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117015 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117015 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117015 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117015 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.641805 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.641805 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39182.965957 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39182.965957 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.487818 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.487818 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31249.610828 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31249.610828 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31249.610828 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31249.610828 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -532,64 +521,64 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838265 # number of writebacks -system.cpu.dcache.writebacks::total 838265 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127268 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127268 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269487 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269487 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838171 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10249005096 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10249005096 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 196537750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196537750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37166642096 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37166642096 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37166642096 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37166642096 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423897500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423897500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2002909000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002909000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3426806500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426806500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119164 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119164 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049475 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049475 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086416 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086416 # 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average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26958.761117 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26958.761117 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26958.761117 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26958.761117 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 396104 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 396104 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 396104 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 396104 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074431 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074431 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304253 # 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number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2018255500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3451560000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3451560000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049470 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049470 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085964 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085964 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090899 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17111152616 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17111152616 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17111152616 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071489 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071489 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071489 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11718.691332 # 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number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887480500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3221270000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221270000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011271 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249365 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113128 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383443 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383443 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011271 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278592 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141928 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011271 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278592 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141928 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60215.531385 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52608.159389 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53041.852143 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15942 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15942 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56539.364471 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56539.364471 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60215.531385 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53787.611893 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54048.584026 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60215.531385 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53787.611893 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54048.584026 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 76588 # number of writebacks +system.cpu.l2cache.writebacks::total 76588 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16444 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272210 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288654 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 20 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 20 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116658 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116658 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16444 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388868 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405312 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16444 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388868 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405312 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1116961750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16343103250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17460065000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 455517 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 455517 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7500878889 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7500878889 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1116961750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23843982139 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24960943889 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1116961750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23843982139 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24960943889 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336266500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336266500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893208000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893208000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229474500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229474500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249369 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113140 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.833333 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.833333 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383419 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383419 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278588 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141938 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278588 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141938 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67925.185478 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60038.585100 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60487.867828 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22775.850000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22775.850000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64298.024045 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64298.024045 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67925.185478 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61316.390495 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61584.517332 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67925.185478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61316.390495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61584.517332 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -861,42 +850,42 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2558889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2558856 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2558469 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2558436 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 838265 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304285 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304285 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 838171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41593 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304257 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304257 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2920255 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663385 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6583640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93446144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143040604 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236486748 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41944 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3736082 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.011168 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105088 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2919473 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663181 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6582654 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93421056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143030876 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236451932 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41987 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3735584 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.011181 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105146 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3694357 98.88% 98.88% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41725 1.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3693818 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41766 1.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3736082 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2698528498 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3735584 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2698164499 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2193867384 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2193277658 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194759654 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2194690407 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -969,23 +958,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406197789 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242093194 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.296028 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.302259 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1728025570000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.296028 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081002 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081002 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1729989085000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.302259 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081391 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081391 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -999,14 +988,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635920906 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13635920906 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8777958811 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8777958811 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) @@ -1023,19 +1012,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328165.212409 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328165.212409 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206267 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211252.378008 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 211252.378008 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 73082 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23556 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10004 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.756453 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.305278 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1049,14 +1038,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11475216906 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11475216906 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6617254811 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6617254811 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1065,61 +1054,61 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276165.212409 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276165.212409 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159252.378008 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159252.378008 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 295774 # Transaction distribution -system.membus.trans_dist::ReadResp 295758 # Transaction distribution +system.membus.trans_dist::ReadReq 295757 # Transaction distribution +system.membus.trans_dist::ReadResp 295741 # Transaction distribution system.membus.trans_dist::WriteReq 9619 # Transaction distribution system.membus.trans_dist::WriteResp 9619 # Transaction distribution -system.membus.trans_dist::Writeback 118154 # Transaction distribution +system.membus.trans_dist::Writeback 118100 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 156 # Transaction distribution -system.membus.trans_dist::UpgradeResp 156 # Transaction distribution -system.membus.trans_dist::ReadExReq 116537 # Transaction distribution -system.membus.trans_dist::ReadExResp 116537 # Transaction distribution +system.membus.trans_dist::UpgradeReq 159 # Transaction distribution +system.membus.trans_dist::UpgradeResp 159 # Transaction distribution +system.membus.trans_dist::ReadExReq 116519 # Transaction distribution +system.membus.trans_dist::ReadExResp 116519 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887063 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886945 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920193 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920075 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1044997 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1044879 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30819904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30864220 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30814208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30858524 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36181276 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36175580 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 565243 # Request fanout histogram +system.membus.snoop_fanout::samples 565206 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 565243 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 565206 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 565243 # Request fanout histogram -system.membus.reqLayer0.occupancy 30308000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 565206 # Request fanout histogram +system.membus.reqLayer0.occupancy 30238000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1878196000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1230315562 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3792332596 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160768093 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 38c6e11f9..24a65d69d 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.901175 # Number of seconds simulated -sim_ticks 1901175003500 # Number of ticks simulated -final_tick 1901175003500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.904438 # Number of seconds simulated +sim_ticks 1904437574000 # Number of ticks simulated +final_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 154934 # Simulator instruction rate (inst/s) -host_op_rate 154934 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5197600055 # Simulator tick rate (ticks/s) -host_mem_usage 378544 # Number of bytes of host memory used -host_seconds 365.78 # Real time elapsed on the host -sim_insts 56671579 # Number of instructions simulated -sim_ops 56671579 # Number of ops (including micro ops) simulated +host_inst_rate 150033 # Simulator instruction rate (inst/s) +host_op_rate 150033 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5049661741 # Simulator tick rate (ticks/s) +host_mem_usage 379720 # Number of bytes of host memory used +host_seconds 377.14 # Real time elapsed on the host +sim_insts 56583768 # Number of instructions simulated +sim_ops 56583768 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 885824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24795264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 95808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 496320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 878144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24662016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 107328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 745792 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26274176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 885824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 95808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 981632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7885056 # Number of bytes written to this memory -system.physmem.bytes_written::total 7885056 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13841 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387426 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1497 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7755 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26394240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 878144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 107328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 985472 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7983616 # Number of bytes written to this memory +system.physmem.bytes_written::total 7983616 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13721 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385344 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1677 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11653 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410534 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123204 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123204 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 465935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13042073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 50394 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 261060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13819967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 465935 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 50394 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4147465 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4147465 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4147465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 465935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13042073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 50394 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 261060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 505 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17967432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410534 # Number of read requests accepted -system.physmem.writeReqs 164756 # Number of write requests accepted -system.physmem.readBursts 410534 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 164756 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26267904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6272 # Total number of bytes read from write queue -system.physmem.bytesWritten 10393408 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26274176 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10544384 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 98 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2335 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4921 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25742 # Per bank write bursts -system.physmem.perBankRdBursts::1 25822 # Per bank write bursts -system.physmem.perBankRdBursts::2 25939 # Per bank write bursts -system.physmem.perBankRdBursts::3 25643 # Per bank write bursts -system.physmem.perBankRdBursts::4 25873 # Per bank write bursts -system.physmem.perBankRdBursts::5 25657 # Per bank write bursts -system.physmem.perBankRdBursts::6 25709 # Per bank write bursts -system.physmem.perBankRdBursts::7 25201 # Per bank write bursts -system.physmem.perBankRdBursts::8 25222 # Per bank write bursts -system.physmem.perBankRdBursts::9 26115 # Per bank write bursts -system.physmem.perBankRdBursts::10 25677 # Per bank write bursts -system.physmem.perBankRdBursts::11 25575 # Per bank write bursts -system.physmem.perBankRdBursts::12 25800 # Per bank write bursts -system.physmem.perBankRdBursts::13 26085 # Per bank write bursts -system.physmem.perBankRdBursts::14 25301 # Per bank write bursts -system.physmem.perBankRdBursts::15 25075 # Per bank write bursts -system.physmem.perBankWrBursts::0 10194 # Per bank write bursts -system.physmem.perBankWrBursts::1 10103 # Per bank write bursts -system.physmem.perBankWrBursts::2 10030 # Per bank write bursts -system.physmem.perBankWrBursts::3 9736 # Per bank write bursts -system.physmem.perBankWrBursts::4 9490 # Per bank write bursts -system.physmem.perBankWrBursts::5 10167 # Per bank write bursts -system.physmem.perBankWrBursts::6 10200 # Per bank write bursts -system.physmem.perBankWrBursts::7 9338 # Per bank write bursts -system.physmem.perBankWrBursts::8 9741 # Per bank write bursts -system.physmem.perBankWrBursts::9 10459 # Per bank write bursts -system.physmem.perBankWrBursts::10 10157 # Per bank write bursts -system.physmem.perBankWrBursts::11 10688 # Per bank write bursts -system.physmem.perBankWrBursts::12 11170 # Per bank write bursts -system.physmem.perBankWrBursts::13 11200 # Per bank write bursts -system.physmem.perBankWrBursts::14 10147 # Per bank write bursts -system.physmem.perBankWrBursts::15 9577 # Per bank write bursts +system.physmem.num_reads::total 412410 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124744 # Number of write requests responded to by this memory +system.physmem.num_writes::total 124744 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 461104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12949763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 391607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13859336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 461104 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517461 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4192112 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4192112 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4192112 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 461104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12949763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 56357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 391607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18051448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 412410 # Number of read requests accepted +system.physmem.writeReqs 166296 # Number of write requests accepted +system.physmem.readBursts 412410 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 166296 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26387648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue +system.physmem.bytesWritten 9015296 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26394240 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10642944 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 25417 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4739 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25681 # Per bank write bursts +system.physmem.perBankRdBursts::1 26031 # Per bank write bursts +system.physmem.perBankRdBursts::2 26262 # Per bank write bursts +system.physmem.perBankRdBursts::3 25929 # Per bank write bursts +system.physmem.perBankRdBursts::4 25778 # Per bank write bursts +system.physmem.perBankRdBursts::5 25597 # Per bank write bursts +system.physmem.perBankRdBursts::6 26273 # Per bank write bursts +system.physmem.perBankRdBursts::7 25295 # Per bank write bursts +system.physmem.perBankRdBursts::8 25970 # Per bank write bursts +system.physmem.perBankRdBursts::9 26150 # Per bank write bursts +system.physmem.perBankRdBursts::10 25721 # Per bank write bursts +system.physmem.perBankRdBursts::11 25208 # Per bank write bursts +system.physmem.perBankRdBursts::12 25640 # Per bank write bursts +system.physmem.perBankRdBursts::13 25768 # Per bank write bursts +system.physmem.perBankRdBursts::14 25547 # Per bank write bursts +system.physmem.perBankRdBursts::15 25457 # Per bank write bursts +system.physmem.perBankWrBursts::0 9358 # Per bank write bursts +system.physmem.perBankWrBursts::1 9077 # Per bank write bursts +system.physmem.perBankWrBursts::2 9200 # Per bank write bursts +system.physmem.perBankWrBursts::3 8756 # Per bank write bursts +system.physmem.perBankWrBursts::4 8419 # Per bank write bursts +system.physmem.perBankWrBursts::5 8251 # Per bank write bursts +system.physmem.perBankWrBursts::6 9072 # Per bank write bursts +system.physmem.perBankWrBursts::7 8046 # Per bank write bursts +system.physmem.perBankWrBursts::8 8692 # Per bank write bursts +system.physmem.perBankWrBursts::9 8978 # Per bank write bursts +system.physmem.perBankWrBursts::10 8574 # Per bank write bursts +system.physmem.perBankWrBursts::11 8968 # Per bank write bursts +system.physmem.perBankWrBursts::12 8555 # Per bank write bursts +system.physmem.perBankWrBursts::13 9260 # Per bank write bursts +system.physmem.perBankWrBursts::14 8896 # Per bank write bursts +system.physmem.perBankWrBursts::15 8762 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 1901170614000 # Total gap between requests +system.physmem.numWrRetry 50 # Number of times write queue was full causing retry +system.physmem.totGap 1904433039500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410534 # Read request sizes (log2) +system.physmem.readPktSize::6 412410 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 164756 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 40588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 166296 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 39027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,193 +158,200 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67203 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 545.527075 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 333.566914 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.530844 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14928 22.21% 22.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11337 16.87% 39.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5205 7.75% 46.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2937 4.37% 51.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2377 3.54% 54.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1798 2.68% 57.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1602 2.38% 59.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1684 2.51% 62.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25335 37.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67203 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6020 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 68.178073 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2721.311016 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 6017 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 92 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66375 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 533.371902 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 326.032515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.702689 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14841 22.36% 22.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11366 17.12% 39.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5910 8.90% 48.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2909 4.38% 52.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2416 3.64% 56.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1747 2.63% 59.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1634 2.46% 61.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1312 1.98% 63.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24240 36.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66375 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5272 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.206942 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2891.855588 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5269 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6020 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6020 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 26.976246 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.646869 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 33.117275 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4955 82.31% 82.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 186 3.09% 85.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 316 5.25% 90.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 58 0.96% 91.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 93 1.54% 93.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 41 0.68% 93.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 21 0.35% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 11 0.18% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 26 0.43% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.07% 94.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 17 0.28% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.07% 95.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 7 0.12% 95.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.03% 95.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 20 0.33% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 42 0.70% 96.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 17 0.28% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 7 0.12% 96.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 80 1.33% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 45 0.75% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 12 0.20% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 27 0.45% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 6 0.10% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.08% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 4 0.07% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.03% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.07% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 4 0.07% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6020 # Writes before turning the bus around for reads -system.physmem.totQLat 3885054500 # Total ticks spent queuing -system.physmem.totMemAccLat 11580729500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2052180000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9465.68 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5272 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5272 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 26.719272 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.348145 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 60.306865 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5026 95.33% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 55 1.04% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 6 0.11% 96.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 3 0.06% 96.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 6 0.11% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 3 0.06% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 3 0.06% 96.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 6 0.11% 96.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 24 0.46% 97.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 10 0.19% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 9 0.17% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 16 0.30% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 2 0.04% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 3 0.06% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.06% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 4 0.08% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 1 0.02% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 4 0.08% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 6 0.11% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 11 0.21% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 13 0.25% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 7 0.13% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 10 0.19% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.06% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 2 0.04% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 11 0.21% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.06% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 5 0.09% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 3 0.06% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 2 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 3 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::896-911 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5272 # Writes before turning the bus around for reads +system.physmem.totQLat 4111304500 # Total ticks spent queuing +system.physmem.totMemAccLat 11842060750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2061535000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9971.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28215.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.47 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.55 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28721.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.86 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.77 # Average write queue length when enqueuing -system.physmem.readRowHits 370181 # Number of row buffer hits during reads -system.physmem.writeRowHits 135448 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.39 # Row buffer hit rate for writes -system.physmem.avgGap 3304716.95 # Average gap between requests -system.physmem.pageHitRate 88.26 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 253260000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 138187500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1603570800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 513591840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124175095200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 57090888495 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1090621618500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1274396212335 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.322456 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1814181645000 # Time in different power states -system.physmem_0.memoryStateTime::REF 63484200000 # Time in different power states +system.physmem.avgRdQLen 2.27 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing +system.physmem.readRowHits 371693 # Number of row buffer hits during reads +system.physmem.writeRowHits 115102 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.15 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.70 # Row buffer hit rate for writes +system.physmem.avgGap 3290847.23 # Average gap between requests +system.physmem.pageHitRate 88.00 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 251551440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 137255250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1613398800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 454759920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 57693505320 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1092050470500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1276589123070 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.325620 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1816548038492 # Time in different power states +system.physmem_0.memoryStateTime::REF 63593140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23503077500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 24290182758 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 254688840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 138967125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1597455600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 538429680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124175095200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 57028143465 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1090676670000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1274409449910 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.329412 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1814277217000 # Time in different power states -system.physmem_1.memoryStateTime::REF 63484200000 # Time in different power states +system.physmem_1.actEnergy 250137720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136483875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1602190200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 457604640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 57661176915 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1092078837000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1276574612190 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.317995 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1816597555496 # Time in different power states +system.physmem_1.memoryStateTime::REF 63593140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23408681000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 24242350004 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 16131633 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14074847 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 326763 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 9526803 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5411642 # Number of BTB hits +system.cpu0.branchPred.lookups 16050181 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14012515 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 321303 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 9883832 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5384164 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 56.804387 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 814199 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 17678 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 54.474459 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 809394 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 17633 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9231009 # DTB read hits -system.cpu0.dtb.read_misses 34580 # DTB read misses -system.cpu0.dtb.read_acv 535 # DTB read access violations -system.cpu0.dtb.read_accesses 687791 # DTB read accesses -system.cpu0.dtb.write_hits 5940395 # DTB write hits -system.cpu0.dtb.write_misses 7538 # DTB write misses -system.cpu0.dtb.write_acv 382 # DTB write access violations -system.cpu0.dtb.write_accesses 237219 # DTB write accesses -system.cpu0.dtb.data_hits 15171404 # DTB hits -system.cpu0.dtb.data_misses 42118 # DTB misses -system.cpu0.dtb.data_acv 917 # DTB access violations -system.cpu0.dtb.data_accesses 925010 # DTB accesses -system.cpu0.itb.fetch_hits 1435355 # ITB hits -system.cpu0.itb.fetch_misses 29386 # ITB misses -system.cpu0.itb.fetch_acv 625 # ITB acv -system.cpu0.itb.fetch_accesses 1464741 # ITB accesses +system.cpu0.dtb.read_hits 9185685 # DTB read hits +system.cpu0.dtb.read_misses 31794 # DTB read misses +system.cpu0.dtb.read_acv 464 # DTB read access violations +system.cpu0.dtb.read_accesses 674724 # DTB read accesses +system.cpu0.dtb.write_hits 5856177 # DTB write hits +system.cpu0.dtb.write_misses 6642 # DTB write misses +system.cpu0.dtb.write_acv 308 # DTB write access violations +system.cpu0.dtb.write_accesses 220970 # DTB write accesses +system.cpu0.dtb.data_hits 15041862 # DTB hits +system.cpu0.dtb.data_misses 38436 # DTB misses +system.cpu0.dtb.data_acv 772 # DTB access violations +system.cpu0.dtb.data_accesses 895694 # DTB accesses +system.cpu0.itb.fetch_hits 1413849 # ITB hits +system.cpu0.itb.fetch_misses 27924 # ITB misses +system.cpu0.itb.fetch_acv 522 # ITB acv +system.cpu0.itb.fetch_accesses 1441773 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -357,466 +364,465 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 112944275 # number of cpu cycles simulated +system.cpu0.numCycles 115311619 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26734623 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 70871158 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16131633 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6225841 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 78572167 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1087344 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 938 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 28136 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1452901 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 461019 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 278 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8195583 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 233790 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 107793734 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.657470 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.965319 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 26308115 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 70327057 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16050181 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6193558 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 81501759 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1071492 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 564 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 28477 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1405877 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 453989 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 199 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8110639 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 231031 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 110234726 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.637976 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.938280 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 94531257 87.70% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 858509 0.80% 88.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1823492 1.69% 90.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 785861 0.73% 90.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2602190 2.41% 93.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 590625 0.55% 93.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 664328 0.62% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 839547 0.78% 95.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5097925 4.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 97059343 88.05% 88.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 844439 0.77% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1832569 1.66% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 778966 0.71% 91.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2587591 2.35% 93.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 590382 0.54% 94.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 655112 0.59% 94.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 842956 0.76% 95.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5043368 4.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 107793734 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.142828 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.627488 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 21731474 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 75223274 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8544304 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1787077 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 507604 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 524648 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 36495 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62167212 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 115754 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 507604 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 22589385 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 48401768 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 19164228 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9376952 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7753795 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 60013920 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 204923 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2024034 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 144343 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 3822558 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 40119139 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72975711 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72834321 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 131688 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 35221894 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4897237 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1480119 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 216056 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12920416 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9368350 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6206352 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1340557 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 962340 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53512619 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1895957 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52599778 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 52230 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6392747 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3006442 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1305426 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 107793734 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.487967 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.221871 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 110234726 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.139190 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.609887 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 21404943 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 78060690 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8511786 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1756604 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 500702 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 518589 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35397 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 61724420 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 110442 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 500702 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 22241314 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 51035680 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18875449 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9340106 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 8241473 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 59592973 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 194522 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2018079 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 142482 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4327383 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 39868450 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72416227 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72269697 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 136600 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34997307 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4871143 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1466604 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 213801 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12439963 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9310742 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6112181 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1342468 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 951279 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 53110388 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1887245 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52243998 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 50112 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6322079 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2924940 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1298251 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 110234726 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.473934 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.210494 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 86044446 79.82% 79.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9475309 8.79% 88.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3928815 3.64% 92.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2790586 2.59% 94.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2836372 2.63% 97.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1349941 1.25% 98.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 893970 0.83% 99.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 358292 0.33% 99.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 116003 0.11% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 88757561 80.52% 80.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9303542 8.44% 88.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3888317 3.53% 92.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2690563 2.44% 94.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2829805 2.57% 97.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1399486 1.27% 98.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 891988 0.81% 99.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 364157 0.33% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 109307 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 107793734 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 110234726 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 177733 18.25% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 467063 47.95% 66.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 329340 33.81% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 184539 19.02% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 463483 47.76% 66.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 322428 33.22% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 36087462 68.61% 68.61% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57222 0.11% 68.72% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.72% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 28709 0.05% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9582527 18.22% 87.00% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6011046 11.43% 98.43% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 827159 1.57% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 4481 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35873428 68.67% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57323 0.11% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 30345 0.06% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 2234 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9533353 18.25% 87.09% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5924969 11.34% 98.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 817865 1.57% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52599778 # Type of FU issued -system.cpu0.iq.rate 0.465714 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 974136 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018520 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 213441030 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61548330 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 51220095 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 578625 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 270952 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 265721 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 53258517 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 311627 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 583786 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52243998 # Type of FU issued +system.cpu0.iq.rate 0.453068 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 970450 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018575 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 215148578 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61059123 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50866456 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 594706 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 278076 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 273817 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 52889876 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 320091 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 579148 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1112279 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 5019 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18330 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 503254 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1102308 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4274 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 17841 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 488268 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18853 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 369989 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18769 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 362429 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 507604 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 44339596 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1604348 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58817574 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 124782 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9368350 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6206352 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1675353 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 48473 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1332642 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18330 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 164161 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 356822 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 520983 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 52091421 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9288991 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 508356 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 500702 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 47770294 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 975694 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 58389413 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 117266 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9310742 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6112181 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1666926 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 38737 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 734939 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 17841 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 161758 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 354564 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 516322 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51738600 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9239994 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 505398 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3408998 # number of nop insts executed -system.cpu0.iew.exec_refs 15250639 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8273174 # Number of branches executed -system.cpu0.iew.exec_stores 5961648 # Number of stores executed -system.cpu0.iew.exec_rate 0.461213 # Inst execution rate -system.cpu0.iew.wb_sent 51600991 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51485816 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26436063 # num instructions producing a value -system.cpu0.iew.wb_consumers 36546981 # num instructions consuming a value +system.cpu0.iew.exec_nop 3391780 # number of nop insts executed +system.cpu0.iew.exec_refs 15116199 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8225133 # Number of branches executed +system.cpu0.iew.exec_stores 5876205 # Number of stores executed +system.cpu0.iew.exec_rate 0.448685 # Inst execution rate +system.cpu0.iew.wb_sent 51252595 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51140273 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26435135 # num instructions producing a value +system.cpu0.iew.wb_consumers 36676301 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.455851 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.723345 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.443496 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.720769 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7016261 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 590531 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 476969 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 106554717 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.485172 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.424408 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6957791 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 588994 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 471378 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 109009912 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.470894 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.405994 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 88252662 82.82% 82.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7298996 6.85% 89.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3974083 3.73% 93.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2090799 1.96% 95.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1561874 1.47% 96.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 585444 0.55% 97.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 439090 0.41% 97.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 445608 0.42% 98.21% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1906161 1.79% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 90895183 83.38% 83.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7166067 6.57% 89.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3956975 3.63% 93.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2029230 1.86% 95.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1623676 1.49% 96.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 582620 0.53% 97.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 429957 0.39% 97.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 432812 0.40% 98.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1893392 1.74% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 106554717 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51697359 # Number of instructions committed -system.cpu0.commit.committedOps 51697359 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 109009912 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51332073 # Number of instructions committed +system.cpu0.commit.committedOps 51332073 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13959169 # Number of memory references committed -system.cpu0.commit.loads 8256071 # Number of loads committed -system.cpu0.commit.membars 200989 # Number of memory barriers committed -system.cpu0.commit.branches 7816314 # Number of branches committed -system.cpu0.commit.fp_insts 262681 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47879291 # Number of committed integer instructions. -system.cpu0.commit.function_calls 663768 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2971590 5.75% 5.75% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 33646334 65.08% 70.83% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55999 0.11% 70.94% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.94% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 28236 0.05% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8457060 16.36% 87.36% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5709098 11.04% 98.40% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 827159 1.60% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13832347 # Number of memory references committed +system.cpu0.commit.loads 8208434 # Number of loads committed +system.cpu0.commit.membars 200823 # Number of memory barriers committed +system.cpu0.commit.branches 7767218 # Number of branches committed +system.cpu0.commit.fp_insts 270478 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47526784 # Number of committed integer instructions. +system.cpu0.commit.function_calls 660195 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2960587 5.77% 5.77% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 33426068 65.12% 70.88% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 56116 0.11% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 30044 0.06% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 2234 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8409257 16.38% 87.44% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5629902 10.97% 98.41% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 817865 1.59% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51697359 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1906161 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 51332073 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1893392 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 163161097 # The number of ROB reads -system.cpu0.rob.rob_writes 118660594 # The number of ROB writes -system.cpu0.timesIdled 501791 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5150541 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3689405733 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48729536 # Number of Instructions Simulated -system.cpu0.committedOps 48729536 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.317779 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.317779 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.431448 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.431448 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 68466406 # number of integer regfile reads -system.cpu0.int_regfile_writes 37249066 # number of integer regfile writes -system.cpu0.fp_regfile_reads 130692 # number of floating regfile reads -system.cpu0.fp_regfile_writes 131766 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1811017 # number of misc regfile reads -system.cpu0.misc_regfile_writes 827352 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1291740 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.889209 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10636670 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1292252 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.231111 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 25151000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.889209 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988065 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988065 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 57483025 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 57483025 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6556019 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6556019 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3715997 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3715997 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164872 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 164872 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189733 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 189733 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10272016 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10272016 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10272016 # number of overall hits -system.cpu0.dcache.overall_hits::total 10272016 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1615331 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1615331 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1779982 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1779982 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21282 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21282 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2627 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2627 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3395313 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3395313 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3395313 # number of overall misses -system.cpu0.dcache.overall_misses::total 3395313 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40801843239 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 40801843239 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 80191363617 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 80191363617 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336613990 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 336613990 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 19436381 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 19436381 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 120993206856 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 120993206856 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 120993206856 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 120993206856 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8171350 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8171350 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495979 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5495979 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 186154 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 186154 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192360 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 192360 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13667329 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13667329 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13667329 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13667329 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197682 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197682 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323870 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323870 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.114325 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.114325 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.013657 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.013657 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248425 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248425 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248425 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248425 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25259.122272 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25259.122272 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45051.783455 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45051.783455 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15816.840053 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15816.840053 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7398.698515 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7398.698515 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35635.361705 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35635.361705 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35635.361705 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35635.361705 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3895440 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3799 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 167914 # number of cycles access was blocked +system.cpu0.rob.rob_reads 165216916 # The number of ROB reads +system.cpu0.rob.rob_writes 117798939 # The number of ROB writes +system.cpu0.timesIdled 506110 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5076893 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3693292578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48375955 # Number of Instructions Simulated +system.cpu0.committedOps 48375955 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.383656 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.383656 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.419524 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.419524 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 67964697 # number of integer regfile reads +system.cpu0.int_regfile_writes 37032803 # number of integer regfile writes +system.cpu0.fp_regfile_reads 135608 # number of floating regfile reads +system.cpu0.fp_regfile_writes 136877 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1822860 # number of misc regfile reads +system.cpu0.misc_regfile_writes 821150 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1283357 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.867544 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10588066 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1283792 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.247493 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 26416000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.867544 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988023 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988023 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 435 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.849609 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 56965784 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56965784 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6531926 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6531926 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3699481 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3699481 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164387 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 164387 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189172 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 189172 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10231407 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10231407 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10231407 # number of overall hits +system.cpu0.dcache.overall_hits::total 10231407 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1592146 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1592146 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1718300 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1718300 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20836 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20836 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2478 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2478 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3310446 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3310446 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3310446 # number of overall misses +system.cpu0.dcache.overall_misses::total 3310446 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39294199360 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 39294199360 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76231824796 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 76231824796 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326020750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 326020750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20798848 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 20798848 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 115526024156 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 115526024156 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 115526024156 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 115526024156 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8124072 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8124072 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5417781 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5417781 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 185223 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 185223 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191650 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 191650 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13541853 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13541853 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13541853 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13541853 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195979 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.195979 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.317159 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.317159 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112491 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112491 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.012930 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.012930 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244460 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.244460 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244460 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.244460 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24680.022661 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 24680.022661 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44364.677179 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44364.677179 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15646.993185 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15646.993185 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8393.401130 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8393.401130 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34897.419911 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34897.419911 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4226969 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4392 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 103766 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.199019 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 40.414894 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.735588 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 46.723404 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 762456 # number of writebacks -system.cpu0.dcache.writebacks::total 762456 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 593909 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 593909 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1512221 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1512221 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5168 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5168 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2106130 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2106130 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2106130 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2106130 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1021422 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1021422 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 267761 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 267761 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16114 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16114 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2626 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2626 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1289183 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1289183 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1289183 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1289183 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27591103326 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27591103326 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11693886534 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11693886534 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 178834256 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 178834256 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14183619 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14183619 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 39284989860 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 39284989860 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 39284989860 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 39284989860 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1458359000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1458359000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2137811998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2137811998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3596170998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3596170998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125000 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125000 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048719 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048719 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086563 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086563 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.013651 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.013651 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094326 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094326 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094326 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094326 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27012.442777 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27012.442777 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43672.852036 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43672.852036 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11098.067271 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11098.067271 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5401.225819 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5401.225819 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30472.779939 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30472.779939 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30472.779939 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30472.779939 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 752753 # number of writebacks +system.cpu0.dcache.writebacks::total 752753 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 572031 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 572031 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1457971 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1457971 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4881 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4881 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2030002 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2030002 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2030002 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2030002 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1020115 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1020115 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 260329 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 260329 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15955 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15955 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2477 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2477 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1280444 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1280444 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1280444 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1280444 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28982142208 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28982142208 # 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average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14177.227819 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14177.227819 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14177.227819 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14177.227819 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4960 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 911417 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.418391 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7153262 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 911929 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.844100 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 28352545250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.418391 # 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miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118040 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.118040 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14051.329995 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14051.329995 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14051.329995 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14051.329995 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5687 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 197 # 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average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12261.106866 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12261.106866 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45264 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 45264 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 45264 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 45264 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 45264 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 45264 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 912112 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 912112 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 912112 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 912112 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 912112 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 912112 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11511971092 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11511971092 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11511971092 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11511971092 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11511971092 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11511971092 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112459 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.112459 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.112459 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12621.225345 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 3410499 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2981782 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 63006 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1861186 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 813170 # Number of BTB hits +system.cpu1.branchPred.lookups 3445639 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3003437 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 69264 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1910439 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 836162 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 43.690958 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 161954 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 4822 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 43.768055 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 167186 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 4809 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1800297 # DTB read hits -system.cpu1.dtb.read_misses 9623 # DTB read misses -system.cpu1.dtb.read_acv 4 # DTB read access violations -system.cpu1.dtb.read_accesses 290908 # DTB read accesses -system.cpu1.dtb.write_hits 1120103 # DTB write hits -system.cpu1.dtb.write_misses 2035 # DTB write misses -system.cpu1.dtb.write_acv 37 # DTB write access violations -system.cpu1.dtb.write_accesses 109629 # DTB write accesses -system.cpu1.dtb.data_hits 2920400 # DTB hits -system.cpu1.dtb.data_misses 11658 # DTB misses -system.cpu1.dtb.data_acv 41 # DTB access violations -system.cpu1.dtb.data_accesses 400537 # DTB accesses -system.cpu1.itb.fetch_hits 513208 # ITB hits -system.cpu1.itb.fetch_misses 5417 # ITB misses -system.cpu1.itb.fetch_acv 59 # ITB acv -system.cpu1.itb.fetch_accesses 518625 # ITB accesses +system.cpu1.dtb.read_hits 1858276 # DTB read hits +system.cpu1.dtb.read_misses 10905 # DTB read misses +system.cpu1.dtb.read_acv 64 # DTB read access violations +system.cpu1.dtb.read_accesses 300263 # DTB read accesses +system.cpu1.dtb.write_hits 1193771 # DTB write hits +system.cpu1.dtb.write_misses 2902 # DTB write misses +system.cpu1.dtb.write_acv 104 # DTB write access violations +system.cpu1.dtb.write_accesses 125157 # DTB write accesses +system.cpu1.dtb.data_hits 3052047 # DTB hits +system.cpu1.dtb.data_misses 13807 # DTB misses +system.cpu1.dtb.data_acv 168 # DTB access violations +system.cpu1.dtb.data_accesses 425420 # DTB accesses +system.cpu1.itb.fetch_hits 529068 # ITB hits +system.cpu1.itb.fetch_misses 7485 # ITB misses +system.cpu1.itb.fetch_acv 158 # ITB acv +system.cpu1.itb.fetch_accesses 536553 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -956,463 +960,467 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 13834996 # number of cpu cycles simulated +system.cpu1.numCycles 14296923 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5742756 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 13201278 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3410499 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 975124 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 7052078 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 251690 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 24829 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 212437 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 51117 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1482208 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 50416 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 13209086 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.999409 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.408470 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 5827989 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13624759 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3445639 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1003348 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 7312463 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 270756 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 304 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 25051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 299772 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 60327 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1551048 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 55046 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 13661307 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.997325 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.404073 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 10898169 82.51% 82.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 144102 1.09% 83.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 239022 1.81% 85.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 173764 1.32% 86.72% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 293834 2.22% 88.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 119928 0.91% 89.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 132080 1.00% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 175112 1.33% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1033075 7.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 11273523 82.52% 82.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 149434 1.09% 83.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 236962 1.73% 85.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 182278 1.33% 86.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 319422 2.34% 89.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 124907 0.91% 89.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 138046 1.01% 90.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 169812 1.24% 92.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1066923 7.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 13209086 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.246512 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.954195 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 4781490 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6446001 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1665086 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 196515 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 119993 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 102189 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 5928 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 10739248 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 19374 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 119993 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 4918512 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 544557 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5139003 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1724887 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 762132 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10178184 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 4877 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 68265 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 13199 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 289695 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 6692544 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12133960 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 12078154 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 50250 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5671659 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1020885 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 419664 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 38232 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1772644 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1865226 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1191683 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 210655 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 119712 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 8963290 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 478811 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 8726606 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 20522 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1437541 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 698510 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 352654 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 13209086 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.660652 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.378469 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 13661307 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.241006 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.952985 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 4848979 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6756897 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1724085 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 202692 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 128653 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 104901 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 6833 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 11127112 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21450 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 128653 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 4991483 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 690115 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5206241 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1784475 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 860338 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 10551561 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3558 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 63390 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 12017 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 381484 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 6914568 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 12620115 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 12571129 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 43721 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5829921 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1084639 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 430965 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 39644 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1821487 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1910201 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1273290 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 221141 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 146764 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9284732 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 487174 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9053277 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 20996 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1498950 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 731721 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 360528 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 13661307 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.662695 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.384311 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 9547804 72.28% 72.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1625741 12.31% 84.59% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 686242 5.20% 89.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 474957 3.60% 93.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 417301 3.16% 96.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 221804 1.68% 98.22% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 145793 1.10% 99.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 65024 0.49% 99.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 24420 0.18% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 9895925 72.44% 72.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1648518 12.07% 84.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 704790 5.16% 89.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 494622 3.62% 93.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 437905 3.21% 96.49% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 233549 1.71% 98.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 155573 1.14% 99.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 64890 0.47% 99.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 25535 0.19% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 13209086 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 13661307 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 22353 9.61% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 126163 54.23% 63.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 84116 36.16% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 22279 8.85% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 136629 54.29% 63.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 92774 36.86% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5425627 62.17% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 15090 0.17% 62.39% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10661 0.12% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1878240 21.52% 84.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1141614 13.08% 97.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 250097 2.87% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 2817 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5609130 61.96% 61.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 14890 0.16% 62.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 8778 0.10% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1408 0.02% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1940639 21.44% 83.70% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1217689 13.45% 97.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 257926 2.85% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 8726606 # Type of FU issued -system.cpu1.iq.rate 0.630763 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 232632 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.026658 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 30722514 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 10791679 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8409842 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 192938 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 91772 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 89511 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 8852667 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 103053 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 90033 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9053277 # Type of FU issued +system.cpu1.iq.rate 0.633233 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 251682 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.027800 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 31870123 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11194643 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8718718 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 170415 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 80450 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 78899 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9210850 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 91292 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 92092 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 271460 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 498 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 3940 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 125337 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 283440 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 879 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4333 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 136775 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 380 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 50736 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 421 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 73078 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 119993 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 268498 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 245239 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 9936241 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 29107 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1865226 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1191683 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 435120 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4465 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 239666 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 3940 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 28286 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 93108 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 121394 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 8606074 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1816179 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 120532 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 128653 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 295868 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 364148 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10275512 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 29401 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1910201 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1273290 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 443383 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 3815 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 359581 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4333 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 31404 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 95843 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 127247 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 8933578 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1876162 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 119698 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 494140 # number of nop insts executed -system.cpu1.iew.exec_refs 2943760 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1279494 # Number of branches executed -system.cpu1.iew.exec_stores 1127581 # Number of stores executed -system.cpu1.iew.exec_rate 0.622051 # Inst execution rate -system.cpu1.iew.wb_sent 8526125 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8499353 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4051784 # num instructions producing a value -system.cpu1.iew.wb_consumers 5752933 # num instructions consuming a value +system.cpu1.iew.exec_nop 503606 # number of nop insts executed +system.cpu1.iew.exec_refs 3078439 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1318456 # Number of branches executed +system.cpu1.iew.exec_stores 1202277 # Number of stores executed +system.cpu1.iew.exec_rate 0.624860 # Inst execution rate +system.cpu1.iew.wb_sent 8830913 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8797617 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4148200 # num instructions producing a value +system.cpu1.iew.wb_consumers 5856949 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.614337 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.704299 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.615350 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.708253 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1506985 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 126157 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 110245 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 12932417 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.645119 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.622232 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1592161 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 126646 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 116539 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 13369044 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.644454 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.620421 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 9905025 76.59% 76.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1407731 10.89% 87.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 501740 3.88% 91.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 308618 2.39% 93.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 224670 1.74% 95.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 96970 0.75% 96.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 89070 0.69% 96.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 100805 0.78% 97.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 297788 2.30% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10245809 76.64% 76.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1446725 10.82% 87.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 518907 3.88% 91.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 315988 2.36% 93.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 242120 1.81% 95.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 97246 0.73% 96.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 91600 0.69% 96.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 106270 0.79% 97.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 304379 2.28% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 12932417 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8342954 # Number of instructions committed -system.cpu1.commit.committedOps 8342954 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 13369044 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8615735 # Number of instructions committed +system.cpu1.commit.committedOps 8615735 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2660112 # Number of memory references committed -system.cpu1.commit.loads 1593766 # Number of loads committed -system.cpu1.commit.membars 39768 # Number of memory barriers committed -system.cpu1.commit.branches 1189273 # Number of branches committed -system.cpu1.commit.fp_insts 87820 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 7729091 # Number of committed integer instructions. -system.cpu1.commit.function_calls 132492 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 404429 4.85% 4.85% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 4960733 59.46% 64.31% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 14917 0.18% 64.49% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 10656 0.13% 64.61% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.61% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.61% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.61% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1633534 19.58% 84.22% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1066829 12.79% 97.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 250097 3.00% 100.00% # Class of committed instruction +system.cpu1.commit.refs 2763276 # Number of memory references committed +system.cpu1.commit.loads 1626761 # Number of loads committed +system.cpu1.commit.membars 39485 # Number of memory barriers committed +system.cpu1.commit.branches 1225974 # Number of branches committed +system.cpu1.commit.fp_insts 77544 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 7995429 # Number of committed integer instructions. +system.cpu1.commit.function_calls 135018 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 410738 4.77% 4.77% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 5119196 59.42% 64.18% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 14466 0.17% 64.35% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 8774 0.10% 64.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1408 0.02% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1666246 19.34% 83.81% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1136981 13.20% 97.01% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 257926 2.99% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 8342954 # Class of committed instruction -system.cpu1.commit.bw_lim_events 297788 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 8615735 # Class of committed instruction +system.cpu1.commit.bw_lim_events 304379 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 22401053 # The number of ROB reads -system.cpu1.rob.rob_writes 19972727 # The number of ROB writes -system.cpu1.timesIdled 110858 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 625910 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3787862669 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 7942043 # Number of Instructions Simulated -system.cpu1.committedOps 7942043 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.741995 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.741995 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.574055 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.574055 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11080172 # number of integer regfile reads -system.cpu1.int_regfile_writes 6056867 # number of integer regfile writes -system.cpu1.fp_regfile_reads 49492 # number of floating regfile reads -system.cpu1.fp_regfile_writes 48750 # number of floating regfile writes -system.cpu1.misc_regfile_reads 911686 # number of misc regfile reads -system.cpu1.misc_regfile_writes 198554 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 93396 # number of replacements -system.cpu1.dcache.tags.tagsinuse 491.127271 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2362095 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 93708 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 25.206973 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1032235519500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.127271 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.959233 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.959233 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.609375 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 11044469 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 11044469 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1462423 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1462423 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 846221 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 846221 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29364 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 29364 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 27945 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 27945 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2308644 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2308644 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2308644 # number of overall hits -system.cpu1.dcache.overall_hits::total 2308644 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 178507 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 178507 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 183677 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 183677 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4603 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4603 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2762 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2762 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 362184 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 362184 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 362184 # number of overall misses -system.cpu1.dcache.overall_misses::total 362184 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2741731463 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2741731463 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7132330313 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7132330313 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 45481992 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 45481992 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 20461911 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 20461911 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 9874061776 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 9874061776 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 9874061776 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 9874061776 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1640930 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1640930 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1029898 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1029898 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 33967 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 33967 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 30707 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 30707 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2670828 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2670828 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2670828 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2670828 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.108784 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.108784 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.178345 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.178345 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135514 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135514 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.089947 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.089947 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135607 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135607 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135607 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135607 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15359.237806 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15359.237806 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38830.829734 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 38830.829734 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9880.945470 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9880.945470 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7408.367487 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7408.367487 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27262.556535 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 27262.556535 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27262.556535 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 27262.556535 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 351094 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 268 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 15302 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 22.944321 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 17.866667 # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 23176968 # The number of ROB reads +system.cpu1.rob.rob_writes 20704388 # The number of ROB writes +system.cpu1.timesIdled 112605 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 635616 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3794578226 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8207813 # Number of Instructions Simulated +system.cpu1.committedOps 8207813 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.741868 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.741868 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.574096 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.574096 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 11535994 # number of integer regfile reads +system.cpu1.int_regfile_writes 6250844 # number of integer regfile writes +system.cpu1.fp_regfile_reads 43175 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42684 # number of floating regfile writes +system.cpu1.misc_regfile_reads 891820 # number of misc regfile reads +system.cpu1.misc_regfile_writes 203240 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 102439 # number of replacements +system.cpu1.dcache.tags.tagsinuse 489.756832 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2417231 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 102951 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.479432 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1034185261500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 489.756832 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.956556 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.956556 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 11476458 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 11476458 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1494681 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1494681 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 855193 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 855193 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29899 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 29899 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 28520 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 28520 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2349874 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2349874 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2349874 # number of overall hits +system.cpu1.dcache.overall_hits::total 2349874 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 181396 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 181396 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 244262 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 244262 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4731 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4731 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2607 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2607 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 425658 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 425658 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 425658 # number of overall misses +system.cpu1.dcache.overall_misses::total 425658 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2290258065 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2290258065 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9952106154 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 9952106154 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46237999 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 46237999 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22188385 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 22188385 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12242364219 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12242364219 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12242364219 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12242364219 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1676077 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1676077 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1099455 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1099455 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 34630 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 34630 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 31127 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 31127 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2775532 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2775532 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2775532 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2775532 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.108227 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.108227 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.222166 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.222166 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.136616 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.136616 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083754 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083754 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.153361 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.153361 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.153361 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.153361 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12625.736317 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12625.736317 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40743.571059 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 40743.571059 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9773.409216 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9773.409216 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8511.079785 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8511.079785 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 28761.034020 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 28761.034020 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 574336 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 346 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 18255 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 31.461846 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 43.250000 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 60059 # number of writebacks -system.cpu1.dcache.writebacks::total 60059 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 108966 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 108966 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 150714 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 150714 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 427 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 259680 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 259680 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 259680 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 259680 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 69541 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 69541 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 32963 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 32963 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4176 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4176 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2762 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2762 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 102504 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 102504 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 102504 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 102504 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 829052502 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 829052502 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1081287205 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1081287205 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 31817008 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 31817008 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14937089 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14937089 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1910339707 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1910339707 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1910339707 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1910339707 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 24846500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 24846500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 618764500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 618764500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 643611000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 643611000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042379 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042379 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032006 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032006 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.122943 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.122943 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.089947 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.089947 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038379 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.038379 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038379 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.038379 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11921.779986 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11921.779986 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32803.058126 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32803.058126 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7619.015326 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7619.015326 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5408.069877 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5408.069877 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18636.733269 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18636.733269 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18636.733269 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18636.733269 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 70134 # number of writebacks +system.cpu1.dcache.writebacks::total 70134 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 110614 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 110614 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 203686 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 203686 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 700 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 700 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 314300 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 314300 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 314300 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 314300 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 70782 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 70782 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 40576 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 40576 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4031 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4031 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2607 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2607 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 111358 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 111358 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 111358 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 111358 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 815361518 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 815361518 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1580599049 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1580599049 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 32399501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 32399501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 18277115 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 18277115 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2395960567 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2395960567 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2395960567 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2395960567 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29330000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29330000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 630993000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 630993000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 660323000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 660323000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042231 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042231 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036906 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036906 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.116402 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.116402 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083754 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083754 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.040121 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.040121 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11519.334266 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11519.334266 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38954.038077 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 38954.038077 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8037.583974 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8037.583974 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7010.784427 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7010.784427 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1420,95 +1428,97 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 205003 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.613699 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1269898 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 205514 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.179131 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1878408675250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.613699 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919167 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.919167 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1687783 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1687783 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1269898 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1269898 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1269898 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1269898 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1269898 # number of overall hits -system.cpu1.icache.overall_hits::total 1269898 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 212310 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 212310 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 212310 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 212310 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 212310 # number of overall misses -system.cpu1.icache.overall_misses::total 212310 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2888653039 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2888653039 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2888653039 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2888653039 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2888653039 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2888653039 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1482208 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1482208 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1482208 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1482208 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1482208 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1482208 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.143239 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.143239 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.143239 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.143239 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.143239 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.143239 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13605.826570 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13605.826570 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13605.826570 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13605.826570 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13605.826570 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13605.826570 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 412 # number of cycles access was blocked +system.cpu1.icache.tags.replacements 211356 # number of replacements +system.cpu1.icache.tags.tagsinuse 472.195820 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1331062 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 211865 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.282595 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1880244277250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 472.195820 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.922257 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.922257 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 392 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 1762968 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1762968 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1331062 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1331062 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1331062 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1331062 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1331062 # number of overall hits +system.cpu1.icache.overall_hits::total 1331062 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 219986 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 219986 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 219986 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 219986 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 219986 # number of overall misses +system.cpu1.icache.overall_misses::total 219986 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2974295730 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2974295730 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2974295730 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2974295730 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2974295730 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2974295730 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1551048 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1551048 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1551048 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1551048 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1551048 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1551048 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.141831 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.141831 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.141831 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.141831 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.141831 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.141831 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13520.386434 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13520.386434 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13520.386434 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13520.386434 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 613 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 40 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.846154 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.325000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6735 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 6735 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 6735 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 6735 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 6735 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 6735 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 205575 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 205575 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 205575 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 205575 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 205575 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 205575 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2403236890 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2403236890 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2403236890 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2403236890 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2403236890 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2403236890 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.138695 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.138695 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.138695 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11690.316867 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11690.316867 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11690.316867 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8066 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 8066 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 8066 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 8066 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 8066 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 8066 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 211920 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 211920 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 211920 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 211920 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 211920 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 211920 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2567742004 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2567742004 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2567742004 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2567742004 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2567742004 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2567742004 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.136630 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.136630 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.136630 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12116.562873 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1522,58 +1532,58 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7377 # Transaction distribution -system.iobus.trans_dist::ReadResp 7377 # Transaction distribution -system.iobus.trans_dist::WriteReq 54536 # Transaction distribution -system.iobus.trans_dist::WriteResp 12984 # Transaction distribution +system.iobus.trans_dist::ReadReq 7375 # Transaction distribution +system.iobus.trans_dist::ReadResp 7375 # Transaction distribution +system.iobus.trans_dist::WriteReq 54477 # Transaction distribution +system.iobus.trans_dist::WriteResp 12925 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11756 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11660 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 172 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18142 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40360 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123826 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47024 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 123704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 46640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 149 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9071 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 73266 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661672 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661672 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2734938 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 11111000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 72837 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2734485 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 11011000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 148000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 13500000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) @@ -1581,52 +1591,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406222784 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242105442 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27376000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27319000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42026793 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42037503 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41701 # number of replacements -system.iocache.tags.tagsinuse 0.465228 # Cycle average of tags in use +system.iocache.tags.replacements 41698 # number of replacements +system.iocache.tags.tagsinuse 0.483577 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41717 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710337218000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.465228 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.029077 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.029077 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1711318407000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.483577 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.030224 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.030224 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375597 # Number of tag accesses -system.iocache.tags.data_accesses 375597 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 181 # number of ReadReq misses -system.iocache.ReadReq_misses::total 181 # number of ReadReq misses +system.iocache.tags.tag_accesses 375570 # Number of tag accesses +system.iocache.tags.data_accesses 375570 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses +system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 181 # number of demand (read+write) misses -system.iocache.demand_misses::total 181 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 181 # number of overall misses -system.iocache.overall_misses::total 181 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22038383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22038383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13652440608 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13652440608 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22038383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22038383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22038383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22038383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 181 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 181 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 178 # number of demand (read+write) misses +system.iocache.demand_misses::total 178 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 178 # number of overall misses +system.iocache.overall_misses::total 178 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22300881 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22300881 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8783600058 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8783600058 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22300881 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22300881 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22300881 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22300881 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 181 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 181 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 181 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 181 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 178 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 178 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 178 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 178 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1635,40 +1645,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121759.022099 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 121759.022099 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328562.779361 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328562.779361 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 121759.022099 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 121759.022099 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 121759.022099 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 121759.022099 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206720 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125285.848315 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125285.848315 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211388.141558 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 211388.141558 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125285.848315 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125285.848315 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 73351 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23552 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10036 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.777174 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.308788 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 181 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 181 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 181 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 181 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 181 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12625383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12625383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11491649194 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11491649194 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12625383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12625383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12625383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12625383 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 178 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 178 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 178 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 178 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12879885 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12879885 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6622894060 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6622894060 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12879885 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12879885 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12879885 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12879885 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1677,189 +1687,189 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 69753.497238 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276560.675635 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276560.675635 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 69753.497238 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 69753.497238 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72358.904494 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159388.093473 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159388.093473 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 345072 # number of replacements -system.l2c.tags.tagsinuse 65237.196274 # Cycle average of tags in use -system.l2c.tags.total_refs 2611817 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 410198 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.367210 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7093665750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53609.898857 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5305.766317 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6049.152476 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 209.737010 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 62.641613 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.818022 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080960 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.092303 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003200 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000956 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995441 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65126 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2602 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5798 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5210 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51300 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.993744 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27343076 # Number of tag accesses -system.l2c.tags.data_accesses 27343076 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 901250 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 743094 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 204045 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 62863 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1911252 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 822515 # number of Writeback hits -system.l2c.Writeback_hits::total 822515 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 236 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 410 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 50 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 78 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 157590 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 21227 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 178817 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 901250 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 900684 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 204045 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27118000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1392738000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1999167500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 591543000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2590710500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3364787500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 618661000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3983448500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.268883 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012634 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.131244 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.938440 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.809154 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.898264 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.868159 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.927885 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.898533 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425487 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.303494 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.410883 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.301306 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.116680 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.164864 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.301306 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.116680 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.164864 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60591.911792 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79611.552567 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61211.455363 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17849.112561 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17729.183126 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17815.541331 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17817.616046 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17740.634715 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17777.187755 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76264.731559 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99981.523666 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 78361.955043 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 65174.151113 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65174.151113 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1997,101 +2007,101 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296649 # Transaction distribution -system.membus.trans_dist::ReadResp 296568 # Transaction distribution -system.membus.trans_dist::WriteReq 12984 # Transaction distribution -system.membus.trans_dist::WriteResp 12984 # Transaction distribution -system.membus.trans_dist::Writeback 123204 # Transaction distribution +system.membus.trans_dist::ReadReq 296650 # Transaction distribution +system.membus.trans_dist::ReadResp 296572 # Transaction distribution +system.membus.trans_dist::WriteReq 12925 # Transaction distribution +system.membus.trans_dist::WriteResp 12925 # Transaction distribution +system.membus.trans_dist::Writeback 124744 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9668 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5310 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4924 # Transaction distribution -system.membus.trans_dist::ReadExReq 121989 # Transaction distribution -system.membus.trans_dist::ReadExResp 121610 # Transaction distribution -system.membus.trans_dist::BadAddressError 81 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40360 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 923282 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 162 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 963804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1088624 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73266 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31500992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31574258 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 9402 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5001 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4742 # Transaction distribution +system.membus.trans_dist::ReadExReq 123808 # Transaction distribution +system.membus.trans_dist::ReadExResp 123481 # Transaction distribution +system.membus.trans_dist::BadAddressError 78 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40244 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 968166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1092983 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 72837 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31719616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31792453 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36891826 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 10884 # Total snoops (count) -system.membus.snoop_fanout::samples 591178 # Request fanout histogram +system.membus.pkt_size::total 37110021 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 10437 # Total snoops (count) +system.membus.snoop_fanout::samples 594010 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 591178 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 594010 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 591178 # Request fanout histogram -system.membus.reqLayer0.occupancy 38973998 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 594010 # Request fanout histogram +system.membus.reqLayer0.occupancy 36342500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1927807998 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1279237311 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 100000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3829664091 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43225207 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2197321028 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 42525497 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2228449 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2228352 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12984 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12984 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 822515 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41553 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 9795 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5388 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 15183 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 301926 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 301926 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1830333 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3396960 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 411121 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 269188 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5907602 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58566720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 131328844 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13154944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 9749222 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 212799730 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 73699 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3402430 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012266 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.110070 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2231372 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2231278 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12925 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12925 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 822887 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41587 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 9543 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5084 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 14627 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302295 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302295 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1824058 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369862 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 423804 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 296769 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5914493 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58364544 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130195442 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13560576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10962579 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213083141 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 72565 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3405571 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012264 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.110061 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3360696 98.77% 98.77% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41734 1.23% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3363806 98.77% 98.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41765 1.23% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3402430 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4987291538 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3405571 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2521355915 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4124247177 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5936070669 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 925874109 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1371805405 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 2024294017 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 318303496 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 467054772 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 173244936 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2125,161 +2135,171 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6564 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 186274 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65832 40.54% 40.54% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.62% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1922 1.18% 41.81% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 173 0.11% 41.91% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 94323 58.09% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 162381 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64799 49.22% 49.22% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1922 1.46% 50.78% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 173 0.13% 50.91% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 64626 49.09% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 131651 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1859979639500 97.83% 97.83% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 61305500 0.00% 97.84% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 538798500 0.03% 97.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 78674500 0.00% 97.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 40515747500 2.13% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1901174165500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984309 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6519 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 185119 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65685 40.48% 40.48% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 132 0.08% 40.56% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1924 1.19% 41.75% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 154 0.09% 41.84% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 94359 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 162254 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64617 49.22% 49.22% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 132 0.10% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1924 1.47% 50.78% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 154 0.12% 50.90% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 64464 49.10% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 131291 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1861341200000 97.74% 97.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 60253000 0.00% 97.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 540538500 0.03% 97.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 69963500 0.00% 97.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 42290129000 2.22% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1904302084000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983741 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.685156 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810754 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.22% 28.02% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.45% # number of syscalls executed -system.cpu0.kern.syscall::17 9 3.88% 32.33% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.31% 36.64% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.59% 39.22% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.66% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.29% 40.95% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.02% 43.97% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.86% 44.83% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.81% 61.64% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.29% 62.93% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.31% 67.24% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.31% 71.55% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 71.98% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.59% 74.57% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.64% 86.21% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.29% 87.50% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.02% 90.52% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 90.95% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.29% 92.24% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.88% 96.12% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.86% 96.98% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.86% 97.84% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.28% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.86% 99.14% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 232 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.683178 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.809170 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 6 2.79% 2.79% # number of syscalls executed +system.cpu0.kern.syscall::3 18 8.37% 11.16% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.40% 12.56% # number of syscalls executed +system.cpu0.kern.syscall::6 29 13.49% 26.05% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.47% 26.51% # number of syscalls executed +system.cpu0.kern.syscall::15 1 0.47% 26.98% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.19% 31.16% # number of syscalls executed +system.cpu0.kern.syscall::19 6 2.79% 33.95% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.86% 35.81% # number of syscalls executed +system.cpu0.kern.syscall::23 2 0.93% 36.74% # number of syscalls executed +system.cpu0.kern.syscall::24 4 1.86% 38.60% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.26% 41.86% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.93% 42.79% # number of syscalls executed +system.cpu0.kern.syscall::45 35 16.28% 59.07% # number of syscalls executed +system.cpu0.kern.syscall::47 4 1.86% 60.93% # number of syscalls executed +system.cpu0.kern.syscall::48 7 3.26% 64.19% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.19% 68.37% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.47% 68.84% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.33% 71.16% # number of syscalls executed +system.cpu0.kern.syscall::71 32 14.88% 86.05% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.40% 87.44% # number of syscalls executed +system.cpu0.kern.syscall::74 9 4.19% 91.63% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.47% 92.09% # number of syscalls executed +system.cpu0.kern.syscall::90 1 0.47% 92.56% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.26% 95.81% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.93% 96.74% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.93% 97.67% # number of syscalls executed +system.cpu0.kern.syscall::132 2 0.93% 98.60% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.47% 99.07% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 215 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 266 0.16% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3573 2.09% 2.25% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.28% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed -system.cpu0.kern.callpal::swpipl 155550 90.98% 93.26% # number of callpals executed -system.cpu0.kern.callpal::rdps 6382 3.73% 96.99% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 97.00% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed -system.cpu0.kern.callpal::rti 4604 2.69% 99.69% # number of callpals executed -system.cpu0.kern.callpal::callsys 391 0.23% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 170980 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7167 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1355 # number of protection mode switches +system.cpu0.kern.callpal::wripir 255 0.15% 0.15% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.15% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.15% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.15% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3502 2.05% 2.20% # number of callpals executed +system.cpu0.kern.callpal::tbi 43 0.03% 2.23% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.23% # number of callpals executed +system.cpu0.kern.callpal::swpipl 155594 91.14% 93.38% # number of callpals executed +system.cpu0.kern.callpal::rdps 6351 3.72% 97.10% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::rti 4450 2.61% 99.71% # number of callpals executed +system.cpu0.kern.callpal::callsys 347 0.20% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 148 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 170714 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6908 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1181 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1354 -system.cpu0.kern.mode_good::user 1355 +system.cpu0.kern.mode_good::kernel 1181 +system.cpu0.kern.mode_good::user 1181 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.188921 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.170961 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.317883 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1899194834000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1979323500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.292001 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1901823094000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1927479500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3574 # number of times the context was actually changed +system.cpu0.kern.swap_context 3503 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2428 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 53091 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 16423 36.25% 36.25% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1920 4.24% 40.49% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 266 0.59% 41.08% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 26695 58.92% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 45304 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16079 47.18% 47.18% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1920 5.63% 52.82% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 266 0.78% 53.60% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 15813 46.40% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 34078 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870417466500 98.40% 98.40% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 530332500 0.03% 98.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 120265000 0.01% 98.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29780754000 1.57% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1900848818000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.979054 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2448 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 54000 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 16487 36.42% 36.42% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1922 4.25% 40.66% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 255 0.56% 41.23% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 26607 58.77% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 45271 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16178 47.20% 47.20% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1922 5.61% 52.80% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 255 0.74% 53.55% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 15923 46.45% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 34278 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1872287559000 98.31% 98.31% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533777500 0.03% 98.34% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 116465000 0.01% 98.35% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 31498958000 1.65% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1904436759500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981258 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.592358 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.752207 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed -system.cpu1.kern.syscall::17 6 6.38% 27.66% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.19% 30.85% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.19% 34.04% # number of syscalls executed -system.cpu1.kern.syscall::33 4 4.26% 38.30% # number of syscalls executed -system.cpu1.kern.syscall::45 15 15.96% 54.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.19% 57.45% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.06% 58.51% # number of syscalls executed -system.cpu1.kern.syscall::71 27 28.72% 87.23% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.57% 96.81% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 94 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.598452 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.757173 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 2 1.80% 1.80% # number of syscalls executed +system.cpu1.kern.syscall::3 12 10.81% 12.61% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.90% 13.51% # number of syscalls executed +system.cpu1.kern.syscall::6 13 11.71% 25.23% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.41% 30.63% # number of syscalls executed +system.cpu1.kern.syscall::19 4 3.60% 34.23% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.80% 36.04% # number of syscalls executed +system.cpu1.kern.syscall::23 2 1.80% 37.84% # number of syscalls executed +system.cpu1.kern.syscall::24 2 1.80% 39.64% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.60% 43.24% # number of syscalls executed +system.cpu1.kern.syscall::45 19 17.12% 60.36% # number of syscalls executed +system.cpu1.kern.syscall::47 2 1.80% 62.16% # number of syscalls executed +system.cpu1.kern.syscall::48 3 2.70% 64.86% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.90% 65.77% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.80% 67.57% # number of syscalls executed +system.cpu1.kern.syscall::71 22 19.82% 87.39% # number of syscalls executed +system.cpu1.kern.syscall::74 7 6.31% 93.69% # number of syscalls executed +system.cpu1.kern.syscall::90 2 1.80% 95.50% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.80% 97.30% # number of syscalls executed +system.cpu1.kern.syscall::132 2 1.80% 99.10% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.90% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 111 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 173 0.37% 0.37% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::swpctx 989 2.11% 2.49% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 2.49% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed -system.cpu1.kern.callpal::swpipl 40205 85.85% 88.36% # number of callpals executed -system.cpu1.kern.callpal::rdps 2366 5.05% 93.41% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.42% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed -system.cpu1.kern.callpal::rti 2912 6.22% 99.64% # number of callpals executed -system.cpu1.kern.callpal::callsys 124 0.26% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 154 0.33% 0.33% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.33% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1023 2.18% 2.52% # number of callpals executed +system.cpu1.kern.callpal::tbi 10 0.02% 2.54% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.55% # number of callpals executed +system.cpu1.kern.callpal::swpipl 40053 85.39% 87.95% # number of callpals executed +system.cpu1.kern.callpal::rdps 2403 5.12% 93.07% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.07% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.08% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.00% 93.08% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.09% # number of callpals executed +system.cpu1.kern.callpal::rti 3040 6.48% 99.57% # number of callpals executed +system.cpu1.kern.callpal::callsys 168 0.36% 99.93% # number of callpals executed +system.cpu1.kern.callpal::imb 32 0.07% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 46833 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1197 # number of protection mode switches -system.cpu1.kern.mode_switch::user 384 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2372 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 574 -system.cpu1.kern.mode_good::user 384 -system.cpu1.kern.mode_good::idle 190 -system.cpu1.kern.mode_switch_good::kernel 0.479532 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 46904 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1413 # number of protection mode switches +system.cpu1.kern.mode_switch::user 554 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2352 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 733 +system.cpu1.kern.mode_good::user 554 +system.cpu1.kern.mode_good::idle 179 +system.cpu1.kern.mode_switch_good::kernel 0.518754 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.080101 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.290412 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 3852720500 0.20% 0.20% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 690217500 0.04% 0.24% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1895996394000 99.76% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 990 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.076105 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.339430 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4023798000 0.21% 0.21% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 775821000 0.04% 0.25% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1899637132500 99.75% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1024 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index aba3b9944..12a10aeec 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,113 +1,113 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.859045 # Number of seconds simulated -sim_ticks 1859045389000 # Number of ticks simulated -final_tick 1859045389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.861006 # Number of seconds simulated +sim_ticks 1861005569500 # Number of ticks simulated +final_tick 1861005569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 155751 # Simulator instruction rate (inst/s) -host_op_rate 155751 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5470499619 # Simulator tick rate (ticks/s) -host_mem_usage 374716 # Number of bytes of host memory used -host_seconds 339.83 # Real time elapsed on the host -sim_insts 52929026 # Number of instructions simulated -sim_ops 52929026 # Number of ops (including micro ops) simulated +host_inst_rate 153218 # Simulator instruction rate (inst/s) +host_op_rate 153218 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5386630373 # Simulator tick rate (ticks/s) +host_mem_usage 376136 # Number of bytes of host memory used +host_seconds 345.49 # Real time elapsed on the host +sim_insts 52934565 # Number of instructions simulated +sim_ops 52934565 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 968128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24876416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 968000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24876864 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25845504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 968128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 968128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7516800 # Number of bytes written to this memory -system.physmem.bytes_written::total 7516800 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15127 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388694 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25845824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 968000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 968000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7517248 # Number of bytes written to this memory +system.physmem.bytes_written::total 7517248 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15125 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388701 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403836 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117450 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117450 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13381285 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403841 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117457 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117457 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 520149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13367431 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13902567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520766 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520766 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4043366 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4043366 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4043366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520766 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13381285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13888096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 520149 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520149 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4039347 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4039347 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4039347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 520149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13367431 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17945933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403836 # Number of read requests accepted -system.physmem.writeReqs 159002 # Number of write requests accepted -system.physmem.readBursts 403836 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159002 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25838848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue -system.physmem.bytesWritten 10042304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25845504 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10176128 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2068 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 208 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25744 # Per bank write bursts -system.physmem.perBankRdBursts::1 25557 # Per bank write bursts -system.physmem.perBankRdBursts::2 25510 # Per bank write bursts -system.physmem.perBankRdBursts::3 25348 # Per bank write bursts -system.physmem.perBankRdBursts::4 25387 # Per bank write bursts -system.physmem.perBankRdBursts::5 24799 # Per bank write bursts +system.physmem.bw_total::total 17927443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403841 # Number of read requests accepted +system.physmem.writeReqs 159009 # Number of write requests accepted +system.physmem.readBursts 403841 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159009 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25839488 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue +system.physmem.bytesWritten 8519424 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25845824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10176576 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 25870 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 187 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25748 # Per bank write bursts +system.physmem.perBankRdBursts::1 25559 # Per bank write bursts +system.physmem.perBankRdBursts::2 25508 # Per bank write bursts +system.physmem.perBankRdBursts::3 25346 # Per bank write bursts +system.physmem.perBankRdBursts::4 25393 # Per bank write bursts +system.physmem.perBankRdBursts::5 24806 # Per bank write bursts system.physmem.perBankRdBursts::6 25027 # Per bank write bursts -system.physmem.perBankRdBursts::7 25129 # Per bank write bursts -system.physmem.perBankRdBursts::8 24928 # Per bank write bursts -system.physmem.perBankRdBursts::9 25032 # Per bank write bursts +system.physmem.perBankRdBursts::7 25127 # Per bank write bursts +system.physmem.perBankRdBursts::8 24925 # Per bank write bursts +system.physmem.perBankRdBursts::9 25034 # Per bank write bursts system.physmem.perBankRdBursts::10 25436 # Per bank write bursts -system.physmem.perBankRdBursts::11 24784 # Per bank write bursts +system.physmem.perBankRdBursts::11 24774 # Per bank write bursts system.physmem.perBankRdBursts::12 24551 # Per bank write bursts -system.physmem.perBankRdBursts::13 25235 # Per bank write bursts -system.physmem.perBankRdBursts::14 25659 # Per bank write bursts -system.physmem.perBankRdBursts::15 25606 # Per bank write bursts -system.physmem.perBankWrBursts::0 10485 # Per bank write bursts -system.physmem.perBankWrBursts::1 10108 # Per bank write bursts -system.physmem.perBankWrBursts::2 10574 # Per bank write bursts -system.physmem.perBankWrBursts::3 9632 # Per bank write bursts -system.physmem.perBankWrBursts::4 9668 # Per bank write bursts -system.physmem.perBankWrBursts::5 9137 # Per bank write bursts -system.physmem.perBankWrBursts::6 9064 # Per bank write bursts -system.physmem.perBankWrBursts::7 8900 # Per bank write bursts -system.physmem.perBankWrBursts::8 9821 # Per bank write bursts -system.physmem.perBankWrBursts::9 8750 # Per bank write bursts -system.physmem.perBankWrBursts::10 9677 # Per bank write bursts -system.physmem.perBankWrBursts::11 9460 # Per bank write bursts -system.physmem.perBankWrBursts::12 10019 # Per bank write bursts -system.physmem.perBankWrBursts::13 10709 # Per bank write bursts -system.physmem.perBankWrBursts::14 10502 # Per bank write bursts -system.physmem.perBankWrBursts::15 10405 # Per bank write bursts +system.physmem.perBankRdBursts::13 25233 # Per bank write bursts +system.physmem.perBankRdBursts::14 25663 # Per bank write bursts +system.physmem.perBankRdBursts::15 25612 # Per bank write bursts +system.physmem.perBankWrBursts::0 9148 # Per bank write bursts +system.physmem.perBankWrBursts::1 8514 # Per bank write bursts +system.physmem.perBankWrBursts::2 8998 # Per bank write bursts +system.physmem.perBankWrBursts::3 8298 # Per bank write bursts +system.physmem.perBankWrBursts::4 8214 # Per bank write bursts +system.physmem.perBankWrBursts::5 7705 # Per bank write bursts +system.physmem.perBankWrBursts::6 7696 # Per bank write bursts +system.physmem.perBankWrBursts::7 7707 # Per bank write bursts +system.physmem.perBankWrBursts::8 8055 # Per bank write bursts +system.physmem.perBankWrBursts::9 7602 # Per bank write bursts +system.physmem.perBankWrBursts::10 8149 # Per bank write bursts +system.physmem.perBankWrBursts::11 7799 # Per bank write bursts +system.physmem.perBankWrBursts::12 8377 # Per bank write bursts +system.physmem.perBankWrBursts::13 9062 # Per bank write bursts +system.physmem.perBankWrBursts::14 8903 # Per bank write bursts +system.physmem.perBankWrBursts::15 8889 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 1859040142000 # Total gap between requests +system.physmem.numWrRetry 85 # Number of times write queue was full causing retry +system.physmem.totGap 1861000236500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403836 # Read request sizes (log2) +system.physmem.readPktSize::6 403841 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 159002 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 37560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 159009 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314763 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -148,193 +148,199 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63696 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 563.318764 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 349.809758 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.596932 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13378 21.00% 21.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10306 16.18% 37.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4860 7.63% 44.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2855 4.48% 49.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2272 3.57% 52.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1671 2.62% 55.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1518 2.38% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1616 2.54% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25220 39.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63696 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5671 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.190619 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2803.945627 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5668 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 323 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62685 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 548.114030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 339.010384 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.134053 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13424 21.42% 21.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10425 16.63% 38.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5386 8.59% 46.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2710 4.32% 50.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2462 3.93% 54.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1644 2.62% 57.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1512 2.41% 59.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1300 2.07% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23822 38.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62685 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4847 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 83.295234 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3032.862596 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4844 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5671 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5671 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.669018 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.928355 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 34.069194 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4623 81.52% 81.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 171 3.02% 84.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 302 5.33% 89.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 63 1.11% 90.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 97 1.71% 92.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 43 0.76% 93.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 19 0.34% 93.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 6 0.11% 93.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 22 0.39% 94.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.07% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 17 0.30% 94.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.07% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 14 0.25% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 6 0.11% 95.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 18 0.32% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 43 0.76% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 8 0.14% 96.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 17 0.30% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 89 1.57% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 36 0.63% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 17 0.30% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 22 0.39% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 13 0.23% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 4 0.07% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 5 0.09% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5671 # Writes before turning the bus around for reads -system.physmem.totQLat 3621320000 # Total ticks spent queuing -system.physmem.totMemAccLat 11191295000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018660000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8969.61 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4847 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4847 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.463586 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.516932 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 62.014286 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4601 94.92% 94.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 56 1.16% 96.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 4 0.08% 96.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 1 0.02% 96.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 13 0.27% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 3 0.06% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 3 0.06% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 6 0.12% 96.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 21 0.43% 97.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 18 0.37% 97.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 8 0.17% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 12 0.25% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 2 0.04% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.08% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.04% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 5 0.10% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 17 0.35% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 13 0.27% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 3 0.06% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 11 0.23% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 4 0.08% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 2 0.04% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 2 0.04% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 4 0.08% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 4 0.08% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 4 0.08% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.04% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.04% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 8 0.17% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.04% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::624-639 2 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 2 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4847 # Writes before turning the bus around for reads +system.physmem.totQLat 3741903500 # Total ticks spent queuing +system.physmem.totMemAccLat 11312066000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018710000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9268.06 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27719.61 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.40 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.90 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28018.06 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.58 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 5.47 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage +system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.54 # Average write queue length when enqueuing -system.physmem.readRowHits 364717 # Number of row buffer hits during reads -system.physmem.writeRowHits 132230 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.26 # Row buffer hit rate for writes -system.physmem.avgGap 3302975.53 # Average gap between requests -system.physmem.pageHitRate 88.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 239009400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 130411875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1579507800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 502640640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 121423785600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 55671864660 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1066592208750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1246139428725 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.311493 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1774205493250 # Time in different power states -system.physmem_0.memoryStateTime::REF 62077600000 # Time in different power states +system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.77 # Average write queue length when enqueuing +system.physmem.readRowHits 364326 # Number of row buffer hits during reads +system.physmem.writeRowHits 109846 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.24 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.50 # Row buffer hit rate for writes +system.physmem.avgGap 3306387.56 # Average gap between requests +system.physmem.pageHitRate 88.32 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 235516680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 128506125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1579609200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 429494400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 56182721175 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1067316698250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1247423979990 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.297807 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1775410357162 # Time in different power states +system.physmem_0.memoryStateTime::REF 62142860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22762216750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23446441588 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 242532360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 132334125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1569601800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 514142640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 121423785600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 55569327930 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1066682161500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1246133885955 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.308507 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1774360012750 # Time in different power states -system.physmem_1.memoryStateTime::REF 62077600000 # Time in different power states +system.physmem_1.actEnergy 238381920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 130069500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1569531600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 433097280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 56034129015 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1067447050500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1247403693975 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.286901 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1775626000168 # Time in different power states +system.physmem_1.memoryStateTime::REF 62142860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22607711000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23231077332 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17755011 # Number of BP lookups -system.cpu.branchPred.condPredicted 15447257 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 380557 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11928628 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5915753 # Number of BTB hits +system.cpu.branchPred.lookups 17721924 # Number of BP lookups +system.cpu.branchPred.condPredicted 15403228 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 380344 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11703979 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5913014 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 49.592904 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 917507 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21428 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 50.521400 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 923784 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21447 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10297861 # DTB read hits -system.cpu.dtb.read_misses 41459 # DTB read misses -system.cpu.dtb.read_acv 502 # DTB read access violations -system.cpu.dtb.read_accesses 968382 # DTB read accesses -system.cpu.dtb.write_hits 6648165 # DTB write hits -system.cpu.dtb.write_misses 9537 # DTB write misses -system.cpu.dtb.write_acv 407 # DTB write access violations -system.cpu.dtb.write_accesses 342637 # DTB write accesses -system.cpu.dtb.data_hits 16946026 # DTB hits -system.cpu.dtb.data_misses 50996 # DTB misses +system.cpu.dtb.read_hits 10269214 # DTB read hits +system.cpu.dtb.read_misses 41261 # DTB read misses +system.cpu.dtb.read_acv 507 # DTB read access violations +system.cpu.dtb.read_accesses 967301 # DTB read accesses +system.cpu.dtb.write_hits 6648637 # DTB write hits +system.cpu.dtb.write_misses 9303 # DTB write misses +system.cpu.dtb.write_acv 402 # DTB write access violations +system.cpu.dtb.write_accesses 342644 # DTB write accesses +system.cpu.dtb.data_hits 16917851 # DTB hits +system.cpu.dtb.data_misses 50564 # DTB misses system.cpu.dtb.data_acv 909 # DTB access violations -system.cpu.dtb.data_accesses 1311019 # DTB accesses -system.cpu.itb.fetch_hits 1769037 # ITB hits -system.cpu.itb.fetch_misses 35976 # ITB misses -system.cpu.itb.fetch_acv 675 # ITB acv -system.cpu.itb.fetch_accesses 1805013 # ITB accesses +system.cpu.dtb.data_accesses 1309945 # DTB accesses +system.cpu.itb.fetch_hits 1769158 # ITB hits +system.cpu.itb.fetch_misses 36068 # ITB misses +system.cpu.itb.fetch_acv 660 # ITB acv +system.cpu.itb.fetch_accesses 1805226 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -347,254 +353,253 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 118253854 # number of cpu cycles simulated +system.cpu.numCycles 122572361 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29528041 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78024704 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17755011 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6833260 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80443267 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1255548 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1917 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 27791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1737879 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 457742 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 201 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9020958 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 272859 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 112824612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.691557 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.011053 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29541441 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78093998 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17721924 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6836798 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 84630340 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1254210 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1349 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 26888 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1745325 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 441267 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9051182 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 273719 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 117014009 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.667390 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.979034 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 98261708 87.09% 87.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 933543 0.83% 87.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1973411 1.75% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 908515 0.81% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2794922 2.48% 92.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 638903 0.57% 93.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 728605 0.65% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1007079 0.89% 95.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5577926 4.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 102427448 87.53% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 934169 0.80% 88.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1984138 1.70% 90.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 910061 0.78% 90.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2793690 2.39% 93.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 647956 0.55% 93.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 739168 0.63% 94.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1007210 0.86% 95.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5570169 4.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 112824612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.150143 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.659807 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24062318 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 76790103 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9490656 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1896068 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 585466 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 586954 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42767 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68209057 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 130935 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 585466 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24987088 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 47248716 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20734654 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10372019 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8896667 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65782894 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 200446 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2040001 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 143212 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4746299 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43863584 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79748694 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79567373 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168869 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38138490 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5725086 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1691130 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 241601 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13583154 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10423192 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6953251 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1496634 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1073096 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58558441 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2136854 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57535876 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 59225 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7428094 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3503981 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1475675 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 112824612 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.509959 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.252016 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 117014009 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.144583 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.637126 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24038562 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 80987042 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9497307 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1906242 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 584855 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 586733 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42672 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68295720 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 134238 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 584855 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24961940 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 51456366 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20841952 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10391329 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8777565 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65857652 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 204161 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2078785 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 153522 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4578544 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43917673 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79850033 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79669145 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168436 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38142428 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5775237 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1690640 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 240974 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13460569 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10430513 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6961741 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1496363 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1107330 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58622970 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2136022 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57539781 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 62715 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7497440 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3554737 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1474907 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 117014009 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.491734 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.229968 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 89346173 79.19% 79.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10029271 8.89% 88.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4305402 3.82% 91.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 2956038 2.62% 94.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3073019 2.72% 97.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1592834 1.41% 98.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1003723 0.89% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 396113 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 122039 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 93391036 79.81% 79.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10179391 8.70% 88.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4310458 3.68% 92.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3008330 2.57% 94.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3082993 2.63% 97.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1515378 1.30% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1001152 0.86% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 403458 0.34% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 121813 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 112824612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 117014009 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 206156 18.23% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547934 48.46% 66.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 376604 33.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 210088 18.84% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 537781 48.22% 67.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 367353 32.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39037949 67.85% 67.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61847 0.11% 67.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38375 0.07% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10709010 18.61% 86.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6728743 11.69% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949030 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39070075 67.90% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61902 0.11% 68.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38396 0.07% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10678994 18.56% 86.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6730550 11.70% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948942 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57535876 # Type of FU issued -system.cpu.iq.rate 0.486545 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1130694 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019652 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 228371695 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67806986 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55854530 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 714587 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336328 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 329574 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58275622 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 383662 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 641458 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57539781 # Type of FU issued +system.cpu.iq.rate 0.469435 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1115222 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019382 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 232558247 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67941522 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55883323 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 713260 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 334790 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 329169 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58264568 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 383149 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 636979 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1338736 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3932 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20392 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 579549 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1345105 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3404 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20302 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 587155 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18260 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 537508 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18243 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 442852 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 585466 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 44292826 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 620223 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64391845 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 145304 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10423192 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6953251 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1888969 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 42563 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 374293 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20392 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 192990 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 410068 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 603058 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56949005 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10367007 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 586870 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 584855 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 48003305 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1105801 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64465821 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 144286 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10430513 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6961741 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1886655 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 45598 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 856378 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20302 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 189944 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 410798 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 600742 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56947023 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10338131 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 592757 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3696550 # number of nop insts executed -system.cpu.iew.exec_refs 17039818 # number of memory reference insts executed -system.cpu.iew.exec_branches 8972525 # Number of branches executed -system.cpu.iew.exec_stores 6672811 # Number of stores executed -system.cpu.iew.exec_rate 0.481583 # Inst execution rate -system.cpu.iew.wb_sent 56323297 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56184104 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28889312 # num instructions producing a value -system.cpu.iew.wb_consumers 40263081 # num instructions consuming a value +system.cpu.iew.exec_nop 3706829 # number of nop insts executed +system.cpu.iew.exec_refs 17011176 # number of memory reference insts executed +system.cpu.iew.exec_branches 8976912 # Number of branches executed +system.cpu.iew.exec_stores 6673045 # Number of stores executed +system.cpu.iew.exec_rate 0.464599 # Inst execution rate +system.cpu.iew.wb_sent 56353404 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56212492 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28792537 # num instructions producing a value +system.cpu.iew.wb_consumers 40027235 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.475114 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717514 # average fanout of values written-back +system.cpu.iew.wb_rate 0.458607 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.719324 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8158001 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661179 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 549251 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 111396128 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.503767 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.456242 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8228560 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661115 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 549076 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 115576332 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.485596 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.428292 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91779533 82.39% 82.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7802293 7.00% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4122327 3.70% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2151634 1.93% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1854051 1.66% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 612708 0.55% 97.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 470628 0.42% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 511278 0.46% 98.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2091676 1.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 95814381 82.90% 82.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7848857 6.79% 89.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4272054 3.70% 93.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2211253 1.91% 95.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1764307 1.53% 96.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 615369 0.53% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 473670 0.41% 97.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 490996 0.42% 98.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2085445 1.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 111396128 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56117715 # Number of instructions committed -system.cpu.commit.committedOps 56117715 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 115576332 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56123349 # Number of instructions committed +system.cpu.commit.committedOps 56123349 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15458158 # Number of memory references committed -system.cpu.commit.loads 9084456 # Number of loads committed -system.cpu.commit.membars 226347 # Number of memory barriers committed -system.cpu.commit.branches 8434758 # Number of branches committed +system.cpu.commit.refs 15459994 # Number of memory references committed +system.cpu.commit.loads 9085408 # Number of loads committed +system.cpu.commit.membars 226308 # Number of memory barriers committed +system.cpu.commit.branches 8435685 # Number of branches committed system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. -system.cpu.commit.int_insts 51969244 # Number of committed integer instructions. -system.cpu.commit.function_calls 739915 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3195962 5.70% 5.70% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36179881 64.47% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60661 0.11% 70.27% # Class of committed instruction +system.cpu.commit.int_insts 51974864 # Number of committed integer instructions. +system.cpu.commit.function_calls 740049 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3196057 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36183700 64.47% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60673 0.11% 70.27% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.34% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction @@ -622,192 +627,192 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9310803 16.59% 86.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6379655 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949030 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9311716 16.59% 86.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6380538 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 948942 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56117715 # Class of committed instruction -system.cpu.commit.bw_lim_events 2091676 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction +system.cpu.commit.bw_lim_events 2085445 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 173330307 # The number of ROB reads -system.cpu.rob.rob_writes 129976168 # The number of ROB writes -system.cpu.timesIdled 574999 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5429242 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599836925 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52929026 # Number of Instructions Simulated -system.cpu.committedOps 52929026 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.234197 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.234197 # CPI: Total CPI of All Threads -system.cpu.ipc 0.447588 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.447588 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74582639 # number of integer regfile reads -system.cpu.int_regfile_writes 40531859 # number of integer regfile writes -system.cpu.fp_regfile_reads 167323 # number of floating regfile reads -system.cpu.fp_regfile_writes 167888 # number of floating regfile writes -system.cpu.misc_regfile_reads 2030592 # number of misc regfile reads -system.cpu.misc_regfile_writes 939419 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1404198 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994647 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11876238 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1404710 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.454584 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994647 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy +system.cpu.rob.rob_reads 177593269 # The number of ROB reads +system.cpu.rob.rob_writes 130137832 # The number of ROB writes +system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5558352 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599438779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52934565 # Number of Instructions Simulated +system.cpu.committedOps 52934565 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.315545 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.315545 # CPI: Total CPI of All Threads +system.cpu.ipc 0.431864 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.431864 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74599299 # number of integer regfile reads +system.cpu.int_regfile_writes 40560409 # number of integer regfile writes +system.cpu.fp_regfile_reads 167171 # number of floating regfile reads +system.cpu.fp_regfile_writes 167579 # number of floating regfile writes +system.cpu.misc_regfile_reads 2029670 # number of misc regfile reads +system.cpu.misc_regfile_writes 939349 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1403663 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994456 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11858482 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1404175 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.445160 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 26416000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994456 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 413 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63918355 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63918355 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7286393 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7286393 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4187319 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4187319 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186500 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186500 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215720 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215720 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11473712 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11473712 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11473712 # number of overall hits -system.cpu.dcache.overall_hits::total 11473712 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1773211 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1773211 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1955934 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1955934 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23306 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23306 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3729145 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3729145 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3729145 # number of overall misses -system.cpu.dcache.overall_misses::total 3729145 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 39410540501 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39410540501 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 77932908678 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 77932908678 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 363692999 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 363692999 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 466008 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 466008 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117343449179 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117343449179 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117343449179 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117343449179 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9059604 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9059604 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6143253 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6143253 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209806 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209806 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215748 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215748 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15202857 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15202857 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15202857 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15202857 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.195727 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.195727 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318387 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.318387 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111084 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111084 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.245292 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.245292 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.245292 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.245292 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.522231 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.522231 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39844.344788 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39844.344788 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15605.123101 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15605.123101 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16643.142857 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16643.142857 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31466.582602 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31466.582602 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31466.582602 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31466.582602 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3975824 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1887 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 179816 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 63936372 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63936372 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7267066 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7267066 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4189300 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4189300 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186111 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186111 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215710 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215710 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11456366 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11456366 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11456366 # number of overall hits +system.cpu.dcache.overall_hits::total 11456366 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1796718 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1796718 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1954848 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1954848 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23269 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23269 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 27 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 27 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3751566 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3751566 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3751566 # number of overall misses +system.cpu.dcache.overall_misses::total 3751566 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 41841354315 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 41841354315 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890671511 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 80890671511 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376182249 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 376182249 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 455005 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 455005 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 122732025826 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 122732025826 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 122732025826 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 122732025826 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9063784 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9063784 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6144148 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6144148 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209380 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209380 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215737 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215737 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15207932 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15207932 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15207932 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15207932 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198230 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.198230 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318164 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318164 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111133 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111133 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000125 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000125 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.246685 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.246685 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.246685 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.246685 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23287.658005 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23287.658005 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.519794 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.519794 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16166.670205 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16166.670205 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16852.037037 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16852.037037 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32714.878487 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32714.878487 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4477815 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2036 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 123579 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.110513 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 82.043478 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.234433 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 88.521739 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 842396 # number of writebacks -system.cpu.dcache.writebacks::total 842396 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 677447 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 677447 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664842 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1664842 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5278 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5278 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2342289 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2342289 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2342289 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2342289 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1095764 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1095764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291092 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 291092 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18028 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 18028 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1386856 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1386856 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1386856 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1386856 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27504145773 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27504145773 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11747551273 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11747551273 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205106501 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205106501 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 409992 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 409992 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39251697046 # 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number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120951 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120951 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047384 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047384 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085927 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085927 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091223 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091223 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78045.233528 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1030,80 +1035,80 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75938 # number of writebacks -system.cpu.l2cache.writebacks::total 75938 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75945 # number of writebacks +system.cpu.l2cache.writebacks::total 75945 # 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number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014617 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248275 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135159 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.647727 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.647727 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382173 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382173 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014617 # 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average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71432.829575 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71432.829575 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63767.269302 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58620.224217 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58812.802249 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63767.269302 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58620.224217 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58812.802249 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15126 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273931 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 289057 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115274 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115274 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15126 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389205 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1887182500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887182500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3223869000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3223869000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248428 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135326 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.607595 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.607595 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.185185 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60628.026766 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61177.285964 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20844.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20844.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 17801 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17801 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76874.300675 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76874.300675 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1111,43 +1116,43 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # 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Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 86 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2070119 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3685432 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5755551 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66237760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143868972 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 210106732 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 42071 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3324189 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012552 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.111331 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::Writeback 842087 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41601 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 106 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301613 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301613 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 94 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2066871 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3684049 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5750920 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66134528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143814956 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 209949484 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 42097 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3321757 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.012576 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.111435 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3282463 98.74% 98.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41726 1.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3279983 98.74% 98.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41774 1.26% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3324189 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2496690997 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3321757 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2495140999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1556745400 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1554402947 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2189304171 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2190379384 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1220,23 +1225,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406216778 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242053963 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42011283 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42024003 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.260535 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.259192 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1709356303000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.260535 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078783 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078783 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1711311066000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.259192 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078699 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078699 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1250,14 +1255,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13645647112 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13645647112 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21719383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21719383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8765491577 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8765491577 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21719383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21719383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21719383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21719383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) @@ -1274,19 +1279,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328399.285522 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328399.285522 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206436 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125545.566474 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125545.566474 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210952.338684 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 210952.338684 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125545.566474 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125545.566474 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125545.566474 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125545.566474 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 73146 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23523 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10015 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.775921 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.303645 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1300,14 +1305,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11484876678 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11484876678 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12567383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12567383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6604781583 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6604781583 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12567383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12567383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12567383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12567383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1316,62 +1321,62 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276397.686706 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276397.686706 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72643.832370 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158952.194431 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158952.194431 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72643.832370 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72643.832370 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296054 # Transaction distribution -system.membus.trans_dist::ReadResp 295968 # Transaction distribution +system.membus.trans_dist::ReadReq 296160 # Transaction distribution +system.membus.trans_dist::ReadResp 296066 # Transaction distribution system.membus.trans_dist::WriteReq 9597 # Transaction distribution system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117450 # Transaction distribution +system.membus.trans_dist::Writeback 117457 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 203 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution -system.membus.trans_dist::UpgradeResp 211 # Transaction distribution -system.membus.trans_dist::ReadExReq 115230 # Transaction distribution -system.membus.trans_dist::ReadExResp 115230 # Transaction distribution -system.membus.trans_dist::BadAddressError 86 # Transaction distribution +system.membus.trans_dist::UpgradeReq 185 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.membus.trans_dist::UpgradeResp 190 # Transaction distribution +system.membus.trans_dist::ReadExReq 115137 # Transaction distribution +system.membus.trans_dist::ReadExResp 115137 # Transaction distribution +system.membus.trans_dist::BadAddressError 94 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884273 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 172 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917499 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884248 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 188 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917490 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042303 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042294 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30748716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30705344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30749484 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36065772 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36066540 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 563568 # Request fanout histogram +system.membus.snoop_fanout::samples 563651 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 563568 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 563651 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 563568 # Request fanout histogram -system.membus.reqLayer0.occupancy 31570500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 563651 # Request fanout histogram +system.membus.reqLayer0.occupancy 29181000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1858044250 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1226048062 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 107000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 118000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3754720043 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43142717 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2139454565 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 42497997 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1405,28 +1410,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211002 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6445 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210982 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74654 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105562 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182233 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105549 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182213 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73287 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817332157500 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 61952500 0.00% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 528077500 0.03% 97.79% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41122369500 2.21% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1859044557000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73287 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148584 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817355802000 97.65% 97.65% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 62075500 0.00% 97.66% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 532990500 0.03% 97.69% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 43053863500 2.31% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1861004731500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981689 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694322 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815429 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815441 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1465,7 +1470,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175118 91.23% 93.44% # number of callpals executed +system.cpu.kern.callpal::swpipl 175098 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1474,20 +1479,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191962 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches -system.cpu.kern.mode_switch::user 1743 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1913 -system.cpu.kern.mode_good::user 1743 +system.cpu.kern.callpal::total 191942 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1741 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326953 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326667 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394840 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29081819500 1.56% 1.56% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2655993500 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827306736000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394509 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29153631500 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2692582500 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1829158509500 98.29% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index b0cdac391..43a4f79aa 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.842592 # Number of seconds simulated -sim_ticks 1842591955000 # Number of ticks simulated -final_tick 1842591955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841539 # Number of seconds simulated +sim_ticks 1841538755500 # Number of ticks simulated +final_tick 1841538755500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212167 # Simulator instruction rate (inst/s) -host_op_rate 212167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5858461865 # Simulator tick rate (ticks/s) -host_mem_usage 373744 # Number of bytes of host memory used -host_seconds 314.52 # Real time elapsed on the host -sim_insts 66730424 # Number of instructions simulated -sim_ops 66730424 # Number of ops (including micro ops) simulated +host_inst_rate 221552 # Simulator instruction rate (inst/s) +host_op_rate 221552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5785089232 # Simulator tick rate (ticks/s) +host_mem_usage 374344 # Number of bytes of host memory used +host_seconds 318.33 # Real time elapsed on the host +sim_insts 70525499 # Number of instructions simulated +sim_ops 70525499 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 480192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20072256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 146880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2246976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 294016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2555648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 467648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20091072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2148032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 308096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2634304 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25796928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 480192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 146880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 294016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 921088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7481920 # Number of bytes written to this memory -system.physmem.bytes_written::total 7481920 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7503 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 313629 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2295 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 35109 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4594 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39932 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25797120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 467648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 308096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 922752 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7481856 # Number of bytes written to this memory +system.physmem.bytes_written::total 7481856 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7307 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 313923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 33563 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4814 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41161 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403077 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116905 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116905 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 260607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10893489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1219465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 159567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1386985 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403080 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116904 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116904 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 253944 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10909937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79829 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1166433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 167304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1430491 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14000348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 260607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 159567 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 499887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4060541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4060541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4060541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10893489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1219465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 159567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1386985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 14008459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 253944 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79829 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 167304 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 501077 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4062828 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4062828 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4062828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 253944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10909937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1166433 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 167304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1430491 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18060889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 81945 # Number of read requests accepted -system.physmem.writeReqs 62218 # Number of write requests accepted -system.physmem.readBursts 81945 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 62218 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5243136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1344 # Total number of bytes read from write queue -system.physmem.bytesWritten 3931008 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5244480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 3981952 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 21 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 773 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 65 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5216 # Per bank write bursts -system.physmem.perBankRdBursts::1 4952 # Per bank write bursts -system.physmem.perBankRdBursts::2 4966 # Per bank write bursts -system.physmem.perBankRdBursts::3 5032 # Per bank write bursts -system.physmem.perBankRdBursts::4 5011 # Per bank write bursts -system.physmem.perBankRdBursts::5 5077 # Per bank write bursts -system.physmem.perBankRdBursts::6 5139 # Per bank write bursts -system.physmem.perBankRdBursts::7 5153 # Per bank write bursts -system.physmem.perBankRdBursts::8 5336 # Per bank write bursts -system.physmem.perBankRdBursts::9 5012 # Per bank write bursts -system.physmem.perBankRdBursts::10 5284 # Per bank write bursts -system.physmem.perBankRdBursts::11 5137 # Per bank write bursts -system.physmem.perBankRdBursts::12 4814 # Per bank write bursts -system.physmem.perBankRdBursts::13 5083 # Per bank write bursts -system.physmem.perBankRdBursts::14 5582 # Per bank write bursts -system.physmem.perBankRdBursts::15 5130 # Per bank write bursts -system.physmem.perBankWrBursts::0 3820 # Per bank write bursts -system.physmem.perBankWrBursts::1 3672 # Per bank write bursts -system.physmem.perBankWrBursts::2 3762 # Per bank write bursts -system.physmem.perBankWrBursts::3 4075 # Per bank write bursts -system.physmem.perBankWrBursts::4 3759 # Per bank write bursts -system.physmem.perBankWrBursts::5 3520 # Per bank write bursts -system.physmem.perBankWrBursts::6 4123 # Per bank write bursts -system.physmem.perBankWrBursts::7 3706 # Per bank write bursts -system.physmem.perBankWrBursts::8 4379 # Per bank write bursts -system.physmem.perBankWrBursts::9 3471 # Per bank write bursts -system.physmem.perBankWrBursts::10 3889 # Per bank write bursts -system.physmem.perBankWrBursts::11 3981 # Per bank write bursts -system.physmem.perBankWrBursts::12 3541 # Per bank write bursts -system.physmem.perBankWrBursts::13 3879 # Per bank write bursts -system.physmem.perBankWrBursts::14 4169 # Per bank write bursts -system.physmem.perBankWrBursts::15 3676 # Per bank write bursts +system.physmem.bw_total::total 18071287 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 81850 # Number of read requests accepted +system.physmem.writeReqs 64472 # Number of write requests accepted +system.physmem.readBursts 81850 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 64472 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5236928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1472 # Total number of bytes read from write queue +system.physmem.bytesWritten 3416192 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5238400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4126208 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 23 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 11076 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 49 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 4878 # Per bank write bursts +system.physmem.perBankRdBursts::1 4919 # Per bank write bursts +system.physmem.perBankRdBursts::2 4947 # Per bank write bursts +system.physmem.perBankRdBursts::3 4947 # Per bank write bursts +system.physmem.perBankRdBursts::4 5010 # Per bank write bursts +system.physmem.perBankRdBursts::5 5136 # Per bank write bursts +system.physmem.perBankRdBursts::6 5318 # Per bank write bursts +system.physmem.perBankRdBursts::7 5111 # Per bank write bursts +system.physmem.perBankRdBursts::8 5349 # Per bank write bursts +system.physmem.perBankRdBursts::9 4830 # Per bank write bursts +system.physmem.perBankRdBursts::10 5530 # Per bank write bursts +system.physmem.perBankRdBursts::11 5119 # Per bank write bursts +system.physmem.perBankRdBursts::12 4880 # Per bank write bursts +system.physmem.perBankRdBursts::13 5044 # Per bank write bursts +system.physmem.perBankRdBursts::14 5637 # Per bank write bursts +system.physmem.perBankRdBursts::15 5172 # Per bank write bursts +system.physmem.perBankWrBursts::0 3097 # Per bank write bursts +system.physmem.perBankWrBursts::1 3264 # Per bank write bursts +system.physmem.perBankWrBursts::2 3389 # Per bank write bursts +system.physmem.perBankWrBursts::3 3378 # Per bank write bursts +system.physmem.perBankWrBursts::4 3165 # Per bank write bursts +system.physmem.perBankWrBursts::5 3060 # Per bank write bursts +system.physmem.perBankWrBursts::6 3647 # Per bank write bursts +system.physmem.perBankWrBursts::7 3165 # Per bank write bursts +system.physmem.perBankWrBursts::8 3847 # Per bank write bursts +system.physmem.perBankWrBursts::9 3079 # Per bank write bursts +system.physmem.perBankWrBursts::10 3680 # Per bank write bursts +system.physmem.perBankWrBursts::11 3339 # Per bank write bursts +system.physmem.perBankWrBursts::12 2997 # Per bank write bursts +system.physmem.perBankWrBursts::13 3248 # Per bank write bursts +system.physmem.perBankWrBursts::14 3739 # Per bank write bursts +system.physmem.perBankWrBursts::15 3284 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1841579678500 # Total gap between requests +system.physmem.numWrRetry 18 # Number of times write queue was full causing retry +system.physmem.totGap 1840526879500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 81945 # Read request sizes (log2) +system.physmem.readPktSize::6 81850 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 62218 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 65839 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64472 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 63937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7813 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5603 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -153,216 +153,196 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 37 # 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Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7102 31.88% 31.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4721 21.19% 53.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1798 8.07% 61.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1010 4.53% 65.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 955 4.29% 69.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 478 2.15% 72.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 370 1.66% 73.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 364 1.63% 75.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5481 24.60% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 22279 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2129 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 38.475810 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1006.180082 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2127 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 38 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 22135 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 390.924780 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 222.627349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 384.024543 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7145 32.28% 32.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4994 22.56% 54.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1972 8.91% 63.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1000 4.52% 68.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 834 3.77% 72.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 471 2.13% 74.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 534 2.41% 76.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 337 1.52% 78.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4848 21.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 22135 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 1909 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 42.863279 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1017.016663 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 1907 99.90% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2129 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2129 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 28.850164 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.675931 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 36.499081 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 34 1.60% 1.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.33% 1.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.05% 1.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 1 0.05% 2.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1615 75.86% 77.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 35 1.64% 79.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 10 0.47% 79.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 84 3.95% 83.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 64 3.01% 86.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 45 2.11% 89.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 9 0.42% 89.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 11 0.52% 90.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 35 1.64% 91.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.23% 91.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 21 0.99% 92.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.09% 92.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 3 0.14% 93.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.09% 93.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.23% 93.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.05% 93.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.19% 93.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.05% 93.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.14% 93.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.19% 94.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.05% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.05% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.28% 94.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.09% 94.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.05% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 15 0.70% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 3 0.14% 95.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.09% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.05% 95.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.19% 95.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 43 2.02% 97.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.05% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 11 0.52% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.14% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.14% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.09% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 6 0.28% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 4 0.19% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 5 0.23% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 3 0.14% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.14% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 3 0.14% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.09% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2129 # Writes before turning the bus around for reads -system.physmem.totQLat 814366500 # Total ticks spent queuing -system.physmem.totMemAccLat 2350441500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 409620000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9940.51 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 1909 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 1909 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.961236 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.965205 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 62.780578 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 45 2.36% 2.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 1768 92.61% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 14 0.73% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 2 0.10% 95.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 2 0.10% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 1 0.05% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 1 0.05% 96.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 2 0.10% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 11 0.58% 96.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 12 0.63% 97.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 5 0.26% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 8 0.42% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 1 0.05% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.05% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.10% 98.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 2 0.10% 98.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 6 0.31% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 5 0.26% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 2 0.10% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.10% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.05% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.05% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.10% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.10% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.16% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 4 0.21% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 2 0.10% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 1909 # Writes before turning the bus around for reads +system.physmem.totQLat 884680000 # Total ticks spent queuing +system.physmem.totMemAccLat 2418936250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 409135000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10811.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28690.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.85 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.85 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29561.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.24 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.28 # Average write queue length when enqueuing -system.physmem.readRowHits 70260 # Number of row buffer hits during reads -system.physmem.writeRowHits 50807 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.76 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.69 # Row buffer hit rate for writes -system.physmem.avgGap 12774287.98 # Average gap between requests -system.physmem.pageHitRate 84.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 83779920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 45618375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 316258800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 197231760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89126157120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 35724246975 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 802806617250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 928299910200 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.726630 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1309959191250 # Time in different power states -system.physmem_0.memoryStateTime::REF 45565260000 # Time in different power states +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.99 # Average write queue length when enqueuing +system.physmem.readRowHits 70087 # Number of row buffer hits during reads +system.physmem.writeRowHits 42983 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.50 # Row buffer hit rate for writes +system.physmem.avgGap 12578606.63 # Average gap between requests +system.physmem.pageHitRate 83.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 81814320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 44558250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 314074800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 169549200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 35647575705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 798651060750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 923964608865 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.989912 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1309028017250 # Time in different power states +system.physmem_0.memoryStateTime::REF 45529640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9222216250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9101184500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 84649320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 46030875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 322748400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 200782800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89126157120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35431940430 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 799831550250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 925043859195 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.972279 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1310405285500 # Time in different power states -system.physmem_1.memoryStateTime::REF 45565260000 # Time in different power states +system.physmem_1.actEnergy 85526280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 46513500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 324175800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 176340240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35475772860 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 801505403250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 926669707770 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.770193 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1309231204000 # Time in different power states +system.physmem_1.memoryStateTime::REF 45529640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8771812500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8903896000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4841130 # DTB read hits -system.cpu0.dtb.read_misses 6162 # DTB read misses -system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 429577 # DTB read accesses -system.cpu0.dtb.write_hits 3448228 # DTB write hits -system.cpu0.dtb.write_misses 688 # DTB write misses -system.cpu0.dtb.write_acv 85 # DTB write access violations -system.cpu0.dtb.write_accesses 165228 # DTB write accesses -system.cpu0.dtb.data_hits 8289358 # DTB hits -system.cpu0.dtb.data_misses 6850 # DTB misses -system.cpu0.dtb.data_acv 211 # DTB access violations -system.cpu0.dtb.data_accesses 594805 # DTB accesses -system.cpu0.itb.fetch_hits 2744473 # ITB hits -system.cpu0.itb.fetch_misses 3071 # ITB misses -system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2747544 # ITB accesses +system.cpu0.dtb.read_hits 4781172 # DTB read hits +system.cpu0.dtb.read_misses 6058 # DTB read misses +system.cpu0.dtb.read_acv 118 # DTB read access violations +system.cpu0.dtb.read_accesses 428328 # DTB read accesses +system.cpu0.dtb.write_hits 3391530 # DTB write hits +system.cpu0.dtb.write_misses 675 # DTB write misses +system.cpu0.dtb.write_acv 82 # DTB write access violations +system.cpu0.dtb.write_accesses 163639 # DTB write accesses +system.cpu0.dtb.data_hits 8172702 # DTB hits +system.cpu0.dtb.data_misses 6733 # DTB misses +system.cpu0.dtb.data_acv 200 # DTB access violations +system.cpu0.dtb.data_accesses 591967 # DTB accesses +system.cpu0.itb.fetch_hits 2720050 # ITB hits +system.cpu0.itb.fetch_misses 3046 # ITB misses +system.cpu0.itb.fetch_acv 99 # ITB acv +system.cpu0.itb.fetch_accesses 2723096 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -375,87 +355,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 929111283 # number of cpu cycles simulated +system.cpu0.numCycles 930048733 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 30392058 # Number of instructions committed -system.cpu0.committedOps 30392058 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 28296981 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 165313 # Number of float alu accesses -system.cpu0.num_func_calls 800920 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3653475 # number of instructions that are conditional controls -system.cpu0.num_int_insts 28296981 # number of integer instructions -system.cpu0.num_fp_insts 165313 # number of float instructions -system.cpu0.num_int_register_reads 38988704 # number of times the integer registers were read -system.cpu0.num_int_register_writes 20831324 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 85482 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 86956 # number of times the floating registers were written -system.cpu0.num_mem_refs 8319320 # number of memory refs -system.cpu0.num_load_insts 4862427 # Number of load instructions -system.cpu0.num_store_insts 3456893 # Number of store instructions -system.cpu0.num_idle_cycles 905971177.002448 # Number of idle cycles -system.cpu0.num_busy_cycles 23140105.997552 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024906 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975094 # Percentage of idle cycles -system.cpu0.Branches 4712544 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1584509 5.21% 5.21% # Class of executed instruction -system.cpu0.op_class::IntAlu 19793641 65.11% 70.32% # Class of executed instruction -system.cpu0.op_class::IntMult 31883 0.10% 70.43% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 70.43% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12951 0.04% 70.47% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 70.47% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 70.47% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 70.47% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1606 0.01% 70.48% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::MemRead 4993701 16.43% 86.90% # Class of executed instruction -system.cpu0.op_class::MemWrite 3459999 11.38% 98.29% # Class of executed instruction -system.cpu0.op_class::IprAccess 520829 1.71% 100.00% # Class of executed instruction +system.cpu0.committedInsts 31504183 # Number of instructions committed +system.cpu0.committedOps 31504183 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 29439494 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 162688 # Number of float alu accesses +system.cpu0.num_func_calls 792913 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4107229 # number of instructions that are conditional controls +system.cpu0.num_int_insts 29439494 # number of integer instructions +system.cpu0.num_fp_insts 162688 # number of float instructions +system.cpu0.num_int_register_reads 41004383 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21582488 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 84172 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 85625 # number of times the floating registers were written +system.cpu0.num_mem_refs 8202083 # number of memory refs +system.cpu0.num_load_insts 4802046 # Number of load instructions +system.cpu0.num_store_insts 3400037 # Number of store instructions +system.cpu0.num_idle_cycles 907048310.649553 # Number of idle cycles +system.cpu0.num_busy_cycles 23000422.350447 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024730 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975270 # Percentage of idle cycles +system.cpu0.Branches 5154717 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1560474 4.95% 4.95% # Class of executed instruction +system.cpu0.op_class::IntAlu 21056937 66.82% 71.78% # Class of executed instruction +system.cpu0.op_class::IntMult 31354 0.10% 71.88% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.88% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12843 0.04% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1601 0.01% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::MemRead 4932088 15.65% 87.57% # Class of executed instruction +system.cpu0.op_class::MemWrite 3403118 10.80% 98.37% # Class of executed instruction +system.cpu0.op_class::IprAccess 512701 1.63% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 30399119 # Class of executed instruction +system.cpu0.op_class::total 31511116 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6424 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211373 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74797 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211361 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74795 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105693 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182572 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73430 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105682 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182558 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73428 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73430 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148942 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819763275500 98.76% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38885000 0.00% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 357575500 0.02% 98.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22431449500 1.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842591185500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73428 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148937 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818811073000 98.77% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38572000 0.00% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 355311500 0.02% 98.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22333065000 1.21% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841538021500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694748 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815799 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694801 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815834 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -491,278 +471,276 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175313 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175301 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192228 # number of callpals executed +system.cpu0.kern.callpal::total 192212 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1910 -system.cpu0.kern.mode_good::user 1740 -system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322526 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1906 +system.cpu0.kern.mode_good::user 1737 +system.cpu0.kern.mode_good::idle 169 +system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391474 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29641344500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2562591500 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810387245000 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4177 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1393017 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997818 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13281490 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393529 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.530831 # Average number of references to valid blocks. +system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.390894 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29730845000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2571229000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809235945500 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4175 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1393219 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13266024 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393731 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.518353 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 260.752731 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 75.043138 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.201949 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.509283 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.146569 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.344144 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 178.252416 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 164.663502 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 169.081899 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.348149 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.321608 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.330238 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63366474 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63366474 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4014509 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1053432 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2506621 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7574562 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3156846 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 808200 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1357961 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5323007 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114880 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 18791 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 50813 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184484 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123743 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 20765 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 54820 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199328 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7171355 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1861632 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3864582 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12897569 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7171355 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1861632 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3864582 # number of overall hits -system.cpu0.dcache.overall_hits::total 12897569 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 713110 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 94552 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 558128 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1365790 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 166356 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 43595 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 617033 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 826984 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9412 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2104 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7556 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19072 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 7 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 879466 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 138147 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1175161 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2192774 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 879466 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 138147 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1175161 # number of overall misses -system.cpu0.dcache.overall_misses::total 2192774 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2193347250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9664547340 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11857894590 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1652894510 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19391335975 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 21044230485 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27729500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 125483249 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 153212749 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 91000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 91000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 3846241760 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 29055883315 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 32902125075 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3846241760 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 29055883315 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 32902125075 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4727619 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1147984 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3064749 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8940352 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3323202 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 851795 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1974994 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6149991 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124292 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 20895 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58369 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203556 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123745 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 20765 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 54827 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199337 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8050821 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 1999779 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5039743 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15090343 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8050821 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 1999779 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5039743 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15090343 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150839 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082364 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.182112 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.152767 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050059 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051180 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.312423 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.134469 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075725 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100694 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.129452 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.093694 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000016 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000128 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000045 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109239 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069081 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233179 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.145310 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109239 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069081 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.233179 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.145310 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23197.259180 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17316.005182 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8682.077472 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37914.772566 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31426.740507 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25446.962075 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13179.420152 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16607.100185 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8033.386588 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10111.111111 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27841.659681 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24725.023478 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15004.795330 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27841.659681 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24725.023478 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15004.795330 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 825255 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1343 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 61465 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.426422 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 149.222222 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 63377040 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63377040 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 3961674 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1077685 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2542197 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7581556 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3105087 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 828848 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1366589 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5300524 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113741 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19662 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51148 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184551 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122328 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21764 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55225 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199317 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7066761 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1906533 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3908786 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12882080 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7066761 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1906533 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3908786 # number of overall hits +system.cpu0.dcache.overall_hits::total 12882080 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 706841 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 96965 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 557653 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1361459 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 162721 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 43998 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 642629 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11086168542 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3795432990 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7290735552 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11086168542 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 222473500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 331326000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 553799500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 293979000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 446199000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740178000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 516452500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 777525000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1293977500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082548 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087131 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041044 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050408 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047670 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022729 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101905 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.102034 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040445 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000199 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000055 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.068847 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071612 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033581 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.068847 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071612 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033581 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21811.633063 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15810.589349 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17395.873429 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38194.190418 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31534.830267 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33631.000823 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11726.355894 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11998.625916 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11924.863388 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 15318 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15318 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26925.029901 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19926.957037 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21873.285524 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26925.029901 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19926.957037 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21873.285524 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # 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average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6716.906439 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2709 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 43227698 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 43227698 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 31004099 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7794052 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2481801 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 41279952 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31004099 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7794052 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2481801 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 41279952 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31004099 # 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number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 42262186 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016090 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016263 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122471 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.023241 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016090 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016263 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122471 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.023241 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016090 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016263 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122471 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.023241 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14274.651139 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13970.038652 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6798.836701 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14274.651139 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13970.038652 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6798.836701 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14274.651139 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13970.038652 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6798.836701 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4002 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 225 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.705882 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.786667 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16232 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16232 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16232 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16232 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16232 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16232 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 124188 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 326610 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 450798 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 124188 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 326610 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 450798 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 124188 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 326610 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 450798 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1522394000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3982795175 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5505189175 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1522394000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3982795175 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5505189175 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1522394000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3982795175 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5505189175 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011087 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011087 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011087 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12212.097602 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12212.097602 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12212.097602 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16722 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16722 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16722 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16722 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16722 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16722 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 128848 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 329647 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 458495 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 128848 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 329647 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 458495 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 128848 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 329647 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 458495 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1645092750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4148478396 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5793571146 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1645092750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4148478396 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5793571146 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1645092750 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4148478396 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5793571146 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016263 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116558 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010849 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016263 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116558 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010849 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016263 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116558 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010849 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12767.701090 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12584.608372 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12636.061780 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12767.701090 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12584.608372 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12636.061780 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12767.701090 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12584.608372 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12636.061780 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1166781 # DTB read hits -system.cpu1.dtb.read_misses 1314 # DTB read misses -system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 141633 # DTB read accesses -system.cpu1.dtb.write_hits 872888 # DTB write hits -system.cpu1.dtb.write_misses 168 # DTB write misses +system.cpu1.dtb.read_hits 1194215 # DTB read hits +system.cpu1.dtb.read_misses 1316 # DTB read misses +system.cpu1.dtb.read_acv 35 # DTB read access violations +system.cpu1.dtb.read_accesses 141030 # DTB read accesses +system.cpu1.dtb.write_hits 894755 # DTB write hits +system.cpu1.dtb.write_misses 169 # DTB write misses system.cpu1.dtb.write_acv 22 # DTB write access violations -system.cpu1.dtb.write_accesses 57088 # DTB write accesses -system.cpu1.dtb.data_hits 2039669 # DTB hits -system.cpu1.dtb.data_misses 1482 # DTB misses -system.cpu1.dtb.data_acv 56 # DTB access violations -system.cpu1.dtb.data_accesses 198721 # DTB accesses -system.cpu1.itb.fetch_hits 848090 # ITB hits -system.cpu1.itb.fetch_misses 662 # ITB misses -system.cpu1.itb.fetch_acv 32 # ITB acv -system.cpu1.itb.fetch_accesses 848752 # ITB accesses +system.cpu1.dtb.write_accesses 57515 # DTB write accesses +system.cpu1.dtb.data_hits 2088970 # DTB hits +system.cpu1.dtb.data_misses 1485 # DTB misses +system.cpu1.dtb.data_acv 57 # DTB access violations +system.cpu1.dtb.data_accesses 198545 # DTB accesses +system.cpu1.itb.fetch_hits 856400 # ITB hits +system.cpu1.itb.fetch_misses 653 # ITB misses +system.cpu1.itb.fetch_acv 34 # ITB acv +system.cpu1.itb.fetch_accesses 857053 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -942,64 +920,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953408444 # number of cpu cycles simulated +system.cpu1.numCycles 953255662 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7454598 # Number of instructions committed -system.cpu1.committedOps 7454598 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6929268 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 43953 # Number of float alu accesses -system.cpu1.num_func_calls 203515 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 903765 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6929268 # number of integer instructions -system.cpu1.num_fp_insts 43953 # number of float instructions -system.cpu1.num_int_register_reads 9641119 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5054145 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 23746 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24129 # number of times the floating registers were written -system.cpu1.num_mem_refs 2046592 # number of memory refs -system.cpu1.num_load_insts 1171450 # Number of load instructions -system.cpu1.num_store_insts 875142 # Number of store instructions -system.cpu1.num_idle_cycles 924951081.946169 # Number of idle cycles -system.cpu1.num_busy_cycles 28457362.053831 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029848 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970152 # Percentage of idle cycles -system.cpu1.Branches 1171881 # Number of branches fetched -system.cpu1.op_class::No_OpClass 398972 5.35% 5.35% # Class of executed instruction -system.cpu1.op_class::IntAlu 4837309 64.88% 70.23% # Class of executed instruction -system.cpu1.op_class::IntMult 8193 0.11% 70.34% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.34% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5097 0.07% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::MemRead 1199545 16.09% 86.50% # Class of executed instruction -system.cpu1.op_class::MemWrite 876356 11.75% 98.26% # Class of executed instruction -system.cpu1.op_class::IprAccess 129854 1.74% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7921357 # Number of instructions committed +system.cpu1.committedOps 7921357 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7380748 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45896 # Number of float alu accesses +system.cpu1.num_func_calls 207012 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1022630 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7380748 # number of integer instructions +system.cpu1.num_fp_insts 45896 # number of float instructions +system.cpu1.num_int_register_reads 10351742 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5363285 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24726 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 25085 # number of times the floating registers were written +system.cpu1.num_mem_refs 2096070 # number of memory refs +system.cpu1.num_load_insts 1198996 # Number of load instructions +system.cpu1.num_store_insts 897074 # Number of store instructions +system.cpu1.num_idle_cycles 923177922.874727 # Number of idle cycles +system.cpu1.num_busy_cycles 30077739.125273 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031553 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968447 # Percentage of idle cycles +system.cpu1.Branches 1296149 # Number of branches fetched +system.cpu1.op_class::No_OpClass 410448 5.18% 5.18% # Class of executed instruction +system.cpu1.op_class::IntAlu 5236817 66.10% 71.28% # Class of executed instruction +system.cpu1.op_class::IntMult 8727 0.11% 71.39% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 71.39% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5162 0.07% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 71.46% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::MemRead 1228055 15.50% 86.96% # Class of executed instruction +system.cpu1.op_class::MemWrite 898300 11.34% 98.30% # Class of executed instruction +system.cpu1.op_class::IprAccess 134580 1.70% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7456136 # Class of executed instruction +system.cpu1.op_class::total 7922899 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1017,35 +995,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9673449 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8936896 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 125098 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7569787 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5584968 # Number of BTB hits +system.cpu2.branchPred.lookups 10412478 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9668294 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 126557 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 8251745 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6275895 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 73.779725 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 299823 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7809 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 76.055368 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 302998 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7851 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3461968 # DTB read hits -system.cpu2.dtb.read_misses 12174 # DTB read misses -system.cpu2.dtb.read_acv 114 # DTB read access violations -system.cpu2.dtb.read_accesses 224881 # DTB read accesses -system.cpu2.dtb.write_hits 2122047 # DTB write hits -system.cpu2.dtb.write_misses 2563 # DTB write misses -system.cpu2.dtb.write_acv 106 # DTB write access violations -system.cpu2.dtb.write_accesses 83942 # DTB write accesses -system.cpu2.dtb.data_hits 5584015 # DTB hits -system.cpu2.dtb.data_misses 14737 # DTB misses -system.cpu2.dtb.data_acv 220 # DTB access violations -system.cpu2.dtb.data_accesses 308823 # DTB accesses -system.cpu2.itb.fetch_hits 534012 # ITB hits -system.cpu2.itb.fetch_misses 5788 # ITB misses -system.cpu2.itb.fetch_acv 158 # ITB acv -system.cpu2.itb.fetch_accesses 539800 # ITB accesses +system.cpu2.dtb.read_hits 3529660 # DTB read hits +system.cpu2.dtb.read_misses 12347 # DTB read misses +system.cpu2.dtb.read_acv 141 # DTB read access violations +system.cpu2.dtb.read_accesses 225697 # DTB read accesses +system.cpu2.dtb.write_hits 2155841 # DTB write hits +system.cpu2.dtb.write_misses 2820 # DTB write misses +system.cpu2.dtb.write_acv 143 # DTB write access violations +system.cpu2.dtb.write_accesses 84900 # DTB write accesses +system.cpu2.dtb.data_hits 5685501 # DTB hits +system.cpu2.dtb.data_misses 15167 # DTB misses +system.cpu2.dtb.data_acv 284 # DTB access violations +system.cpu2.dtb.data_accesses 310597 # DTB accesses +system.cpu2.itb.fetch_hits 538073 # ITB hits +system.cpu2.itb.fetch_misses 5955 # ITB misses +system.cpu2.itb.fetch_acv 169 # ITB acv +system.cpu2.itb.fetch_accesses 544028 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1058,305 +1036,305 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30013580 # number of cpu cycles simulated +system.cpu2.numCycles 30702821 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9363383 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 37425902 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9673449 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 5884791 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 18558568 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 408186 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 247 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 10133 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1974 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 231517 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 99918 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 308 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2804138 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 92736 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 28469903 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.314578 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.374234 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9319148 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 39738878 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 10412478 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6578893 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 19243837 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 412304 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 656 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1927 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 233877 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 108804 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2828172 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 93139 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 29124256 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.364460 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.368556 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20072313 70.50% 70.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 312422 1.10% 71.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 471724 1.66% 73.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3982470 13.99% 87.25% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 833365 2.93% 90.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 193345 0.68% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 238464 0.84% 91.69% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 434747 1.53% 93.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1931053 6.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 20002999 68.68% 68.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 306830 1.05% 69.74% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 477568 1.64% 71.37% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4658363 15.99% 87.37% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 855343 2.94% 90.31% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 200502 0.69% 90.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 234860 0.81% 91.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433547 1.49% 93.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1954244 6.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 28469903 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.322302 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.246966 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7673000 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 13050358 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6778876 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 530616 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 191226 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 175016 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13225 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34075356 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 43360 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 191226 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7953535 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4758129 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6310003 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 6998808 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2012380 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33260601 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 68695 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 404029 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 57097 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 943831 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 22264761 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41311324 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41251440 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56013 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20369021 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1895740 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 527174 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63098 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3903100 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3489643 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2214871 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 462169 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 329723 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30742037 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 676819 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30393110 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 17376 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2421658 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1144384 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 483915 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 28469903 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.067552 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.605150 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 29124256 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.339138 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.294307 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7666487 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 12991565 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7744961 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 527663 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 193001 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 177358 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13514 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36364188 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 42851 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 193001 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7942048 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4601261 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6305683 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7969678 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2112012 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35538074 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 62867 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 396006 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 59218 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1045972 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 23773076 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 44310063 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 44249815 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56335 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21846032 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1927044 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 532665 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63556 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3796199 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3529311 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2248768 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 470664 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 333419 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32987424 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 681806 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32666998 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 16031 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2457717 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1151235 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 487594 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 29124256 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.121642 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.623821 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17422923 61.20% 61.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2767864 9.72% 70.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1373994 4.83% 75.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4735624 16.63% 92.38% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1013556 3.56% 95.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 570411 2.00% 97.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 382804 1.34% 99.29% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 154533 0.54% 99.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 48194 0.17% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17381860 59.68% 59.68% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2746661 9.43% 69.11% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1371662 4.71% 73.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5386342 18.49% 92.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1029310 3.53% 95.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 605779 2.08% 97.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 390861 1.34% 99.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 167562 0.58% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 44219 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 28469903 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 29124256 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 82144 21.47% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 176872 46.24% 67.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 123495 32.29% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 85214 22.02% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 179569 46.41% 68.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 122132 31.57% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24311305 79.99% 80.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21079 0.07% 80.07% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 80.07% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20485 0.07% 80.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 80.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 80.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 80.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3589842 11.81% 91.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2146129 7.06% 99.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 300610 0.99% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2450 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26477502 81.05% 81.06% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21078 0.06% 81.12% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20355 0.06% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1225 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3659635 11.20% 92.39% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2180799 6.68% 99.07% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 303954 0.93% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30393110 # Type of FU issued -system.cpu2.iq.rate 1.012645 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 382511 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.012585 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 89403074 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33727235 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 29817840 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 252936 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 119279 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 116815 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30637549 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 135632 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 205530 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32666998 # Type of FU issued +system.cpu2.iq.rate 1.063974 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 386915 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.011844 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 94607462 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 36013478 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 32054290 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 253736 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 119374 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 117198 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32915380 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 136083 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 205891 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 436638 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1484 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6154 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 181627 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 443704 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1465 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6049 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 180746 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4994 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 170094 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5094 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 200289 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 191226 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3996466 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 295299 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32798710 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 54858 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3489643 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2214871 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 602209 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 15595 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 231865 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6154 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 62873 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 134195 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197068 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30195469 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3482644 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 197641 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 193001 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3976817 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 219021 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 35063617 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 53776 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3529311 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2248768 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 606766 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 12977 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 164349 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6049 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63932 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 135830 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 199762 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 32464526 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3550760 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 202472 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1379854 # number of nop insts executed -system.cpu2.iew.exec_refs 5611883 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6643679 # Number of branches executed -system.cpu2.iew.exec_stores 2129239 # Number of stores executed -system.cpu2.iew.exec_rate 1.006060 # Inst execution rate -system.cpu2.iew.wb_sent 29976342 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 29934655 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17254819 # num instructions producing a value -system.cpu2.iew.wb_consumers 20895222 # num instructions consuming a value +system.cpu2.iew.exec_nop 1394387 # number of nop insts executed +system.cpu2.iew.exec_refs 5714159 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7350868 # Number of branches executed +system.cpu2.iew.exec_stores 2163399 # Number of stores executed +system.cpu2.iew.exec_rate 1.057379 # Inst execution rate +system.cpu2.iew.wb_sent 32215343 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 32171488 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18756374 # num instructions producing a value +system.cpu2.iew.wb_consumers 22505351 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.997370 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.825778 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.047835 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.833418 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2658447 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 192904 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 180111 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 28004103 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.074728 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.862098 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2693673 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 194212 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 181849 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 28653786 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.128143 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.870801 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18216020 65.05% 65.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2235913 7.98% 73.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1176646 4.20% 77.23% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4445185 15.87% 93.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 540129 1.93% 95.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 200547 0.72% 95.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 166033 0.59% 96.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 176455 0.63% 96.97% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 847175 3.03% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18143596 63.32% 63.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2243135 7.83% 71.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1187950 4.15% 75.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5112990 17.84% 93.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 566123 1.98% 95.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 201198 0.70% 95.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 164794 0.58% 96.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 163684 0.57% 96.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 870316 3.04% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 28004103 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30096794 # Number of instructions committed -system.cpu2.commit.committedOps 30096794 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 28653786 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32325567 # Number of instructions committed +system.cpu2.commit.committedOps 32325567 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5086249 # Number of memory references committed -system.cpu2.commit.loads 3053005 # Number of loads committed -system.cpu2.commit.membars 67981 # Number of memory barriers committed -system.cpu2.commit.branches 6474041 # Number of branches committed -system.cpu2.commit.fp_insts 115125 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28589001 # Number of committed integer instructions. -system.cpu2.commit.function_calls 239427 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1215466 4.04% 4.04% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 23382957 77.69% 81.73% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20643 0.07% 81.80% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 81.80% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20037 0.07% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3120986 10.37% 92.24% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2034876 6.76% 99.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 300609 1.00% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5153629 # Number of memory references committed +system.cpu2.commit.loads 3085607 # Number of loads committed +system.cpu2.commit.membars 68228 # Number of memory barriers committed +system.cpu2.commit.branches 7176692 # Number of branches committed +system.cpu2.commit.fp_insts 115672 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 30802580 # Number of committed integer instructions. +system.cpu2.commit.function_calls 241655 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1228058 3.80% 3.80% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 25528107 78.97% 82.77% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20647 0.06% 82.83% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 82.83% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20076 0.06% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1225 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3153835 9.76% 92.66% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2069665 6.40% 99.06% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 303954 0.94% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 30096794 # Class of committed instruction -system.cpu2.commit.bw_lim_events 847175 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 32325567 # Class of committed instruction +system.cpu2.commit.bw_lim_events 870316 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 59838509 # The number of ROB reads -system.cpu2.rob.rob_writes 65974697 # The number of ROB writes -system.cpu2.timesIdled 175016 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1543677 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1747747743 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 28883768 # Number of Instructions Simulated -system.cpu2.committedOps 28883768 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.039116 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.039116 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.962357 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.962357 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39632695 # number of integer regfile reads -system.cpu2.int_regfile_writes 21162382 # number of integer regfile writes -system.cpu2.fp_regfile_reads 70702 # number of floating regfile reads -system.cpu2.fp_regfile_writes 70843 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4340126 # number of misc regfile reads -system.cpu2.misc_regfile_writes 270474 # number of misc regfile writes +system.cpu2.rob.rob_reads 62726939 # The number of ROB reads +system.cpu2.rob.rob_writes 70507401 # The number of ROB writes +system.cpu2.timesIdled 178497 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1578565 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745106872 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31099959 # Number of Instructions Simulated +system.cpu2.committedOps 31099959 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.987230 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.987230 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.012935 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.012935 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42640475 # number of integer regfile reads +system.cpu2.int_regfile_writes 22658201 # number of integer regfile writes +system.cpu2.fp_regfile_reads 70901 # number of floating regfile reads +system.cpu2.fp_regfile_writes 71243 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5010785 # number of misc regfile reads +system.cpu2.misc_regfile_writes 273099 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1371,10 +1349,10 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7317 # Transaction distribution system.iobus.trans_dist::ReadResp 7317 # Transaction distribution -system.iobus.trans_dist::WriteReq 51363 # Transaction distribution -system.iobus.trans_dist::WriteResp 9811 # Transaction distribution +system.iobus.trans_dist::WriteReq 51362 # Transaction distribution +system.iobus.trans_dist::WriteResp 9810 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5194 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1386,11 +1364,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33910 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 117360 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1402,37 +1380,41 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 45576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2707184 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2201000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2232000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5529000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5364000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2073000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 1863000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 58000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 7000 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 166547212 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 100878274 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9356000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 8843000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17276500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17495500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.262651 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254165 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693890143000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.262651 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078916 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078916 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1693892917000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254165 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078385 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078385 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1446,14 +1428,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9417462 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9417462 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 5628764250 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 5628764250 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9417462 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9417462 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9417462 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9417462 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9444962 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9444962 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 3667270812 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 3667270812 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9444962 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9444962 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9444962 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9444962 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) @@ -1470,19 +1452,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54436.196532 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 54436.196532 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 135463.136552 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 135463.136552 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 54436.196532 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 54436.196532 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 86158 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54595.156069 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54595.156069 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 88257.383808 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 88257.383808 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 54595.156069 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 54595.156069 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 54595.156069 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 54595.156069 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31008 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9840 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4243 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.755894 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.308037 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1490,234 +1472,237 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17024 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 17024 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17280 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 17280 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5776462 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5776462 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 4743516250 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4743516250 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5776462 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59620.392398 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62365.141612 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55227.480517 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63094.090118 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62924.282154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59620.392398 # average overall mshr miss latency +system.l2c.writebacks::writebacks 75392 # number of writebacks +system.l2c.writebacks::total 75392 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu1.inst 2297 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 15641 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 4814 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 16829 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 418496000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 694509000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 483058500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 727940000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1210998500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.017827 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.157678 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014605 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.061015 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.019247 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.578947 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.354839 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408460 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.254337 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.140043 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017827 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.234732 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014605 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.110945 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034749 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017827 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.234732 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014605 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.110945 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034749 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69074.989116 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61949.204015 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62185.646800 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 63528.132185 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 31591.636364 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 31591.636364 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 18001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63351.177453 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 75924.889630 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70595.341502 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69074.989116 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62698.783470 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 70320.426823 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 67183.160187 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69074.989116 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62698.783470 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70320.426823 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 67183.160187 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1827,92 +1820,92 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 294932 # Transaction distribution -system.membus.trans_dist::ReadResp 294926 # Transaction distribution -system.membus.trans_dist::WriteReq 9811 # Transaction distribution -system.membus.trans_dist::WriteResp 9811 # Transaction distribution -system.membus.trans_dist::Writeback 116905 # Transaction distribution +system.membus.trans_dist::ReadReq 295002 # Transaction distribution +system.membus.trans_dist::ReadResp 294996 # Transaction distribution +system.membus.trans_dist::WriteReq 9810 # Transaction distribution +system.membus.trans_dist::WriteResp 9810 # Transaction distribution +system.membus.trans_dist::Writeback 116904 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 163 # Transaction distribution +system.membus.trans_dist::UpgradeReq 145 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 165 # Transaction distribution -system.membus.trans_dist::ReadExReq 115724 # Transaction distribution -system.membus.trans_dist::ReadExResp 115724 # Transaction distribution +system.membus.trans_dist::UpgradeResp 147 # Transaction distribution +system.membus.trans_dist::ReadExReq 115657 # Transaction distribution +system.membus.trans_dist::ReadExResp 115657 # Transaction distribution system.membus.trans_dist::BadAddressError 6 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882256 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 916226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 916176 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124907 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124907 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1041133 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30633216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30678792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1041083 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30632256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30677824 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5323648 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5323648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36002440 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 140 # Total snoops (count) -system.membus.snoop_fanout::samples 562134 # Request fanout histogram +system.membus.pkt_size::total 36001472 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 157 # Total snoops (count) +system.membus.snoop_fanout::samples 562136 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 562134 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 562136 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 562134 # Request fanout histogram -system.membus.reqLayer0.occupancy 11832500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 562136 # Request fanout histogram +system.membus.reqLayer0.occupancy 11072500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 654960000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 412860298 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 7500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 770434435 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 438835201 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 17654500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 17657500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2063004 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2062983 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 9811 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 9811 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 835667 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 17024 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 48 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 57 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302779 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302779 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2063715 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2063694 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 835707 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 17293 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 31 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 42 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302749 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302749 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1930013 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3656818 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5586831 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61758720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142717704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 204476424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1930984 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3657230 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5588214 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61790208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142733184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 204523392 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 41934 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3236018 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012894 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112817 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3236737 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012895 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112822 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3194293 98.71% 98.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 41725 1.29% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3194999 98.71% 98.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 41738 1.29% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3236018 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2201638999 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3236737 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1080719000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 82500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2030846564 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2289452792 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 689338845 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 790311532 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA |