diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
| commit | 8b4b1dcb86b0799a8c32056427581a8b6249a3bf (patch) | |
| tree | 96016b415513dc6c2c29877e1a76220e0edae629 /tests/long/fs/10.linux-boot/ref/alpha | |
| parent | a00383a40aeb8347af7e05f3966ab141484921a5 (diff) | |
| download | gem5-8b4b1dcb86b0799a8c32056427581a8b6249a3bf.tar.xz | |
stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
3 files changed, 4180 insertions, 4399 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 4177c2e35..bc7291548 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.903338 # Number of seconds simulated -sim_ticks 1903338216000 # Number of ticks simulated -final_tick 1903338216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.905240 # Number of seconds simulated +sim_ticks 1905239522500 # Number of ticks simulated +final_tick 1905239522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 150214 # Simulator instruction rate (inst/s) -host_op_rate 150214 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5096064990 # Simulator tick rate (ticks/s) -host_mem_usage 314972 # Number of bytes of host memory used -host_seconds 373.49 # Real time elapsed on the host -sim_insts 56103611 # Number of instructions simulated -sim_ops 56103611 # Number of ops (including micro ops) simulated +host_inst_rate 125426 # Simulator instruction rate (inst/s) +host_op_rate 125426 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4213194084 # Simulator tick rate (ticks/s) +host_mem_usage 351852 # Number of bytes of host memory used +host_seconds 452.21 # Real time elapsed on the host +sim_insts 56718526 # Number of instructions simulated +sim_ops 56718526 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 740992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24346432 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 236544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 996032 # Number of bytes read from this memory -system.physmem.bytes_read::total 28970176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 740992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 236544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7923904 # Number of bytes written to this memory -system.physmem.bytes_written::total 7923904 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11578 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 380413 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41409 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3696 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 15563 # Number of read requests responded to by this memory -system.physmem.num_reads::total 452659 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123811 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123811 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 389312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12791438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1392383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 124278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 523308 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15220719 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 389312 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 124278 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513590 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4163161 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4163161 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4163161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 389312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12791438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1392383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 124278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 523308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19383880 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 452659 # Number of read requests accepted -system.physmem.writeReqs 123811 # Number of write requests accepted -system.physmem.readBursts 452659 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123811 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28966400 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3776 # Total number of bytes read from write queue -system.physmem.bytesWritten 7923264 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28970176 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7923904 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 59 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 764480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24384256 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2649344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 214080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 925440 # Number of bytes read from this memory +system.physmem.bytes_read::total 28937600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 764480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 214080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 978560 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7885248 # Number of bytes written to this memory +system.physmem.bytes_written::total 7885248 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11945 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 381004 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41396 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3345 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 14460 # Number of read requests responded to by this memory +system.physmem.num_reads::total 452150 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 123207 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123207 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 401251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12798525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1390557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 112364 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 485734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15188432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 401251 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 112364 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 513615 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4138717 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4138717 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4138717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 401251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12798525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1390557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 112364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 485734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19327149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 452150 # Number of read requests accepted +system.physmem.writeReqs 123207 # Number of write requests accepted +system.physmem.readBursts 452150 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123207 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28929984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue +system.physmem.bytesWritten 7883136 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28937600 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7885248 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3474 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28542 # Per bank write bursts -system.physmem.perBankRdBursts::1 28115 # Per bank write bursts -system.physmem.perBankRdBursts::2 28449 # Per bank write bursts -system.physmem.perBankRdBursts::3 28319 # Per bank write bursts -system.physmem.perBankRdBursts::4 28001 # Per bank write bursts -system.physmem.perBankRdBursts::5 28388 # Per bank write bursts -system.physmem.perBankRdBursts::6 28437 # Per bank write bursts -system.physmem.perBankRdBursts::7 28681 # Per bank write bursts -system.physmem.perBankRdBursts::8 28670 # Per bank write bursts -system.physmem.perBankRdBursts::9 28576 # Per bank write bursts -system.physmem.perBankRdBursts::10 28034 # Per bank write bursts -system.physmem.perBankRdBursts::11 27899 # Per bank write bursts -system.physmem.perBankRdBursts::12 27884 # Per bank write bursts -system.physmem.perBankRdBursts::13 28245 # Per bank write bursts -system.physmem.perBankRdBursts::14 28268 # Per bank write bursts -system.physmem.perBankRdBursts::15 28092 # Per bank write bursts -system.physmem.perBankWrBursts::0 8222 # Per bank write bursts -system.physmem.perBankWrBursts::1 7571 # Per bank write bursts -system.physmem.perBankWrBursts::2 7821 # Per bank write bursts -system.physmem.perBankWrBursts::3 7782 # Per bank write bursts -system.physmem.perBankWrBursts::4 7428 # Per bank write bursts -system.physmem.perBankWrBursts::5 7859 # Per bank write bursts -system.physmem.perBankWrBursts::6 7924 # Per bank write bursts -system.physmem.perBankWrBursts::7 7992 # Per bank write bursts -system.physmem.perBankWrBursts::8 7912 # Per bank write bursts -system.physmem.perBankWrBursts::9 7920 # Per bank write bursts -system.physmem.perBankWrBursts::10 7418 # Per bank write bursts -system.physmem.perBankWrBursts::11 7297 # Per bank write bursts -system.physmem.perBankWrBursts::12 7319 # Per bank write bursts -system.physmem.perBankWrBursts::13 7829 # Per bank write bursts -system.physmem.perBankWrBursts::14 7922 # Per bank write bursts -system.physmem.perBankWrBursts::15 7585 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 5017 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28700 # Per bank write bursts +system.physmem.perBankRdBursts::1 28863 # Per bank write bursts +system.physmem.perBankRdBursts::2 29008 # Per bank write bursts +system.physmem.perBankRdBursts::3 28541 # Per bank write bursts +system.physmem.perBankRdBursts::4 28135 # Per bank write bursts +system.physmem.perBankRdBursts::5 28059 # Per bank write bursts +system.physmem.perBankRdBursts::6 27918 # Per bank write bursts +system.physmem.perBankRdBursts::7 27861 # Per bank write bursts +system.physmem.perBankRdBursts::8 27885 # Per bank write bursts +system.physmem.perBankRdBursts::9 28003 # Per bank write bursts +system.physmem.perBankRdBursts::10 27955 # Per bank write bursts +system.physmem.perBankRdBursts::11 28030 # Per bank write bursts +system.physmem.perBankRdBursts::12 28165 # Per bank write bursts +system.physmem.perBankRdBursts::13 28514 # Per bank write bursts +system.physmem.perBankRdBursts::14 28239 # Per bank write bursts +system.physmem.perBankRdBursts::15 28155 # Per bank write bursts +system.physmem.perBankWrBursts::0 8383 # Per bank write bursts +system.physmem.perBankWrBursts::1 8222 # Per bank write bursts +system.physmem.perBankWrBursts::2 8291 # Per bank write bursts +system.physmem.perBankWrBursts::3 7900 # Per bank write bursts +system.physmem.perBankWrBursts::4 7506 # Per bank write bursts +system.physmem.perBankWrBursts::5 7518 # Per bank write bursts +system.physmem.perBankWrBursts::6 7426 # Per bank write bursts +system.physmem.perBankWrBursts::7 7231 # Per bank write bursts +system.physmem.perBankWrBursts::8 7193 # Per bank write bursts +system.physmem.perBankWrBursts::9 7295 # Per bank write bursts +system.physmem.perBankWrBursts::10 7315 # Per bank write bursts +system.physmem.perBankWrBursts::11 7381 # Per bank write bursts +system.physmem.perBankWrBursts::12 7680 # Per bank write bursts +system.physmem.perBankWrBursts::13 8142 # Per bank write bursts +system.physmem.perBankWrBursts::14 8013 # Per bank write bursts +system.physmem.perBankWrBursts::15 7678 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1903333578000 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 1905235063000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 452659 # Read request sizes (log2) +system.physmem.readPktSize::6 452150 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123811 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 323009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 67548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1491 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 123207 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 319865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3776 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3798 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1685 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -143,461 +143,375 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 47120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 782.856367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 226.112166 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1866.075506 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 16751 35.55% 35.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6847 14.53% 50.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4876 10.35% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2833 6.01% 66.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1808 3.84% 70.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1449 3.08% 73.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1103 2.34% 75.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 806 1.71% 77.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 633 1.34% 78.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 628 1.33% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 650 1.38% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 508 1.08% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 311 0.66% 83.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 305 0.65% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 262 0.56% 84.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 366 0.78% 85.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 155 0.33% 85.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 210 0.45% 85.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 130 0.28% 86.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 135 0.29% 86.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 148 0.31% 86.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 388 0.82% 87.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 228 0.48% 88.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 713 1.51% 89.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 124 0.26% 89.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 79 0.17% 90.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 68 0.14% 90.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 140 0.30% 90.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 59 0.13% 90.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 90 0.19% 90.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 49 0.10% 90.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 89 0.19% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 69 0.15% 91.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 88 0.19% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 28 0.06% 91.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 26 0.06% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 54 0.11% 91.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 52 0.11% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 27 0.06% 91.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 28 0.06% 91.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 27 0.06% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 54 0.11% 92.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 53 0.11% 92.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 17 0.04% 92.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 31 0.07% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 83 0.18% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 40 0.08% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 35 0.07% 92.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 42 0.09% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 86 0.18% 92.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 24 0.05% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 15 0.03% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 51 0.11% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 50 0.11% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 24 0.05% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 22 0.05% 93.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 24 0.05% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 52 0.11% 93.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 51 0.11% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 12 0.03% 93.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 29 0.06% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 84 0.18% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 41 0.09% 93.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 31 0.07% 94.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 38 0.08% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 87 0.18% 94.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 24 0.05% 94.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 17 0.04% 94.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 52 0.11% 94.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 51 0.11% 94.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 24 0.05% 94.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 22 0.05% 94.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 23 0.05% 94.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 50 0.11% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 51 0.11% 94.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 12 0.03% 94.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 27 0.06% 95.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 86 0.18% 95.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 41 0.09% 95.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 30 0.06% 95.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 39 0.08% 95.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 84 0.18% 95.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 24 0.05% 95.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 9 0.02% 95.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 53 0.11% 95.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 50 0.11% 95.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 23 0.05% 95.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 22 0.05% 95.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 22 0.05% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 49 0.10% 96.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 50 0.11% 96.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 9 0.02% 96.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 25 0.05% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 85 0.18% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 41 0.09% 96.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 30 0.06% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 42 0.09% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 84 0.18% 96.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 24 0.05% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 10 0.02% 96.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 52 0.11% 97.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 52 0.11% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 24 0.05% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 22 0.05% 97.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 25 0.05% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 49 0.10% 97.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 49 0.10% 97.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 8 0.02% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 27 0.06% 97.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 87 0.18% 97.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 41 0.09% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 317 0.67% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 2 0.00% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 1 0.00% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 6 0.01% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7491 1 0.00% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 14 0.03% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 2 0.00% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 8 0.02% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.00% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 3 0.01% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 322 0.68% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 2 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 3 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 3 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11331 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11587 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11907 2 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 3 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 3 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 3 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 39 0.08% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 175 0.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 47120 # Bytes accessed per row activation -system.physmem.totQLat 8783315250 # Total ticks spent queuing -system.physmem.totMemAccLat 16310447750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2263000000 # Total ticks spent in databus transfers -system.physmem.totBankLat 5264132500 # Total ticks spent accessing banks -system.physmem.avgQLat 19406.35 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11630.87 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 51367 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 630.908404 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 404.510586 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 424.248985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 9707 18.90% 18.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6974 13.58% 32.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3124 6.08% 38.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1892 3.68% 42.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1518 2.96% 45.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 943 1.84% 47.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 823 1.60% 48.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 886 1.72% 50.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25500 49.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 51367 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7232 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 62.502074 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2469.163441 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 7229 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7232 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7232 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.031803 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.787924 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.763450 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6148 85.01% 85.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 35 0.48% 85.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 69 0.95% 86.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 422 5.84% 92.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 144 1.99% 94.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 50 0.69% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 33 0.46% 95.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 29 0.40% 95.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 50 0.69% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 33 0.46% 96.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 22 0.30% 97.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 30 0.41% 97.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 23 0.32% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 33 0.46% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.04% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 10 0.14% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 7 0.10% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 5 0.07% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.03% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 3 0.04% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 4 0.06% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 3 0.04% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 4 0.06% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 6 0.08% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 7 0.10% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 2 0.03% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 5 0.07% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 4 0.06% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 2 0.03% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 2 0.03% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 2 0.03% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 9 0.12% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 8 0.11% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 6 0.08% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 1 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 4 0.06% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 3 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 4 0.06% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7232 # Writes before turning the bus around for reads +system.physmem.totQLat 10473139750 # Total ticks spent queuing +system.physmem.totMemAccLat 18209837250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2260155000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5476542500 # Total ticks spent accessing banks +system.physmem.avgQLat 23169.07 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 12115.41 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 36037.22 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.22 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.16 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40284.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.32 # Average write queue length when enqueuing -system.physmem.readRowHits 430734 # Number of row buffer hits during reads -system.physmem.writeRowHits 98547 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.59 # Row buffer hit rate for writes -system.physmem.avgGap 3301704.47 # Average gap between requests -system.physmem.pageHitRate 91.82 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19439855 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296479 # Transaction distribution -system.membus.trans_dist::ReadResp 296230 # Transaction distribution -system.membus.trans_dist::WriteReq 12351 # Transaction distribution -system.membus.trans_dist::WriteResp 12351 # Transaction distribution -system.membus.trans_dist::Writeback 123811 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5304 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1475 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3474 # Transaction distribution -system.membus.trans_dist::ReadExReq 164353 # Transaction distribution -system.membus.trans_dist::ReadExResp 164224 # Transaction distribution -system.membus.trans_dist::BadAddressError 249 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39094 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 915454 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 498 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 955046 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124656 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124656 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1079702 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68202 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31586624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31654826 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5307456 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36962282 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36962282 # Total data (bytes) -system.membus.snoop_data_through_bus 38336 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 36252500 # Layer occupancy (ticks) +system.physmem.avgRdQLen 1.83 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.68 # Average write queue length when enqueuing +system.physmem.readRowHits 407908 # Number of row buffer hits during reads +system.physmem.writeRowHits 99848 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.24 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.04 # Row buffer hit rate for writes +system.physmem.avgGap 3311396.34 # Average gap between requests +system.physmem.pageHitRate 88.27 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.40 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 19386335 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 296672 # Transaction distribution +system.membus.trans_dist::ReadResp 296448 # Transaction distribution +system.membus.trans_dist::WriteReq 13044 # Transaction distribution +system.membus.trans_dist::WriteResp 13044 # Transaction distribution +system.membus.trans_dist::Writeback 123207 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9628 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5545 # Transaction distribution +system.membus.trans_dist::UpgradeResp 5017 # Transaction distribution +system.membus.trans_dist::ReadExReq 163957 # Transaction distribution +system.membus.trans_dist::ReadExResp 163513 # Transaction distribution +system.membus.trans_dist::BadAddressError 224 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40492 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 924104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 448 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 965044 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124646 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124646 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1089690 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 73787 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31516032 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31589819 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306816 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5306816 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36896635 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36896635 # Total data (bytes) +system.membus.snoop_data_through_bus 38976 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 37949499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1624596499 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1621348498 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 317500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 283500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3836772510 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3837196476 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376321991 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376708248 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 345713 # number of replacements -system.l2c.tags.tagsinuse 65292.619294 # Cycle average of tags in use -system.l2c.tags.total_refs 2607692 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 410924 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.345923 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7069563750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53648.503329 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4120.078366 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5598.798644 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1365.340117 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 559.898838 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.818611 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.062867 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.085431 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.020833 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008543 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996286 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65211 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2154 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5524 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6881 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50473 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.995041 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27399611 # Number of tag accesses -system.l2c.tags.data_accesses 27399611 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 754547 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 572386 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 313557 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 249669 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1890159 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 840492 # number of Writeback hits -system.l2c.Writeback_hits::total 840492 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 74 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 204 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 33 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 144073 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 44330 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 188403 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 754547 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 716459 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 313557 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 293999 # number of demand (read+write) hits -system.l2c.demand_hits::total 2078562 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 754547 # number of overall hits -system.l2c.overall_hits::cpu0.data 716459 # number of overall hits -system.l2c.overall_hits::cpu1.inst 313557 # number of overall hits -system.l2c.overall_hits::cpu1.data 293999 # number of overall hits -system.l2c.overall_hits::total 2078562 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11586 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 272059 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3706 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1775 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289126 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2565 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 587 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3152 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 58 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 107 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 108741 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 14088 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122829 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11586 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 380800 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3706 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 15863 # number of demand (read+write) misses -system.l2c.demand_misses::total 411955 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11586 # number of overall misses -system.l2c.overall_misses::cpu0.data 380800 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3706 # number of overall misses -system.l2c.overall_misses::cpu1.data 15863 # number of overall misses -system.l2c.overall_misses::total 411955 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 929054999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17693461250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 314236981 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 144928247 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 19081681477 # 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mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64110.329818 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53070.867711 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67735.355456 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76765.153760 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 53842.237225 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10019.190521 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.523416 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10018.881135 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.298153 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10010.343458 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10022.063197 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70714.722875 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 87695.479725 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72530.037020 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64110.329818 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58121.888530 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67735.355456 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86384.017237 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59393.760756 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64110.329818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58121.888530 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67735.355456 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86384.017237 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59393.760756 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -735,15 +649,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.213166 # Cycle average of tags in use +system.iocache.tags.replacements 41698 # number of replacements +system.iocache.tags.tagsinuse 0.475429 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1712301131000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.213166 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.013323 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.013323 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1712299730000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.475429 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.029714 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.029714 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -757,14 +671,14 @@ system.iocache.demand_misses::tsunami.ide 41727 # n system.iocache.demand_misses::total 41727 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21368383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21368383 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 13021515788 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 13021515788 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 13042884171 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 13042884171 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 13042884171 # number of overall miss cycles -system.iocache.overall_miss_latency::total 13042884171 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21363133 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21363133 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 13166015946 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 13166015946 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13187379079 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13187379079 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13187379079 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13187379079 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -781,24 +695,24 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122105.045714 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122105.045714 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 313378.797362 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 313378.797362 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 312576.609174 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 312576.609174 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 312576.609174 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 312576.609174 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 407057 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122075.045714 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122075.045714 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 316856.371438 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 316856.371438 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 316039.472739 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 316039.472739 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 316039.472739 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 316039.472739 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 391077 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 29358 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28468 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.865284 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.737424 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks +system.iocache.writebacks::writebacks 41523 # number of writebacks +system.iocache.writebacks::total 41523 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses @@ -807,14 +721,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41727 system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12267383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12267383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10859254806 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10859254806 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10871522189 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10871522189 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10871522189 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10871522189 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12262133 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12262133 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 11002982450 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 11002982450 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 11015244583 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 11015244583 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 11015244583 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 11015244583 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -823,14 +737,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70099.331429 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70099.331429 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 261341.326675 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 261341.326675 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 260539.271671 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 260539.271671 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 260539.271671 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 260539.271671 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70069.331429 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70069.331429 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 264800.309251 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 264800.309251 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263983.621708 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 263983.621708 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263983.621708 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 263983.621708 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -844,35 +758,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 11006012 # Number of BP lookups -system.cpu0.branchPred.condPredicted 9319545 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 291548 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 7161716 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4729334 # Number of BTB hits +system.cpu0.branchPred.lookups 12197818 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10301308 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 323625 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 8091894 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5160475 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.036324 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 682987 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 26515 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 63.773389 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 773216 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29770 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7888949 # DTB read hits -system.cpu0.dtb.read_misses 30101 # DTB read misses -system.cpu0.dtb.read_acv 574 # DTB read access violations -system.cpu0.dtb.read_accesses 665608 # DTB read accesses -system.cpu0.dtb.write_hits 5247941 # DTB write hits -system.cpu0.dtb.write_misses 8093 # DTB write misses -system.cpu0.dtb.write_acv 365 # DTB write access violations -system.cpu0.dtb.write_accesses 232480 # DTB write accesses -system.cpu0.dtb.data_hits 13136890 # DTB hits -system.cpu0.dtb.data_misses 38194 # DTB misses -system.cpu0.dtb.data_acv 939 # DTB access violations -system.cpu0.dtb.data_accesses 898088 # DTB accesses -system.cpu0.itb.fetch_hits 973403 # ITB hits -system.cpu0.itb.fetch_misses 31216 # ITB misses -system.cpu0.itb.fetch_acv 1004 # ITB acv -system.cpu0.itb.fetch_accesses 1004619 # ITB accesses +system.cpu0.dtb.read_hits 8724392 # DTB read hits +system.cpu0.dtb.read_misses 30821 # DTB read misses +system.cpu0.dtb.read_acv 561 # DTB read access violations +system.cpu0.dtb.read_accesses 667825 # DTB read accesses +system.cpu0.dtb.write_hits 5867379 # DTB write hits +system.cpu0.dtb.write_misses 8333 # DTB write misses +system.cpu0.dtb.write_acv 362 # DTB write access violations +system.cpu0.dtb.write_accesses 233878 # DTB write accesses +system.cpu0.dtb.data_hits 14591771 # DTB hits +system.cpu0.dtb.data_misses 39154 # DTB misses +system.cpu0.dtb.data_acv 923 # DTB access violations +system.cpu0.dtb.data_accesses 901703 # DTB accesses +system.cpu0.itb.fetch_hits 1047253 # ITB hits +system.cpu0.itb.fetch_misses 31067 # ITB misses +system.cpu0.itb.fetch_acv 998 # ITB acv +system.cpu0.itb.fetch_accesses 1078320 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -885,269 +799,269 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 104578589 # number of cpu cycles simulated +system.cpu0.numCycles 112262549 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 21960114 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 56555379 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 11006012 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5412321 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10656012 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1518801 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 32354382 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 30030 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 204805 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 243991 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6896028 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 198863 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 66418859 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.851496 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.187669 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 25337690 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 62232975 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 12197818 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5933691 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11660813 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1669062 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 34963299 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 31852 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 204835 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 245581 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7519019 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 220862 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 73507816 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.846617 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.186991 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 55762847 83.96% 83.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 696881 1.05% 85.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1363707 2.05% 87.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 607827 0.92% 87.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2362378 3.56% 91.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 460793 0.69% 92.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 493104 0.74% 92.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 775074 1.17% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3896248 5.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 61847003 84.14% 84.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 769960 1.05% 85.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1463561 1.99% 87.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 676221 0.92% 88.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2490968 3.39% 91.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 505392 0.69% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 543861 0.74% 92.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 933568 1.27% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4277282 5.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 66418859 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.105242 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.540793 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 23145338 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 31820288 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9657130 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 858074 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 938028 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 439220 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 31710 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 55497748 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 98418 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 938028 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 24047696 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12280609 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 16434779 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9089203 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3628542 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 52477613 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 6876 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 427894 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1374075 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 35152162 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 63950241 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 63830636 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 110747 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30925813 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4226341 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1321793 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 195129 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 9844333 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8256385 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5476723 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1002198 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 667476 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 46574896 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1622063 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 45553168 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 69417 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5159281 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2712846 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1098313 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 66418859 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.685847 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.329893 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 73507816 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.108654 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.554352 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26369028 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 34601594 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10599753 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 908827 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1028613 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 489342 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35202 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 61098455 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 108348 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1028613 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27370799 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12650473 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18559497 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9975684 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3922748 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 57686354 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 6807 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 465136 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1446625 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 38461887 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 70023385 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 69867874 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 145011 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33864047 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4597832 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1504040 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 221397 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 10820518 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9135753 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6149920 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1079808 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 706714 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 51077926 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1853906 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 49994907 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 110749 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5661802 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2962344 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1252355 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 73507816 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.680130 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.328001 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 46042875 69.32% 69.32% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9328009 14.04% 83.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4252197 6.40% 89.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2720710 4.10% 93.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2085310 3.14% 97.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1089347 1.64% 98.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 576580 0.87% 99.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 279468 0.42% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 44363 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 51188064 69.64% 69.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10233888 13.92% 83.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4604901 6.26% 89.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2962380 4.03% 93.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2331848 3.17% 97.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1189595 1.62% 98.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 642601 0.87% 99.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 303208 0.41% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 51331 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 66418859 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 73507816 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 65077 10.66% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.66% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 284948 46.66% 57.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 260601 42.68% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 67972 10.01% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.01% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 320913 47.27% 57.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 290070 42.72% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 31229788 68.56% 68.57% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47289 0.10% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.67% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 14649 0.03% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.71% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8205422 18.01% 86.72% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5307142 11.65% 98.37% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 743210 1.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 34052559 68.11% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 53588 0.11% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 16727 0.03% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.26% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9088781 18.18% 86.44% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5934753 11.87% 98.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 842846 1.69% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 45553168 # Type of FU issued -system.cpu0.iq.rate 0.435588 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 610626 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.013405 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 157729759 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 53136035 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44625486 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 475478 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 231159 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 224228 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 45911492 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 248517 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 497947 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 49994907 # Type of FU issued +system.cpu0.iq.rate 0.445339 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 678955 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.013580 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 173664474 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 58303886 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 48932524 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 622859 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 301167 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 293964 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 50344041 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 326051 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 531595 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1006840 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3517 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 11189 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 378910 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1104780 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2697 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 11676 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 443054 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 13584 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 146356 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 13921 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 147330 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 938028 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8572601 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 702117 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50999649 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 565079 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8256385 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5476723 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1432117 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 572819 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5269 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 11189 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 141170 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 315582 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 456752 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 45215846 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7939970 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 337321 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1028613 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8821962 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 743484 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 56052726 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 628552 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9135753 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6149920 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1633160 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 601804 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5465 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 11676 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 157790 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 354691 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 512481 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 49615767 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8780349 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 379139 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2802690 # number of nop insts executed -system.cpu0.iew.exec_refs 13207799 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7146234 # Number of branches executed -system.cpu0.iew.exec_stores 5267829 # Number of stores executed -system.cpu0.iew.exec_rate 0.432362 # Inst execution rate -system.cpu0.iew.wb_sent 44934571 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44849714 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 22315831 # num instructions producing a value -system.cpu0.iew.wb_consumers 29845824 # num instructions consuming a value +system.cpu0.iew.exec_nop 3120894 # number of nop insts executed +system.cpu0.iew.exec_refs 14670742 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7826693 # Number of branches executed +system.cpu0.iew.exec_stores 5890393 # Number of stores executed +system.cpu0.iew.exec_rate 0.441962 # Inst execution rate +system.cpu0.iew.wb_sent 49317778 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 49226488 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24274382 # num instructions producing a value +system.cpu0.iew.wb_consumers 32670143 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.428861 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.747704 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.438494 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.743014 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5562563 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 523750 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 426483 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 65480831 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.692465 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.608721 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6126865 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 601551 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 478401 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 72479203 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.687487 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.606917 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 48404249 73.92% 73.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7174588 10.96% 84.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3839849 5.86% 90.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2141053 3.27% 94.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1161993 1.77% 95.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 481151 0.73% 96.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 411214 0.63% 97.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 389126 0.59% 97.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1477608 2.26% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 53761554 74.18% 74.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7891628 10.89% 85.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 4152119 5.73% 90.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2321486 3.20% 93.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1304265 1.80% 95.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 530677 0.73% 96.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 447192 0.62% 97.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 447640 0.62% 97.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1622642 2.24% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 65480831 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 45343202 # Number of instructions committed -system.cpu0.commit.committedOps 45343202 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 72479203 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 49828537 # Number of instructions committed +system.cpu0.commit.committedOps 49828537 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 12347358 # Number of memory references committed -system.cpu0.commit.loads 7249545 # Number of loads committed -system.cpu0.commit.membars 175312 # Number of memory barriers committed -system.cpu0.commit.branches 6808554 # Number of branches committed -system.cpu0.commit.fp_insts 222342 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 42040123 # Number of committed integer instructions. -system.cpu0.commit.function_calls 564734 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1477608 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13737839 # Number of memory references committed +system.cpu0.commit.loads 8030973 # Number of loads committed +system.cpu0.commit.membars 204358 # Number of memory barriers committed +system.cpu0.commit.branches 7461649 # Number of branches committed +system.cpu0.commit.fp_insts 291974 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 46136165 # Number of committed integer instructions. +system.cpu0.commit.function_calls 636945 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1622642 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 114710793 # The number of ROB reads -system.cpu0.rob.rob_writes 102749676 # The number of ROB writes -system.cpu0.timesIdled 949561 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 38159730 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3702093008 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 42781436 # Number of Instructions Simulated -system.cpu0.committedOps 42781436 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 42781436 # Number of Instructions Simulated -system.cpu0.cpi 2.444485 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.444485 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.409084 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.409084 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 59516377 # number of integer regfile reads -system.cpu0.int_regfile_writes 32453910 # number of integer regfile writes -system.cpu0.fp_regfile_reads 110308 # number of floating regfile reads -system.cpu0.fp_regfile_writes 111090 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1625466 # number of misc regfile reads -system.cpu0.misc_regfile_writes 747841 # number of misc regfile writes +system.cpu0.rob.rob_reads 126610557 # The number of ROB reads +system.cpu0.rob.rob_writes 112939421 # The number of ROB writes +system.cpu0.timesIdled 1039659 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 38754733 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3698211471 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 46979170 # Number of Instructions Simulated +system.cpu0.committedOps 46979170 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 46979170 # Number of Instructions Simulated +system.cpu0.cpi 2.389624 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.389624 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.418476 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.418476 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 65113755 # number of integer regfile reads +system.cpu0.int_regfile_writes 35503571 # number of integer regfile writes +system.cpu0.fp_regfile_reads 144629 # number of floating regfile reads +system.cpu0.fp_regfile_writes 146446 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1885764 # number of misc regfile reads +system.cpu0.misc_regfile_writes 851290 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1179,81 +1093,81 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 112873708 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2210500 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2210236 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12351 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12351 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 840492 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 5351 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1545 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 6896 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 353777 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 312228 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 249 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1532372 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2827999 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 634560 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 901176 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5896107 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 49032512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 108336621 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20304832 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 35573309 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 213247274 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 213236842 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 1600000 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5059383343 # Layer occupancy (ticks) +system.toL2Bus.throughput 110236199 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2184890 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2184651 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13044 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13044 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 807199 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 9705 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5617 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 15322 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 337408 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295861 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 224 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1805066 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3017885 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 369158 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 600045 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5792154 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 57759168 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 115626954 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 11812096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23360753 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 208558971 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 208548411 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 1477952 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4893610631 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 733500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3452114362 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4065813860 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5048329138 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5358512161 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1429282335 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1486623569 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 831641640 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 971081953 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1434231 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7371 # Transaction distribution -system.iobus.trans_dist::ReadResp 7371 # Transaction distribution -system.iobus.trans_dist::WriteReq 53903 # Transaction distribution -system.iobus.trans_dist::WriteResp 53903 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10490 # Packet count per connected master and slave (bytes) +system.iobus.throughput 1435731 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7377 # Transaction distribution +system.iobus.trans_dist::ReadResp 7377 # Transaction distribution +system.iobus.trans_dist::WriteReq 54596 # Transaction distribution +system.iobus.trans_dist::WriteResp 54596 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11886 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39094 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40492 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122548 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41960 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 123946 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 47544 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 68202 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 73787 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2729826 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2729826 # Total data (bytes) -system.iobus.reqLayer0.occupancy 9845000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2735411 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2735411 # Total data (bytes) +system.iobus.reqLayer0.occupancy 11236000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1267,7 +1181,7 @@ system.iobus.reqLayer23.occupancy 13505000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) @@ -1275,267 +1189,267 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 377802180 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 379995831 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26743000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27448000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42660009 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43184752 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 765570 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.693534 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6090993 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 766079 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.950868 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26716185250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.693534 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995495 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995495 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7662265 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7662265 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6090993 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6090993 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6090993 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6090993 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6090993 # number of overall hits -system.cpu0.icache.overall_hits::total 6090993 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 805033 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 805033 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 805033 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 805033 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 805033 # number of overall misses -system.cpu0.icache.overall_misses::total 805033 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11432598915 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11432598915 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11432598915 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11432598915 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11432598915 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11432598915 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6896026 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6896026 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6896026 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6896026 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6896026 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6896026 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116739 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.116739 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116739 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.116739 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116739 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.116739 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14201.404060 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14201.404060 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14201.404060 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14201.404060 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14201.404060 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14201.404060 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4227 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 138 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.630435 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.tags.replacements 901902 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.676111 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6573395 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 902414 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.284234 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26905725250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.676111 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995461 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995461 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8421597 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8421597 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6573395 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6573395 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6573395 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6573395 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6573395 # number of overall hits +system.cpu0.icache.overall_hits::total 6573395 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 945623 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 945623 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 945623 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 945623 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 945623 # number of overall misses +system.cpu0.icache.overall_misses::total 945623 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13224491137 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13224491137 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13224491137 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13224491137 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13224491137 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13224491137 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7519018 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7519018 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7519018 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7519018 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7519018 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7519018 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125764 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.125764 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125764 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.125764 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125764 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.125764 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13984.950807 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13984.950807 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13984.950807 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13984.950807 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13984.950807 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13984.950807 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3461 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 139 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 144 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.034722 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 139 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 38794 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 38794 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 38794 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 38794 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 38794 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 38794 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 766239 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 766239 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 766239 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 766239 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 766239 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 766239 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9400829636 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9400829636 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9400829636 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9400829636 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9400829636 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9400829636 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111113 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.111113 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111113 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.111113 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12268.795553 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12268.795553 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12268.795553 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12268.795553 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43044 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43044 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43044 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43044 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43044 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43044 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 902579 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 902579 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 902579 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 902579 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 902579 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 902579 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10909532635 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10909532635 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10909532635 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10909532635 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10909532635 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10909532635 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.120039 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.120039 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.120039 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.120039 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.120039 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.120039 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12087.066766 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12087.066766 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12087.066766 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12087.066766 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12087.066766 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12087.066766 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1099493 # number of replacements -system.cpu0.dcache.tags.tagsinuse 471.490981 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9327298 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1100005 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.479323 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 25754000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.490981 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920881 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.920881 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 1164537 # number of replacements +system.cpu0.dcache.tags.tagsinuse 498.695388 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10555909 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1165049 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.060485 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 26173000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.695388 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.974014 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.974014 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50559091 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50559091 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5751167 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5751167 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3244504 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3244504 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151160 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 151160 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 174499 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 174499 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8995671 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8995671 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8995671 # number of overall hits -system.cpu0.dcache.overall_hits::total 8995671 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1359261 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1359261 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1665675 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1665675 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 17016 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 17016 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 764 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 764 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3024936 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3024936 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3024936 # number of overall misses -system.cpu0.dcache.overall_misses::total 3024936 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36687958870 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 36687958870 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74828467074 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 74828467074 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 254575245 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 254575245 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4747557 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4747557 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 111516425944 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 111516425944 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 111516425944 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 111516425944 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7110428 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7110428 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4910179 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4910179 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 168176 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 168176 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 175263 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 175263 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12020607 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12020607 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12020607 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12020607 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.191164 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.191164 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.339229 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.339229 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.101180 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.101180 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004359 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004359 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.251646 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.251646 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.251646 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.251646 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26991.106837 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26991.106837 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44923.809911 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44923.809911 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14960.933533 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14960.933533 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6214.079843 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6214.079843 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36865.714165 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36865.714165 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36865.714165 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36865.714165 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 2890749 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 819 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 46898 # number of cycles access was blocked +system.cpu0.dcache.tags.tag_accesses 56283368 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56283368 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6422745 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6422745 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3752316 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3752316 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172180 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 172180 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 196241 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 196241 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10175061 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10175061 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10175061 # number of overall hits +system.cpu0.dcache.overall_hits::total 10175061 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1468970 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1468970 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1742020 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1742020 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20433 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20433 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2875 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2875 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3210990 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3210990 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3210990 # number of overall misses +system.cpu0.dcache.overall_misses::total 3210990 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 38326965830 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 38326965830 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76755016444 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 76755016444 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 286872989 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 286872989 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20380878 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 20380878 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 115081982274 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 115081982274 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 115081982274 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 115081982274 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7891715 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7891715 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5494336 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5494336 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 192613 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 192613 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 199116 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 199116 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13386051 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13386051 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13386051 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13386051 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186141 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.186141 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.317057 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.317057 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.106083 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.106083 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.014439 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.014439 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239876 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.239876 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239876 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.239876 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26091.047353 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 26091.047353 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44060.927225 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44060.927225 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14039.690158 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14039.690158 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7089.001043 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7089.001043 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35840.031353 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35840.031353 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35840.031353 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35840.031353 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 2903843 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 789 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 48428 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 61.639068 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 117 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 59.962067 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 112.714286 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 594718 # number of writebacks -system.cpu0.dcache.writebacks::total 594718 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 521771 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 521771 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1409219 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1409219 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4206 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4206 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1930990 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1930990 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1930990 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1930990 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 837490 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 837490 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256456 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 256456 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12810 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12810 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 764 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 764 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1093946 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1093946 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1093946 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1093946 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24898598196 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24898598196 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10973118276 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10973118276 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 152117754 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 152117754 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3219443 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3219443 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35871716472 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 35871716472 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35871716472 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 35871716472 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 993486001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 993486001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1673832998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1673832998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2667318999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2667318999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117783 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117783 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.052229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.052229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.076170 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.076170 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004359 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004359 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091006 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.091006 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091006 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.091006 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29730.024473 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29730.024473 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42787.527981 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42787.527981 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11874.922248 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11874.922248 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4213.930628 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4213.930628 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32791.121748 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32791.121748 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32791.121748 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32791.121748 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 644423 # number of writebacks +system.cpu0.dcache.writebacks::total 644423 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 578811 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 578811 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1469624 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1469624 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4269 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4269 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2048435 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2048435 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2048435 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2048435 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 890159 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 890159 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272396 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 272396 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16164 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16164 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2875 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2875 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1162555 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1162555 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1162555 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1162555 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25660783347 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25660783347 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11256320137 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11256320137 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 175450760 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 175450760 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14630122 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14630122 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 36917103484 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 36917103484 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 36917103484 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 36917103484 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 999097000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 999097000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1765340999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1765340999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2764437999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2764437999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.112797 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.112797 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049578 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049578 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.083920 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.083920 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.014439 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.014439 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086848 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.086848 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086848 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.086848 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28827.190813 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28827.190813 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41323.367953 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41323.367953 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10854.414749 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10854.414749 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5088.738087 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5088.738087 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31755.145764 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31755.145764 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31755.145764 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31755.145764 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1543,35 +1457,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 3875512 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3181518 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 119538 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2413999 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1363069 # Number of BTB hits +system.cpu1.branchPred.lookups 2770041 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2267711 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 80921 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1482926 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 969002 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 56.465185 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 281270 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 11131 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 65.343921 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 198874 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 6522 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2756439 # DTB read hits -system.cpu1.dtb.read_misses 11971 # DTB read misses +system.cpu1.dtb.read_hits 2016743 # DTB read hits +system.cpu1.dtb.read_misses 9789 # DTB read misses system.cpu1.dtb.read_acv 6 # DTB read access violations -system.cpu1.dtb.read_accesses 281635 # DTB read accesses -system.cpu1.dtb.write_hits 1697476 # DTB write hits -system.cpu1.dtb.write_misses 2261 # DTB write misses -system.cpu1.dtb.write_acv 35 # DTB write access violations -system.cpu1.dtb.write_accesses 106637 # DTB write accesses -system.cpu1.dtb.data_hits 4453915 # DTB hits -system.cpu1.dtb.data_misses 14232 # DTB misses -system.cpu1.dtb.data_acv 41 # DTB access violations -system.cpu1.dtb.data_accesses 388272 # DTB accesses -system.cpu1.itb.fetch_hits 435796 # ITB hits -system.cpu1.itb.fetch_misses 5916 # ITB misses -system.cpu1.itb.fetch_acv 132 # ITB acv -system.cpu1.itb.fetch_accesses 441712 # ITB accesses +system.cpu1.dtb.read_accesses 278621 # DTB read accesses +system.cpu1.dtb.write_hits 1132288 # DTB write hits +system.cpu1.dtb.write_misses 1938 # DTB write misses +system.cpu1.dtb.write_acv 37 # DTB write access violations +system.cpu1.dtb.write_accesses 105909 # DTB write accesses +system.cpu1.dtb.data_hits 3149031 # DTB hits +system.cpu1.dtb.data_misses 11727 # DTB misses +system.cpu1.dtb.data_acv 43 # DTB access violations +system.cpu1.dtb.data_accesses 384530 # DTB accesses +system.cpu1.itb.fetch_hits 369710 # ITB hits +system.cpu1.itb.fetch_misses 5636 # ITB misses +system.cpu1.itb.fetch_acv 119 # ITB acv +system.cpu1.itb.fetch_accesses 375346 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1584,520 +1498,519 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 25703316 # number of cpu cycles simulated +system.cpu1.numCycles 18798992 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8513027 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 18550498 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3875512 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1644339 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 3370867 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 594419 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 10509044 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 24053 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 56236 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 158916 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 118 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 2181303 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 77306 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 23021613 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.805786 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.167146 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 5357256 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13511342 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 2770041 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1167876 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 2476292 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 427198 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 8263333 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 26082 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 54640 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 162618 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1630522 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 50477 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 16624070 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.812758 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.170685 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 19650746 85.36% 85.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 192109 0.83% 86.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 424155 1.84% 88.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 258878 1.12% 89.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 512227 2.22% 91.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 176251 0.77% 92.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 202668 0.88% 93.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 249358 1.08% 94.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1355221 5.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 14147778 85.10% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 131100 0.79% 85.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 332329 2.00% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 198517 1.19% 89.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 395957 2.38% 91.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 132924 0.80% 92.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 159356 0.96% 93.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 93423 0.56% 93.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1032686 6.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 23021613 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.150779 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.721716 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 8599650 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 10723354 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 3129491 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 191921 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 377196 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 176309 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 12258 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 18185515 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 36387 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 377196 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 8917984 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3106321 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6595327 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2921217 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1103566 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 17011608 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 230 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 267059 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 236234 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 11254383 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 20310939 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 20246817 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58360 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 9542826 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1711557 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 544600 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 54677 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 3272980 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2918733 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1792509 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 312208 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 170960 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 14943030 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 650638 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 14484391 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 37394 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2166782 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1088105 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 467114 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 23021613 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.629165 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.310842 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 16624070 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.147351 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.718727 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5556172 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8353280 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2307081 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 131115 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 276421 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 130911 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7501 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 13245951 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 18855 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 276421 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5775463 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2664230 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 4961239 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2147700 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 799015 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 12421307 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 241 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 220838 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 145988 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 8355946 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 15113763 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 15073339 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 35607 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 7070748 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1285198 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 385003 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 30758 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2314294 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2123178 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1208247 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 244787 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 150121 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 10996175 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 428151 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 10636944 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 28046 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1617836 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 831016 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 312637 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 16624070 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.639852 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.326685 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 16750827 72.76% 72.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2784830 12.10% 84.86% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1224236 5.32% 90.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 874900 3.80% 93.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 759442 3.30% 97.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 313710 1.36% 98.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 192948 0.84% 99.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 103377 0.45% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 17343 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 12087523 72.71% 72.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1967089 11.83% 84.54% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 877391 5.28% 89.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 655455 3.94% 93.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 567827 3.42% 97.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 232884 1.40% 98.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 149324 0.90% 99.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 75580 0.45% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 10997 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 23021613 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 16624070 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 19111 7.55% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 7.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 130840 51.68% 59.23% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 103199 40.77% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 16676 8.84% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 99378 52.65% 61.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 72683 38.51% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 9521262 65.73% 65.76% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 23052 0.16% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.92% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11116 0.08% 65.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2876494 19.86% 85.87% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1724250 11.90% 97.77% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 322940 2.23% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7118581 66.92% 66.96% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 18880 0.18% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 9739 0.09% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2093745 19.68% 86.93% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1155572 10.86% 97.79% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 235150 2.21% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 14484391 # Type of FU issued -system.cpu1.iq.rate 0.563522 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 253150 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.017477 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 52052620 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 17652734 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 14115090 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 228319 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 110924 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 107745 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 14614655 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 119368 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 134347 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 10636944 # Type of FU issued +system.cpu1.iq.rate 0.565825 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 188737 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.017744 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 37986289 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 12982235 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 10383881 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 128452 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 62754 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 61527 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 10755461 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 66702 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 101929 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 418294 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 981 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 3304 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 169372 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 306426 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 815 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 2923 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 138344 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 5236 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 20861 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 4845 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 18286 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 377196 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2407064 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 140680 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 16469424 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 189598 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2918733 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1792509 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 583051 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 52184 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2431 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 3304 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 57543 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 133828 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 191371 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 14348807 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2776029 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 135584 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 276421 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2089253 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 85247 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 12015910 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 137996 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2123178 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1208247 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 388932 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 10076 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1666 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 2923 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 39900 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 91880 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 131780 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 10541126 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2031671 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 95818 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 875756 # number of nop insts executed -system.cpu1.iew.exec_refs 4481633 # number of memory reference insts executed -system.cpu1.iew.exec_branches 2254475 # Number of branches executed -system.cpu1.iew.exec_stores 1705604 # Number of stores executed -system.cpu1.iew.exec_rate 0.558247 # Inst execution rate -system.cpu1.iew.wb_sent 14259530 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 14222835 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 6903248 # num instructions producing a value -system.cpu1.iew.wb_consumers 9726426 # num instructions consuming a value +system.cpu1.iew.exec_nop 591584 # number of nop insts executed +system.cpu1.iew.exec_refs 3170643 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1658996 # Number of branches executed +system.cpu1.iew.exec_stores 1138972 # Number of stores executed +system.cpu1.iew.exec_rate 0.560728 # Inst execution rate +system.cpu1.iew.wb_sent 10475567 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 10445408 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5214693 # num instructions producing a value +system.cpu1.iew.wb_consumers 7314185 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.553346 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.709741 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.555637 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.712956 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 2312839 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 183524 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 178531 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 22644417 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.622505 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.551942 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1685534 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 115514 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 123376 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 16347649 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.627728 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.542862 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 17386197 76.78% 76.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2263939 10.00% 86.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1130304 4.99% 91.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 578693 2.56% 94.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 365284 1.61% 95.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 174241 0.77% 96.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 166825 0.74% 97.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 129123 0.57% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 449811 1.99% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 12457643 76.20% 76.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1697144 10.38% 86.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 844179 5.16% 91.75% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 419187 2.56% 94.31% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 268727 1.64% 95.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 133453 0.82% 96.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 126834 0.78% 97.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 88227 0.54% 98.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 312255 1.91% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 22644417 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 14096266 # Number of instructions committed -system.cpu1.commit.committedOps 14096266 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 16347649 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 10261869 # Number of instructions committed +system.cpu1.commit.committedOps 10261869 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 4123576 # Number of memory references committed -system.cpu1.commit.loads 2500439 # Number of loads committed -system.cpu1.commit.membars 61456 # Number of memory barriers committed -system.cpu1.commit.branches 2105755 # Number of branches committed -system.cpu1.commit.fp_insts 106451 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 13014804 # Number of committed integer instructions. -system.cpu1.commit.function_calls 225813 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 449811 # number cycles where commit BW limit reached +system.cpu1.commit.refs 2886655 # Number of memory references committed +system.cpu1.commit.loads 1816752 # Number of loads committed +system.cpu1.commit.membars 36648 # Number of memory barriers committed +system.cpu1.commit.branches 1542101 # Number of branches committed +system.cpu1.commit.fp_insts 60269 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 9518406 # Number of committed integer instructions. +system.cpu1.commit.function_calls 159983 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 312255 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 38521772 # The number of ROB reads -system.cpu1.rob.rob_writes 33194220 # The number of ROB writes -system.cpu1.timesIdled 266846 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2681703 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3780938744 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 13322175 # Number of Instructions Simulated -system.cpu1.committedOps 13322175 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 13322175 # Number of Instructions Simulated -system.cpu1.cpi 1.929363 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.929363 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.518306 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.518306 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 18552962 # number of integer regfile reads -system.cpu1.int_regfile_writes 10191479 # number of integer regfile writes -system.cpu1.fp_regfile_reads 58039 # number of floating regfile reads -system.cpu1.fp_regfile_writes 58174 # number of floating regfile writes -system.cpu1.misc_regfile_reads 1024653 # number of misc regfile reads -system.cpu1.misc_regfile_writes 265032 # number of misc regfile writes -system.cpu1.icache.tags.replacements 316719 # number of replacements -system.cpu1.icache.tags.tagsinuse 504.225697 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1849767 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 317231 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.830978 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 49140510500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.225697 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.984816 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.984816 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 27899142 # The number of ROB reads +system.cpu1.rob.rob_writes 24169847 # The number of ROB writes +system.cpu1.timesIdled 181051 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2174922 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3790987217 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9739356 # Number of Instructions Simulated +system.cpu1.committedOps 9739356 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 9739356 # Number of Instructions Simulated +system.cpu1.cpi 1.930209 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.930209 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.518079 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.518079 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 13792462 # number of integer regfile reads +system.cpu1.int_regfile_writes 7586165 # number of integer regfile writes +system.cpu1.fp_regfile_reads 35303 # number of floating regfile reads +system.cpu1.fp_regfile_writes 34737 # number of floating regfile writes +system.cpu1.misc_regfile_reads 829246 # number of misc regfile reads +system.cpu1.misc_regfile_writes 174995 # number of misc regfile writes +system.cpu1.icache.tags.replacements 184023 # number of replacements +system.cpu1.icache.tags.tagsinuse 502.144736 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1436916 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 184535 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 7.786685 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1712232500000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 502.144736 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980751 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.980751 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 420 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2498600 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2498600 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1849767 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1849767 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1849767 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1849767 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1849767 # number of overall hits -system.cpu1.icache.overall_hits::total 1849767 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 331536 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 331536 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 331536 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 331536 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 331536 # number of overall misses -system.cpu1.icache.overall_misses::total 331536 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4647513106 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4647513106 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4647513106 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4647513106 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4647513106 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4647513106 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 2181303 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2181303 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 2181303 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2181303 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 2181303 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2181303 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.151990 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.151990 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.151990 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.151990 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.151990 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.151990 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14018.125048 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14018.125048 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14018.125048 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14018.125048 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14018.125048 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14018.125048 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1365 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 1815116 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1815116 # 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number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2794361223 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2794361223 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2794361223 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2794361223 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2794361223 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1630522 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1630522 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1630522 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1630522 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1630522 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1630522 # 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average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14433.236692 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1663 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 71 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 63 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 19.225352 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 26.396825 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 14239 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 14239 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 14239 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 14239 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 14239 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 14239 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 317297 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 317297 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 317297 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 317297 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 317297 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 317297 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3842042413 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3842042413 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3842042413 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3842042413 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3842042413 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3842042413 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.145462 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.145462 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.145462 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.145462 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12108.662903 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12108.662903 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12108.662903 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12108.662903 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9012 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 9012 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 9012 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 9012 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 9012 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 9012 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 184594 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 184594 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 184594 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 184594 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 184594 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 184594 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2304763360 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2304763360 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2304763360 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2304763360 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2304763360 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2304763360 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.113212 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.113212 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.113212 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.113212 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.113212 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.113212 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12485.581113 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12485.581113 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12485.581113 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12485.581113 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12485.581113 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12485.581113 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 323504 # number of replacements -system.cpu1.dcache.tags.tagsinuse 495.920224 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3389718 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 323845 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 10.467100 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 42037852500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 495.920224 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968594 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.968594 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.666016 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 17217310 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 17217310 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2089496 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2089496 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1222054 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1222054 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 41428 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 41428 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 44398 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 44398 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3311550 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3311550 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3311550 # number of overall hits -system.cpu1.dcache.overall_hits::total 3311550 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 467553 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 467553 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 348721 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 348721 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 7730 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 7730 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 782 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 782 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 816274 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 816274 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 816274 # number of overall misses -system.cpu1.dcache.overall_misses::total 816274 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7286969700 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 7286969700 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 13547153677 # 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number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1570775 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1570775 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 49158 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 49158 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 45180 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 45180 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4127824 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4127824 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4127824 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4127824 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.182849 # 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Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 12059624 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 12059624 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1586410 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1586410 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 857564 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 857564 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 22125 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 22125 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 21120 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 21120 # 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number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 467030 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 467030 # number of overall misses +system.cpu1.dcache.overall_misses::total 467030 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4578373047 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4578373047 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10436073649 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 10436073649 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 56388497 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 56388497 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 20553927 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 20553927 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15014446696 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15014446696 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15014446696 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15014446696 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1872141 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1872141 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1038863 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1038863 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 26609 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 26609 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 23862 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 23862 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2911004 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2911004 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2911004 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2911004 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.152623 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.152623 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.174517 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.174517 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.168514 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.168514 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.114911 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.114911 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.160436 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.160436 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.160436 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.160436 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16023.368297 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16023.368297 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 57562.775575 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 57562.775575 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12575.489964 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12575.489964 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7495.961707 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7495.961707 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32148.784224 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 32148.784224 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32148.784224 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 32148.784224 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 370227 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 7447 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6127 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 56.862226 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 60.425494 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 245774 # number of writebacks -system.cpu1.dcache.writebacks::total 245774 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 203756 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 203756 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 288423 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 288423 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1420 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1420 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 492179 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 492179 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 492179 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 492179 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 263797 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 263797 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 60298 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 60298 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 6310 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 6310 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 781 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 781 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 324095 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 324095 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 324095 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 324095 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3377520942 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3377520942 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2032860866 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2032860866 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70443003 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70443003 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4174394 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4174394 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5410381808 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5410381808 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5410381808 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5410381808 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 489946000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 489946000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 936242002 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 936242002 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1426188002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1426188002 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.103165 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.103165 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038387 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038387 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128362 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128362 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.017286 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.017286 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.078515 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.078515 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.078515 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.078515 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12803.485036 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12803.485036 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33713.570367 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33713.570367 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11163.708875 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11163.708875 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5344.934699 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5344.934699 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16693.814493 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16693.814493 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16693.814493 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16693.814493 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 162776 # number of writebacks +system.cpu1.dcache.writebacks::total 162776 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 104604 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 104604 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 148843 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 148843 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 899 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 899 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 253447 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 253447 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 253447 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 253447 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 181127 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 181127 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 32456 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 32456 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 3585 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 3585 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2742 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2742 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 213583 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 213583 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 213583 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 213583 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2418933900 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2418933900 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1545787184 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1545787184 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 26756251 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 26756251 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 15069073 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 15069073 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3964721084 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3964721084 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3964721084 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3964721084 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 485705000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 485705000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 998872003 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 998872003 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1484577003 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1484577003 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.096749 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.096749 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.031242 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.031242 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.134729 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.134729 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.114911 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.114911 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.073371 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.073371 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.073371 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.073371 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13354.905122 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13354.905122 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47627.162435 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 47627.162435 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7463.389400 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7463.389400 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5495.650255 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5495.650255 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18562.905681 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18562.905681 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18562.905681 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18562.905681 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2106,161 +2019,161 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4836 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 166329 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 57049 39.81% 39.81% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 39.90% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.34% 41.24% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 41.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 84196 58.75% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 143316 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56102 49.10% 49.10% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.22% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.68% 50.90% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.01% 50.91% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 56086 49.09% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114259 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1865433154000 98.01% 98.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 62620000 0.00% 98.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 558222500 0.03% 98.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8649500 0.00% 98.04% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 37274722500 1.96% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1903337368500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983400 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 5026 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 189626 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 66604 40.25% 40.25% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 133 0.08% 40.33% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1926 1.16% 41.49% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 191 0.12% 41.61% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 96634 58.39% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 165488 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 65244 49.22% 49.22% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 133 0.10% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1926 1.45% 50.78% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 191 0.14% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 65055 49.08% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 132549 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1865394285500 97.91% 97.91% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63356500 0.00% 97.91% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 573165000 0.03% 97.94% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 85999500 0.00% 97.95% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 39121861000 2.05% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1905238667500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.979581 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.666136 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.797252 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.67% 28.44% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.44% 28.89% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.00% 32.89% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.44% 37.33% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.67% 40.00% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.44% 40.44% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.33% 41.78% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.11% 44.89% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.89% 45.78% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.00% 61.78% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.33% 63.11% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.44% 67.56% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.44% 72.00% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.44% 72.44% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.67% 75.11% # number of syscalls executed -system.cpu0.kern.syscall::71 25 11.11% 86.22% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.33% 87.56% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.67% 90.22% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.44% 90.67% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.33% 92.00% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.00% 96.00% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.89% 96.89% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.89% 97.78% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.44% 98.22% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.89% 99.11% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 225 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.673210 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.800958 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.22% 28.02% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.45% # number of syscalls executed +system.cpu0.kern.syscall::17 9 3.88% 32.33% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.31% 36.64% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.59% 39.22% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.66% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.29% 40.95% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.02% 43.97% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.86% 44.83% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.81% 61.64% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.29% 62.93% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.31% 67.24% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.31% 71.55% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 71.98% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.59% 74.57% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.64% 86.21% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.29% 87.50% # number of syscalls executed +system.cpu0.kern.syscall::74 7 3.02% 90.52% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 90.95% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.29% 92.24% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.88% 96.12% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.86% 96.98% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.86% 97.84% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.28% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.86% 99.14% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 232 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 104 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3010 1.99% 2.06% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.09% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.10% # number of callpals executed -system.cpu0.kern.callpal::swpipl 136886 90.50% 92.60% # number of callpals executed -system.cpu0.kern.callpal::rdps 6293 4.16% 96.76% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.77% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.77% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.77% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed -system.cpu0.kern.callpal::rti 4358 2.88% 99.66% # number of callpals executed -system.cpu0.kern.callpal::callsys 382 0.25% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 151247 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6436 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1343 # number of protection mode switches +system.cpu0.kern.callpal::wripir 273 0.16% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3846 2.21% 2.37% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.39% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.40% # number of callpals executed +system.cpu0.kern.callpal::swpipl 158278 90.80% 93.20% # number of callpals executed +system.cpu0.kern.callpal::rdps 6346 3.64% 96.84% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.84% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.84% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.85% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.85% # number of callpals executed +system.cpu0.kern.callpal::rti 4961 2.85% 99.70% # number of callpals executed +system.cpu0.kern.callpal::callsys 391 0.22% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 174309 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7462 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1354 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1342 -system.cpu0.kern.mode_good::user 1343 +system.cpu0.kern.mode_good::kernel 1353 +system.cpu0.kern.mode_good::user 1354 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.208515 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.181319 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.345160 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1901289587500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2047773000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.307055 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1903211741000 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2026918500 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3011 # number of times the context was actually changed +system.cpu0.kern.swap_context 3847 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3850 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 71149 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 24567 38.92% 38.92% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1923 3.05% 41.97% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 104 0.16% 42.13% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 36529 57.87% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 63123 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 24137 48.08% 48.08% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1923 3.83% 51.92% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 104 0.21% 52.12% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 24033 47.88% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 50197 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1869107624500 98.20% 98.20% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 533184500 0.03% 98.23% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 48972500 0.00% 98.23% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 33633158500 1.77% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1903322940000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.982497 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3999 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 49848 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 15658 37.06% 37.06% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 4.55% 41.62% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 273 0.65% 42.26% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 24392 57.74% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 42247 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 15641 47.10% 47.10% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 5.79% 52.90% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 273 0.82% 53.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 15369 46.28% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 33207 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1871713408000 98.26% 98.26% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533048500 0.03% 98.29% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 128777500 0.01% 98.29% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 32519855000 1.71% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1904895089000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998914 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.657916 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.795225 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed -system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.94% 26.73% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.97% 29.70% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.97% 32.67% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.96% 36.63% # number of syscalls executed -system.cpu1.kern.syscall::45 18 17.82% 54.46% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.97% 57.43% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.99% 58.42% # number of syscalls executed -system.cpu1.kern.syscall::71 29 28.71% 87.13% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.90% 97.03% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 101 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.630084 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.786020 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed +system.cpu1.kern.syscall::17 6 6.38% 27.66% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.19% 30.85% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.19% 34.04% # number of syscalls executed +system.cpu1.kern.syscall::33 4 4.26% 38.30% # number of syscalls executed +system.cpu1.kern.syscall::45 15 15.96% 54.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.19% 57.45% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.06% 58.51% # number of syscalls executed +system.cpu1.kern.syscall::71 27 28.72% 87.23% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.57% 96.81% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 94 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1228 1.89% 1.92% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 1.92% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 1.93% # number of callpals executed -system.cpu1.kern.callpal::swpipl 58251 89.62% 91.55% # number of callpals executed -system.cpu1.kern.callpal::rdps 2464 3.79% 95.34% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 95.34% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 95.35% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 95.35% # number of callpals executed -system.cpu1.kern.callpal::rti 2844 4.38% 99.73% # number of callpals executed -system.cpu1.kern.callpal::callsys 133 0.20% 99.93% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 191 0.44% 0.44% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.44% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.45% # number of callpals executed +system.cpu1.kern.callpal::swpctx 742 1.70% 2.15% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 2.15% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 2.17% # number of callpals executed +system.cpu1.kern.callpal::swpipl 37463 85.96% 88.13% # number of callpals executed +system.cpu1.kern.callpal::rdps 2409 5.53% 93.66% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.66% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.67% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.68% # number of callpals executed +system.cpu1.kern.callpal::rti 2587 5.94% 99.62% # number of callpals executed +system.cpu1.kern.callpal::callsys 124 0.28% 99.90% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.10% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 65000 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1608 # number of protection mode switches -system.cpu1.kern.mode_switch::user 397 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2054 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 463 -system.cpu1.kern.mode_good::user 397 -system.cpu1.kern.mode_good::idle 66 -system.cpu1.kern.mode_switch_good::kernel 0.287935 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 43580 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 937 # number of protection mode switches +system.cpu1.kern.mode_switch::user 383 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2395 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 617 +system.cpu1.kern.mode_good::user 383 +system.cpu1.kern.mode_good::idle 234 +system.cpu1.kern.mode_switch_good::kernel 0.658485 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.032132 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.228135 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 38501499500 2.02% 2.02% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 724848000 0.04% 2.06% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1863406690000 97.94% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1229 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.097704 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.332167 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 34875641000 1.83% 1.83% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 708299500 0.04% 1.87% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1868990228500 98.13% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 743 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 674a7dfd5..0b1609ec3 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,128 +1,128 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.860198 # Number of seconds simulated -sim_ticks 1860197780500 # Number of ticks simulated -final_tick 1860197780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.860192 # Number of seconds simulated +sim_ticks 1860191785500 # Number of ticks simulated +final_tick 1860191785500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 153122 # Simulator instruction rate (inst/s) -host_op_rate 153122 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5376333902 # Simulator tick rate (ticks/s) -host_mem_usage 310876 # Number of bytes of host memory used -host_seconds 346.00 # Real time elapsed on the host -sim_insts 52979882 # Number of instructions simulated -sim_ops 52979882 # Number of ops (including micro ops) simulated +host_inst_rate 128947 # Simulator instruction rate (inst/s) +host_op_rate 128947 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4527634915 # Simulator tick rate (ticks/s) +host_mem_usage 347764 # Number of bytes of host memory used +host_seconds 410.85 # Real time elapsed on the host +sim_insts 52978349 # Number of instructions simulated +sim_ops 52978349 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24878976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 963264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24877248 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28495232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7515456 # Number of bytes written to this memory -system.physmem.bytes_written::total 7515456 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388734 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28492800 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 963264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 963264 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7515392 # Number of bytes written to this memory +system.physmem.bytes_written::total 7515392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15051 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388707 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445238 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117429 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117429 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 518207 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13374371 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1425810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15318388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 518207 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518207 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4040138 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4040138 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4040138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 518207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13374371 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1425810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19358526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445238 # Number of read requests accepted -system.physmem.writeReqs 117429 # Number of write requests accepted -system.physmem.readBursts 445238 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117429 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28492032 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3200 # Total number of bytes read from write queue -system.physmem.bytesWritten 7514752 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28495232 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7515456 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 445200 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117428 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117428 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 517830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13373486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1425814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15317130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 517830 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517830 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4040117 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4040117 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4040117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 517830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13373486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1425814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19357247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445200 # Number of read requests accepted +system.physmem.writeReqs 117428 # Number of write requests accepted +system.physmem.readBursts 445200 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117428 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28485504 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue +system.physmem.bytesWritten 7513728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28492800 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7515392 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 179 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28229 # Per bank write bursts -system.physmem.perBankRdBursts::1 27970 # Per bank write bursts -system.physmem.perBankRdBursts::2 28433 # Per bank write bursts -system.physmem.perBankRdBursts::3 28029 # Per bank write bursts -system.physmem.perBankRdBursts::4 27802 # Per bank write bursts -system.physmem.perBankRdBursts::5 27222 # Per bank write bursts -system.physmem.perBankRdBursts::6 27248 # Per bank write bursts -system.physmem.perBankRdBursts::7 27296 # Per bank write bursts -system.physmem.perBankRdBursts::8 27665 # Per bank write bursts -system.physmem.perBankRdBursts::9 27395 # Per bank write bursts -system.physmem.perBankRdBursts::10 27922 # Per bank write bursts -system.physmem.perBankRdBursts::11 27539 # Per bank write bursts -system.physmem.perBankRdBursts::12 27561 # Per bank write bursts -system.physmem.perBankRdBursts::13 28227 # Per bank write bursts -system.physmem.perBankRdBursts::14 28327 # Per bank write bursts -system.physmem.perBankRdBursts::15 28323 # Per bank write bursts -system.physmem.perBankWrBursts::0 7932 # Per bank write bursts -system.physmem.perBankWrBursts::1 7497 # Per bank write bursts -system.physmem.perBankWrBursts::2 7944 # Per bank write bursts -system.physmem.perBankWrBursts::3 7517 # Per bank write bursts -system.physmem.perBankWrBursts::4 7343 # Per bank write bursts -system.physmem.perBankWrBursts::5 6680 # Per bank write bursts -system.physmem.perBankWrBursts::6 6761 # Per bank write bursts -system.physmem.perBankWrBursts::7 6683 # Per bank write bursts -system.physmem.perBankWrBursts::8 7104 # Per bank write bursts -system.physmem.perBankWrBursts::9 6801 # Per bank write bursts -system.physmem.perBankWrBursts::10 7313 # Per bank write bursts -system.physmem.perBankWrBursts::11 6981 # Per bank write bursts -system.physmem.perBankWrBursts::12 7123 # Per bank write bursts -system.physmem.perBankWrBursts::13 7875 # Per bank write bursts -system.physmem.perBankWrBursts::14 8050 # Per bank write bursts -system.physmem.perBankWrBursts::15 7814 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 178 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28210 # Per bank write bursts +system.physmem.perBankRdBursts::1 27995 # Per bank write bursts +system.physmem.perBankRdBursts::2 28357 # Per bank write bursts +system.physmem.perBankRdBursts::3 27829 # Per bank write bursts +system.physmem.perBankRdBursts::4 27761 # Per bank write bursts +system.physmem.perBankRdBursts::5 27267 # Per bank write bursts +system.physmem.perBankRdBursts::6 27371 # Per bank write bursts +system.physmem.perBankRdBursts::7 27375 # Per bank write bursts +system.physmem.perBankRdBursts::8 27696 # Per bank write bursts +system.physmem.perBankRdBursts::9 27269 # Per bank write bursts +system.physmem.perBankRdBursts::10 28017 # Per bank write bursts +system.physmem.perBankRdBursts::11 27509 # Per bank write bursts +system.physmem.perBankRdBursts::12 27546 # Per bank write bursts +system.physmem.perBankRdBursts::13 28232 # Per bank write bursts +system.physmem.perBankRdBursts::14 28342 # Per bank write bursts +system.physmem.perBankRdBursts::15 28310 # Per bank write bursts +system.physmem.perBankWrBursts::0 7920 # Per bank write bursts +system.physmem.perBankWrBursts::1 7516 # Per bank write bursts +system.physmem.perBankWrBursts::2 7873 # Per bank write bursts +system.physmem.perBankWrBursts::3 7373 # Per bank write bursts +system.physmem.perBankWrBursts::4 7309 # Per bank write bursts +system.physmem.perBankWrBursts::5 6720 # Per bank write bursts +system.physmem.perBankWrBursts::6 6881 # Per bank write bursts +system.physmem.perBankWrBursts::7 6774 # Per bank write bursts +system.physmem.perBankWrBursts::8 7136 # Per bank write bursts +system.physmem.perBankWrBursts::9 6679 # Per bank write bursts +system.physmem.perBankWrBursts::10 7411 # Per bank write bursts +system.physmem.perBankWrBursts::11 6967 # Per bank write bursts +system.physmem.perBankWrBursts::12 7107 # Per bank write bursts +system.physmem.perBankWrBursts::13 7877 # Per bank write bursts +system.physmem.perBankWrBursts::14 8064 # Per bank write bursts +system.physmem.perBankWrBursts::15 7795 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 1860192344000 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 1860186344000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 445238 # Read request sizes (log2) +system.physmem.readPktSize::6 445200 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117429 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 332275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2335 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1359 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117428 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 322906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56729 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 22897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5869 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3757 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1891 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1835 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -133,230 +133,147 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 43301 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 831.507817 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 237.255649 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1940.687281 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 14819 34.22% 34.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6274 14.49% 48.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4433 10.24% 58.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2614 6.04% 64.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1636 3.78% 68.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1435 3.31% 72.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 928 2.14% 74.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 854 1.97% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 632 1.46% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 524 1.21% 78.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 594 1.37% 80.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 623 1.44% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 284 0.66% 82.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 262 0.61% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 268 0.62% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 398 0.92% 84.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 204 0.47% 84.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 163 0.38% 85.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 93 0.21% 85.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 193 0.45% 85.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 100 0.23% 86.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 353 0.82% 87.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 186 0.43% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 655 1.51% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 89 0.21% 89.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 28 0.06% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 40 0.09% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 175 0.40% 89.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 41 0.09% 89.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 79 0.18% 90.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 86 0.20% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 82 0.19% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 104 0.24% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 73 0.17% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 16 0.04% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 102 0.24% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 26 0.06% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 14 0.03% 91.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 2 0.00% 91.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 17 0.04% 91.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 4 0.01% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 13 0.03% 91.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 25 0.06% 91.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 100 0.23% 91.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 15 0.03% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 67 0.15% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 82 0.19% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 42 0.10% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 83 0.19% 92.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 68 0.16% 92.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 12 0.03% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 94 0.22% 92.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 22 0.05% 92.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 9 0.02% 92.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 5 0.01% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 12 0.03% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 4 0.01% 92.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 11 0.03% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 22 0.05% 92.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 92 0.21% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 13 0.03% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 66 0.15% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 81 0.19% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 40 0.09% 93.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 80 0.18% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 68 0.16% 93.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 12 0.03% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 95 0.22% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 21 0.05% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 10 0.02% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.00% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 11 0.03% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 4 0.01% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 13 0.03% 94.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 21 0.05% 94.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 92 0.21% 94.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 14 0.03% 94.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 68 0.16% 94.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 81 0.19% 94.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 35 0.08% 94.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 79 0.18% 95.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 65 0.15% 95.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 12 0.03% 95.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 98 0.23% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 22 0.05% 95.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 10 0.02% 95.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 1 0.00% 95.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 12 0.03% 95.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 11 0.03% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 21 0.05% 95.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 92 0.21% 95.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 13 0.03% 95.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 64 0.15% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 81 0.19% 96.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 41 0.09% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 82 0.19% 96.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 69 0.16% 96.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 14 0.03% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 94 0.22% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 21 0.05% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 8 0.02% 97.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 12 0.03% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 2 0.00% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 10 0.02% 97.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 22 0.05% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 89 0.21% 97.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 14 0.03% 97.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 66 0.15% 97.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 80 0.18% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 307 0.71% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7363 1 0.00% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 17 0.04% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7491 2 0.00% 98.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 5 0.01% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 1 0.00% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 16 0.04% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 1 0.00% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 2 0.00% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 330 0.76% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 2 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9411 2 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9987 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11651 2 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 4 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12480-12483 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12739 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13187 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 4 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 7 0.02% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 4 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 3 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 40 0.09% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 2 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 174 0.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 43301 # Bytes accessed per row activation -system.physmem.totQLat 8362787000 # Total ticks spent queuing -system.physmem.totMemAccLat 15768695750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2225940000 # Total ticks spent in databus transfers -system.physmem.totBankLat 5179968750 # Total ticks spent accessing banks -system.physmem.avgQLat 18784.84 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11635.46 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 48603 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 651.388927 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 428.580055 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 419.495686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8350 17.18% 17.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6347 13.06% 30.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2940 6.05% 36.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1813 3.73% 40.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1501 3.09% 43.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 899 1.85% 44.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 723 1.49% 46.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 886 1.82% 48.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 25144 51.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48603 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6893 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 64.568403 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2543.170744 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 6890 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6893 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6893 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.032062 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.789521 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.768510 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 5850 84.87% 84.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 28 0.41% 85.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 70 1.02% 86.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 418 6.06% 92.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 134 1.94% 94.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 49 0.71% 95.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 24 0.35% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 22 0.32% 95.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 53 0.77% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 38 0.55% 97.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 20 0.29% 97.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 34 0.49% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 19 0.28% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 34 0.49% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 7 0.10% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 10 0.15% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.03% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.03% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 3 0.04% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 6 0.09% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 5 0.07% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 5 0.07% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 8 0.12% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 4 0.06% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 2 0.03% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 1 0.01% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 2 0.03% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 5 0.07% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 2 0.03% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 6 0.09% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 6 0.09% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 4 0.06% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 2 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 1 0.01% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 2 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 2 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54 3 0.04% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 6 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6893 # Writes before turning the bus around for reads +system.physmem.totQLat 10196532000 # Total ticks spent queuing +system.physmem.totMemAccLat 17805650750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2225430000 # Total ticks spent in databus transfers +system.physmem.totBankLat 5383688750 # Total ticks spent accessing banks +system.physmem.avgQLat 22909.13 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 12095.84 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35420.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 40004.97 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.31 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.32 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s @@ -364,61 +281,60 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.24 # Average write queue length when enqueuing -system.physmem.readRowHits 424550 # Number of row buffer hits during reads -system.physmem.writeRowHits 94755 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.69 # Row buffer hit rate for writes -system.physmem.avgGap 3306027.09 # Average gap between requests -system.physmem.pageHitRate 92.30 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.39 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19401389 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295980 # Transaction distribution -system.membus.trans_dist::ReadResp 295901 # Transaction distribution -system.membus.trans_dist::WriteReq 9598 # Transaction distribution -system.membus.trans_dist::WriteResp 9598 # Transaction distribution -system.membus.trans_dist::Writeback 117429 # Transaction distribution +system.physmem.avgRdQLen 1.54 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.57 # Average write queue length when enqueuing +system.physmem.readRowHits 402462 # Number of row buffer hits during reads +system.physmem.writeRowHits 96189 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.91 # Row buffer hit rate for writes +system.physmem.avgGap 3306245.59 # Average gap between requests +system.physmem.pageHitRate 88.65 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 19400105 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 295926 # Transaction distribution +system.membus.trans_dist::ReadResp 295846 # Transaction distribution +system.membus.trans_dist::WriteReq 9597 # Transaction distribution +system.membus.trans_dist::WriteResp 9597 # Transaction distribution +system.membus.trans_dist::Writeback 117428 # Transaction distribution system.membus.trans_dist::UpgradeReq 181 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 182 # Transaction distribution -system.membus.trans_dist::ReadExReq 156823 # Transaction distribution -system.membus.trans_dist::ReadExResp 156823 # Transaction distribution -system.membus.trans_dist::BadAddressError 79 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884143 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917357 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 181 # Transaction distribution +system.membus.trans_dist::ReadExReq 156840 # Transaction distribution +system.membus.trans_dist::ReadExResp 156840 # Transaction distribution +system.membus.trans_dist::BadAddressError 80 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884064 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917278 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042036 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701632 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30745780 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1041957 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30699136 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30743276 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36054836 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36054836 # Total data (bytes) +system.membus.tot_pkt_size::total 36052332 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36052332 # Total data (bytes) system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29837500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 29929000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1551324500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1552530249 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 96500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 100500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3763216294 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3767548549 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376313495 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376726994 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.261116 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.261130 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710341603000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.261116 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078820 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078820 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1710337661000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.261130 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078821 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078821 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -434,12 +350,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21133883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21133883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12974928560 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12974928560 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12996062443 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12996062443 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12996062443 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12996062443 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 13194182648 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 13194182648 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13215316531 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13215316531 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13215316531 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13215316531 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -458,17 +374,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122161.173410 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 122161.173410 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312257.618406 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 312257.618406 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 311469.441414 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 311469.441414 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 311469.441414 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 311469.441414 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 401483 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 317534.237774 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 317534.237774 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 316724.182888 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 316724.182888 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 316724.182888 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 316724.182888 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 393531 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 29284 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28535 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.709978 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.791169 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -484,12 +400,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12136883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10812648570 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10812648570 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10824785453 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10824785453 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10824785453 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10824785453 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 11031075660 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 11031075660 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 11043212543 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 11043212543 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 11043212543 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 11043212543 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -500,12 +416,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70155.393064 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70155.393064 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260219.690268 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 260219.690268 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259431.646567 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 259431.646567 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259431.646567 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 259431.646567 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 265476.406912 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 265476.406912 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 264666.567837 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 264666.567837 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 264666.567837 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 264666.567837 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -519,36 +435,36 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13863448 # Number of BP lookups -system.cpu.branchPred.condPredicted 11631259 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 399718 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9400932 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5821857 # Number of BTB hits +system.cpu.branchPred.lookups 13847711 # Number of BP lookups +system.cpu.branchPred.condPredicted 11622265 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 397151 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9355929 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5809145 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.928509 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 906521 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39211 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 62.090520 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 903416 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 38861 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9926517 # DTB read hits -system.cpu.dtb.read_misses 41406 # DTB read misses -system.cpu.dtb.read_acv 531 # DTB read access violations -system.cpu.dtb.read_accesses 940700 # DTB read accesses -system.cpu.dtb.write_hits 6593963 # DTB write hits -system.cpu.dtb.write_misses 10630 # DTB write misses -system.cpu.dtb.write_acv 410 # DTB write access violations -system.cpu.dtb.write_accesses 338096 # DTB write accesses -system.cpu.dtb.data_hits 16520480 # DTB hits -system.cpu.dtb.data_misses 52036 # DTB misses -system.cpu.dtb.data_acv 941 # DTB access violations -system.cpu.dtb.data_accesses 1278796 # DTB accesses -system.cpu.itb.fetch_hits 1306353 # ITB hits -system.cpu.itb.fetch_misses 36823 # ITB misses -system.cpu.itb.fetch_acv 1069 # ITB acv -system.cpu.itb.fetch_accesses 1343176 # ITB accesses +system.cpu.dtb.read_hits 9926060 # DTB read hits +system.cpu.dtb.read_misses 41229 # DTB read misses +system.cpu.dtb.read_acv 545 # DTB read access violations +system.cpu.dtb.read_accesses 943227 # DTB read accesses +system.cpu.dtb.write_hits 6592681 # DTB write hits +system.cpu.dtb.write_misses 10567 # DTB write misses +system.cpu.dtb.write_acv 408 # DTB write access violations +system.cpu.dtb.write_accesses 338977 # DTB write accesses +system.cpu.dtb.data_hits 16518741 # DTB hits +system.cpu.dtb.data_misses 51796 # DTB misses +system.cpu.dtb.data_acv 953 # DTB access violations +system.cpu.dtb.data_accesses 1282204 # DTB accesses +system.cpu.itb.fetch_hits 1307907 # ITB hits +system.cpu.itb.fetch_misses 36763 # ITB misses +system.cpu.itb.fetch_acv 1058 # ITB acv +system.cpu.itb.fetch_accesses 1344670 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -561,269 +477,269 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 121966998 # number of cpu cycles simulated +system.cpu.numCycles 122133073 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28067964 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70813073 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13863448 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6728378 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13263425 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1999195 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 38181411 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33091 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 255000 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 364206 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 297 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8556045 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 264477 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 81457086 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.869330 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.212823 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28029052 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70711644 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13847711 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6712561 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13244944 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1986135 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38034896 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 253831 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 364385 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8541461 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 263003 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 81242947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.870373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.213979 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68193661 83.72% 83.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 852857 1.05% 84.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1696439 2.08% 86.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 825181 1.01% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2758325 3.39% 91.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 561473 0.69% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 645881 0.79% 92.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1010308 1.24% 93.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4912961 6.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67998003 83.70% 83.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 851901 1.05% 84.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1695578 2.09% 86.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 822984 1.01% 87.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2755109 3.39% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 560259 0.69% 91.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 643349 0.79% 92.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1008302 1.24% 93.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4907462 6.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81457086 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.113666 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.580592 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29256938 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37863691 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12127839 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 959156 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1249461 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 584263 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42640 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69481989 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129319 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1249461 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30407522 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14148846 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20005990 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11332374 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4312891 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65679549 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 7211 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 504797 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1541440 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43855166 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79746051 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79567055 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 166544 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38180329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5674829 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682909 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 240455 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12257327 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10441163 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6908790 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1318239 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 851396 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58211664 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2050007 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56814932 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 114609 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6922962 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3587498 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1389025 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 81457086 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697483 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.359485 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 81242947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.113382 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.578972 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29204589 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37726390 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12112827 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 958015 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1241125 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 582779 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42656 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69393384 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129440 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1241125 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30348079 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14012797 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20034433 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11321379 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4285132 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65602946 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7156 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 505213 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1511728 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43797820 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79654521 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79475437 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 166633 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38179156 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5618656 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682920 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 240154 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12205182 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10434201 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6904424 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1321264 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 860087 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58162225 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2049609 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56784496 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 110090 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6876207 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3554384 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1388666 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 81242947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.698947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.361354 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56746030 69.66% 69.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10887232 13.37% 83.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5162469 6.34% 89.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3392471 4.16% 93.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2625915 3.22% 96.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1461124 1.79% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 753330 0.92% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 332031 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 96484 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56591956 69.66% 69.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10816248 13.31% 82.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5164366 6.36% 89.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3390360 4.17% 93.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2636798 3.25% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1463129 1.80% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 751413 0.92% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 332295 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 96382 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 81457086 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 81242947 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 91940 11.62% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 373423 47.20% 58.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 325849 41.18% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 91428 11.57% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 372699 47.16% 58.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 326088 41.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38737583 68.18% 68.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61738 0.11% 68.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10357242 18.23% 86.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6672763 11.74% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38710597 68.17% 68.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61705 0.11% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10355398 18.24% 86.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6671255 11.75% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949012 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56814932 # Type of FU issued -system.cpu.iq.rate 0.465822 # Inst issue rate -system.cpu.iq.fu_busy_cnt 791212 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013926 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 195300199 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66861892 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55573336 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692571 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336551 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 327871 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57237458 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361400 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 598272 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 56784496 # Type of FU issued +system.cpu.iq.rate 0.464940 # Inst issue rate +system.cpu.iq.fu_busy_cnt 790215 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013916 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 195020122 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66766340 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55549754 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692121 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 335594 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 327937 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 57205980 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361445 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 599867 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1348718 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3201 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14139 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 530806 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1342082 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3325 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14250 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 526611 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17937 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 182742 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17915 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 172386 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1249461 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10237116 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 702035 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63785040 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 690324 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10441163 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6908790 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1805677 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 512237 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17569 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14139 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 202047 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411314 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 613361 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56348369 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9996094 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 466562 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1241125 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10205447 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 698563 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63733516 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 684669 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10434201 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6904424 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1805473 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512478 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17546 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14250 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 200257 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411476 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 611733 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56321962 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9995488 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 462533 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3523369 # number of nop insts executed -system.cpu.iew.exec_refs 16615920 # number of memory reference insts executed -system.cpu.iew.exec_branches 8927027 # Number of branches executed -system.cpu.iew.exec_stores 6619826 # Number of stores executed -system.cpu.iew.exec_rate 0.461997 # Inst execution rate -system.cpu.iew.wb_sent 56016387 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55901207 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27709617 # num instructions producing a value -system.cpu.iew.wb_consumers 37531222 # num instructions consuming a value +system.cpu.iew.exec_nop 3521682 # number of nop insts executed +system.cpu.iew.exec_refs 16613940 # number of memory reference insts executed +system.cpu.iew.exec_branches 8922207 # Number of branches executed +system.cpu.iew.exec_stores 6618452 # Number of stores executed +system.cpu.iew.exec_rate 0.461152 # Inst execution rate +system.cpu.iew.wb_sent 55993079 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55877691 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27722224 # num instructions producing a value +system.cpu.iew.wb_consumers 37565081 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.458331 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738308 # average fanout of values written-back +system.cpu.iew.wb_rate 0.457515 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.737979 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7496348 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660982 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 568504 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 80207625 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.700316 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.629380 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7447390 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660943 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 565908 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 80001822 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.702098 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.631989 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 59390670 74.05% 74.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8659340 10.80% 84.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4620197 5.76% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2517886 3.14% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1507376 1.88% 95.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 612052 0.76% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 525608 0.66% 97.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 522089 0.65% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1852407 2.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59240837 74.05% 74.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8588333 10.74% 84.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4609463 5.76% 90.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2533581 3.17% 93.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1517845 1.90% 95.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 611107 0.76% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 522353 0.65% 97.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 526375 0.66% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1851928 2.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 80207625 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56170683 # Number of instructions committed -system.cpu.commit.committedOps 56170683 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 80001822 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56169084 # Number of instructions committed +system.cpu.commit.committedOps 56169084 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470429 # Number of memory references committed -system.cpu.commit.loads 9092445 # Number of loads committed -system.cpu.commit.membars 226358 # Number of memory barriers committed -system.cpu.commit.branches 8439899 # Number of branches committed +system.cpu.commit.refs 15469932 # Number of memory references committed +system.cpu.commit.loads 9092119 # Number of loads committed +system.cpu.commit.membars 226344 # Number of memory barriers committed +system.cpu.commit.branches 8439731 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52020266 # Number of committed integer instructions. -system.cpu.commit.function_calls 740581 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1852407 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52018783 # Number of committed integer instructions. +system.cpu.commit.function_calls 740550 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1851928 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 141772543 # The number of ROB reads -system.cpu.rob.rob_writes 128585215 # The number of ROB writes -system.cpu.timesIdled 1193212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 40509912 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598422122 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52979882 # Number of Instructions Simulated -system.cpu.committedOps 52979882 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52979882 # Number of Instructions Simulated -system.cpu.cpi 2.302138 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.302138 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434379 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434379 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73881277 # number of integer regfile reads -system.cpu.int_regfile_writes 40316653 # number of integer regfile writes -system.cpu.fp_regfile_reads 166009 # number of floating regfile reads -system.cpu.fp_regfile_writes 167434 # number of floating regfile writes -system.cpu.misc_regfile_reads 2028435 # number of misc regfile reads -system.cpu.misc_regfile_writes 938984 # number of misc regfile writes +system.cpu.rob.rob_reads 141516799 # The number of ROB reads +system.cpu.rob.rob_writes 128475885 # The number of ROB writes +system.cpu.timesIdled 1198400 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 40890126 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598244060 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52978349 # Number of Instructions Simulated +system.cpu.committedOps 52978349 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52978349 # Number of Instructions Simulated +system.cpu.cpi 2.305339 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.305339 # CPI: Total CPI of All Threads +system.cpu.ipc 0.433776 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.433776 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73853807 # number of integer regfile reads +system.cpu.int_regfile_writes 40298046 # number of integer regfile writes +system.cpu.fp_regfile_reads 166062 # number of floating regfile reads +system.cpu.fp_regfile_writes 167446 # number of floating regfile writes +system.cpu.misc_regfile_reads 2027357 # number of misc regfile reads +system.cpu.misc_regfile_writes 938942 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -858,9 +774,9 @@ system.tsunami.ethernet.droppedPackets 0 # nu system.iobus.throughput 1454553 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51150 # Transaction distribution -system.iobus.trans_dist::WriteResp 51150 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51149 # Transaction distribution +system.iobus.trans_dist::WriteResp 51149 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -872,11 +788,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33054 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116504 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20200 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -888,12 +804,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 44140 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2705756 # Total data (bytes) -system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2705748 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2705748 # Total data (bytes) +system.iobus.reqLayer0.occupancy 4661000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -915,249 +831,241 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 377738948 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380111537 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42679505 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43192006 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 111941811 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2118263 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2118167 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 840743 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 342536 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 300985 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 79 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020543 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677710 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5698253 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64653440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143572596 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 208226036 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 208215988 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 17920 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2480284498 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 111856774 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2116112 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2116015 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 840541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 62 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 63 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 342408 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 300857 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2017437 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3676056 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5693493 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64554304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143513388 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 208067692 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 208057644 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 17408 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2478840496 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1518802860 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1516414125 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2192631666 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2186111163 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1009602 # number of replacements -system.cpu.icache.tags.tagsinuse 509.660060 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7489391 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1010110 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.414431 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26489829250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.660060 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995430 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995430 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1008048 # number of replacements +system.cpu.icache.tags.tagsinuse 509.665585 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7476650 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1008556 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.413222 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26682759250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.665585 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995441 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995441 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9566377 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9566377 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7489392 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7489392 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7489392 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7489392 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7489392 # number of overall hits -system.cpu.icache.overall_hits::total 7489392 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1066652 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1066652 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1066652 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1066652 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1066652 # number of overall misses -system.cpu.icache.overall_misses::total 1066652 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14896343949 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14896343949 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14896343949 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14896343949 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14896343949 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14896343949 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8556044 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8556044 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8556044 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8556044 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8556044 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8556044 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124666 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124666 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124666 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124666 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124666 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124666 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13965.514478 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13965.514478 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13965.514478 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13965.514478 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13965.514478 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13965.514478 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4660 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 199 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 23.417085 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 9550236 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9550236 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7476651 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7476651 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7476651 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7476651 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7476651 # number of overall hits +system.cpu.icache.overall_hits::total 7476651 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1064809 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1064809 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1064809 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1064809 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1064809 # number of overall misses +system.cpu.icache.overall_misses::total 1064809 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14791038698 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14791038698 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14791038698 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14791038698 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14791038698 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14791038698 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8541460 # 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average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13643.738095 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71068.072375 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71068.072375 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64551.472030 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58467.981996 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58694.497004 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64551.472030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58467.981996 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58694.497004 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1247,13 +1147,13 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1401219 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994567 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11810743 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1401731 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.425827 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25477000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994567 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1400496 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994513 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11811358 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1401008 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.430614 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 25856000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994513 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1261,154 +1161,154 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63738376 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63738376 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7205308 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7205308 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4203634 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4203634 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186044 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186044 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215517 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215517 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11408942 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11408942 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11408942 # number of overall hits -system.cpu.dcache.overall_hits::total 11408942 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1806790 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1806790 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1944128 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1944128 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22738 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22738 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3750918 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3750918 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3750918 # number of overall misses -system.cpu.dcache.overall_misses::total 3750918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 40335866684 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 40335866684 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 77256495609 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 77256495609 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 322518001 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 322518001 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 39001 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 39001 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117592362293 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117592362293 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117592362293 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117592362293 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9012098 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9012098 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147762 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147762 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208782 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 208782 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215519 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215519 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15159860 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15159860 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15159860 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15159860 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200485 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.200485 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316233 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316233 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108908 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108908 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247424 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247424 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247424 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247424 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22324.601467 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22324.601467 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39738.379165 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39738.379165 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14184.097150 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14184.097150 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19500.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19500.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31350.288727 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31350.288727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31350.288727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31350.288727 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3041849 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 98391 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 63734677 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63734677 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7206132 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7206132 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4203012 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4203012 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186466 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186466 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215515 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215515 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11409144 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11409144 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11409144 # number of overall hits +system.cpu.dcache.overall_hits::total 11409144 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1805019 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1805019 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1944584 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1944584 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22688 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22688 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3749603 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3749603 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3749603 # number of overall misses +system.cpu.dcache.overall_misses::total 3749603 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40356893890 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40356893890 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 77719104532 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 77719104532 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321753501 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 321753501 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 118075998422 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 118075998422 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 118075998422 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 118075998422 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9011151 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9011151 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147596 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147596 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209154 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209154 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215516 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215516 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15158747 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15158747 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15158747 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15158747 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200309 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.200309 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316316 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316316 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108475 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108475 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.247356 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247356 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247356 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247356 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22358.154618 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22358.154618 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39966.956702 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39966.956702 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14181.659952 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14181.659952 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31490.266682 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31490.266682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31490.266682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31490.266682 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3050951 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 663 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 86776 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.915927 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.158926 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 94.714286 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840743 # number of writebacks -system.cpu.dcache.writebacks::total 840743 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 722826 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 722826 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643736 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1643736 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5220 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5220 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2366562 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2366562 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2366562 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2366562 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083964 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083964 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300392 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300392 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17518 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17518 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384356 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384356 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384356 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384356 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27183263254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27183263254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11761438359 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11761438359 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200916999 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200916999 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 34999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 34999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38944701613 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 38944701613 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38944701613 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 38944701613 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424030000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424030000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997779498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997779498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421809498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421809498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120279 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120279 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048862 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048862 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083906 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091317 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091317 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091317 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091317 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25077.643957 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25077.643957 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39153.633782 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39153.633782 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11469.174506 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11469.174506 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17499.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17499.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28131.999004 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28131.999004 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28131.999004 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28131.999004 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 840541 # number of writebacks +system.cpu.dcache.writebacks::total 840541 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721694 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 721694 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1644324 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1644324 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5123 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5123 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2366018 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2366018 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2366018 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2366018 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083325 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1083325 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300260 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300260 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17565 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17565 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1383585 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1383585 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1383585 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1383585 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27323478009 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27323478009 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11844407335 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11844407335 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200869499 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200869499 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39167885344 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 39167885344 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39167885344 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 39167885344 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424097000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424097000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997590998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997590998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421687998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421687998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120220 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120220 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048842 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048842 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083981 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083981 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091273 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091273 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091273 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25221.866023 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25221.866023 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39447.170236 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39447.170236 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11435.781327 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11435.781327 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28308.983795 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28308.983795 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28308.983795 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28308.983795 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1417,28 +1317,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211003 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182248 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105563 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182234 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818029044000 97.73% 97.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64103000 0.00% 97.74% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 561251500 0.03% 97.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41542545500 2.23% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860196944000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817851866500 97.72% 97.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64172000 0.00% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 559556500 0.03% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41715361500 2.24% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1860190956500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694294 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694315 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815424 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1477,29 +1377,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175131 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175119 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191976 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches +system.cpu.kern.callpal::total 191963 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches system.cpu.kern.mode_switch::user 1740 # number of protection mode switches system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326384 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29636227500 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2736556500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827824152000 98.26% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29573655500 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2713841000 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827903452000 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 76117c4c2..d0170b803 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,147 +1,147 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.842697 # Number of seconds simulated -sim_ticks 1842697218000 # Number of ticks simulated -final_tick 1842697218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.842694 # Number of seconds simulated +sim_ticks 1842693728000 # Number of ticks simulated +final_tick 1842693728000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 281851 # Simulator instruction rate (inst/s) -host_op_rate 281851 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7098045398 # Simulator tick rate (ticks/s) -host_mem_usage 310872 # Number of bytes of host memory used -host_seconds 259.61 # Real time elapsed on the host -sim_insts 73170192 # Number of instructions simulated -sim_ops 73170192 # Number of ops (including micro ops) simulated +host_inst_rate 239111 # Simulator instruction rate (inst/s) +host_op_rate 239111 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5964368765 # Simulator tick rate (ticks/s) +host_mem_usage 346744 # Number of bytes of host memory used +host_seconds 308.95 # Real time elapsed on the host +sim_insts 73873335 # Number of instructions simulated +sim_ops 73873335 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 489152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20102912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 489024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20126208 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 144448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2236224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 284928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2526528 # Number of bytes read from this memory -system.physmem.bytes_read::total 28436544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 489152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 144448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 284928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 918528 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7459712 # Number of bytes written to this memory -system.physmem.bytes_written::total 7459712 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7643 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 314108 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 143680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2232768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 285376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2509376 # Number of bytes read from this memory +system.physmem.bytes_read::total 28438784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 489024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 143680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 285376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 918080 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7463104 # Number of bytes written to this memory +system.physmem.bytes_written::total 7463104 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7641 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 314472 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2257 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 34941 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4452 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39477 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444321 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116558 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116558 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 265454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10909504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1439386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 78389 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1213560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 154626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1371103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15432022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 265454 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 78389 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 154626 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498469 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4048257 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4048257 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4048257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 265454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10909504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1439386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 78389 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1213560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 154626 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1371103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19480279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 98018 # Number of read requests accepted -system.physmem.writeReqs 44365 # Number of write requests accepted -system.physmem.readBursts 98018 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 44365 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6272576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue -system.physmem.bytesWritten 2838464 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6273152 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2839360 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu1.inst 2245 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 34887 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4459 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39209 # Number of read requests responded to by this memory +system.physmem.num_reads::total 444356 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116611 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116611 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 265385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10922167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1439388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 77973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1211687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 154869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1361798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15433267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 265385 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 77973 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 154869 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4050105 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4050105 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4050105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 265385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10922167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1439388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 77973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1211687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 154869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1361798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 19483372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 97691 # Number of read requests accepted +system.physmem.writeReqs 44282 # Number of write requests accepted +system.physmem.readBursts 97691 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 44282 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6250944 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1280 # Total number of bytes read from write queue +system.physmem.bytesWritten 2832576 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6252224 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2834048 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 20 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 42 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6238 # Per bank write bursts -system.physmem.perBankRdBursts::1 6029 # Per bank write bursts -system.physmem.perBankRdBursts::2 6222 # Per bank write bursts -system.physmem.perBankRdBursts::3 6415 # Per bank write bursts -system.physmem.perBankRdBursts::4 5671 # Per bank write bursts -system.physmem.perBankRdBursts::5 6259 # Per bank write bursts -system.physmem.perBankRdBursts::6 6020 # Per bank write bursts -system.physmem.perBankRdBursts::7 6028 # Per bank write bursts -system.physmem.perBankRdBursts::8 6370 # Per bank write bursts -system.physmem.perBankRdBursts::9 6122 # Per bank write bursts -system.physmem.perBankRdBursts::10 6366 # Per bank write bursts -system.physmem.perBankRdBursts::11 5871 # Per bank write bursts -system.physmem.perBankRdBursts::12 5882 # Per bank write bursts -system.physmem.perBankRdBursts::13 6242 # Per bank write bursts -system.physmem.perBankRdBursts::14 6237 # Per bank write bursts -system.physmem.perBankRdBursts::15 6037 # Per bank write bursts -system.physmem.perBankWrBursts::0 2849 # Per bank write bursts -system.physmem.perBankWrBursts::1 2656 # Per bank write bursts -system.physmem.perBankWrBursts::2 2849 # Per bank write bursts -system.physmem.perBankWrBursts::3 3015 # Per bank write bursts -system.physmem.perBankWrBursts::4 2565 # Per bank write bursts -system.physmem.perBankWrBursts::5 2994 # Per bank write bursts -system.physmem.perBankWrBursts::6 2937 # Per bank write bursts -system.physmem.perBankWrBursts::7 2695 # Per bank write bursts -system.physmem.perBankWrBursts::8 3093 # Per bank write bursts -system.physmem.perBankWrBursts::9 2622 # Per bank write bursts -system.physmem.perBankWrBursts::10 2879 # Per bank write bursts -system.physmem.perBankWrBursts::11 2436 # Per bank write bursts -system.physmem.perBankWrBursts::12 2462 # Per bank write bursts -system.physmem.perBankWrBursts::13 2714 # Per bank write bursts -system.physmem.perBankWrBursts::14 2848 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 39 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6114 # Per bank write bursts +system.physmem.perBankRdBursts::1 5899 # Per bank write bursts +system.physmem.perBankRdBursts::2 6060 # Per bank write bursts +system.physmem.perBankRdBursts::3 6276 # Per bank write bursts +system.physmem.perBankRdBursts::4 5549 # Per bank write bursts +system.physmem.perBankRdBursts::5 6233 # Per bank write bursts +system.physmem.perBankRdBursts::6 6082 # Per bank write bursts +system.physmem.perBankRdBursts::7 6075 # Per bank write bursts +system.physmem.perBankRdBursts::8 6372 # Per bank write bursts +system.physmem.perBankRdBursts::9 6119 # Per bank write bursts +system.physmem.perBankRdBursts::10 6443 # Per bank write bursts +system.physmem.perBankRdBursts::11 5953 # Per bank write bursts +system.physmem.perBankRdBursts::12 5846 # Per bank write bursts +system.physmem.perBankRdBursts::13 6273 # Per bank write bursts +system.physmem.perBankRdBursts::14 6335 # Per bank write bursts +system.physmem.perBankRdBursts::15 6042 # Per bank write bursts +system.physmem.perBankWrBursts::0 2746 # Per bank write bursts +system.physmem.perBankWrBursts::1 2526 # Per bank write bursts +system.physmem.perBankWrBursts::2 2727 # Per bank write bursts +system.physmem.perBankWrBursts::3 3010 # Per bank write bursts +system.physmem.perBankWrBursts::4 2533 # Per bank write bursts +system.physmem.perBankWrBursts::5 2968 # Per bank write bursts +system.physmem.perBankWrBursts::6 2994 # Per bank write bursts +system.physmem.perBankWrBursts::7 2697 # Per bank write bursts +system.physmem.perBankWrBursts::8 3092 # Per bank write bursts +system.physmem.perBankWrBursts::9 2617 # Per bank write bursts +system.physmem.perBankWrBursts::10 2969 # Per bank write bursts +system.physmem.perBankWrBursts::11 2522 # Per bank write bursts +system.physmem.perBankWrBursts::12 2428 # Per bank write bursts +system.physmem.perBankWrBursts::13 2745 # Per bank write bursts +system.physmem.perBankWrBursts::14 2948 # Per bank write bursts system.physmem.perBankWrBursts::15 2737 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 1841684892500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 1841681402500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 98018 # Read request sizes (log2) +system.physmem.readPktSize::6 97691 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 44365 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 66438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 14086 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2022 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 553 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 609 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 44282 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 65712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 488 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 859 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 762 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 609 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -153,423 +153,391 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 2181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 2225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 2215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 17929 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 508.069831 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.315652 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1577.422962 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 7580 42.28% 42.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 2972 16.58% 58.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 1827 10.19% 69.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 983 5.48% 74.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 676 3.77% 78.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 569 3.17% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 353 1.97% 83.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 316 1.76% 85.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 239 1.33% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 212 1.18% 87.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 225 1.25% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 207 1.15% 90.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 92 0.51% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 80 0.45% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 62 0.35% 91.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 115 0.64% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 35 0.20% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 50 0.28% 92.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 54 0.30% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 63 0.35% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 30 0.17% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 123 0.69% 94.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 74 0.41% 94.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 80 0.45% 94.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 19 0.11% 95.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 17 0.09% 95.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 7 0.04% 95.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 37 0.21% 95.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 7 0.04% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 18 0.10% 95.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 6 0.03% 95.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 15 0.08% 95.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 9 0.05% 95.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 16 0.09% 95.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 1 0.01% 95.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 23 0.13% 95.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 12 0.07% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 4 0.02% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 9 0.05% 96.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 2 0.01% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 15 0.08% 96.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 22 0.12% 96.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 1 0.01% 96.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 14 0.08% 96.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 3 0.02% 96.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 12 0.07% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 2 0.01% 96.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 12 0.07% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 2 0.01% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 20 0.11% 96.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 11 0.06% 96.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.01% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 9 0.05% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 1 0.01% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 13 0.07% 96.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 21 0.12% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.01% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 13 0.07% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 2 0.01% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 8 0.04% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 3 0.02% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 14 0.08% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 22 0.12% 97.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 13 0.07% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 1 0.01% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 77 0.43% 97.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 3 0.02% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 19 0.11% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 5 0.03% 97.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.01% 97.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 8 0.04% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 4 0.02% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 21 0.12% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 6 0.03% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 9 0.05% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 2 0.01% 98.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 3 0.02% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 21 0.12% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 3 0.02% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 6 0.03% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 5 0.03% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 19 0.11% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 6 0.03% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 6 0.03% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 25 0.14% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.01% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 15 0.08% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 1 0.01% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.01% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 21 0.12% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 4 0.02% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 52 0.29% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 1 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9411 1 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 1 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 2 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11011 1 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11331 1 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 1 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 1 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12099 1 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 1 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12803 2 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 1 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 2 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 1 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 1 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 2 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14464-14467 1 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 1 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 1 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 1 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 16 0.09% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 1 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 1 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 1 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 75 0.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 17929 # Bytes accessed per row activation -system.physmem.totQLat 2679388500 # Total ticks spent queuing -system.physmem.totMemAccLat 4331514750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 490045000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1162081250 # Total ticks spent accessing banks -system.physmem.avgQLat 27338.19 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11856.88 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 15110 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 511.250298 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 300.938727 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 421.415256 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3831 25.35% 25.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 2740 18.13% 43.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1074 7.11% 50.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 703 4.65% 55.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 520 3.44% 58.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 360 2.38% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 225 1.49% 62.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 226 1.50% 64.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5431 35.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 15110 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2571 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.985220 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 914.533013 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2569 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.04% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.04% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 2571 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.214702 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.506808 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 4.396297 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 28 1.09% 1.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 8 0.31% 1.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 1 0.04% 1.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 1 0.04% 1.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 1 0.04% 1.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 1 0.04% 1.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 2 0.08% 1.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 2 0.08% 1.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 1 0.04% 1.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 1 0.04% 1.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1798 69.93% 71.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 69 2.68% 74.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 74 2.88% 77.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 370 14.39% 91.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 34 1.32% 93.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 19 0.74% 93.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 12 0.47% 94.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 7 0.27% 94.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 34 1.32% 95.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 15 0.58% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.19% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 15 0.58% 97.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 11 0.43% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 14 0.54% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.16% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 5 0.19% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 6 0.23% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 3 0.12% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.04% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.04% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 2 0.08% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 2 0.08% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 3 0.12% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 4 0.16% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 3 0.12% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 5 0.19% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 2 0.08% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 1 0.04% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 2 0.08% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 2 0.08% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 2 0.08% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2571 # Writes before turning the bus around for reads +system.physmem.totQLat 3372876000 # Total ticks spent queuing +system.physmem.totMemAccLat 5050468500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 488355000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1189237500 # Total ticks spent accessing banks +system.physmem.avgQLat 34533.03 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 12175.95 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44195.07 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 51708.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.39 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.40 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.39 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.16 # Average write queue length when enqueuing -system.physmem.readRowHits 89637 # Number of row buffer hits during reads -system.physmem.writeRowHits 34794 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.46 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.43 # Row buffer hit rate for writes -system.physmem.avgGap 12934724.60 # Average gap between requests -system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 4.13 # Average write queue length when enqueuing +system.physmem.readRowHits 85060 # Number of row buffer hits during reads +system.physmem.writeRowHits 35225 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.55 # Row buffer hit rate for writes +system.physmem.avgGap 12972053.86 # Average gap between requests +system.physmem.pageHitRate 84.74 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 19524219 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 44737 # Transaction distribution -system.membus.trans_dist::ReadResp 44533 # Transaction distribution -system.membus.trans_dist::WriteReq 3749 # Transaction distribution -system.membus.trans_dist::WriteResp 3749 # Transaction distribution -system.membus.trans_dist::Writeback 44365 # Transaction distribution -system.membus.trans_dist::UpgradeReq 45 # Transaction distribution -system.membus.trans_dist::UpgradeResp 45 # Transaction distribution -system.membus.trans_dist::ReadExReq 56547 # Transaction distribution -system.membus.trans_dist::ReadExResp 56547 # Transaction distribution -system.membus.trans_dist::BadAddressError 204 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13310 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189932 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 408 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 203650 # Packet count per connected master and slave (bytes) +system.membus.throughput 19527312 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 44337 # Transaction distribution +system.membus.trans_dist::ReadResp 44306 # Transaction distribution +system.membus.trans_dist::WriteReq 3779 # Transaction distribution +system.membus.trans_dist::WriteResp 3779 # Transaction distribution +system.membus.trans_dist::Writeback 44282 # Transaction distribution +system.membus.trans_dist::UpgradeReq 42 # Transaction distribution +system.membus.trans_dist::UpgradeResp 42 # Transaction distribution +system.membus.trans_dist::ReadExReq 56476 # Transaction distribution +system.membus.trans_dist::ReadExResp 56476 # Transaction distribution +system.membus.trans_dist::BadAddressError 31 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 13428 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 189189 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 62 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 202679 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 50712 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 50712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 254362 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15689 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6952704 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 6968393 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 253391 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15748 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 6926464 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 6942212 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2159808 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 2159808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 9128201 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35967240 # Total data (bytes) +system.membus.tot_pkt_size::total 9102020 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35972872 # Total data (bytes) system.membus.snoop_data_through_bus 9984 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12468500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12574500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 514332500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 513408250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 252500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 40000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 764298954 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 761373958 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 152995500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 153163000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 337398 # number of replacements -system.l2c.tags.tagsinuse 65420.701532 # Cycle average of tags in use -system.l2c.tags.total_refs 2472173 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402561 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.141114 # Average number of references to valid blocks. +system.l2c.tags.replacements 337430 # number of replacements +system.l2c.tags.tagsinuse 65422.148259 # Cycle average of tags in use +system.l2c.tags.total_refs 2473441 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402593 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.143775 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54886.932182 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2458.825580 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2703.778525 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 528.462620 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 622.296328 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2148.830278 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2071.576019 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.837508 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 54880.563920 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2458.853214 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2711.613848 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 517.416897 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 618.305247 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2161.633442 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2073.761691 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.837411 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.037519 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041256 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008064 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009495 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.032789 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.031610 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998241 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041376 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.007895 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009435 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.032984 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.031643 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998263 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 988 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5636 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2991 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55380 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1047 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5588 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2973 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55387 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26143118 # Number of tag accesses -system.l2c.tags.data_accesses 26143118 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 520243 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 493553 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 124286 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 83912 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 292769 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 239004 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1753767 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835523 # number of Writeback hits -system.l2c.Writeback_hits::total 835523 # number of Writeback hits +system.l2c.tags.tag_accesses 26153114 # Number of tag accesses +system.l2c.tags.data_accesses 26153114 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 521024 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 493028 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 125251 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 84722 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 291154 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 239311 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1754490 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 836107 # number of Writeback hits +system.l2c.Writeback_hits::total 836107 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu2.data 1 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 92938 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 26217 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 67761 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186916 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 520243 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 586491 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 124286 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 110129 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 292769 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 306765 # number of demand (read+write) hits -system.l2c.demand_hits::total 1940683 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 520243 # number of overall hits -system.l2c.overall_hits::cpu0.data 586491 # number of overall hits -system.l2c.overall_hits::cpu1.inst 124286 # number of overall hits -system.l2c.overall_hits::cpu1.data 110129 # number of overall hits -system.l2c.overall_hits::cpu2.inst 292769 # number of overall hits -system.l2c.overall_hits::cpu2.data 306765 # number of overall hits -system.l2c.overall_hits::total 1940683 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 7643 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 238324 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2257 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 16911 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4452 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 18142 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287729 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu0.data 93137 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 26426 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 67420 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 186983 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 521024 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 586165 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 125251 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 111148 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 291154 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 306731 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 4834368536 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 279416000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 295991000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 575407000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 345820000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 406371500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 752191500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 625236000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 702362500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1327598500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.017608 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.165448 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015084 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.069350 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020241 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.750000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.375000 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.407037 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.241560 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.130844 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017608 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.239150 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015084 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.113589 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034521 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017608 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.239150 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015084 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.113589 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034521 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59847.551448 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54323.484758 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63710.417134 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54576.837885 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 55745.493988 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 26778.444444 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 26778.444444 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55577.191841 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70882.958739 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63873.981597 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59847.551448 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 54974.453572 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63710.417134 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63484.926551 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59723.377758 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59847.551448 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 54974.453572 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63710.417134 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63484.926551 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59723.377758 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -680,14 +648,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254904 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254944 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694870354000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254904 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078431 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078431 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1694864715000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254944 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078434 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078434 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -703,12 +671,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 9303463 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 9303463 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5314732731 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5314732731 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5324036194 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5324036194 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5324036194 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5324036194 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5375933278 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5375933278 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5385236741 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5385236741 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5385236741 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5385236741 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -727,17 +695,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 53777.242775 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 53777.242775 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 127905.581705 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 127905.581705 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 127598.231132 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 127598.231132 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 127598.231132 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 127598.231132 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 168308 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 129378.448161 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 129378.448161 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 129064.990797 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129064.990797 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 129064.990797 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129064.990797 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 158120 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 12241 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11558 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.749530 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.680568 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -753,12 +721,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 16965 system.iocache.overall_mshr_misses::total 16965 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5714463 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 5714463 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4435520731 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4435520731 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 4441235194 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4441235194 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 4441235194 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4441235194 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 4496386278 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4496386278 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 4502100741 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4502100741 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 4502100741 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4502100741 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.406623 # mshr miss rate for WriteReq accesses @@ -769,12 +737,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 0.406591 system.iocache.overall_mshr_miss_rate::total 0.406591 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82818.304348 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 82818.304348 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 262518.982659 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 262518.982659 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 261788.104568 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 261788.104568 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 261788.104568 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 261788.104568 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 266121.346946 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 266121.346946 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 265375.817330 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 265375.817330 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 265375.817330 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 265375.817330 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -792,22 +760,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4920578 # DTB read hits +system.cpu0.dtb.read_hits 4928404 # DTB read hits system.cpu0.dtb.read_misses 6099 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations system.cpu0.dtb.read_accesses 428233 # DTB read accesses -system.cpu0.dtb.write_hits 3510258 # DTB write hits +system.cpu0.dtb.write_hits 3518338 # DTB write hits system.cpu0.dtb.write_misses 670 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations system.cpu0.dtb.write_accesses 163777 # DTB write accesses -system.cpu0.dtb.data_hits 8430836 # DTB hits +system.cpu0.dtb.data_hits 8446742 # DTB hits system.cpu0.dtb.data_misses 6769 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations system.cpu0.dtb.data_accesses 592010 # DTB accesses -system.cpu0.itb.fetch_hits 2762930 # ITB hits +system.cpu0.itb.fetch_hits 2763962 # ITB hits system.cpu0.itb.fetch_misses 3034 # ITB misses system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2765964 # ITB accesses +system.cpu0.itb.fetch_accesses 2766996 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -820,52 +788,52 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 928345000 # number of cpu cycles simulated +system.cpu0.numCycles 928692350 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33879417 # Number of instructions committed -system.cpu0.committedOps 33879417 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 31738664 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 170028 # Number of float alu accesses -system.cpu0.num_func_calls 812853 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4700164 # number of instructions that are conditional controls -system.cpu0.num_int_insts 31738664 # number of integer instructions -system.cpu0.num_fp_insts 170028 # number of float instructions -system.cpu0.num_int_register_reads 44595421 # number of times the integer registers were read -system.cpu0.num_int_register_writes 23158595 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 87794 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 89338 # number of times the floating registers were written -system.cpu0.num_mem_refs 8461010 # number of memory refs -system.cpu0.num_load_insts 4941975 # Number of load instructions -system.cpu0.num_store_insts 3519035 # Number of store instructions -system.cpu0.num_idle_cycles 904626845.998199 # Number of idle cycles -system.cpu0.num_busy_cycles 23718154.001801 # Number of busy cycles -system.cpu0.not_idle_fraction 0.025549 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.974451 # Percentage of idle cycles -system.cpu0.Branches 5776800 # Number of branches fetched +system.cpu0.committedInsts 34273964 # Number of instructions committed +system.cpu0.committedOps 34273964 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 32130742 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 169948 # Number of float alu accesses +system.cpu0.num_func_calls 813899 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4819398 # number of instructions that are conditional controls +system.cpu0.num_int_insts 32130742 # number of integer instructions +system.cpu0.num_fp_insts 169948 # number of float instructions +system.cpu0.num_int_register_reads 45237353 # number of times the integer registers were read +system.cpu0.num_int_register_writes 23423813 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 87792 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 89256 # number of times the floating registers were written +system.cpu0.num_mem_refs 8476912 # number of memory refs +system.cpu0.num_load_insts 4949798 # Number of load instructions +system.cpu0.num_store_insts 3527114 # Number of store instructions +system.cpu0.num_idle_cycles 904863863.789935 # Number of idle cycles +system.cpu0.num_busy_cycles 23828486.210065 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025658 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974342 # Percentage of idle cycles +system.cpu0.Branches 5897308 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6418 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211383 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74805 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6415 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211374 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74800 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182584 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73438 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 105691 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182573 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73433 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73438 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148958 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819507118500 98.74% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38781000 0.00% 98.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 365071000 0.02% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22785478000 1.24% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842696448500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 73433 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148948 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1819462416000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38889500 0.00% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 365010500 0.02% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22826642500 1.24% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1842692958500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694797 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815833 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694790 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815827 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -901,10 +869,10 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175325 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175314 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -913,21 +881,21 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192238 # number of callpals executed +system.cpu0.kern.callpal::total 192229 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1907 -system.cpu0.kern.mode_good::user 1738 -system.cpu0.kern.mode_good::idle 169 +system.cpu0.kern.mode_good::user 1737 +system.cpu0.kern.mode_good::idle 170 system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391019 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29794763000 1.62% 1.62% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2592746500 0.14% 1.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810308934500 98.24% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4175 # number of times the context was actually changed +system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.390979 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29759204500 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2578304000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1810355445500 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -959,59 +927,59 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 110459996 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 784722 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 784503 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 3749 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 3749 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 371354 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution +system.toL2Bus.throughput 110509038 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 784786 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 784740 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 3779 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 3779 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 372271 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 150558 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 133662 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 204 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 847542 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1368014 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 2215556 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27120896 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55237129 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 82358025 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 203533320 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 11008 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2134008000 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 150355 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 133459 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 31 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 846229 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1370023 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 2216252 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27078976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 55338308 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 82417284 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 203623496 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 10816 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2138093500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1908780020 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1905810483 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2230620167 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2232783145 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1469142 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 2975 # Transaction distribution -system.iobus.trans_dist::ReadResp 2975 # Transaction distribution -system.iobus.trans_dist::WriteReq 20645 # Transaction distribution -system.iobus.trans_dist::WriteResp 20645 # Transaction distribution +system.iobus.throughput 1469145 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 3004 # Transaction distribution +system.iobus.trans_dist::ReadResp 3004 # Transaction distribution +system.iobus.trans_dist::WriteReq 20675 # Transaction distribution +system.iobus.trans_dist::WriteResp 20675 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2330 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 136 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 66 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8370 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 8488 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2374 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 13310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 13428 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 33930 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 33930 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 47240 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 47358 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9320 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 544 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 61 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4185 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 4244 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 1548 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 31 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 15689 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 15748 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1082792 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1082792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1098481 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1098540 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 2707184 # Total data (bytes) system.iobus.reqLayer0.occupancy 2199000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) @@ -1019,398 +987,398 @@ system.iobus.reqLayer1.occupancy 102000 # La system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 57000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6237000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6326000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 1789000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 153613694 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 154493741 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9561000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9649000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17409500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17628000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 951005 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.190319 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43429541 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 951516 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 45.642471 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10399272250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.342896 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 99.592582 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 160.254842 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.490904 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.194517 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.312998 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998419 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 951123 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.189701 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 44044625 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 951634 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 46.283156 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10406456250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 252.370031 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 94.623296 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 164.196374 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.492910 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.184811 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.320696 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998417 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 45349405 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 45349405 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 33358489 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7831408 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2239644 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12225.579648 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12205.383827 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1391788 # number of replacements +system.cpu0.dcache.tags.replacements 1392490 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997811 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13285278 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1392300 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.541965 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 13295207 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393002 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.544284 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 249.411553 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 131.959093 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 130.627166 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.487132 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.257733 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.255131 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 249.168016 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 132.479618 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 130.350177 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.486656 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.258749 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.254590 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63261634 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63261634 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4082373 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1085171 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2396693 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7564237 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3213874 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 832734 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1291048 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5337656 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117262 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19372 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47406 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184040 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126440 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21396 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51446 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7296247 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1917905 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3687741 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12901893 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7296247 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1917905 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3687741 # number of overall hits -system.cpu0.dcache.overall_hits::total 12901893 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 722135 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 98671 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 532767 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1353573 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 169009 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 44296 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 596502 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 809807 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9742 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2152 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6843 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18737 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 63289936 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63289936 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4090319 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1090270 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2387407 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7567996 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3221527 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 836656 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1285562 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5343745 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117421 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19406 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 47293 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184120 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126604 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21447 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 51238 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199289 # 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number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 44567 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 593518 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 807386 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9749 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2170 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 6797 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 18716 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu2.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 891144 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 142967 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1129269 # 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number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 102729249 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 131218249 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 891176 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 143915 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1125275 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2160366 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 891176 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 143915 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1125275 # number of overall misses +system.cpu0.dcache.overall_misses::total 2160366 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2256659500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9313664253 # 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miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069372 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.234434 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.143600 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.108843 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069372 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.234434 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.143600 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 22860.582137 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17546.677570 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8572.841856 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37450.723745 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 310560000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 607082000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 364175500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 426698000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 790873500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 660697500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 737258000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1397955500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083348 # 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number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 431165001 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 797542001 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 664630500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 746482001 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1411112501 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083513 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086327 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.039385 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050574 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047182 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021659 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100575 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.099593 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.037257 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000020 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069372 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070813 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032132 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069372 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070813 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032132 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20779.393135 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16909.565995 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17998.529801 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35258.527655 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29455.363865 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31381.923082 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11237.918216 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12112.592251 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11864.005547 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069496 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070997 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032150 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069496 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070997 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032150 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20639.031485 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16811.977655 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17894.118381 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34679.443086 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29666.299104 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31343.317591 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11179.608295 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12106.553369 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11840.380177 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25265.517504 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20187.819839 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21687.476300 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25265.517504 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20187.819839 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21687.476300 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24987.007887 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20157.361413 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21591.728791 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24987.007887 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20157.361413 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21591.728791 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1425,22 +1393,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1203332 # DTB read hits -system.cpu1.dtb.read_misses 1366 # DTB read misses +system.cpu1.dtb.read_hits 1209129 # DTB read hits +system.cpu1.dtb.read_misses 1367 # DTB read misses system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 142940 # DTB read accesses -system.cpu1.dtb.write_hits 898898 # DTB write hits -system.cpu1.dtb.write_misses 183 # DTB write misses -system.cpu1.dtb.write_acv 22 # DTB write access violations -system.cpu1.dtb.write_accesses 58529 # DTB write accesses -system.cpu1.dtb.data_hits 2102230 # DTB hits -system.cpu1.dtb.data_misses 1549 # DTB misses -system.cpu1.dtb.data_acv 56 # DTB access violations -system.cpu1.dtb.data_accesses 201469 # DTB accesses -system.cpu1.itb.fetch_hits 859402 # ITB hits -system.cpu1.itb.fetch_misses 692 # ITB misses +system.cpu1.dtb.read_accesses 142945 # DTB read accesses +system.cpu1.dtb.write_hits 903134 # DTB write hits +system.cpu1.dtb.write_misses 185 # DTB write misses +system.cpu1.dtb.write_acv 23 # DTB write access violations +system.cpu1.dtb.write_accesses 58533 # DTB write accesses +system.cpu1.dtb.data_hits 2112263 # DTB hits +system.cpu1.dtb.data_misses 1552 # DTB misses +system.cpu1.dtb.data_acv 57 # DTB access violations +system.cpu1.dtb.data_accesses 201478 # DTB accesses +system.cpu1.itb.fetch_hits 860790 # ITB hits +system.cpu1.itb.fetch_misses 693 # ITB misses system.cpu1.itb.fetch_acv 30 # ITB acv -system.cpu1.itb.fetch_accesses 860094 # ITB accesses +system.cpu1.itb.fetch_accesses 861483 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1453,29 +1421,29 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953617285 # number of cpu cycles simulated +system.cpu1.numCycles 953612854 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7956345 # Number of instructions committed -system.cpu1.committedOps 7956345 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7412681 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 44901 # Number of float alu accesses -system.cpu1.num_func_calls 213028 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1020887 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7412681 # number of integer instructions -system.cpu1.num_fp_insts 44901 # number of float instructions -system.cpu1.num_int_register_reads 10388601 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5388855 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 24208 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24605 # number of times the floating registers were written -system.cpu1.num_mem_refs 2109439 # number of memory refs -system.cpu1.num_load_insts 1208206 # Number of load instructions -system.cpu1.num_store_insts 901233 # Number of store instructions -system.cpu1.num_idle_cycles 922131579.439540 # Number of idle cycles -system.cpu1.num_busy_cycles 31485705.560460 # Number of busy cycles -system.cpu1.not_idle_fraction 0.033017 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.966983 # Percentage of idle cycles -system.cpu1.Branches 1300702 # Number of branches fetched +system.cpu1.committedInsts 8186270 # Number of instructions committed +system.cpu1.committedOps 8186270 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7639715 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45422 # Number of float alu accesses +system.cpu1.num_func_calls 213980 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1089106 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7639715 # number of integer instructions +system.cpu1.num_fp_insts 45422 # number of float instructions +system.cpu1.num_int_register_reads 10757840 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5542682 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24502 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24833 # number of times the floating registers were written +system.cpu1.num_mem_refs 2119540 # number of memory refs +system.cpu1.num_load_insts 1214044 # Number of load instructions +system.cpu1.num_store_insts 905496 # Number of store instructions +system.cpu1.num_idle_cycles 923510145.865154 # Number of idle cycles +system.cpu1.num_busy_cycles 30102708.134846 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031567 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968433 # Percentage of idle cycles +system.cpu1.Branches 1370105 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1493,35 +1461,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9131296 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8453261 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 124867 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7606484 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6524985 # Number of BTB hits +system.cpu2.branchPred.lookups 9158053 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8481927 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 123683 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 7604727 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6560922 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 85.781880 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 282035 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 13344 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 86.274261 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 280761 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 13305 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3186348 # DTB read hits -system.cpu2.dtb.read_misses 11810 # DTB read misses -system.cpu2.dtb.read_acv 124 # DTB read access violations -system.cpu2.dtb.read_accesses 217745 # DTB read accesses -system.cpu2.dtb.write_hits 2009701 # DTB write hits -system.cpu2.dtb.write_misses 2606 # DTB write misses -system.cpu2.dtb.write_acv 109 # DTB write access violations -system.cpu2.dtb.write_accesses 82375 # DTB write accesses -system.cpu2.dtb.data_hits 5196049 # DTB hits -system.cpu2.dtb.data_misses 14416 # DTB misses -system.cpu2.dtb.data_acv 233 # DTB access violations -system.cpu2.dtb.data_accesses 300120 # DTB accesses -system.cpu2.itb.fetch_hits 370442 # ITB hits -system.cpu2.itb.fetch_misses 5628 # ITB misses -system.cpu2.itb.fetch_acv 253 # ITB acv -system.cpu2.itb.fetch_accesses 376070 # ITB accesses +system.cpu2.dtb.read_hits 3175061 # DTB read hits +system.cpu2.dtb.read_misses 11717 # DTB read misses +system.cpu2.dtb.read_acv 122 # DTB read access violations +system.cpu2.dtb.read_accesses 217137 # DTB read accesses +system.cpu2.dtb.write_hits 2001578 # DTB write hits +system.cpu2.dtb.write_misses 2618 # DTB write misses +system.cpu2.dtb.write_acv 106 # DTB write access violations +system.cpu2.dtb.write_accesses 82142 # DTB write accesses +system.cpu2.dtb.data_hits 5176639 # DTB hits +system.cpu2.dtb.data_misses 14335 # DTB misses +system.cpu2.dtb.data_acv 228 # DTB access violations +system.cpu2.dtb.data_accesses 299279 # DTB accesses +system.cpu2.itb.fetch_hits 368924 # ITB hits +system.cpu2.itb.fetch_misses 5740 # ITB misses +system.cpu2.itb.fetch_acv 243 # ITB acv +system.cpu2.itb.fetch_accesses 374664 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1534,270 +1502,270 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 31313073 # number of cpu cycles simulated +system.cpu2.numCycles 31279022 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8328585 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 37006400 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9131296 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6807020 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8851345 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 606644 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9641968 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 10046 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1931 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 63228 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 87070 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 340 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2553376 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 86779 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27379324 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.351618 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.293970 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 8287542 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 37055340 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9158053 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6841683 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 8878582 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 603474 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9658598 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 9919 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 63764 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 87901 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 585 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2543899 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 85179 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27382085 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.353269 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.291783 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18527979 67.67% 67.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 269262 0.98% 68.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 428968 1.57% 70.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 5000608 18.26% 88.49% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 759354 2.77% 91.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 165275 0.60% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 190932 0.70% 92.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 427573 1.56% 94.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1609373 5.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18503503 67.58% 67.58% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 267960 0.98% 68.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 427466 1.56% 70.11% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 5038940 18.40% 88.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 758703 2.77% 91.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 165190 0.60% 91.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 190909 0.70% 92.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 425900 1.56% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1603514 5.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27379324 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.291613 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.181819 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8475609 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9724872 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 8241247 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 308907 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 382752 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 165606 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12712 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36612854 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 39749 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 382752 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 8834671 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2773280 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5760129 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8113478 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1269087 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 35472103 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2436 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 230799 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 444723 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 23769376 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 44394567 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 44338159 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 52651 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 21967508 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1801868 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 500326 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 58967 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3713170 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3346051 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2099971 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 366369 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 258671 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32979578 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 619087 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 32529976 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 34753 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2147129 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1082645 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 436861 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27379324 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.188122 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.575744 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27382085 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.292786 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.184671 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8439244 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9737555 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 8269995 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 308345 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 381075 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 165536 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12831 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36664015 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 39751 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 381075 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 8796739 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2804819 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5741072 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8142606 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1269911 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35531036 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2469 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 231647 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 446543 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 23808302 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 44475961 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 44419812 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 52401 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 22020270 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1788032 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 498319 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 58753 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3705896 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3335757 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2091143 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 366529 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 285241 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 33051386 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 616780 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32598005 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 35098 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2143170 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1082478 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 435207 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27382085 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.190487 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.575531 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15104518 55.17% 55.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3059496 11.17% 66.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1557193 5.69% 72.03% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5827645 21.28% 93.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 904106 3.30% 96.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 480512 1.76% 98.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 285612 1.04% 99.41% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 141433 0.52% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 18809 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15085778 55.09% 55.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3054879 11.16% 66.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1548873 5.66% 71.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5868849 21.43% 93.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 901287 3.29% 96.63% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 476925 1.74% 98.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 288026 1.05% 99.42% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 138840 0.51% 99.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 18628 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27379324 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27382085 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 32920 13.41% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.41% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 112185 45.69% 59.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 100449 40.91% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 33655 13.83% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.83% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 111431 45.78% 59.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 98340 40.40% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 26864472 82.58% 82.59% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 20045 0.06% 82.65% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.65% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 8419 0.03% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.68% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3313279 10.19% 92.87% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2032055 6.25% 99.11% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 288046 0.89% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26953534 82.68% 82.69% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 19910 0.06% 82.75% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.75% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 8410 0.03% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.78% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3301438 10.13% 92.91% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2024047 6.21% 99.12% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 287006 0.88% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 32529976 # Type of FU issued -system.cpu2.iq.rate 1.038862 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 245554 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007549 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 92485827 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 35635212 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 32132884 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 233756 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 114401 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 110529 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 32651329 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 121761 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 186414 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32598005 # Type of FU issued +system.cpu2.iq.rate 1.042168 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 243426 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007468 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 92623863 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 35700994 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 32205742 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 232756 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 114085 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 110215 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32717888 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 121103 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 185687 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 413956 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1112 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 3936 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 157547 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 410803 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1083 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 3827 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 157383 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4151 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 27254 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 4176 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 27619 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 382752 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 2003866 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 204399 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 34866454 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 220221 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3346051 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2099971 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 549960 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 142228 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1969 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 3936 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 63951 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 128015 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 191966 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 32372492 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3206448 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 157484 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 381075 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2023183 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 204607 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 34934170 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 220301 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3335757 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2091143 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 547666 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 141469 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2123 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 3827 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63090 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 127121 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 190211 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 32442083 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3195032 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 155922 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1267789 # number of nop insts executed -system.cpu2.iew.exec_refs 5223192 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7564928 # Number of branches executed -system.cpu2.iew.exec_stores 2016744 # Number of stores executed -system.cpu2.iew.exec_rate 1.033833 # Inst execution rate -system.cpu2.iew.wb_sent 32276755 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 32243413 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 18781769 # num instructions producing a value -system.cpu2.iew.wb_consumers 21976070 # num instructions consuming a value +system.cpu2.iew.exec_nop 1266004 # number of nop insts executed +system.cpu2.iew.exec_refs 5203645 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7597485 # Number of branches executed +system.cpu2.iew.exec_stores 2008613 # Number of stores executed +system.cpu2.iew.exec_rate 1.037183 # Inst execution rate +system.cpu2.iew.wb_sent 32348485 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 32315957 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18839799 # num instructions producing a value +system.cpu2.iew.wb_consumers 22025525 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.029711 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.854646 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.033151 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.855362 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2322975 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 182226 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 177336 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26996572 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.203754 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.846865 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2315429 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 181573 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 175784 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 27001010 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.206363 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.845727 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16110852 59.68% 59.68% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2323792 8.61% 68.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1227035 4.55% 72.83% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5572191 20.64% 93.47% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 501625 1.86% 95.33% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 185779 0.69% 96.02% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 177561 0.66% 96.67% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 179863 0.67% 97.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 717874 2.66% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16087817 59.58% 59.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2320535 8.59% 68.18% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1221811 4.53% 72.70% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5612171 20.79% 93.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 500601 1.85% 95.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 184383 0.68% 96.02% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 174610 0.65% 96.67% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 192284 0.71% 97.38% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 706798 2.62% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26996572 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 32497229 # Number of instructions committed -system.cpu2.commit.committedOps 32497229 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 27001010 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32573021 # Number of instructions committed +system.cpu2.commit.committedOps 32573021 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4874519 # Number of memory references committed -system.cpu2.commit.loads 2932095 # Number of loads committed -system.cpu2.commit.membars 63814 # Number of memory barriers committed -system.cpu2.commit.branches 7417113 # Number of branches committed -system.cpu2.commit.fp_insts 109328 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 31054650 # Number of committed integer instructions. -system.cpu2.commit.function_calls 228340 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 717874 # number cycles where commit BW limit reached +system.cpu2.commit.refs 4858714 # Number of memory references committed +system.cpu2.commit.loads 2924954 # Number of loads committed +system.cpu2.commit.membars 63567 # Number of memory barriers committed +system.cpu2.commit.branches 7451291 # Number of branches committed +system.cpu2.commit.fp_insts 109021 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 31134232 # Number of committed integer instructions. +system.cpu2.commit.function_calls 227850 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 706798 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 61024976 # The number of ROB reads -system.cpu2.rob.rob_writes 70022633 # The number of ROB writes -system.cpu2.timesIdled 244840 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3933749 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1746460059 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 31334430 # Number of Instructions Simulated -system.cpu2.committedOps 31334430 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 31334430 # Number of Instructions Simulated -system.cpu2.cpi 0.999318 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.999318 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.000682 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.000682 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 42582766 # number of integer regfile reads -system.cpu2.int_regfile_writes 22654603 # number of integer regfile writes -system.cpu2.fp_regfile_reads 67639 # number of floating regfile reads -system.cpu2.fp_regfile_writes 67817 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5361637 # number of misc regfile reads -system.cpu2.misc_regfile_writes 256988 # number of misc regfile writes +system.cpu2.rob.rob_reads 61108801 # The number of ROB reads +system.cpu2.rob.rob_writes 70157468 # The number of ROB writes +system.cpu2.timesIdled 244589 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3896937 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746488839 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31413101 # Number of Instructions Simulated +system.cpu2.committedOps 31413101 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 31413101 # Number of Instructions Simulated +system.cpu2.cpi 0.995732 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.995732 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.004287 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.004287 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42678646 # number of integer regfile reads +system.cpu2.int_regfile_writes 22701958 # number of integer regfile writes +system.cpu2.fp_regfile_reads 67399 # number of floating regfile reads +system.cpu2.fp_regfile_writes 67744 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5400058 # number of misc regfile reads +system.cpu2.misc_regfile_writes 256035 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed |