stats: update stale config.ini files, eio and few other stats.

8 files changed, 211 insertions, 215 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
index 7683e2958..a7c751a3c 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
@@ -15,19 +15,20 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/dist/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
 eventq_index=0
 init_param=0
-kernel=/dist/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
 mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
+mmap_using_noreserve=false
 num_work_ids=16
-pal=/dist/binaries/ts_osfpal
-readfile=/work/gem5.latest/tests/halt.sh
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -124,7 +125,7 @@ dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.branchPred]
-type=BranchPredictor
+type=TournamentBP
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -138,7 +139,6 @@ localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
-predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
@@ -150,7 +150,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -161,7 +161,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -574,7 +573,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -585,7 +584,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -624,7 +622,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -635,7 +633,6 @@ size=4194304
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -654,8 +651,11 @@ size=4194304
 type=CoherentXBar
 clk_domain=system.cpu_clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
 snoop_filter=Null
+snoop_response_latency=1
 system=system
 use_default_range=false
 width=32
@@ -694,7 +694,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -717,7 +717,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -737,9 +737,11 @@ sys=system
 type=NoncoherentXBar
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
 use_default_range=true
-width=8
+width=16
 default=system.tsunami.pciconfig.pio
 master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
 slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
@@ -754,7 +756,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -765,7 +767,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
@@ -785,11 +786,14 @@ type=CoherentXBar
 children=badaddr_responder
 clk_domain=system.clk_domain
 eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
 snoop_filter=Null
+snoop_response_latency=4
 system=system
 use_default_range=false
-width=8
+width=16
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
@@ -839,7 +843,7 @@ IDD62=0.000000
 VDD=1.500000
 VDD2=0.000000
 activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
 bank_groups_per_rank=0
 banks_per_rank=8
 burst_length=8
@@ -899,7 +903,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal
index 075c19401..455709c02 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal
@@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 30 cycles, load miss latency 140 cycles
+
4096K Bcache detected; load hit latency 30 cycles, load miss latency 152 cycles
 
SMP: 1 CPUs probed -- cpu_present_mask = 1
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index aca399d8a..2b4d92c81 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/home/stever/m5/m5_system_2.0b3/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
 eventq_index=0
 init_param=0
-kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -27,8 +27,8 @@ mem_ranges=0:134217727
 memories=system.physmem
 mmap_using_noreserve=false
 num_work_ids=16
-pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
-readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -175,7 +175,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -186,7 +186,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
@@ -222,9 +221,9 @@ opList=system.cpu0.fuPool.FUList0.opList
 [system.cpu0.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList1]
 type=FUDesc
@@ -236,16 +235,16 @@ opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
 [system.cpu0.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu0.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu0.fuPool.FUList2]
 type=FUDesc
@@ -257,23 +256,23 @@ opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 sys
 [system.cpu0.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu0.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu0.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu0.fuPool.FUList3]
 type=FUDesc
@@ -285,23 +284,23 @@ opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 sys
 [system.cpu0.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu0.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu0.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu0.fuPool.FUList4]
 type=FUDesc
@@ -313,9 +312,9 @@ opList=system.cpu0.fuPool.FUList4.opList
 [system.cpu0.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5]
 type=FUDesc
@@ -327,142 +326,142 @@ opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 s
 [system.cpu0.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList6]
 type=FUDesc
@@ -474,9 +473,9 @@ opList=system.cpu0.fuPool.FUList6.opList
 [system.cpu0.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList7]
 type=FUDesc
@@ -488,16 +487,16 @@ opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
 [system.cpu0.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu0.fuPool.FUList8]
 type=FUDesc
@@ -509,9 +508,9 @@ opList=system.cpu0.fuPool.FUList8.opList
 [system.cpu0.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu0.icache]
 type=BaseCache
@@ -523,7 +522,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -534,7 +533,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
@@ -682,7 +680,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -693,7 +691,6 @@ size=32768
 system=system
 tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
@@ -729,9 +726,9 @@ opList=system.cpu1.fuPool.FUList0.opList
 [system.cpu1.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList1]
 type=FUDesc
@@ -743,16 +740,16 @@ opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
 [system.cpu1.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu1.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu1.fuPool.FUList2]
 type=FUDesc
@@ -764,23 +761,23 @@ opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 sys
 [system.cpu1.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu1.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu1.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu1.fuPool.FUList3]
 type=FUDesc
@@ -792,23 +789,23 @@ opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 sys
 [system.cpu1.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu1.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu1.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu1.fuPool.FUList4]
 type=FUDesc
@@ -820,9 +817,9 @@ opList=system.cpu1.fuPool.FUList4.opList
 [system.cpu1.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5]
 type=FUDesc
@@ -834,142 +831,142 @@ opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 s
 [system.cpu1.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList6]
 type=FUDesc
@@ -981,9 +978,9 @@ opList=system.cpu1.fuPool.FUList6.opList
 [system.cpu1.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList7]
 type=FUDesc
@@ -995,16 +992,16 @@ opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
 [system.cpu1.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu1.fuPool.FUList8]
 type=FUDesc
@@ -1016,9 +1013,9 @@ opList=system.cpu1.fuPool.FUList8.opList
 [system.cpu1.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu1.icache]
 type=BaseCache
@@ -1030,7 +1027,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -1041,7 +1038,6 @@ size=32768
 system=system
 tags=system.cpu1.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
@@ -1102,7 +1098,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -1125,7 +1121,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -1164,7 +1160,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1175,7 +1171,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
@@ -1200,7 +1195,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -1211,7 +1206,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -1348,7 +1342,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
index 7e0283697..1425d639e 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
@@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 30 cycles, load miss latency 154 cycles
+
4096K Bcache detected; load hit latency 30 cycles, load miss latency 152 cycles
 
SMP: 2 CPUs probed -- cpu_present_mask = 3
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index 4de22817f..3eacf4507 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/home/stever/m5/m5_system_2.0b3/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
 eventq_index=0
 init_param=0
-kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -27,8 +27,8 @@ mem_ranges=0:134217727
 memories=system.physmem
 mmap_using_noreserve=false
 num_work_ids=16
-pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
-readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -175,7 +175,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -186,7 +186,6 @@ size=32768
 system=system
 tags=system.cpu.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
@@ -222,9 +221,9 @@ opList=system.cpu.fuPool.FUList0.opList
 [system.cpu.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList1]
 type=FUDesc
@@ -236,16 +235,16 @@ opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
 [system.cpu.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu.fuPool.FUList2]
 type=FUDesc
@@ -257,23 +256,23 @@ opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 syste
 [system.cpu.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu.fuPool.FUList3]
 type=FUDesc
@@ -285,23 +284,23 @@ opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 syste
 [system.cpu.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu.fuPool.FUList4]
 type=FUDesc
@@ -313,9 +312,9 @@ opList=system.cpu.fuPool.FUList4.opList
 [system.cpu.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5]
 type=FUDesc
@@ -327,142 +326,142 @@ opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 sys
 [system.cpu.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList6]
 type=FUDesc
@@ -474,9 +473,9 @@ opList=system.cpu.fuPool.FUList6.opList
 [system.cpu.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7]
 type=FUDesc
@@ -488,16 +487,16 @@ opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
 [system.cpu.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu.fuPool.FUList8]
 type=FUDesc
@@ -509,9 +508,9 @@ opList=system.cpu.fuPool.FUList8.opList
 [system.cpu.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu.icache]
 type=BaseCache
@@ -523,7 +522,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -534,7 +533,6 @@ size=32768
 system=system
 tags=system.cpu.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
@@ -573,7 +571,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -584,7 +582,6 @@ size=4194304
 system=system
 tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -646,7 +643,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -669,7 +666,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -708,7 +705,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -719,7 +716,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
@@ -856,7 +852,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
index 008c44f37..455709c02 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
@@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 30 cycles, load miss latency 154 cycles
+
4096K Bcache detected; load hit latency 30 cycles, load miss latency 152 cycles
 
SMP: 1 CPUs probed -- cpu_present_mask = 1
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
index 2d4d2bc38..d49d26c09 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/home/stever/m5/m5_system_2.0b3/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
 eventq_index=0
 init_param=0
-kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -27,8 +27,8 @@ mem_ranges=0:134217727
 memories=system.physmem
 mmap_using_noreserve=false
 num_work_ids=16
-pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
-readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -107,7 +107,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -118,7 +118,6 @@ size=32768
 system=system
 tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
@@ -148,7 +147,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
-is_top_level=true
+is_read_only=true
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
@@ -159,7 +158,6 @@ size=32768
 system=system
 tags=system.cpu0.icache.tags
 tgts_per_mshr=20
-two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
@@ -366,9 +364,9 @@ opList=system.cpu2.fuPool.FUList0.opList
 [system.cpu2.fuPool.FUList0.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList1]
 type=FUDesc
@@ -380,16 +378,16 @@ opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
 [system.cpu2.fuPool.FUList1.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=IntMult
 opLat=3
+pipelined=true
 
 [system.cpu2.fuPool.FUList1.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=19
 opClass=IntDiv
 opLat=20
+pipelined=false
 
 [system.cpu2.fuPool.FUList2]
 type=FUDesc
@@ -401,23 +399,23 @@ opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 sys
 [system.cpu2.fuPool.FUList2.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatAdd
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList2.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCmp
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList2.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatCvt
 opLat=2
+pipelined=true
 
 [system.cpu2.fuPool.FUList3]
 type=FUDesc
@@ -429,23 +427,23 @@ opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 sys
 [system.cpu2.fuPool.FUList3.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=FloatMult
 opLat=4
+pipelined=true
 
 [system.cpu2.fuPool.FUList3.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=12
 opClass=FloatDiv
 opLat=12
+pipelined=false
 
 [system.cpu2.fuPool.FUList3.opList2]
 type=OpDesc
 eventq_index=0
-issueLat=24
 opClass=FloatSqrt
 opLat=24
+pipelined=false
 
 [system.cpu2.fuPool.FUList4]
 type=FUDesc
@@ -457,9 +455,9 @@ opList=system.cpu2.fuPool.FUList4.opList
 [system.cpu2.fuPool.FUList4.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5]
 type=FUDesc
@@ -471,142 +469,142 @@ opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 s
 [system.cpu2.fuPool.FUList5.opList00]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAdd
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList01]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAddAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList02]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList03]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCmp
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList04]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdCvt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList05]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMisc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList06]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMult
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList07]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList08]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShift
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList09]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdShiftAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList10]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdSqrt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList11]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAdd
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList12]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatAlu
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList13]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCmp
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList14]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatCvt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList15]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatDiv
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList16]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMisc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList17]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMult
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList18]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatMultAcc
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList5.opList19]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=SimdFloatSqrt
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList6]
 type=FUDesc
@@ -618,9 +616,9 @@ opList=system.cpu2.fuPool.FUList6.opList
 [system.cpu2.fuPool.FUList6.opList]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList7]
 type=FUDesc
@@ -632,16 +630,16 @@ opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
 [system.cpu2.fuPool.FUList7.opList0]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemRead
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList7.opList1]
 type=OpDesc
 eventq_index=0
-issueLat=1
 opClass=MemWrite
 opLat=1
+pipelined=true
 
 [system.cpu2.fuPool.FUList8]
 type=FUDesc
@@ -653,9 +651,9 @@ opList=system.cpu2.fuPool.FUList8.opList
 [system.cpu2.fuPool.FUList8.opList]
 type=OpDesc
 eventq_index=0
-issueLat=3
 opClass=IprAccess
 opLat=3
+pipelined=false
 
 [system.cpu2.isa]
 type=AlphaISA
@@ -699,7 +697,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -722,7 +720,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -761,7 +759,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
-is_top_level=true
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -772,7 +770,6 @@ size=1024
 system=system
 tags=system.iocache.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
@@ -797,7 +794,7 @@ demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
-is_top_level=false
+is_read_only=false
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
@@ -808,7 +805,6 @@ size=4194304
 system=system
 tags=system.l2c.tags
 tgts_per_mshr=12
-two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
@@ -945,7 +941,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
index ffff6ec3c..ae9247519 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
@@ -3,12 +3,12 @@ warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: Prefetch instructions in Alpha do not do anything
 warn: Prefetch instructions in Alpha do not do anything
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8155, Bank: 7
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -20,7 +20,13 @@ Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 10136, Bank: 0
+Command: 0, Timestamp: 11185, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -48,6 +54,6 @@ Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: Bank is already active!
-Command: 0, Timestamp: 11138, Bank: 3
+Command: 0, Timestamp: 11369, Bank: 3
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0