diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-21 04:48:24 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-21 04:48:24 -0400 |
| commit | b006ad26d45dae3e336d7fc422adab0a330ba24a (patch) | |
| tree | 306fd2f75944fe4ad8f19f0a374d7c72ad97a5cc /tests/long/fs/10.linux-boot/ref/alpha | |
| parent | 5a1dea51d2d4e2798eade7bbe3362098fc5f7f91 (diff) | |
| download | gem5-b006ad26d45dae3e336d7fc422adab0a330ba24a.tar.xz | |
stats: Update stats to reflect cache changes
Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
4 files changed, 174 insertions, 270 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 002e59ef5..3a2e9a680 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.907083 # Nu sim_ticks 1907083088000 # Number of ticks simulated final_tick 1907083088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20030 # Simulator instruction rate (inst/s) -host_op_rate 20030 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 680419212 # Simulator tick rate (ticks/s) +host_inst_rate 20979 # Simulator instruction rate (inst/s) +host_op_rate 20979 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 712669715 # Simulator tick rate (ticks/s) host_mem_usage 389460 # Number of bytes of host memory used -host_seconds 2802.81 # Real time elapsed on the host +host_seconds 2675.97 # Real time elapsed on the host sim_insts 56139550 # Number of instructions simulated sim_ops 56139550 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -563,8 +563,6 @@ system.cpu.dcache.blocked::no_mshrs 0 # nu system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 837991 # number of writebacks system.cpu.dcache.writebacks::total 837991 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 126783 # number of ReadReq MSHR hits @@ -605,10 +603,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61084599500 system.cpu.dcache.overall_mshr_miss_latency::total 61084599500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528608000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528608000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2161966000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2161966000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3690574000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3690574000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1528608000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1528608000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118453 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118453 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049434 # mshr miss rate for WriteReq accesses @@ -631,11 +627,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44310.310947 system.cpu.dcache.overall_avg_mshr_miss_latency::total 44310.310947 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220578.354978 # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220578.354978 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224666.528110 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224666.528110 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222954.993053 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222954.993053 # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92346.281641 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92346.281641 # average overall mshr uncacheable latency system.cpu.icache.tags.replacements 1471396 # number of replacements system.cpu.icache.tags.tagsinuse 508.107952 # Cycle average of tags in use system.cpu.icache.tags.total_refs 19138982 # Total number of references to valid blocks. @@ -694,8 +687,6 @@ system.cpu.icache.blocked::no_mshrs 0 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 1471396 # number of writebacks system.cpu.icache.writebacks::total 1471396 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1472080 # number of ReadReq MSHR misses @@ -722,7 +713,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13369.070974 system.cpu.icache.demand_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13369.070974 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 13369.070974 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 339491 # number of replacements system.cpu.l2cache.tags.tagsinuse 65257.604073 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5020229 # Total number of references to valid blocks. @@ -843,8 +833,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 76584 # number of writebacks system.cpu.l2cache.writebacks::total 76584 # number of writebacks system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 15 # number of UpgradeReq MSHR misses @@ -883,10 +871,8 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631457500 system.cpu.l2cache.overall_mshr_miss_latency::total 46615488000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1441963500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1441963500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051300500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051300500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3493264000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3493264000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1441963500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1441963500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.750000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.750000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383353 # mshr miss rate for ReadExReq accesses @@ -917,11 +903,8 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114801.701520 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115069.001182 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208075.541126 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208075.541126 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213166.424192 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213166.424192 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211035.099378 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211035.099378 # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87111.913248 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87111.913248 # average overall mshr uncacheable latency system.cpu.toL2Bus.snoop_filter.tot_requests 5733180 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2866165 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1053,26 +1036,26 @@ system.iocache.ReadReq_misses::tsunami.ide 173 # system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses -system.iocache.demand_misses::total 173 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 173 # number of overall misses -system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses +system.iocache.demand_misses::total 41725 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses +system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21917383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21917383 # number of ReadReq miss cycles system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245324283 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 5245324283 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21917383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21917383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21917383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21917383 # number of overall miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5267241666 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5267241666 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5267241666 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5267241666 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1085,36 +1068,34 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145 system.iocache.ReadReq_avg_miss_latency::total 126690.075145 # average ReadReq miss latency system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126235.182013 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 126235.182013 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126690.075145 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126690.075145 # average overall miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126237.068089 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126237.068089 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126237.068089 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126237.068089 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 83 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 13.833333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13267383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13267383 # number of ReadReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165924983 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 3165924983 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13267383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13267383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13267383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13267383 # number of overall MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3179192366 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3179192366 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3179192366 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3179192366 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1127,11 +1108,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145 system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.879645 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.879645 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76193.945261 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76193.945261 # average overall mshr miss latency system.membus.trans_dist::ReadReq 6930 # Transaction distribution system.membus.trans_dist::ReadResp 295608 # Transaction distribution system.membus.trans_dist::WriteReq 9623 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 1db8d7737..4b8dc4618 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.929078 # Nu sim_ticks 1929077876500 # Number of ticks simulated final_tick 1929077876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158135 # Simulator instruction rate (inst/s) -host_op_rate 158134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5371969736 # Simulator tick rate (ticks/s) +host_inst_rate 169237 # Simulator instruction rate (inst/s) +host_op_rate 169237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5749129790 # Simulator tick rate (ticks/s) host_mem_usage 339544 # Number of bytes of host memory used -host_seconds 359.10 # Real time elapsed on the host +host_seconds 335.54 # Real time elapsed on the host sim_insts 56786201 # Number of instructions simulated sim_ops 56786201 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -746,8 +746,6 @@ system.cpu0.dcache.blocked::no_mshrs 111036 # nu system.cpu0.dcache.blocked::no_targets 116 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs 60.537276 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 152.336207 # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 741086 # number of writebacks system.cpu0.dcache.writebacks::total 741086 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 559859 # number of ReadReq MSHR hits @@ -792,10 +790,8 @@ system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 60954715557 system.cpu0.dcache.overall_mshr_miss_latency::total 60954715557 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1558946000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1558946000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2296787000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2296787000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3855733000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3855733000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1558946000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1558946000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.118415 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.118415 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048081 # mshr miss rate for WriteReq accesses @@ -822,11 +818,8 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48240.612650 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48240.612650 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221724.647987 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221724.647987 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227292.132608 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227292.132608 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 225007.761438 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225007.761438 # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 90974.906629 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 90974.906629 # average overall mshr uncacheable latency system.cpu0.icache.tags.replacements 911237 # number of replacements system.cpu0.icache.tags.tagsinuse 508.249711 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 7675800 # Total number of references to valid blocks. @@ -884,8 +877,6 @@ system.cpu0.icache.blocked::no_mshrs 347 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs 32.965418 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 911237 # number of writebacks system.cpu0.icache.writebacks::total 911237 # number of writebacks system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54272 # number of ReadReq MSHR hits @@ -918,7 +909,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14180.210258 system.cpu0.icache.demand_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14180.210258 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 14180.210258 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.branchPred.lookups 4129053 # Number of BP lookups system.cpu1.branchPred.condPredicted 3551647 # Number of conditional branches predicted system.cpu1.branchPred.condIncorrect 103168 # Number of conditional branches incorrect @@ -1352,8 +1342,6 @@ system.cpu1.dcache.blocked::no_mshrs 22564 # nu system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.664820 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets 131.916667 # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 79554 # number of writebacks system.cpu1.dcache.writebacks::total 79554 # number of writebacks system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 136401 # number of ReadReq MSHR hits @@ -1398,10 +1386,8 @@ system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3154256462 system.cpu1.dcache.overall_mshr_miss_latency::total 3154256462 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 32176000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 32176000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 696582500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 696582500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 728758500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 728758500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 32176000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 32176000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042091 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042091 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036289 # mshr miss rate for WriteReq accesses @@ -1428,11 +1414,8 @@ system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24211.363694 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24211.363694 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 198617.283951 # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 198617.283951 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 232970.735786 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 232970.735786 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 231205.107868 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 231205.107868 # average overall mshr uncacheable latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 10208.121827 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 10208.121827 # average overall mshr uncacheable latency system.cpu1.icache.tags.replacements 244089 # number of replacements system.cpu1.icache.tags.tagsinuse 469.435893 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 1565201 # Total number of references to valid blocks. @@ -1491,8 +1474,6 @@ system.cpu1.icache.blocked::no_mshrs 56 # nu system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.875000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 244089 # number of writebacks system.cpu1.icache.writebacks::total 244089 # number of writebacks system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11093 # number of ReadReq MSHR hits @@ -1525,7 +1506,6 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13445.297520 system.cpu1.icache.demand_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13445.297520 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 13445.297520 # average overall mshr miss latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1610,26 +1590,26 @@ system.iocache.ReadReq_misses::tsunami.ide 175 # system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses -system.iocache.demand_misses::total 175 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 175 # number of overall misses -system.iocache.overall_misses::total 175 # number of overall misses +system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses +system.iocache.demand_misses::total 41727 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses +system.iocache.overall_misses::total 41727 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 22072883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 22072883 # number of ReadReq miss cycles system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245136282 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 5245136282 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22072883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22072883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22072883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22072883 # number of overall miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5267209165 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5267209165 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5267209165 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5267209165 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1642,36 +1622,34 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126130.760000 system.iocache.ReadReq_avg_miss_latency::total 126130.760000 # average ReadReq miss latency system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.657538 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 126230.657538 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126130.760000 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126130.760000 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126130.760000 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126130.760000 # average overall miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126230.238575 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126230.238575 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126230.238575 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13322883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13322883 # number of ReadReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165734984 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 3165734984 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13322883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13322883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13322883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13322883 # number of overall MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3179057867 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3179057867 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3179057867 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3179057867 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1684,11 +1662,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76130.760000 system.iocache.ReadReq_avg_mshr_miss_latency::total 76130.760000 # average ReadReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.307085 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.307085 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76130.760000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76130.760000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76130.760000 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76187.069931 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76187.069931 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76187.069931 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76187.069931 # average overall mshr miss latency system.l2c.tags.replacements 345263 # number of replacements system.l2c.tags.tagsinuse 65201.794559 # Cycle average of tags in use system.l2c.tags.total_refs 4034348 # Total number of references to valid blocks. @@ -1879,8 +1856,6 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 81472 # number of writebacks system.l2c.writebacks::total 81472 # number of writebacks system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits @@ -1956,12 +1931,9 @@ system.l2c.overall_mshr_miss_latency::total 49061475524 # system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1471043500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 30151000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 1501194500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2180387500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 660346500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2840734000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3651431000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 690497500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4341928500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1471043500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 30151000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1501194500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941646 # mshr miss rate for UpgradeReq accesses @@ -2017,13 +1989,9 @@ system.l2c.overall_avg_mshr_miss_latency::total 119350.368973 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209222.514578 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186117.283951 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208702.140970 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215773.132113 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220851.672241 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216932.722413 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213085.375817 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 219066.465736 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 214014.614550 # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 85845.208917 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 9565.672589 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 73994.208399 # average overall mshr uncacheable latency system.membus.trans_dist::ReadReq 7193 # Transaction distribution system.membus.trans_dist::ReadResp 297247 # Transaction distribution system.membus.trans_dist::WriteReq 13095 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 6d0ef82f7..d6b9de05c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.876794 # Nu sim_ticks 1876794488000 # Number of ticks simulated final_tick 1876794488000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164316 # Simulator instruction rate (inst/s) -host_op_rate 164316 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5820514836 # Simulator tick rate (ticks/s) +host_inst_rate 142986 # Simulator instruction rate (inst/s) +host_op_rate 142986 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5064945596 # Simulator tick rate (ticks/s) host_mem_usage 335448 # Number of bytes of host memory used -host_seconds 322.44 # Real time elapsed on the host +host_seconds 370.55 # Real time elapsed on the host sim_insts 52982943 # Number of instructions simulated sim_ops 52982943 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -734,8 +734,6 @@ system.cpu.dcache.blocked::no_mshrs 133846 # nu system.cpu.dcache.blocked::no_targets 35 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.412332 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 146.257143 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 843569 # number of writebacks system.cpu.dcache.writebacks::total 843569 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 717041 # number of ReadReq MSHR hits @@ -780,10 +778,8 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63069666964 system.cpu.dcache.overall_mshr_miss_latency::total 63069666964 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528639000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528639000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154562000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154562000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3683201000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3683201000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1528639000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1528639000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111881 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111881 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047061 # mshr miss rate for WriteReq accesses @@ -810,11 +806,8 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45383.917418 system.cpu.dcache.overall_avg_mshr_miss_latency::total 45383.917418 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220582.828283 # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220582.828283 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224456.922596 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224456.922596 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222832.657753 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222832.657753 # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92482.243330 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92482.243330 # average overall mshr uncacheable latency system.cpu.icache.tags.replacements 1074186 # number of replacements system.cpu.icache.tags.tagsinuse 507.868793 # Cycle average of tags in use system.cpu.icache.tags.total_refs 8786985 # Total number of references to valid blocks. @@ -873,8 +866,6 @@ system.cpu.icache.blocked::no_mshrs 342 # nu system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 37.815789 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 1074186 # number of writebacks system.cpu.icache.writebacks::total 1074186 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68615 # number of ReadReq MSHR hits @@ -907,7 +898,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13860.792543 system.cpu.icache.demand_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13860.792543 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 13860.792543 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 338591 # number of replacements system.cpu.l2cache.tags.tagsinuse 65285.567334 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4253578 # Total number of references to valid blocks. @@ -1040,8 +1030,6 @@ system.cpu.l2cache.blocked::no_mshrs 0 # nu system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 76108 # number of writebacks system.cpu.l2cache.writebacks::total 76108 # number of writebacks system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 45 # number of UpgradeReq MSHR misses @@ -1084,10 +1072,8 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46238023002 system.cpu.l2cache.overall_mshr_miss_latency::total 48112818002 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442000500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442000500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2044145000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2044145000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3486145500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3486145500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1442000500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1442000500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.562500 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.562500 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.083333 # mshr miss rate for SCUpgradeReq accesses @@ -1122,11 +1108,8 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118769.468474 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118991.875594 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208080.880231 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208080.880231 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212953.953537 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212953.953537 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210910.853651 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210910.853651 # average overall mshr uncacheable latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87240.637667 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87240.637667 # average overall mshr uncacheable latency system.cpu.toL2Bus.snoop_filter.tot_requests 4961718 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2480443 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2186 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1259,26 +1242,26 @@ system.iocache.ReadReq_misses::tsunami.ide 173 # system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses -system.iocache.demand_misses::total 173 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 173 # number of overall misses -system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses +system.iocache.demand_misses::total 41725 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses +system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21828883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21828883 # number of ReadReq miss cycles system.iocache.WriteLineReq_miss_latency::tsunami.ide 5246443280 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 5246443280 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21828883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21828883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21828883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21828883 # number of overall miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5268272163 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5268272163 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5268272163 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5268272163 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1291,36 +1274,34 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126178.514451 system.iocache.ReadReq_avg_miss_latency::total 126178.514451 # average ReadReq miss latency system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126262.112052 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 126262.112052 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126178.514451 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126178.514451 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126178.514451 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126178.514451 # average overall miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126261.765440 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126261.765440 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126261.765440 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13178883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13178883 # number of ReadReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3167048471 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 3167048471 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13178883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13178883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13178883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13178883 # number of overall MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3180227354 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3180227354 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3180227354 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3180227354 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1333,11 +1314,10 @@ system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76178.514451 system.iocache.ReadReq_avg_mshr_miss_latency::total 76178.514451 # average ReadReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76218.917766 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76218.917766 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76178.514451 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76178.514451 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76178.514451 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76218.750246 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76218.750246 # average overall mshr miss latency system.membus.trans_dist::ReadReq 6930 # Transaction distribution system.membus.trans_dist::ReadResp 296606 # Transaction distribution system.membus.trans_dist::WriteReq 9599 # Transaction distribution diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 864d8545a..555ee4194 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.843617 # Nu sim_ticks 1843616607000 # Number of ticks simulated final_tick 1843616607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 222443 # Simulator instruction rate (inst/s) -host_op_rate 222443 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5619525357 # Simulator tick rate (ticks/s) +host_inst_rate 248643 # Simulator instruction rate (inst/s) +host_op_rate 248643 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6281412703 # Simulator tick rate (ticks/s) host_mem_usage 335188 # Number of bytes of host memory used -host_seconds 328.07 # Real time elapsed on the host +host_seconds 293.50 # Real time elapsed on the host sim_insts 72977545 # Number of instructions simulated sim_ops 72977545 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -644,8 +644,6 @@ system.cpu0.dcache.blocked::no_mshrs 58664 # nu system.cpu0.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs 28.111823 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 183.363636 # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 836302 # number of writebacks system.cpu0.dcache.writebacks::total 836302 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 286455 # number of ReadReq MSHR hits @@ -704,12 +702,9 @@ system.cpu0.dcache.overall_mshr_miss_latency::total 13534205301 system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 296833500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 314974000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 611807500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 374975500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 441435000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 816410500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 671809000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 756409000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1428218000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 296833500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 314974000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 611807500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.077888 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.078352 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037572 # mshr miss rate for ReadReq accesses @@ -747,13 +742,9 @@ system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28101.652148 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 220530.089153 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 225626.074499 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223124.544128 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230187.538367 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 223964.992390 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226780.694444 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225818.151261 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 224653.697654 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225199.936928 # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 99775.966387 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 93547.371547 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96469.173762 # average overall mshr uncacheable latency system.cpu0.icache.tags.replacements 969392 # number of replacements system.cpu0.icache.tags.tagsinuse 511.185439 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 43108744 # Total number of references to valid blocks. @@ -846,8 +837,6 @@ system.cpu0.icache.blocked::no_mshrs 386 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs 21.572539 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 969392 # number of writebacks system.cpu0.icache.writebacks::total 969392 # number of writebacks system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 21576 # number of ReadReq MSHR hits @@ -892,7 +881,6 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 13877.737624 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14186.253536 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13756.958453 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 13877.737624 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv @@ -1418,26 +1406,26 @@ system.iocache.ReadReq_misses::tsunami.ide 173 # system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses -system.iocache.demand_misses::total 173 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 173 # number of overall misses -system.iocache.overall_misses::total 173 # number of overall misses +system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses +system.iocache.demand_misses::total 41725 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses +system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 9857962 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 9857962 # number of ReadReq miss cycles system.iocache.WriteLineReq_miss_latency::tsunami.ide 1957317692 # number of WriteLineReq miss cycles system.iocache.WriteLineReq_miss_latency::total 1957317692 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9857962 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9857962 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9857962 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9857962 # number of overall miss cycles +system.iocache.demand_miss_latency::tsunami.ide 1967175654 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1967175654 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 1967175654 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1967175654 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1450,53 +1438,50 @@ system.iocache.ReadReq_avg_miss_latency::tsunami.ide 56982.439306 system.iocache.ReadReq_avg_miss_latency::total 56982.439306 # average ReadReq miss latency system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 47105.258279 # average WriteLineReq miss latency system.iocache.WriteLineReq_avg_miss_latency::total 47105.258279 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 56982.439306 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 56982.439306 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 56982.439306 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 56982.439306 # average overall miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 47146.211001 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 47146.211001 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 47146.211001 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 47146.211001 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 68 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 68 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 15504 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 15504 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 68 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 68 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 68 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 68 # number of overall MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 15572 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 15572 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 15572 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 15572 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6457962 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 6457962 # number of ReadReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1181451904 # number of WriteLineReq MSHR miss cycles system.iocache.WriteLineReq_mshr_miss_latency::total 1181451904 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 6457962 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 6457962 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 6457962 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 6457962 # number of overall MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 1187909866 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1187909866 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 1187909866 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1187909866 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.393064 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.393064 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.373123 # mshr miss rate for WriteLineReq accesses system.iocache.WriteLineReq_mshr_miss_rate::total 0.373123 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.393064 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.393064 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.393064 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.393064 # mshr miss rate for overall accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.373206 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.373206 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.373206 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.373206 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 94970.029412 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 94970.029412 # average ReadReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76203.038184 # average WriteLineReq mshr miss latency system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76203.038184 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 94970.029412 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 94970.029412 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 94970.029412 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 94970.029412 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76284.990110 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76284.990110 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76284.990110 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76284.990110 # average overall mshr miss latency system.l2c.tags.replacements 337717 # number of replacements system.l2c.tags.tagsinuse 65421.749224 # Cycle average of tags in use system.l2c.tags.total_refs 4019101 # Total number of references to valid blocks. @@ -1716,8 +1701,6 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks::writebacks 75320 # number of writebacks system.l2c.writebacks::total 75320 # number of writebacks system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses @@ -1778,12 +1761,9 @@ system.l2c.overall_mshr_miss_latency::total 8481752004 # system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 280001500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 297523000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 577524500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 356232500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 418765500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 774998000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 636234000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 716288500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1352522500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 280001500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 297523000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 577524500 # number of overall MSHR uncacheable cycles system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.681818 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.136364 # mshr miss rate for SCUpgradeReq accesses @@ -1833,13 +1813,9 @@ system.l2c.overall_avg_mshr_miss_latency::total 121109.061370 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 208024.888559 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 213125.358166 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 210621.626550 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218681.706568 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 212463.470320 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 215277.222222 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 213860.168067 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 212737.897238 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 213264.348786 # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 94118.151261 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 88364.419364 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 91063.465784 # average overall mshr uncacheable latency system.membus.trans_dist::ReadReq 7144 # Transaction distribution system.membus.trans_dist::ReadResp 295030 # Transaction distribution system.membus.trans_dist::WriteReq 9812 # Transaction distribution |