diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2013-02-15 17:40:14 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2013-02-15 17:40:14 -0500 |
| commit | bd31a5dc18def5972967a595d65266d1f9ff05cb (patch) | |
| tree | 62897fcc906dfb88f50c52d4ba2129be7ccdc114 /tests/long/fs/10.linux-boot/ref/alpha | |
| parent | 8cef39fb6742d834e383f533539ba90f72bbc7d9 (diff) | |
| download | gem5-bd31a5dc18def5972967a595d65266d1f9ff05cb.tar.xz | |
stats: update regressions for o3 changes in renaming and translation.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha')
5 files changed, 1173 insertions, 1167 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 8b454d95b..a041cd935 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -12,15 +12,15 @@ children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_dis boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 clock=1000 -console=/scratch/nilay/GEM5/system/binaries/console +console=/projects/pd/randd/dist/binaries/console init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/projects/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/projects/pd/randd/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -494,6 +494,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -519,7 +520,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -539,7 +540,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -585,6 +586,7 @@ children=badaddr_responder block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -610,25 +612,27 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false @@ -642,7 +646,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 4fc9bce9f..80fb6a8f2 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout -Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:39:31 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Feb 13 2013 10:45:16 +gem5 started Feb 13 2013 13:46:08 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1854344296500 because m5_exit instruction encountered +Exiting @ tick 1854310111000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 0fbfca2a6..02dc83699 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.854310 # Number of seconds simulated -sim_ticks 1854309852000 # Number of ticks simulated -final_tick 1854309852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1854310111000 # Number of ticks simulated +final_tick 1854310111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 117975 # Simulator instruction rate (inst/s) -host_op_rate 117975 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4129044881 # Simulator tick rate (ticks/s) -host_mem_usage 335500 # Number of bytes of host memory used -host_seconds 449.09 # Real time elapsed on the host -sim_insts 52981417 # Number of instructions simulated -sim_ops 52981417 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 964672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24877888 # Number of bytes read from this memory +host_inst_rate 145253 # Simulator instruction rate (inst/s) +host_op_rate 145253 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5083862253 # Simulator tick rate (ticks/s) +host_mem_usage 332668 # Number of bytes of host memory used +host_seconds 364.74 # Real time elapsed on the host +sim_insts 52980262 # Number of instructions simulated +sim_ops 52980262 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 964224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24877184 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory -system.physmem.bytes_read::total 28494848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 964672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 964672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7516416 # Number of bytes written to this memory -system.physmem.bytes_written::total 7516416 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15073 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388717 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28493696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 964224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 964224 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7514944 # Number of bytes written to this memory +system.physmem.bytes_written::total 7514944 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15066 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388706 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445232 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117444 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117444 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13416252 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 445214 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117421 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117421 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 519991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13415870 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 1430337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15366821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520232 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520232 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4053484 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4053484 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4053484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13416252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 15366198 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 519991 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 519991 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4052690 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4052690 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4052690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 519991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13415870 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1430337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 19420306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445232 # Total number of read requests seen -system.physmem.writeReqs 117444 # Total number of write requests seen -system.physmem.cpureqs 565193 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28494848 # Total number of bytes read from memory -system.physmem.bytesWritten 7516416 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28494848 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7516416 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 171 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28112 # Track reads on a per bank basis +system.physmem.bw_total::total 19418888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445214 # Total number of read requests seen +system.physmem.writeReqs 117421 # Total number of write requests seen +system.physmem.cpureqs 564314 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28493696 # Total number of bytes read from memory +system.physmem.bytesWritten 7514944 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28493696 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7514944 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 174 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28116 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 27866 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27716 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27523 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27754 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27794 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27566 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28230 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27914 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27706 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27921 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27830 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27718 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7631 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7398 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7277 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7173 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7281 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7238 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7147 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7771 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7465 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7554 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7296 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7212 # Track writes on a per bank basis +system.physmem.perBankRdReqs::2 27714 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27520 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27750 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27793 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27726 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27564 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28224 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27918 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27999 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27705 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27923 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27829 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27717 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7633 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7399 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7274 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7170 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7277 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7235 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7211 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7144 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7765 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7469 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7552 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7291 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7210 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 7327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7265 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7201 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7264 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7200 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1787 # Number of times wr buffer was full causing retry -system.physmem.totGap 1854304427000 # Total gap between requests +system.physmem.numWrRetry 946 # Number of times wr buffer was full causing retry +system.physmem.totGap 1854304705000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 445232 # Categorize read packet sizes +system.physmem.readPktSize::6 445214 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -97,7 +97,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 119231 # categorize write packet sizes +system.physmem.writePktSize::6 118367 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -106,31 +106,31 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 171 # categorize neither packet sizes +system.physmem.neitherpktsize::6 174 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 323360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2952 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2640 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1545 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1493 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 761 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 323357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7564 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2705 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2613 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1463 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1409 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1481 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -142,47 +142,47 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5093 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 7898633503 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15636428503 # Sum of mem lat for all requests -system.physmem.totBusLat 2225860000 # Total cycles spent in databus access -system.physmem.totBankLat 5511935000 # Total cycles spent in bank access -system.physmem.avgQLat 17742.88 # Average queueing delay per request -system.physmem.avgBankLat 12381.59 # Average bank access latency per request +system.physmem.totQLat 7913395266 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15649662766 # Sum of mem lat for all requests +system.physmem.totBusLat 2225790000 # Total cycles spent in databus access +system.physmem.totBankLat 5510477500 # Total cycles spent in bank access +system.physmem.avgQLat 17776.60 # Average queueing delay per request +system.physmem.avgBankLat 12378.70 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35124.47 # Average memory access latency +system.physmem.avgMemAccLat 35155.30 # Average memory access latency system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s @@ -190,21 +190,21 @@ system.physmem.avgConsumedWrBW 4.05 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.74 # Average write queue length over time -system.physmem.readRowHits 417598 # Number of row buffer hits during reads -system.physmem.writeRowHits 91555 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.96 # Row buffer hit rate for writes -system.physmem.avgGap 3295510.08 # Average gap between requests +system.physmem.avgWrQLen 11.52 # Average write queue length over time +system.physmem.readRowHits 417628 # Number of row buffer hits during reads +system.physmem.writeRowHits 91533 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.95 # Row buffer hit rate for writes +system.physmem.avgGap 3295750.72 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.265033 # Cycle average of tags in use +system.iocache.tagsinuse 1.265053 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1704476002000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.265033 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.079065 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.079065 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1704474436000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.265053 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -215,12 +215,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10574791806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10574791806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10595719804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10595719804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10595719804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10595719804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10610366806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10610366806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10631294804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10631294804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10631294804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10631294804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -239,17 +239,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254495.374615 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 254495.374615 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 253941.756836 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 253941.756836 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 253941.756836 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 253941.756836 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 280489 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255351.530757 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 255351.530757 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 254794.363188 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 254794.363188 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 282772 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27002 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27194 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.387712 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.398323 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -265,12 +265,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8412803020 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8412803020 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8424734270 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8424734270 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8424734270 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8424734270 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8448369274 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8448369274 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8460300524 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8460300524 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8460300524 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8460300524 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -281,12 +281,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202464.454659 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 202464.454659 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 201910.947154 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 201910.947154 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 201910.947154 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 201910.947154 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203320.400318 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 203320.400318 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -300,35 +300,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 13854519 # Number of BP lookups -system.cpu.branchPred.condPredicted 11622006 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 399782 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9584331 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5815567 # Number of BTB hits +system.cpu.branchPred.lookups 13838840 # Number of BP lookups +system.cpu.branchPred.condPredicted 11607895 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 399412 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9524270 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5814876 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 60.677861 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 905443 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 39042 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.053246 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 905729 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 39052 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9921013 # DTB read hits -system.cpu.dtb.read_misses 41705 # DTB read misses -system.cpu.dtb.read_acv 547 # DTB read access violations -system.cpu.dtb.read_accesses 941529 # DTB read accesses -system.cpu.dtb.write_hits 6598119 # DTB write hits -system.cpu.dtb.write_misses 10489 # DTB write misses -system.cpu.dtb.write_acv 411 # DTB write access violations -system.cpu.dtb.write_accesses 338424 # DTB write accesses -system.cpu.dtb.data_hits 16519132 # DTB hits -system.cpu.dtb.data_misses 52194 # DTB misses -system.cpu.dtb.data_acv 958 # DTB access violations -system.cpu.dtb.data_accesses 1279953 # DTB accesses -system.cpu.itb.fetch_hits 1307587 # ITB hits -system.cpu.itb.fetch_misses 36909 # ITB misses -system.cpu.itb.fetch_acv 1032 # ITB acv -system.cpu.itb.fetch_accesses 1344496 # ITB accesses +system.cpu.dtb.read_hits 9926019 # DTB read hits +system.cpu.dtb.read_misses 41533 # DTB read misses +system.cpu.dtb.read_acv 530 # DTB read access violations +system.cpu.dtb.read_accesses 942239 # DTB read accesses +system.cpu.dtb.write_hits 6593693 # DTB write hits +system.cpu.dtb.write_misses 10528 # DTB write misses +system.cpu.dtb.write_acv 400 # DTB write access violations +system.cpu.dtb.write_accesses 337995 # DTB write accesses +system.cpu.dtb.data_hits 16519712 # DTB hits +system.cpu.dtb.data_misses 52061 # DTB misses +system.cpu.dtb.data_acv 930 # DTB access violations +system.cpu.dtb.data_accesses 1280234 # DTB accesses +system.cpu.itb.fetch_hits 1304342 # ITB hits +system.cpu.itb.fetch_misses 39856 # ITB misses +system.cpu.itb.fetch_acv 1022 # ITB acv +system.cpu.itb.fetch_accesses 1344198 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -341,269 +341,269 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 109625107 # number of cpu cycles simulated +system.cpu.numCycles 109629781 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28053642 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 70690468 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13854519 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6721010 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 13247907 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1985368 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 37409434 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32200 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 254032 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 293409 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 622 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8552479 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 266219 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 80576938 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.877304 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.221000 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28054548 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 70673295 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13838840 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6720605 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 13244077 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1985157 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 37404215 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 256282 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 293547 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8545648 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 265175 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 80570729 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.877158 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.220803 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 67329031 83.56% 83.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 853166 1.06% 84.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1699610 2.11% 86.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 825917 1.03% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2751267 3.41% 91.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 561372 0.70% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 646563 0.80% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1011071 1.25% 93.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4898941 6.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 67326652 83.56% 83.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 851821 1.06% 84.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1698513 2.11% 86.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 825554 1.02% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2751975 3.42% 91.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 562639 0.70% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 645154 0.80% 92.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1011601 1.26% 93.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4896820 6.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 80576938 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126381 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.644838 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29188607 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37070199 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 12111886 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962831 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1243414 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 585279 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42689 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 69390201 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 129780 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1243414 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 30310150 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13624817 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 19789639 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11346848 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4262068 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65638780 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6929 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 510249 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1482252 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 43832025 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79671797 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79192798 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 478999 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38181176 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5650841 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1682596 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239958 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12134086 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10437264 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6898844 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1303944 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 867300 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58187512 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2050080 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 56823763 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 104138 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6892850 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3517048 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1389102 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 80576938 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.705211 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.366405 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 80570729 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126232 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.644654 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29191187 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37065229 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 12109046 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962419 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1242847 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 584292 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42668 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 69380603 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 129620 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1242847 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30314558 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13623750 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 19784463 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 11341758 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4263351 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65627824 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6945 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 510530 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1483365 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 43820100 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79668795 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79189543 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 479252 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38180356 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5639736 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1682796 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239926 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12145356 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10440685 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6902590 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1325482 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 872752 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58180873 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2047058 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 56813064 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 111741 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6883646 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3532849 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1386082 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 80570729 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.705133 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.366225 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55928630 69.41% 69.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10806018 13.41% 82.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5163609 6.41% 89.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3379495 4.19% 93.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2652407 3.29% 96.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1461056 1.81% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 758797 0.94% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 331056 0.41% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 95870 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55925631 69.41% 69.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10804122 13.41% 82.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5164072 6.41% 89.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3379310 4.19% 93.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2651147 3.29% 96.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1461283 1.81% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 759145 0.94% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 331157 0.41% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 94862 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 80576938 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 80570729 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 90990 11.53% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 373752 47.37% 58.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 324325 41.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 89963 11.41% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 373446 47.37% 58.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 325006 41.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 38746520 68.19% 68.20% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61714 0.11% 68.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 38735893 68.18% 68.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61716 0.11% 68.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10353275 18.22% 86.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6676641 11.75% 98.33% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949084 1.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10357569 18.23% 86.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6672257 11.74% 98.33% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949100 1.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 56823763 # Type of FU issued -system.cpu.iq.rate 0.518346 # Inst issue rate -system.cpu.iq.fu_busy_cnt 789067 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013886 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 194424766 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 66808135 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55585961 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 692902 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336093 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 56813064 # Type of FU issued +system.cpu.iq.rate 0.518227 # Inst issue rate +system.cpu.iq.fu_busy_cnt 788415 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013877 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 194404430 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 66788743 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55573367 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 692582 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336629 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 327887 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 57243591 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 361953 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 600271 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 57232794 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 361399 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 600057 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1344993 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3536 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14132 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 520971 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1348422 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4157 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14125 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 524715 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17952 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 173575 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17951 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 174954 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1243414 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9953615 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 683685 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 63765437 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 675848 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10437264 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6898844 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1805870 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 511832 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18204 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14132 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 202521 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411600 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 614121 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56355375 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 9990908 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 468387 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1242847 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9951157 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684131 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 63754506 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 676985 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10440685 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6902590 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1803123 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 512112 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18418 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14125 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 202045 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 411832 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 613877 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56345945 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 9995759 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 467118 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3527845 # number of nop insts executed -system.cpu.iew.exec_refs 16614745 # number of memory reference insts executed -system.cpu.iew.exec_branches 8928138 # Number of branches executed -system.cpu.iew.exec_stores 6623837 # Number of stores executed -system.cpu.iew.exec_rate 0.514074 # Inst execution rate -system.cpu.iew.wb_sent 56029038 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 55913848 # cumulative count of insts written-back -system.cpu.iew.wb_producers 27775021 # num instructions producing a value -system.cpu.iew.wb_consumers 37616621 # num instructions consuming a value +system.cpu.iew.exec_nop 3526575 # number of nop insts executed +system.cpu.iew.exec_refs 16615200 # number of memory reference insts executed +system.cpu.iew.exec_branches 8926807 # Number of branches executed +system.cpu.iew.exec_stores 6619441 # Number of stores executed +system.cpu.iew.exec_rate 0.513966 # Inst execution rate +system.cpu.iew.wb_sent 56016691 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 55901254 # cumulative count of insts written-back +system.cpu.iew.wb_producers 27769565 # num instructions producing a value +system.cpu.iew.wb_consumers 37614191 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.510046 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.738371 # average fanout of values written-back +system.cpu.iew.wb_rate 0.509909 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.738274 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7476360 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 660978 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 568527 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 79333524 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.708051 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.637595 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7465102 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 660976 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 568169 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 79327882 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.708087 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.637784 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58563645 73.82% 73.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8604221 10.85% 84.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4603933 5.80% 90.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2533514 3.19% 93.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1516762 1.91% 95.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 607132 0.77% 96.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 522001 0.66% 97.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 533698 0.67% 97.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1848618 2.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58561818 73.82% 73.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8602415 10.84% 84.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4601651 5.80% 90.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2532853 3.19% 93.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1516154 1.91% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 607730 0.77% 96.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 522045 0.66% 97.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 534524 0.67% 97.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1848692 2.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 79333524 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56172173 # Number of instructions committed -system.cpu.commit.committedOps 56172173 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 79327882 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56171016 # Number of instructions committed +system.cpu.commit.committedOps 56171016 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15470144 # Number of memory references committed -system.cpu.commit.loads 9092271 # Number of loads committed +system.cpu.commit.refs 15470138 # Number of memory references committed +system.cpu.commit.loads 9092263 # Number of loads committed system.cpu.commit.membars 226349 # Number of memory barriers committed -system.cpu.commit.branches 8440686 # Number of branches committed +system.cpu.commit.branches 8440338 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52021801 # Number of committed integer instructions. -system.cpu.commit.function_calls 740555 # Number of function calls committed. -system.cpu.commit.bw_lim_events 1848618 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 52020652 # Number of committed integer instructions. +system.cpu.commit.function_calls 740552 # Number of function calls committed. +system.cpu.commit.bw_lim_events 1848692 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 140883934 # The number of ROB reads -system.cpu.rob.rob_writes 128542305 # The number of ROB writes -system.cpu.timesIdled 1179238 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29048169 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3598988155 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52981417 # Number of Instructions Simulated -system.cpu.committedOps 52981417 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 52981417 # Number of Instructions Simulated -system.cpu.cpi 2.069124 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.069124 # CPI: Total CPI of All Threads -system.cpu.ipc 0.483296 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.483296 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 73895852 # number of integer regfile reads -system.cpu.int_regfile_writes 40324169 # number of integer regfile writes -system.cpu.fp_regfile_reads 166027 # number of floating regfile reads -system.cpu.fp_regfile_writes 167433 # number of floating regfile writes -system.cpu.misc_regfile_reads 1987804 # number of misc regfile reads -system.cpu.misc_regfile_writes 938984 # number of misc regfile writes +system.cpu.rob.rob_reads 140865752 # The number of ROB reads +system.cpu.rob.rob_writes 128516921 # The number of ROB writes +system.cpu.timesIdled 1179002 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29059052 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3598984001 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52980262 # Number of Instructions Simulated +system.cpu.committedOps 52980262 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 52980262 # Number of Instructions Simulated +system.cpu.cpi 2.069257 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.069257 # CPI: Total CPI of All Threads +system.cpu.ipc 0.483265 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.483265 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 73880365 # number of integer regfile reads +system.cpu.int_regfile_writes 40316413 # number of integer regfile writes +system.cpu.fp_regfile_reads 166011 # number of floating regfile reads +system.cpu.fp_regfile_writes 167446 # number of floating regfile writes +system.cpu.misc_regfile_reads 1987331 # number of misc regfile reads +system.cpu.misc_regfile_writes 938994 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -635,189 +635,189 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 1009308 # number of replacements -system.cpu.icache.tagsinuse 510.238404 # Cycle average of tags in use -system.cpu.icache.total_refs 7486940 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1009816 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.414163 # Average number of references to valid blocks. +system.cpu.icache.replacements 1008798 # number of replacements +system.cpu.icache.tagsinuse 510.238342 # Cycle average of tags in use +system.cpu.icache.total_refs 7480626 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1009306 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.411653 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 20723156000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.238404 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 510.238342 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.996559 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996559 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7486941 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7486941 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7486941 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7486941 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7486941 # number of overall hits -system.cpu.icache.overall_hits::total 7486941 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1065537 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1065537 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1065537 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1065537 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1065537 # number of overall misses -system.cpu.icache.overall_misses::total 1065537 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14679368493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14679368493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14679368493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14679368493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14679368493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14679368493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8552478 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8552478 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8552478 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8552478 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8552478 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8552478 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124588 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124588 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124588 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124588 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124588 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124588 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13776.498135 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13776.498135 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13776.498135 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13776.498135 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13776.498135 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13776.498135 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6928 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 616 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 184 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 37.652174 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 308 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 7480627 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7480627 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7480627 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7480627 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7480627 # number of overall hits +system.cpu.icache.overall_hits::total 7480627 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1065018 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1065018 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1065018 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1065018 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1065018 # number of overall misses +system.cpu.icache.overall_misses::total 1065018 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14700112992 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14700112992 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14700112992 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14700112992 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14700112992 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14700112992 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8545645 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8545645 # 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number of cycles access was blocked @@ -826,72 +826,72 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75932 # number of writebacks -system.cpu.l2cache.writebacks::total 75932 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75909 # number of writebacks +system.cpu.l2cache.writebacks::total 75909 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 864374583 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15318152679 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16182527262 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 864374583 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15318152679 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16182527262 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333805500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333805500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882511000 # 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average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14700.885714 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14700.885714 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54224.939947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54224.939947 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57368.725227 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39358.251273 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40029.503573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57368.725227 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39358.251273 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40029.503573 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -899,161 +899,161 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1401345 # number of replacements +system.cpu.dcache.replacements 1401332 # number of replacements system.cpu.dcache.tagsinuse 511.995159 # Cycle average of tags in use -system.cpu.dcache.total_refs 11814052 # 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number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306015000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 306015000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 99654728857 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 99654728857 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 99654728857 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 99654728857 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9010982 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9010982 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147652 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147652 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208748 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 208748 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 99463796398 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 99463796398 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 99463796398 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 99463796398 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9014722 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9014722 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147654 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147654 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208812 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 208812 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 215521 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 215521 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15158634 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15158634 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15158634 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15158634 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200134 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.200134 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316042 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316042 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108978 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108978 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_accesses::cpu.data 15162376 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15162376 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15162376 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15162376 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199959 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.199959 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316015 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316015 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108945 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108945 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247141 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247141 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247141 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247141 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19048.951425 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19048.951425 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33610.193460 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33610.193460 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13445.360236 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13445.360236 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.247014 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247014 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247014 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247014 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19046.236860 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19046.236860 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33525.443289 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33525.443289 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13451.800079 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13451.800079 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26600.712715 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26600.712715 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26600.712715 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26600.712715 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2209173 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1658 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 95967 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26556.786500 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26556.786500 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26556.786500 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26556.786500 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2193487 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 506 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 95928 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 23.020132 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 236.857143 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.865972 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 72.285714 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 840942 # number of writebacks -system.cpu.dcache.writebacks::total 840942 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 719404 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 719404 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642459 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1642459 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5206 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5206 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2361863 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2361863 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2361863 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2361863 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083996 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1083996 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300459 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300459 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17543 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17543 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 840875 # number of writebacks +system.cpu.dcache.writebacks::total 840875 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718560 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 718560 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642321 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1642321 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5210 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5210 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2360881 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2360881 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2360881 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2360881 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084017 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1084017 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300427 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300427 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17539 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17539 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384455 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384455 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384455 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384455 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21792492000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21792492000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9914016773 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9914016773 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199792500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199792500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1384444 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384444 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384444 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384444 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21793042000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21793042000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9888893772 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9888893772 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199306000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199306000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31706508773 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31706508773 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31706508773 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31706508773 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423893000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423893000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997872998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997872998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421765998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421765998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120297 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120297 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048874 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048874 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084039 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084039 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31681935772 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31681935772 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31681935772 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31681935772 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423882500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423882500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997678998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997678998 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421561498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421561498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120250 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120250 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048869 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048869 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083994 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083994 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091331 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091331 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091331 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091331 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20103.849092 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20103.849092 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32996.238332 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32996.238332 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11388.730548 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11388.730548 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091308 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091308 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20103.967004 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20103.967004 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32916.128617 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32916.128617 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11363.589714 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11363.589714 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22901.798017 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22901.798017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22901.798017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22901.798017 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1062,28 +1062,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211023 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211025 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74671 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182254 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105575 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182256 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73304 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73304 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817865196000 98.03% 98.03% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 63825500 0.00% 98.04% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 556558000 0.03% 98.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 35823437500 1.93% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1854309017000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1817868211500 98.03% 98.03% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 63824000 0.00% 98.04% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 559692500 0.03% 98.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 35817544000 1.93% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1854309272000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694344 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815444 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694331 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815435 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1122,7 +1122,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175139 91.23% 93.44% # number of callpals executed +system.cpu.kern.callpal::swpipl 175141 91.23% 93.44% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1131,20 +1131,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191983 # number of callpals executed +system.cpu.kern.callpal::total 191985 # number of callpals executed system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326210 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326552 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394052 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29463172000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2708574500 0.15% 1.73% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1822137262500 98.27% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29467227000 1.59% 1.59% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2708568500 0.15% 1.74% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1822133468500 98.26% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini index 0afd8d12c..d353d9284 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini @@ -12,15 +12,15 @@ children=bridge cpu0 cpu1 cpu2 disk0 disk2 intrctrl iobus iocache l2c membus phy boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 clock=1000 -console=/scratch/nilay/GEM5/system/binaries/console +console=/projects/pd/randd/dist/binaries/console init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/projects/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/projects/pd/randd/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -581,7 +581,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -601,7 +601,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -669,6 +669,7 @@ children=badaddr_responder block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -694,25 +695,27 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false @@ -726,7 +729,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/projects/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -741,6 +744,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 97e7b92d5..014619ced 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.841686 # Nu sim_ticks 1841685645500 # Number of ticks simulated final_tick 1841685645500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 340884 # Simulator instruction rate (inst/s) -host_op_rate 340884 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9045969324 # Simulator tick rate (ticks/s) -host_mem_usage 315876 # Number of bytes of host memory used -host_seconds 203.59 # Real time elapsed on the host +host_inst_rate 300759 # Simulator instruction rate (inst/s) +host_op_rate 300759 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7981184825 # Simulator tick rate (ticks/s) +host_mem_usage 313952 # Number of bytes of host memory used +host_seconds 230.75 # Real time elapsed on the host sim_insts 69401254 # Number of instructions simulated sim_ops 69401254 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 474368 # Number of bytes read from this memory @@ -195,14 +195,14 @@ system.physmem.wrQLenPdf::29 9 # Wh system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2420382927 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4417685427 # Sum of mem lat for all requests +system.physmem.totQLat 2420387927 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4417690427 # Sum of mem lat for all requests system.physmem.totBusLat 546485000 # Total cycles spent in databus access system.physmem.totBankLat 1450817500 # Total cycles spent in bank access -system.physmem.avgQLat 22145.01 # Average queueing delay per request +system.physmem.avgQLat 22145.05 # Average queueing delay per request system.physmem.avgBankLat 13274.08 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40419.09 # Average memory access latency +system.physmem.avgMemAccLat 40419.14 # Average memory access latency system.physmem.avgRdBW 3.80 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.80 # Average consumed read bandwidth in MB/s @@ -218,17 +218,17 @@ system.physmem.writeRowHitRate 75.40 # Ro system.physmem.avgGap 11888044.99 # Average gap between requests system.l2c.replacements 337419 # number of replacements system.l2c.tagsinuse 65421.239766 # Cycle average of tags in use -system.l2c.total_refs 2475143 # Total number of references to valid blocks. +system.l2c.total_refs 2475144 # Total number of references to valid blocks. system.l2c.sampled_refs 402581 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.148186 # Average number of references to valid blocks. +system.l2c.avg_refs 6.148189 # Average number of references to valid blocks. system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. system.l2c.occ_blocks::writebacks 54789.025804 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.inst 2312.416873 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2671.189078 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2671.189079 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.inst 589.820867 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.data 668.130775 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu2.inst 2247.184130 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 2143.472239 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 2143.472240 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.836014 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.035285 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.040759 # Average percentage of cache occupancy @@ -241,9 +241,9 @@ system.l2c.ReadReq_hits::cpu0.inst 513915 # nu system.l2c.ReadReq_hits::cpu0.data 491176 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 126581 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.data 82893 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 298491 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 298492 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.data 243008 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1756064 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1756065 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 836144 # number of Writeback hits system.l2c.Writeback_hits::total 836144 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits @@ -258,16 +258,16 @@ system.l2c.demand_hits::cpu0.inst 513915 # nu system.l2c.demand_hits::cpu0.data 583228 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 126581 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 109937 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 298491 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 298492 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 310850 # number of demand (read+write) hits -system.l2c.demand_hits::total 1943002 # number of demand (read+write) hits +system.l2c.demand_hits::total 1943003 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 513915 # number of overall hits system.l2c.overall_hits::cpu0.data 583228 # number of overall hits system.l2c.overall_hits::cpu1.inst 126581 # number of overall hits system.l2c.overall_hits::cpu1.data 109937 # number of overall hits -system.l2c.overall_hits::cpu2.inst 298491 # number of overall hits +system.l2c.overall_hits::cpu2.inst 298492 # number of overall hits system.l2c.overall_hits::cpu2.data 310850 # number of overall hits -system.l2c.overall_hits::total 1943002 # number of overall hits +system.l2c.overall_hits::total 1943003 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 7412 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 226081 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 2348 # number of ReadReq misses @@ -298,31 +298,31 @@ system.l2c.overall_misses::cpu2.data 41751 # nu system.l2c.overall_misses::total 403338 # number of overall misses system.l2c.ReadReq_miss_latency::cpu1.inst 154067000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 1052058500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 311891000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 311896500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.data 1117922000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2635938500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2635944000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu2.data 295000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 295000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 978615000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 978614500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu2.data 1291616000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2270231000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2270230500 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu1.inst 154067000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2030673500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 311891000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2030673000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 311896500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.data 2409538000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 4906169500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 4906174500 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.inst 154067000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2030673500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 311891000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2030673000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 311896500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.data 2409538000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 4906169500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 4906174500 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 521327 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 717257 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 128929 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 105873 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 303084 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 303085 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 267156 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2043626 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2043627 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 836144 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 836144 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses) @@ -337,16 +337,16 @@ system.l2c.demand_accesses::cpu0.inst 521327 # nu system.l2c.demand_accesses::cpu0.data 886464 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 128929 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.data 153935 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 303084 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 303085 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.data 352601 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2346340 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2346341 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 521327 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 886464 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 128929 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 153935 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 303084 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 303085 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.data 352601 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2346340 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2346341 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.014218 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.315202 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.018212 # miss rate for ReadReq accesses @@ -377,24 +377,24 @@ system.l2c.overall_miss_rate::cpu2.data 0.118409 # mi system.l2c.overall_miss_rate::total 0.171901 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu1.inst 65616.269165 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 45781.483899 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 67905.726105 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 67906.923579 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.data 46294.599967 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 9166.504962 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 9166.524089 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 26818.181818 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 15526.315789 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46560.805024 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46560.781235 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 73374.765665 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 19608.822208 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 19608.817890 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 65616.269165 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 46153.768353 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 67905.726105 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 46153.756989 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 67906.923579 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.data 57712.102704 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 12163.915872 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 12163.928269 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 65616.269165 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 46153.768353 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 67905.726105 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 46153.756989 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 67906.923579 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.data 57712.102704 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 12163.915872 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 12163.928269 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -427,9 +427,9 @@ system.l2c.overall_mshr_misses::cpu2.data 41751 # n system.l2c.overall_mshr_misses::total 92690 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 124527350 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 769462495 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 254593394 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 254598394 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.data 825079853 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1973663092 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1973668092 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 271507 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 271507 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 718879972 # number of ReadExReq MSHR miss cycles @@ -437,23 +437,23 @@ system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1076725373 system.l2c.ReadExReq_mshr_miss_latency::total 1795605345 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 124527350 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.data 1488342467 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 254593394 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 254598394 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.data 1901805226 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 3769268437 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 3769273437 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 124527350 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.data 1488342467 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 254593394 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 254598394 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.data 1901805226 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 3769268437 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 3769273437 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 269404000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 320096500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 589500500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 320097000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 589501000 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 337106000 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 394521000 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 731627000 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.data 606510000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 714617500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1321127500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 714618000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1321128000 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018212 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.217053 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015154 # mshr miss rate for ReadReq accesses @@ -476,9 +476,9 @@ system.l2c.overall_mshr_miss_rate::cpu2.data 0.118409 system.l2c.overall_mshr_miss_rate::total 0.039504 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 53035.498296 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 33484.007615 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 55430.741128 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 55431.829741 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 34167.626843 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 36502.674213 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 36502.766687 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 24682.454545 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 24682.454545 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34203.062708 # average ReadExReq mshr miss latency @@ -486,14 +486,14 @@ system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61167.151792 system.l2c.ReadExReq_avg_mshr_miss_latency::total 46492.979079 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 53035.498296 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33827.502773 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 55430.741128 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 55431.829741 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 45551.129937 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40665.319204 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40665.373147 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 53035.498296 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33827.502773 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 55430.741128 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 55431.829741 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 45551.129937 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40665.319204 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40665.373147 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -612,7 +612,7 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4870224 # DTB read hits +system.cpu0.dtb.read_hits 4870222 # DTB read hits system.cpu0.dtb.read_misses 6004 # DTB read misses system.cpu0.dtb.read_acv 119 # DTB read access violations system.cpu0.dtb.read_accesses 427226 # DTB read accesses @@ -620,7 +620,7 @@ system.cpu0.dtb.write_hits 3495920 # DT system.cpu0.dtb.write_misses 662 # DTB write misses system.cpu0.dtb.write_acv 82 # DTB write access violations system.cpu0.dtb.write_accesses 162893 # DTB write accesses -system.cpu0.dtb.data_hits 8366144 # DTB hits +system.cpu0.dtb.data_hits 8366142 # DTB hits system.cpu0.dtb.data_misses 6666 # DTB misses system.cpu0.dtb.data_acv 201 # DTB access violations system.cpu0.dtb.data_accesses 590119 # DTB accesses @@ -645,18 +645,18 @@ system.cpu0.numWorkItemsStarted 0 # nu system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 32346409 # Number of instructions committed system.cpu0.committedOps 32346409 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 30227601 # Number of integer alu accesses +system.cpu0.num_int_alu_accesses 30227600 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 167714 # Number of float alu accesses system.cpu0.num_func_calls 807221 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 4255838 # number of instructions that are conditional controls -system.cpu0.num_int_insts 30227601 # number of integer instructions +system.cpu0.num_int_insts 30227600 # number of integer instructions system.cpu0.num_fp_insts 167714 # number of float instructions -system.cpu0.num_int_register_reads 42120333 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22107858 # number of times the integer registers were written +system.cpu0.num_int_register_reads 42120330 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22107857 # number of times the integer registers were written system.cpu0.num_fp_register_reads 86620 # number of times the floating registers were read system.cpu0.num_fp_register_writes 88185 # number of times the floating registers were written -system.cpu0.num_mem_refs 8395831 # number of memory refs -system.cpu0.num_load_insts 4891260 # Number of load instructions +system.cpu0.num_mem_refs 8395829 # number of memory refs +system.cpu0.num_load_insts 4891258 # Number of load instructions system.cpu0.num_store_insts 3504571 # Number of store instructions system.cpu0.num_idle_cycles 213109834303.356140 # Number of idle cycles system.cpu0.num_busy_cycles -212181309746.356140 # Number of busy cycles @@ -675,10 +675,10 @@ system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # nu system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73429 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148939 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818585880000 98.75% 98.75% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39023000 0.00% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1818585888500 98.75% 98.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39023500 0.00% 98.75% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 363355500 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22696630500 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22696621500 1.23% 100.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::total 1841684889000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl @@ -743,8 +743,8 @@ system.cpu0.kern.mode_switch_good::kernel 0.322134 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29741942000 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2557109000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 29741940500 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2557110500 0.14% 1.75% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 1809385834500 98.25% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA @@ -778,85 +778,85 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # 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number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 32353276 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7863788 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2608245 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 42825309 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7863784 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2608251 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 42825311 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 32353276 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7863788 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2608245 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 42825309 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7863784 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2608251 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 42825311 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 32353276 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7863788 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2608245 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 42825309 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7863784 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2608251 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 42825311 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016114 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016395 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122714 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122715 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.022658 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016114 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016395 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122714 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122715 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.022658 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016114 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016395 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122714 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122715 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.022658 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14069.483980 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13977.681331 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6479.943222 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13977.672168 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6479.963380 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14069.483980 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13977.681331 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6479.943222 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13977.672168 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6479.963380 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14069.483980 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13977.681331 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6479.943222 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13977.672168 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6479.963380 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 5140 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 170 # number of cycles access was blocked @@ -865,30 +865,30 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.235294 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16973 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16973 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16973 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16973 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16973 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16973 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16975 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16975 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16975 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16975 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16975 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16975 # number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 128929 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 303096 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 432025 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 303097 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 432026 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu1.inst 128929 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 303096 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 432025 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 303097 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 432026 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu1.inst 128929 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 303096 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 432025 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 303097 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 432026 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1556106500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3684192488 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5240298988 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3684207988 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5240314488 # number of ReadReq MSHR miss cycles system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1556106500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3684192488 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5240298988 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3684207988 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5240314488 # number of demand (read+write) MSHR miss cycles system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1556106500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3684192488 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5240298988 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3684207988 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5240314488 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016395 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116207 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010088 # mshr miss rate for ReadReq accesses @@ -899,32 +899,32 @@ system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016395 system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116207 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.010088 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12069.483980 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12155.199963 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12129.619786 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12155.210998 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12129.627587 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12069.483980 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12155.199963 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12129.619786 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12155.210998 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12129.627587 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12069.483980 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12155.199963 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12129.619786 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12155.210998 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12129.627587 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 1392453 # number of replacements system.cpu0.dcache.tagsinuse 511.997817 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13322506 # Total number of references to valid blocks. +system.cpu0.dcache.total_refs 13322507 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 1392965 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.564135 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 9.564136 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 248.356870 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu0.data 248.356869 # Average occupied blocks per requestor system.cpu0.dcache.occ_blocks::cpu1.data 87.947367 # Average occupied blocks per requestor system.cpu0.dcache.occ_blocks::cpu2.data 175.693580 # Average occupied blocks per requestor system.cpu0.dcache.occ_percent::cpu0.data 0.485072 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::cpu1.data 0.171772 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::cpu2.data 0.343152 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4047371 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 4047369 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 1097591 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2422188 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7567150 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2422191 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7567151 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 3200230 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu1.data 858461 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu2.data 1312963 # number of WriteReq hits @@ -937,14 +937,14 @@ system.cpu0.dcache.StoreCondReq_hits::cpu0.data 125392 system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21336 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu2.data 52561 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 199289 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7247601 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 7247599 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::cpu1.data 1956052 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3735151 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12938804 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7247601 # number of overall hits +system.cpu0.dcache.demand_hits::cpu2.data 3735154 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12938805 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7247599 # number of overall hits system.cpu0.dcache.overall_hits::cpu1.data 1956052 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3735151 # number of overall hits -system.cpu0.dcache.overall_hits::total 12938804 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3735154 # number of overall hits +system.cpu0.dcache.overall_hits::total 12938805 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 707756 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu1.data 103680 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::cpu2.data 547661 # number of ReadReq misses @@ -966,24 +966,24 @@ system.cpu0.dcache.overall_misses::cpu1.data 151743 system.cpu0.dcache.overall_misses::cpu2.data 1110663 # number of overall misses system.cpu0.dcache.overall_misses::total 2139380 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2172880000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9444240500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11617120500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1393922000 # number of WriteReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9444239000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11617119000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1393921500 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 14767149219 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 16161071219 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 16161070719 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28928500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 105213000 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 134141500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 3566802000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 24211389719 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 27778191719 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3566802000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 24211389719 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 27778191719 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4755127 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu1.data 3566801500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 24211388219 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 27778189719 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 3566801500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 24211388219 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 27778189719 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4755125 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::cpu1.data 1201271 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 2969849 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8926247 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 2969852 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8926248 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 3369448 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu1.data 906524 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu2.data 1875965 # number of WriteReq accesses(hits+misses) @@ -996,18 +996,18 @@ system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 125392 system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21336 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 52561 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 199289 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8124575 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 8124573 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::cpu1.data 2107795 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 4845814 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15078184 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8124575 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 4845817 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15078185 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8124573 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::cpu1.data 2107795 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 4845814 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15078184 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 4845817 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15078185 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.148841 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.086309 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.184407 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.152259 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.152258 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050221 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.053019 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.300113 # miss rate for WriteReq accesses @@ -1018,27 +1018,27 @@ system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.125879 system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092079 # miss rate for LoadLockedReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.107941 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::cpu1.data 0.071991 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.229201 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.229200 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.141886 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107941 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::cpu1.data 0.071991 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.229201 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.229200 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.141886 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 20957.561728 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17244.683299 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8547.675773 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29001.976572 # average WriteReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17244.680560 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8547.674669 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29001.966169 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26229.301528 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20711.807407 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20711.806766 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13191.290470 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15026.135390 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7174.876979 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23505.545561 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 21799.042301 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 12984.225205 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23505.545561 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21799.042301 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12984.225205 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23505.542266 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 21799.040950 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 12984.224270 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23505.542266 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21799.040950 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12984.224270 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 420237 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 580 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 16818 # number of cycles access was blocked @@ -1075,29 +1075,29 @@ system.cpu0.dcache.overall_mshr_misses::cpu1.data 151743 system.cpu0.dcache.overall_mshr_misses::cpu2.data 347122 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 498865 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1965520000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4314581000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6280101000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1297796000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4314579500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6280099500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1297795500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2151055620 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3448851620 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3448851120 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24542500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69880000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94422500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3263316000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6465636620 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9728952620 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3263316000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6465636620 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9728952620 # number of overall MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3263315500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6465635120 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9728950620 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3263315500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6465635120 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9728950620 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287578500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342019500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 629598000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342020000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 629598500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357171000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 418642000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 775813000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 644749500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 760661500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1405411000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 760662000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1405411500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086309 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088191 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040957 # mshr miss rate for ReadReq accesses @@ -1114,20 +1114,20 @@ system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.071991 system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071633 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.033085 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18957.561728 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16473.273670 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17177.801058 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27001.976572 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16473.267943 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17177.796955 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27001.966169 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25244.761290 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25878.485342 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25878.481590 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11191.290470 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12723.962127 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12286.597267 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21505.545561 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18626.409793 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19502.175178 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21505.545561 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18626.409793 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19502.175178 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21505.542266 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18626.405471 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19502.171169 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21505.542266 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18626.405471 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19502.171169 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1170,26 +1170,26 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953544050 # number of cpu cycles simulated +system.cpu1.numCycles 953544041 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7861954 # Number of instructions committed -system.cpu1.committedOps 7861954 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 7314134 # Number of integer alu accesses +system.cpu1.committedInsts 7861950 # Number of instructions committed +system.cpu1.committedOps 7861950 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7314131 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 45433 # Number of float alu accesses system.cpu1.num_func_calls 212083 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 960162 # number of instructions that are conditional controls -system.cpu1.num_int_insts 7314134 # number of integer instructions +system.cpu1.num_int_insts 7314131 # number of integer instructions system.cpu1.num_fp_insts 45433 # number of float instructions -system.cpu1.num_int_register_reads 10166177 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5323216 # number of times the integer registers were written +system.cpu1.num_int_register_reads 10166174 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5323213 # number of times the integer registers were written system.cpu1.num_fp_register_reads 24545 # number of times the floating registers were read system.cpu1.num_fp_register_writes 24803 # number of times the floating registers were written system.cpu1.num_mem_refs 2156447 # number of memory refs system.cpu1.num_load_insts 1225739 # Number of load instructions system.cpu1.num_store_insts 930708 # Number of store instructions -system.cpu1.num_idle_cycles 195910529.325868 # Number of idle cycles -system.cpu1.num_busy_cycles 757633520.674132 # Number of busy cycles +system.cpu1.num_idle_cycles 195910527.476772 # Number of idle cycles +system.cpu1.num_busy_cycles 757633513.523228 # Number of busy cycles system.cpu1.not_idle_fraction 0.794545 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.205455 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -1209,35 +1209,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 8412637 # Number of BP lookups +system.cpu2.branchPred.lookups 8412639 # Number of BP lookups system.cpu2.branchPred.condPredicted 7718594 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 129281 # Number of conditional branches incorrect +system.cpu2.branchPred.condIncorrect 129283 # Number of conditional branches incorrect system.cpu2.branchPred.BTBLookups 6816710 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5762098 # Number of BTB hits +system.cpu2.branchPred.BTBHits 5762097 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 84.529018 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 288280 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 84.529003 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 288281 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 15520 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3230835 # DTB read hits +system.cpu2.dtb.read_hits 3230838 # DTB read hits system.cpu2.dtb.read_misses 11458 # DTB read misses system.cpu2.dtb.read_acv 112 # DTB read access violations system.cpu2.dtb.read_accesses 217040 # DTB read accesses -system.cpu2.dtb.write_hits 2001660 # DTB write hits +system.cpu2.dtb.write_hits 2001661 # DTB write hits system.cpu2.dtb.write_misses 2605 # DTB write misses system.cpu2.dtb.write_acv 143 # DTB write access violations system.cpu2.dtb.write_accesses 81606 # DTB write accesses -system.cpu2.dtb.data_hits 5232495 # DTB hits +system.cpu2.dtb.data_hits 5232499 # DTB hits system.cpu2.dtb.data_misses 14063 # DTB misses system.cpu2.dtb.data_acv 255 # DTB access violations system.cpu2.dtb.data_accesses 298646 # DTB accesses -system.cpu2.itb.fetch_hits 371714 # ITB hits +system.cpu2.itb.fetch_hits 371716 # ITB hits system.cpu2.itb.fetch_misses 5691 # ITB misses system.cpu2.itb.fetch_acv 245 # ITB acv -system.cpu2.itb.fetch_accesses 377405 # ITB accesses +system.cpu2.itb.fetch_accesses 377407 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1250,98 +1250,98 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30535701 # number of cpu cycles simulated +system.cpu2.numCycles 30535693 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 8533986 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 34964689 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 8412637 # Number of branches that fetch encountered +system.cpu2.fetch.icacheStallCycles 8533990 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 34964700 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 8412639 # Number of branches that fetch encountered system.cpu2.fetch.predictedBranches 6050378 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 8133499 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 621333 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 9684422 # Number of cycles fetch has spent blocked +system.cpu2.fetch.Cycles 8133501 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 621341 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 9684407 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 10316 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain system.cpu2.fetch.PendingTrapStallCycles 62496 # Number of stall cycles due to pending traps system.cpu2.fetch.PendingQuiesceStallCycles 78611 # Number of stall cycles due to pending quiesce instructions system.cpu2.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2608249 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 90274 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 26910354 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.299302 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.CacheLines 2608255 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 90277 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 26910349 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.299303 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::stdev 2.309788 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 18776855 69.78% 69.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 18776848 69.78% 69.78% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::1 272793 1.01% 70.79% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::2 440434 1.64% 72.43% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4254201 15.81% 88.23% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4254202 15.81% 88.23% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::4 737771 2.74% 90.98% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::5 167398 0.62% 91.60% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::6 196636 0.73% 92.33% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::7 433593 1.61% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1630673 6.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1630674 6.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 26910354 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::total 26910349 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.branchRate 0.275502 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.145043 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8661365 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 9779402 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7537150 # Number of cycles decode is running +system.cpu2.fetch.rate 1.145044 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8661368 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 9779389 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7537152 # Number of cycles decode is running system.cpu2.decode.UnblockCycles 294171 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 392382 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 168927 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 12968 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34563094 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 40757 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 392382 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 9017323 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 2819487 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5795757 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 7393744 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1245786 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33400489 # Number of instructions processed by rename +system.cpu2.decode.SquashCycles 392385 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 168928 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 12969 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34563096 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 40760 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 392385 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 9017327 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2819479 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 5795758 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7393745 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1245780 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33400490 # Number of instructions processed by rename system.cpu2.rename.ROBFullEvents 2356 # Number of times rename has blocked due to ROB full system.cpu2.rename.IQFullEvents 234346 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 410991 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 22419821 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41624595 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41459018 # Number of integer rename lookups +system.cpu2.rename.LSQFullEvents 410986 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 22419818 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 41624592 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41459015 # Number of integer rename lookups system.cpu2.rename.fp_rename_lookups 165577 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20586998 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1832823 # Number of HB maps that are undone due to squashing +system.cpu2.rename.CommittedMaps 20587002 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1832816 # Number of HB maps that are undone due to squashing system.cpu2.rename.serializingInsts 505460 # count of serializing insts renamed system.cpu2.rename.tempSerializingInsts 60216 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3692928 # count of insts added to the skid buffer +system.cpu2.rename.skidInsts 3692921 # count of insts added to the skid buffer system.cpu2.memDep0.insertedLoads 3393863 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2097985 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 374320 # Number of conflicting loads. +system.cpu2.memDep0.insertedStores 2097986 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 374319 # Number of conflicting loads. system.cpu2.memDep0.conflictingStores 252386 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30872998 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqInstsAdded 30873003 # Number of instructions added to the IQ (excludes non-spec) system.cpu2.iq.iqNonSpecInstsAdded 630971 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30415497 # Number of instructions issued +system.cpu2.iq.iqInstsIssued 30415505 # Number of instructions issued system.cpu2.iq.iqSquashedInstsIssued 38395 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2194504 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1105046 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedInstsExamined 2194500 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1105040 # Number of squashed operands that are examined and possibly removed from graph system.cpu2.iq.iqSquashedNonSpecRemoved 445283 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 26910354 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::samples 26910349 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::mean 1.130253 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.565604 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.565605 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 15319537 56.93% 56.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3107474 11.55% 68.48% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1555934 5.78% 74.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5075643 18.86% 93.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 913365 3.39% 96.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 492006 1.83% 98.34% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 286832 1.07% 99.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 15319532 56.93% 56.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3107477 11.55% 68.48% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1555924 5.78% 74.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5075651 18.86% 93.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 913363 3.39% 96.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 492005 1.83% 98.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 286833 1.07% 99.41% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::7 141760 0.53% 99.93% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 17803 0.07% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 17804 0.07% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 26910354 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 26910349 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IntAlu 34989 13.90% 13.90% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 0 0.00% 13.90% # attempts to use FU when none available @@ -1377,7 +1377,7 @@ system.cpu2.iq.fu_full::MemWrite 103504 41.11% 100.00% # at system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2444 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24705605 81.23% 81.24% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 24705611 81.23% 81.24% # Type of FU issued system.cpu2.iq.FU_type_0::IntMult 20302 0.07% 81.30% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.30% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 8486 0.03% 81.33% # Type of FU issued @@ -1406,110 +1406,110 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.33% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.33% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3362289 11.05% 92.39% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2024695 6.66% 99.05% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3362290 11.05% 92.39% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2024696 6.66% 99.05% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 290454 0.95% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30415497 # Type of FU issued -system.cpu2.iq.rate 0.996063 # Inst issue rate +system.cpu2.iq.FU_type_0::total 30415505 # Type of FU issued +system.cpu2.iq.rate 0.996064 # Inst issue rate system.cpu2.iq.fu_busy_cnt 251803 # FU busy when requested system.cpu2.iq.fu_busy_rate 0.008279 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 87793643 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33586183 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 30009832 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.int_inst_queue_reads 87793654 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 33586184 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 30009842 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 237903 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 116334 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 112629 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30540939 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 30540947 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 123917 # Number of floating point alu accesses system.cpu2.iew.lsq.thread0.forwLoads 191281 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 420182 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 420180 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 991 # Number of memory responses ignored because the instruction is squashed system.cpu2.iew.lsq.thread0.memOrderViolation 4150 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 166078 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedStores 166079 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 4737 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 23355 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 392382 # Number of cycles IEW is squashing +system.cpu2.iew.iewSquashCycles 392385 # Number of cycles IEW is squashing system.cpu2.iew.iewBlockCycles 2039220 # Number of cycles IEW is blocking system.cpu2.iew.iewUnblockCycles 211536 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32790346 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 224393 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispatchedInsts 32790350 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 224390 # Number of squashed instructions skipped by dispatch system.cpu2.iew.iewDispLoadInsts 3393863 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2097985 # Number of dispatched store instructions +system.cpu2.iew.iewDispStoreInsts 2097986 # Number of dispatched store instructions system.cpu2.iew.iewDispNonSpecInsts 560382 # Number of dispatched non-speculative instructions system.cpu2.iew.iewIQFullEvents 149727 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 2248 # Number of times the LSQ has become full, causing a stall system.cpu2.iew.memOrderViolationEvents 4150 # Number of memory order violations system.cpu2.iew.predictedTakenIncorrect 66680 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 129830 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196510 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30250738 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3250585 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 164759 # Number of squashed instructions skipped in execute +system.cpu2.iew.predictedNotTakenIncorrect 129831 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 196511 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 30250749 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3250588 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 164756 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1286377 # number of nop insts executed -system.cpu2.iew.exec_refs 5259361 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6817854 # Number of branches executed -system.cpu2.iew.exec_stores 2008776 # Number of stores executed +system.cpu2.iew.exec_nop 1286376 # number of nop insts executed +system.cpu2.iew.exec_refs 5259365 # number of memory reference insts executed +system.cpu2.iew.exec_branches 6817857 # Number of branches executed +system.cpu2.iew.exec_stores 2008777 # Number of stores executed system.cpu2.iew.exec_rate 0.990668 # Inst execution rate -system.cpu2.iew.wb_sent 30155470 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 30122461 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17393526 # num instructions producing a value -system.cpu2.iew.wb_consumers 20640191 # num instructions consuming a value +system.cpu2.iew.wb_sent 30155480 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 30122471 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17393530 # num instructions producing a value +system.cpu2.iew.wb_consumers 20640200 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.986467 # insts written-back per cycle +system.cpu2.iew.wb_rate 0.986468 # insts written-back per cycle system.cpu2.iew.wb_fanout 0.842702 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu2.commit.commitSquashedInsts 2374784 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 185688 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 182288 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 26517972 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.145282 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.851176 # Number of insts commited each cycle +system.cpu2.commit.branchMispredicts 182289 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 26517964 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.145283 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.851177 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 16375650 61.75% 61.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2329506 8.78% 70.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1218962 4.60% 75.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4807374 18.13% 93.26% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 16375646 61.75% 61.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2329504 8.78% 70.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1218959 4.60% 75.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 4807373 18.13% 93.26% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::4 502647 1.90% 95.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 186920 0.70% 95.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 179412 0.68% 96.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 186921 0.70% 95.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 179411 0.68% 96.54% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::7 180660 0.68% 97.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 736841 2.78% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 736843 2.78% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 26517972 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30370560 # Number of instructions committed -system.cpu2.commit.committedOps 30370560 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 26517964 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 30370564 # Number of instructions committed +system.cpu2.commit.committedOps 30370564 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 4905588 # Number of memory references committed -system.cpu2.commit.loads 2973681 # Number of loads committed +system.cpu2.commit.refs 4905590 # Number of memory references committed +system.cpu2.commit.loads 2973683 # Number of loads committed system.cpu2.commit.membars 65235 # Number of memory barriers committed system.cpu2.commit.branches 6667985 # Number of branches committed system.cpu2.commit.fp_insts 111312 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28908362 # Number of committed integer instructions. +system.cpu2.commit.int_insts 28908366 # Number of committed integer instructions. system.cpu2.commit.function_calls 232233 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 736841 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 736843 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 58454827 # The number of ROB reads -system.cpu2.rob.rob_writes 65882898 # The number of ROB writes -system.cpu2.timesIdled 242873 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 3625347 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.rob.rob_reads 58454819 # The number of ROB reads +system.cpu2.rob.rob_writes 65882909 # The number of ROB writes +system.cpu2.timesIdled 242872 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3625344 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu2.quiesceCycles 1745288097 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 29192891 # Number of Instructions Simulated -system.cpu2.committedOps 29192891 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 29192891 # Number of Instructions Simulated -system.cpu2.cpi 1.045998 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.045998 # CPI: Total CPI of All Threads +system.cpu2.committedInsts 29192895 # Number of Instructions Simulated +system.cpu2.committedOps 29192895 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 29192895 # Number of Instructions Simulated +system.cpu2.cpi 1.045997 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.045997 # CPI: Total CPI of All Threads system.cpu2.ipc 0.956025 # IPC: Instructions Per Cycle system.cpu2.ipc_total 0.956025 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39779581 # number of integer regfile reads -system.cpu2.int_regfile_writes 21289103 # number of integer regfile writes +system.cpu2.int_regfile_reads 39779596 # number of integer regfile reads +system.cpu2.int_regfile_writes 21289109 # number of integer regfile writes system.cpu2.fp_regfile_reads 68643 # number of floating regfile reads system.cpu2.fp_regfile_writes 68941 # number of floating regfile writes system.cpu2.misc_regfile_reads 4607989 # number of misc regfile reads |